KR100282228B1 - Data output buffer - Google Patents

Abstract

The present invention relates to a data output buffer, and has a purpose of providing a well-bias control circuit so that a well-bias voltage having the same level as an input signal is supplied to a pull-up control circuit.

The present invention for this purpose comprises a data output stage, a driver, a well-bias controller, a pull-up controller, a pull-down controller. The first signal of the first level or the second level is input / output to the data output terminal. The driver receives the data signal and the output enable signal and generates a pull-up control signal and a pull-down control signal of a third level. The well-bias control unit is configured to generate a well-bias voltage of a first level when the first signal is a first level, and to generate a well-bias voltage of a second level when the first signal is a second level. The pull-up control unit receives a well-bias voltage and is controlled by a pull-up control signal to pull up the data output terminal. The pull-down control unit is controlled by a pull-down control signal to pull down the data output stage.

Description

Data output buffer

The present invention relates to a data output buffer, and more particularly, to a data output buffer configured to output a data signal through an input / output pad capable of inputting and outputting data.

The semiconductor integrated circuit uses a data output buffer to output data signals generated therein to the outside. In general, internal signals of semiconductor integrated circuits use low-level signals for high operating speeds and low power consumption, but signals output to the outside use enhanced levels of signals for sufficient load driving capability.

1 is a circuit diagram illustrating a conventional data output buffer. The output enable signal EN and the data signal DOUT are input to the pre-driver 102. Supply voltage VDD is 2.5V. The pre-driver 102 outputs a pull-up control signal PU and a pull-down control signal PD. If the data signal DOUT is at a high level, the pull-up control signal PU is also at a high level. If the data signal DOUT is at a low level, the pull-down control signal PD is at a low level. The pull-up control signal PU drives the pull-up control circuit 104, and the pull-down control signal PD drives the pull-down control circuit 106. Both the pull-up control signal PU and the pull-down control signal PD have a voltage level of 3.3V.

The pull-up control circuit 104 and the pull-down control circuit 106 are both connected to the input / output pad 108. The input / output pad 108 allows both input and output of data. The data signal input through the input / output pad 108 is transferred into the chip through a separate input terminal 110, and at this time, both the pull-up control circuit 104 and the pull-down control circuit 106 constituting the data output buffer are turned. Off to tri-state.

However, when a 5V signal is input through the input / output pad 108, the PMOS transistor 112 is turned on (since the gate voltage is 3.3 V-Vtn), and a current path is formed from the input / output pad 108 to the VDD3. In order to prevent this, the PMOS transistor 114 is used. When a 5V signal is input through the input / output pad 108, the PMOS transistor 116 is turned on to transmit a 5V signal to the node 120. For this reason, the PMOS transistor 112 is not turned on.

In the PN junction of the drain (P + region) of the PMOS transistor 112 and the n-well, 5V (input signal) is applied to the drain and 3.3 volts (VDD3) is applied to the n-well to form a forward bias. In order to prevent the PMOS transistor 114 is used. When the node 120 becomes 5V, the gate of the PMOS transistor 114 also takes 5V, so that the well-bias connected to VDD3 to the bulk n-well of each PMOS transistor 112 to 116 is cut off. Float The NMOS transistor 118 is for preventing the 5V voltage of the node 120 from being transmitted to the pre-driver 102.

However, in the conventional data output buffer, the NMOS transistor 118 is used to prevent the 5V voltage of the node 120 from being transmitted to the pre-driver 102. The voltage at the NMOS transistor 118 is used. The PMOS transistor 112 may not be completely turned off due to the drop Vt. Therefore, a separate circuit is needed to compensate for this. In addition, if the power supply voltage of the pre-driver 102 is about 2.5V, which is lower than 3.3V, a separate level shift circuit is required. When the level shift circuit is connected in series with the NMOS transistor 118, the pull-up control signal PU is applied. The longer the transmission path, the worse the signal transmission characteristic.

Accordingly, an object of the present invention is to provide a well-bias control circuit so that a well-bias voltage having the same level as an input signal is supplied to a pull-up control circuit.

The present invention for this purpose comprises a data output stage, a driver, a well-bias controller, a pull-up controller, a pull-down controller.

The first signal of the first level or the second level is input / output to the data output terminal. The driver receives the data signal and the output enable signal and generates a pull-up control signal and a pull-down control signal of a third level. The well-bias control unit is configured to generate a well-bias voltage of a first level when the first signal is a first level, and to generate a well-bias voltage of a second level when the first signal is a second level. The pull-up control unit receives a well-bias voltage and is controlled by a pull-up control signal to pull up the data output terminal. The pull-down control unit is controlled by a pull-down control signal to pull down the data output stage.

1 is a circuit diagram of a conventional data output buffer.

2 is a circuit diagram of a data output buffer according to the present invention.

Explanation of symbols on the main parts of the drawings

102, 202: pre-driver 104, 204, pull-up control circuit

106, 206: pull-down control circuit 108, 208: input / output pad

110, 232: Input terminal VDD3: 3.3V power supply voltage

VDD: 2.5V or 3.3V Supply Voltage

The preferred embodiment of the present invention thus made will be described with reference to FIG. 2 as follows. 2 is a circuit diagram illustrating a data output buffer according to the present invention.

As shown in FIG.

The output enable signal EN and the data signal DOUT are input to the pre-driver 202. Supply voltage VDD is 2.5V. The pre-driver 202 outputs a pull-up control signal PU and a pull-down control signal PD. If the data signal DOUT is at a high level, the pull-up control signal PU is also at a high level. If the data signal DOUT is at a low level, the pull-down control signal PD is at a low level. The pull-up control signal PU drives the pull-up control circuit 204, and the pull-down control signal PD drives the pull-down control circuit 206. Both the pull-up control signal PU and the pull-down control signal PD have a voltage level of 2.5V.

The pull-up control circuit 204 and the pull-down control circuit 206 are both connected to the input / output pad 208 through the data output terminal. Both input and output of data are possible through this input / output pad 208. The data signal input through the input / output pad 208 is transferred to the chip through a separate input terminal 232, and at this time, both the pull-up control circuit 204 and the pull-down control circuit 206 constituting the data output buffer are turned. Off to tri-state.

First, the configuration of the pull-up control circuit 204 will be described. The NMOS transistor 226 is controlled by a signal in which the pull-up control signal PU is inverted by the inverter 234. The source of the NMOS transistor 226 is grounded and another NMOS transistor 224 is connected to the drain. The gate of the NMOS transistor 224 is always turned on by the same voltage as the power supply voltage VDD of the pre-driver 102.

Two PMOS transistors 218 and 220 are connected in series between the 3.3V power supply voltage VDD3 and the data output terminal. The gate of the PMOS transistor 218 is controlled by the output signal of the NMOS transistor 224 described above, and the gate of the PMOS transistor 220 is controlled by the pull-up control signal PU. Both ends of the PMOS transistor 222 are connected between the gate of the PMOS transistor 218 and the data output terminal. The 3.3V voltage VDD3 is always supplied to the gate of the PMOS transistor 222. Each PMOS transistor of the pull-up control circuit 204 has a well-bias voltage output from the well-bias control circuit 210.

The well-bias control circuit 210 is configured as follows. The 3.3V power supply voltage VDD3 is supplied to two PMOS transistors 212 and 214 connected in parallel. The gate of the PMOS transistor 212 is controlled by the output signal of the NMOS transistor 224 of the pull-up control circuit 204, and the gate of the PMOS transistor 214 is controlled by the signal of the data output terminal. The PMOS transistor 216 is connected between the other end of the two PMOS transistors 212 and 214 and the data output terminal. The gate of this PMOS transistor 216 is controlled by the 3.3V power supply voltage VDD3. At the other end of the two PMOS transistors 212 connected in parallel, a well-bias voltage is generated and supplied to the PMOS transistors 218 to 222 of the pull-up control circuit 204 described above.

When the pull-up control signal PU becomes high level (2.5V) to output the data signal of logic 1, the PMOS transistor 220 and the NMOS transistor 226 are turned on. 218) is also turned on to output a 3.3V signal to the data output terminal.

When a 5V signal is input through the input / output pad 208, the PMOS transistor 216 is turned on so that the well-bias voltage becomes 5V. For this reason, the PMOS transistor 222 of the pull-up control circuit 204 is also turned on, and a 5V signal is also supplied to each gate of the PMOS transistor 218 and 212. That is, the well-bias voltage of 5V is supplied to all PMOS transistors 218 to 222 of the pull-up control circuit 204. At this time, the NMOS transistor 224 is used to prevent the 5V voltage of the data output terminal from being directly transmitted to the NMOS transistor 226.

In the above-described embodiment, it is assumed that the supply voltage VDD of the pre-driver 102 is 2.5V. In this case, the pull-up control signal PU must be converted to 3.3V using a level shifter. In this case, the inverter 234 in the pre-driver 102 may be replaced with a level shifter.

Therefore, the present invention includes a well-bias control circuit so that the well-bias voltage having the same level as the input signal is supplied to the pull-up control circuit, thereby improving the breakdown voltage characteristic according to the voltage difference between the internal signal and the external signal.

Claims (4)

In the data output buffer, A data output terminal to which the first signal of the first level or the second level is input / output; A driver which receives a data signal and an output enable signal and generates a pull-up control signal and a pull-down control signal of a third level; A well bias control unit configured to generate a well-bias voltage of a first level when the first signal is at the first level, and to generate a well-bias voltage of a second level when the first signal is at the second level; Wow; A pull-up control unit configured to receive the well-bias voltage and be controlled by the pull-up control signal to pull up the data output terminal; And a pull-down control unit controlled by the pull-down control signal to pull down the data output terminal. The data output buffer according to claim 1, wherein the first level has a minimum value and the third level has a maximum value among the signals of the first to third levels. The method of claim 1, wherein the well bias control unit, A first transistor controlled by a second signal and a second transistor controlled by the first signal are connected in parallel, one end of the first transistor and the second transistor connected to a first voltage and the other end of the well bias voltage And an output terminal, wherein the other end is connected to the data output terminal through a third transistor supplied with the first voltage to a gate, and the first to third transistors have the well bias voltage. The method according to claim 1, wherein the pull-up control unit, A fourth transistor controlled by the inverted signal of the pull-up control signal to output the second signal, a fifth transistor controlled by the second signal and a sixth transistor controlled by the pull-up control signal A data output buffer connected in series between the first voltage and the data output terminal, the second signal being input to a drain of a seventh transistor, a source connected to the data output terminal, and a gate controlled by the first voltage.