KR100551897B1 - Low power consumption latch circuit - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to electronic circuit technology, and more particularly, to a low power latch circuit. SUMMARY OF THE INVENTION An object of the present invention is to provide a latch circuit having a low power consumption characteristic and capable of preventing an unwanted voltage level drop of stored data. According to one aspect of the invention, switching means for switching between the input terminal and the data storage node in response to a clock; First inverting means for inverting a signal applied to the data storage node to generate an output signal; Second inverting means for receiving the output signal as an input; And a driving means for driving the data storage node with an output signal of the second inverting means in response to the clock.

Low Power, Latch Circuit, Leakage, Voltage Drop, Clock

Description

LOW POWER CONSUMPTION LATCH CIRCUIT             

1 shows a general latch circuit.

2 shows a low power latch circuit according to the prior art;

3 is a diagram illustrating a simulation result of the low power latch circuit of FIG. 2.

4 illustrates a low power latch circuit in accordance with an embodiment of the present invention.

5 is a diagram illustrating a simulation result of the low power latch circuit of FIG. 4.

* Explanation of symbols for the main parts of the drawings

B: data storage node

CLK: Clock

TECHNICAL FIELD The present invention relates to electronic circuit technology, and more particularly, to a low power latch circuit.

The LCD, which has been in the spotlight as a new display recently, includes a unique structure called a source driver, and a data latch is provided for each channel in the source driver.

Although the data latch circuit is a relatively simple circuit, since the LCD source driver includes as many data latch circuits as the number of channels, it is difficult to overlook the area and power consumption of the data latch circuit.

1 illustrates a general latch circuit.

Referring to FIG. 1, a general latch circuit includes a NAND gate NAND1 for inputting an input signal IN and a clock CLK, an inverter INV1 for inputting an input signal IN, and an inverter INV1. NAND gate NAND2 for inputting the inverted input signal IN and clock CLK, and NAND gate for inputting the output signal of the NAND gate NAND2 and the final feedback signal OUTB fed back. NIN3, an inverter INV2 for inputting the output signal of the NAND gate NAND1, an inverter INV3 for inputting the output signal of the NAND gate NAND3, an output signal of the inverter INV2, and an inverter ( An OR gate OR1 for outputting the final output signal OUTB by inputting the output signal of INV3).

The latch circuit configured as described above stores the input signal IN at each rising edge of the clock CLK.

However, since such a latch circuit requires at least 24 MOS transistors to implement the circuit, it has disadvantages in terms of layout area and high power consumption.

In view of these problems, efforts have been made to reduce the number of transistors required to implement a latch circuit.

2 illustrates a low power latch circuit according to the prior art.

Referring to FIG. 2, a low power latch circuit according to the related art is connected between an input terminal IN and a node A and inverts a switching NMOS transistor N1 having a clock CLK as a gate input and a signal applied to the node A. Inverter INV4 for generating the output signal OUT, the pull-up PMOS transistor P1 connected between the power supply voltage terminal VDD and the node A and having the feedbacked output signal OUT as a gate input, and ground. It is composed of a pull-down NMOS transistor N2 connected between the voltage terminal VSS and the node A and having a gated input as the output signal OUT fed back.

First, when the input signal IN is at the logic level low, the switching NMOS transistor N1 is turned on at the rising edge of the clock CLK so that the node A is at the logic level low and the output signal OUT is at the logic level high. The output signal OUT of the logic level high is fed back so that the pull-down NMOS transistor N2 is turned on to maintain the node A at the logic level low. In this case, the data level is maintained because the pull-down NMOS transistor N2 continues to discharge the node A even when the clock CLK becomes a logic level low.

Next, when the input signal IN is at the logic level high, the switching NMOS transistor N1 is turned on at the rising edge of the clock CLK so that the node A is at the logic level high and the output signal OUT is at the logic level low. The output signal OUT of the logic level low is fed back so that the pull-up PMOS transistor P1 is turned on to maintain the node A at the logic level high. In this case, the data level is maintained because the pull-up PMOS transistor P1 continues to charge the node A even when the clock CLK goes low.

The conventional low power latch circuit configured and operated as described above can greatly reduce the number of transistors required to five to significantly reduce power consumption compared to the latch circuit shown in FIG. 1.

However, there is a problem in that the voltage level of the input signal IN falls during the period when the clock CLK is at a logic level low.

FIG. 3 is a diagram illustrating a simulation result of the conventional low power latch circuit shown in FIG. 2, and it can be seen that the voltage level of the input signal IN drops by about 0.1 V in a section where the clock CLK is at a logic level low. .

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and has an object of providing a latch circuit having a low power consumption characteristic and preventing an unwanted voltage level drop of stored data.

According to an aspect of the present invention for achieving the above technical problem, switching means for switching between the input terminal and the data storage node in response to the clock; First inverting means for inverting a signal applied to the data storage node to generate an output signal; Second inverting means for receiving the output signal as an input; And a driving means for driving the data storage node with an output signal of the second inverting means in response to the clock.

Here, the switching means and the driving means are enabled at different levels of the clock.

According to another aspect of the present invention, there is provided an NMOS transistor connected between an input terminal and a data storage node and having a clock as a gate input; A first inverter for generating an output signal by inverting a signal applied to the data storage node; A second inverter configured to receive the output signal; And a PMOS transistor connected between an output terminal of the second inverter and the data storage node and having the clock as a gate input.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

4 illustrates a low power latch circuit according to an embodiment of the present invention.

Referring to FIG. 4, a switching NMOS transistor N3 connected between an input terminal IN and a node B (data storage node) and using a clock CLK as a gate input, and an output signal (inverted) by inverting a signal applied to the node B. Drive INV5 for generating OUT, inverter INV6 for inputting output signal OUT, and output terminal of inverter INV6 and node B, and driving clock CLK as a gate input. PMOS transistor P2 is provided.

Herein, it is preferable to implement the inverters INV5 and INV6 as strong feedback inverters.

The operation of the latch circuit shown in FIG. 4 will now be described.

First, when the input signal IN is at the logic level low, the switching NMOS transistor N3 is turned on at the rising edge of the clock CLK so that the node B is at the logic level low and the output signal OUT is at the logic level high. . On the other hand, when the clock CLK is at a logic level low, the driving PMOS transistor P2 is turned on to drive the node B with the inverted value (low) of the output signal OUT fed back through the inverter INV6.

Next, when the input signal IN is at the logic level high, the switching NMOS transistor N3 is turned on at the rising edge of the clock CLK so that the node B is at the logic level high and the output signal OUT is at the logic level low. do. On the other hand, when the clock CLK becomes a logic level low, the driving PMOS transistor P2 is turned on to drive the node B with the inverted value (high) of the output signal OUT fed back through the inverter INV6.

The latch circuit according to the present embodiment configured and operated as described above has a low power consumption characteristic because it is implemented with a total of six transistors, and has a better clock leakage characteristic than the conventional low power latch circuit shown in FIG. The data can be stored while minimizing the voltage level drop of the data in the low section.

FIG. 5 is a diagram illustrating a simulation result of the low power latch circuit of FIG. 4, and it can be seen that a voltage drop of about 0.01 V is shown in a section in which the clock CLK is low, which is illustrated in FIG. 2. This value is about 1/10 of the latch circuit.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although the foregoing only mentions the application of the LCD source driver to the data latch, the latch circuit of the present invention is also suitable for a circuit requiring a large number of latches such as a register.

In addition, even if the NMOS transistor and the PMOS transistor used in the above-described embodiments are implemented in different types of switching elements, the present invention is applicable.

The present invention described above provides a latch circuit that minimizes the voltage level drop of stored data while maintaining low power consumption, thereby reducing power consumption and preventing data errors of an IC employing the latch circuit.

Claims (3)

Switching means for switching between an input terminal and a data storage node in response to a clock; First inverting means for inverting a signal applied to the data storage node to generate an output signal; Second inverting means for receiving the output signal as an input; And Driving means for driving said data storage node with an output signal of said second inverting means in response to said clock; A latch circuit having a. The method of claim 1, The switching means and the driving means are enabled at different levels of the clock. An NMOS transistor connected between an input terminal and a data storage node and having a clock as a gate input; A first inverter for generating an output signal by inverting a signal applied to the data storage node; A second inverter configured to receive the output signal; And A PMOS transistor connected between an output terminal of the second inverter and the data storage node and having the clock as a gate input A latch circuit having a.

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