200947669 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體記憶裝置，特別是有關於一 種具有雙重溝槽電容的記憶裝置及其製造方法。 【先前技锏0 隨著積體電路的發展技術日新月異，可攜式電子產 Φ 品，例如手機，具備了更多的功能。因此，使用於可攜式 電子產品内的高密度記憶裝置，例如低功率虛擬靜態隨機 存取記憶體（lower power pseudo SRAM)及/或低功率動態 隨機存取記憶體（lower power DRAM )，必須能夠降低待 機電流（standby current)以延長電子產品的待機時間來應 付照相、音樂播放、或其他多媒體功能。 對於記憶裝置而言，更新電流（refresh current)佔了 一半以上的待機電流，而更新電流的大小又與資料保留時 間（retention time )的長短成反比與位元線的長短成正比。 因此，增加資料保留時間及/或縮短位元線長度成為記憶裝 置設計的重要的關鍵。 現今大多數的記憶單元是由一個電晶體與一個深溝槽 電容器所構成。在元件積集度要求越來越高的情況下，記 憶單元與電晶體的尺寸需要大幅縮小，才可能製造出記憶 容量更高，處理速度更快的記憶體。在這種情形之下，縮 短位元線長度將使記憶體的尺寸增加且更新電流的降幅有 96-064/0492-A41265-TW/fmal 6 200947669 .限。，此:有人提出雙單元（⑽請⑴記憶裝置。亦即， 。己隐單兀疋由—個電晶體與二個料槽電容器所構成。此 種配置可藉由在二個深溝槽電容器儲存互補的資料信號來 有=降低因漏電所造成儲存資料的喪失，進而增加資料保 留時間。再者’儲存的資料由深溝槽電容器對分，可有效 縮短寫入及讀取的時間，進而提高記憶體的速度並降低工 =電£」而’此種配置將使記憶體的尺寸增加，無法提 ❹★記憶雜集度㈣提升記憶體的記憶容量。 =此’有必要尋求—種新的記憶裝置結構，其能夠具 有雙早兀記憶裝置的優勢，且能夠縮小記憶裝置尺寸而改 善記憶體積集度。 【發明内容】 有ϋιϋ本發明《目的在於提供一種具 電容的記«置及其製造方法， t 電晶體結構與雙重溝槽電容組成-記憶 以θ加貝料保留時間’同時能夠縮小記憶裝置尺寸而改_1 記憶體積集度。 』叩汉菩 4據述之目的，本發明提供一種具有雙重溝槽電容 的記憶裝置’包括：—基底、二埋人式溝槽電容、以及一 垂直電晶體結構。基底具有二深溝槽及一開口位於二深溝 槽之間，其巾深溝槽及開口彼此關。二埋人式溝槽電容 分別設置㈣料的下半部。垂直電晶體結構包括：一閑 極電極、一閘極介雷g m 一源極區、以及二汲極區。閘極 96-064/0492-A41265-TW/fmal 7 200947669 .電極設置於開口内。閘極介電層設置於開口的侧壁及底 4 一源極區刀別δ又置於開口兩侧的基底内且鄰近開口的 頂β 一汲極區分別设置於開口兩側的基底内且鄰近開口 的底部。其中、’沒極區分別電性連接至埋入式溝槽電容。 又根據上述之目的，本發明提供一種具有雙重溝槽電 容的記憶裝置的製造方法，包括：提供一基底，具有二深 溝槽，且一深溝槽彼此隔離。在每一深溝槽下半部形成一 ❹埋入式溝槽電容。在二深溝槽之間的基底内形成一開口， 且開口與深溝槽彼此隔離。在開口側壁及底部形成一閘極 介電層。在開口内形成一閘極電極。在開口兩侧的基底内 且鄰近開口的底部形成二沒極區，以分別電性連接至埋入 式溝槽電容。在開口兩侧的基底内且鄰近開口的頂部分別 形成一源極區。 【實施方式】 以下配合第4F及5圖說明根據本發明實施例之具有雙 ❹重溝槽電容的記憶裝置’例如低功率虛擬SRAM或低功率 DRAM ’其中為了使第5圖更為清晰明瞭，僅繪示出些許 部件’例如位元線140、位元線接觸插塞〗38a及138b、深 溝槽對101a及101b、以及開口 120。在本實施例中，記憶 裝置包括·· 一基底100、複數埋入式溝槽電容、複數垂直 電晶體結構、複數字元線、以及複數位元線14〇。基底1〇〇， 例如一矽基底或其他半導體基底’具有由複數深溝槽對 1 〇 1 a及1 〇 1 b所構成的深溝槽陣列，其中深溝槽陣列的列 方向為位元線140的方向而行方向為字元線的方向。再 96-064/0492-A41265-TW/fmal 200947669 者，在列方向上兩相鄰的深溝槽對l〇la及l〇lb之間的基 底100内具有一開口 120，其中深溝槽對1〇la及i〇lb及 開口 120彼此隔離。特別的是在本實施例的記憶裝置中， 每一記憶單元的基底1〇〇包括：一開口 12〇以及位於開口 120兩側的深溝槽101a及深溝槽101b。 複數埋入式溝槽電容對應設置於深溝槽l〇la及l〇lb 的下半部，每一埋入式溝槽電容包括：埋入式下電極1〇8、 一上電極112及介於兩電極108及112之間的電容介電層 ❹ 11〇。領型絕緣層1〇6設置於每一深溝槽i〇ia/i〇ib的侧壁 且鄰近於上電極112頂部。複數隔離絕緣層118，對應設 置於每一深溝槽對101a及l〇lb的上半部。複數埋入帶層 (buried strap) 116，對應設置於每一深溝槽101a/101b内 隔離絕緣層118與埋入式溝槽電容之間。 每一垂直電晶體結構包括：一字元線（由閘極電極i27 及位於其上方的第二閘極電極129所構成）、一閘極介電 層124、一上蓋層13卜一絕緣間隙壁134、二源極區132、 二沒極區122、以及一隔離摻雜區121。閘極電極127設置 於開口 120内’可由摻雜的複晶矽所構成’而上方的第二 閘極電極129可由金屬或金屬矽化物所構成。閘極介電層 124設置於開口 120的侧壁及底部。上蓋層131設置於字 元線上方’而絕緣間隙壁134設置於字元線的側壁。二源 極區132分別設置於開口 120兩侧的基底1 〇〇内且鄰近開 口 120的頂部。二汲極區122分別設置於開口 120兩侧的 基100内且鄰近開口 120的底部。其中，汲極區122藉由 96-064/0492-A41265-TW/fmal 9 200947669 .對應的埋入帶層Π6而分別電性連接至埋入式溝槽電# 隔離摻雜區12ι設置於開口 120下方的基底100内且ς丄 及極區122相鄰。隔離摻雜區121與汲極區122具有不_ 的導電型（Ν型或Ρ型）。 同 位元線140平行設置於上蓋層131上方，其中二相鄰 的位元線140，分別藉由位元線接觸插塞138a及i38b而 電性連接至直電晶體結構的二源極區132。 以下配合第1A至1B圖、第2A至2C圖、第3八至3d 圖、第4A至4F、及第5圖說明根據本發明實施例之具有 雙重溝槽電容的記憶裝置製造方法。請參照第1八至1B 圖，其中第1A圖繪示出根據本發明實施例之具有用於^ 憶裝置的深溝槽陣列的基底平面示意圖，而第1B圖係續 示出沿第1A圖中1 -1 ’線的剖面示意圖。提供一基底1 例如一矽基底或其他半導體基底’其具有由複數深薄槽對 l〇la及l〇ib所構成的深溝槽陣列，其中深溝槽陣列的列 ❹ 方向為位元線140的方向而行方向為字元線的方向。深填 槽對101a及101b可藉由形成於基底上方的罩幕層定 義形成之。在本實施例中，罩幕層包括一墊氧化矽層1〇2 及一氮化矽層104。另外，每一記憶單元的基底1〇〇包括： 深溝槽l〇la及深溝槽101b，如第1A圖中由虛線圍成的區 域所示。 請參照第2A至2C圖，其係繪示出根據本發明實施例 之埋入式溝槽電容的製造剖面示意圖。如第2A圖所示’ 藉由習知製程步驟，在每一深溝槽對l〇la及101b的上半 96-064/0492-A41265-TW/final 200947669 口户$成頁I絕緣層（collar insulator) 106且在下半部形成 玉埋=式下電極1〇8。舉例而言’將摻雜氣體藉由趨熱擴 政製权使接雜物擴散至深溝槽對l〇la及101b下半部的 美 # 1 〇〇 tb ^ ’而形成一擴散區’用以作為電容器之埋入式 下電極108。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor memory device, and more particularly to a memory device having a dual trench capacitor and a method of fabricating the same. [Previous Technology 0 With the rapid development of integrated circuit technology, portable electronic products such as mobile phones have more functions. Therefore, high-density memory devices used in portable electronic products, such as low-power virtual static random access memory (RAM) and/or low-power dynamic random access memory (lower power DRAM), must Can reduce standby current to extend the standby time of electronic products to cope with photography, music playback, or other multimedia functions. For a memory device, the refresh current accounts for more than half of the standby current, and the magnitude of the update current is inversely proportional to the length of the data retention time and the length of the bit line. Therefore, increasing data retention time and/or shortening bit line lengths is an important key to the design of memory devices. Most memory cells today consist of a transistor and a deep trench capacitor. In the case where the component integration requirement is getting higher and higher, the size of the memory cell and the transistor needs to be greatly reduced, and it is possible to manufacture a memory having a higher memory capacity and a faster processing speed. In this case, shortening the length of the bit line will increase the size of the memory and the decrease in the update current is limited to 96-064/0492-A41265-TW/fmal 6 200947669. This: Some people have proposed a dual unit ((10) please (1) memory device. That is, it has been composed of a transistor and two slot capacitors. This configuration can be stored in two deep trench capacitors. Complementary data signals have = reduce the loss of stored data caused by leakage, and thus increase the data retention time. In addition, the 'stored data is divided by deep trench capacitors, which can effectively shorten the writing and reading time, thereby improving memory. The speed of the body is reduced and the power is reduced. "This configuration will increase the size of the memory, and it will not improve the memory. (4) Improve the memory capacity of the memory. = This is necessary to seek a new memory. The device structure can have the advantages of a double early memory device, and can reduce the size of the memory device to improve the memory volume. [Invention] The present invention has an object of providing a capacitor with a capacitor and a manufacturing method thereof. , t transistor structure and double trench capacitor composition - memory with θ plus bead retention time 'can reduce the size of the memory device and change the memory volume set. The purpose of the present invention is to provide a memory device having a double trench capacitor 'including: a substrate, a buried capacitor, and a vertical transistor structure. The substrate has two deep trenches and an opening. Between the two deep trenches, the deep trenches and the openings of the towel are closed to each other. The two buried trench capacitors respectively set the lower half of the material (four). The vertical transistor structure includes: a idle electrode, a gate dielectric gm source Polar region and diode region. Gate 96-064/0492-A41265-TW/fmal 7 200947669. The electrode is placed in the opening. The gate dielectric layer is placed on the sidewall of the opening and the bottom 4 is a source region knife. The δ is placed in the substrate on both sides of the opening and the top β-dual region adjacent to the opening is respectively disposed in the substrate on both sides of the opening and adjacent to the bottom of the opening. Among them, the 'pole region is electrically connected to the buried type respectively. Trench Capacitance According to the above object, the present invention provides a method of fabricating a memory device having a dual trench capacitor, comprising: providing a substrate having two deep trenches, and a deep trench is isolated from each other. Half formation ❹ Buried trench capacitors. An opening is formed in the substrate between the two deep trenches, and the openings are separated from the deep trenches. A gate dielectric layer is formed on the sidewalls and the bottom of the opening. A gate electrode is formed in the opening. Two dipole regions are formed in the substrate on both sides of the opening and adjacent to the bottom of the opening to be electrically connected to the buried trench capacitors respectively. A source region is formed in the substrate on both sides of the opening and adjacent to the top of the opening. [Embodiment] Hereinafter, a memory device having a double-thickness trench capacitor, such as a low-power dummy SRAM or a low-power DRAM, according to an embodiment of the present invention will be described with reference to FIGS. 4F and 5, in which FIG. 5 is more clear. Only a few components 'such as bit line 140, bit line contact plugs 38a and 138b, deep trench pairs 101a and 101b, and opening 120 are shown. In this embodiment, the memory device includes a substrate 100, a plurality of buried trench capacitors, a plurality of vertical transistor structures, complex digital lines, and a plurality of bit lines 14A. The substrate 1 〇〇, such as a germanium substrate or other semiconductor substrate ′, has a deep trench array of complex deep trench pairs 1 〇 1 a and 1 〇 1 b, wherein the column direction of the deep trench array is the direction of the bit line 140 The row direction is the direction of the word line. Further, in 96-064/0492-A41265-TW/fmal 200947669, an opening 120 is formed in the substrate 100 between two adjacent deep trench pairs l〇1a and 10b in the column direction, wherein the deep trench is 1〇 La and i lb and opening 120 are isolated from each other. In particular, in the memory device of the present embodiment, the substrate 1 of each memory cell includes an opening 12 〇 and a deep trench 101a and a deep trench 101b on both sides of the opening 120. The plurality of buried trench capacitors are correspondingly disposed in the lower half of the deep trenches l〇1a and l〇1b, and each buried trench capacitor includes: a buried lower electrode 1〇8, an upper electrode 112, and A capacitive dielectric layer 两 11〇 between the two electrodes 108 and 112. A collar insulating layer 1〇6 is provided on the sidewall of each deep trench i〇ia/i〇ib and adjacent to the top of the upper electrode 112. A plurality of isolation insulating layers 118 are provided correspondingly to the upper half of each of the deep trench pairs 101a and 101b. A plurality of buried straps 116 are disposed between the isolation insulating layer 118 and the buried trench capacitors in each of the deep trenches 101a/101b. Each vertical transistor structure comprises: a word line (consisting of a gate electrode i27 and a second gate electrode 129 located above), a gate dielectric layer 124, an upper cap layer 13 and an insulating spacer 134, a second source region 132, a second well region 122, and an isolation doping region 121. The gate electrode 127 is disposed in the opening 120 and may be formed of doped polysilicon, and the upper second gate electrode 129 may be composed of a metal or metal halide. The gate dielectric layer 124 is disposed on the sidewalls and the bottom of the opening 120. The upper cap layer 131 is disposed above the word line and the insulating spacer 134 is disposed on the sidewall of the word line. The two source regions 132 are respectively disposed in the substrate 1 两侧 on both sides of the opening 120 and adjacent to the top of the opening 120. The second drain regions 122 are disposed in the base 100 on both sides of the opening 120 and adjacent to the bottom of the opening 120, respectively. The drain region 122 is electrically connected to the buried trench via the corresponding buried strap layer 6 by the 96-064/0492-A41265-TW/fmal 9 200947669. The isolated doped region 12 is disposed at the opening. The substrate 100 below the 120 is adjacent to the crucible and the polar region 122. The isolation doping region 121 and the drain region 122 have a conductivity type (Ν type or Ρ type). The parity lines 140 are disposed in parallel above the upper cap layer 131. The two adjacent bit lines 140 are electrically connected to the two source regions 132 of the direct crystal structure by the bit line contact plugs 138a and i38b, respectively. Hereinafter, a method of manufacturing a memory device having a double trench capacitor according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1B, 2A to 2C, 3rd to 3d, 4A to 4F, and 5th. Please refer to FIGS. 1-8 to 1B, wherein FIG. 1A is a schematic plan view of a substrate having a deep trench array for a memory device according to an embodiment of the present invention, and FIG. 1B is continued along FIG. 1A. A schematic view of the section of the 1 -1 ' line. A substrate 1 is provided, such as a substrate or other semiconductor substrate, having a deep trench array of a plurality of deep trench pairs l〇la and l〇ib, wherein the direction of the column of the deep trench array is the direction of the bit line 140. The row direction is the direction of the word line. The deep fill groove pairs 101a and 101b can be defined by a mask layer formed over the substrate. In this embodiment, the mask layer includes a pad oxide layer 1〇2 and a tantalum nitride layer 104. Further, the substrate 1 of each memory cell includes: a deep trench 10a and a deep trench 101b as shown by a region surrounded by a broken line in Fig. 1A. Referring to Figures 2A through 2C, there are shown schematic cross-sectional views showing the fabrication of a buried trench capacitor in accordance with an embodiment of the present invention. As shown in Figure 2A, by the conventional process steps, the upper half of each deep trench pair l〇la and 101b is 96-064/0492-A41265-TW/final 200947669. Insulating) 106 and forming a lower buried electrode 1〇8 in the lower half. For example, 'the doping gas is diffused by the thermal expansion to make the dopant diffuse to the deep trench pair 〇la and the lower half of the 101b to form a diffusion region' to form a diffusion region' The buried lower electrode 108 is used as a capacitor.
然後，如第2Β圖所示，於深溝槽對101a及101b下半 部的側壁料部形成電容介電層110,其為氮㈣層、氧 化矽-氮化矽（oxide-nitride，ON)的疊層結構、或是氧化 石夕-氣化石夕-氧化石夕（oxide-nitride-oxide，ΟΝΟ)的疊層結 構。 接著，如第2C圖所示，於每一深溝槽對i〇ia及i〇ib 内填滿一摻雜的複晶矽層（未繪示），並將摻雜的複晶矽 層回蝕刻至一預定深度而完成埋入式溝槽電容的上電極 112的製作。 請參照第3A至3D圖，第3A圖係繪示出根據本發明 實施例之定義埋入帶詹區的平面示意圖，而第至3D圖 係繒示出根據本發明實施例之埋入帶製造及主動區定義的 製造剖面示意圖。如第3 A及3B圖所示，沿著深漠槽陣列 的行方向形成複數平行排列的罩幕圖案層114，例如光阻 層，以局部覆蓋每一深溝槽對l〇la及l〇ib。接著，進行 回蝕刻’以局部去除未被罩幕圖案層114所覆蓋的領型絕 緣層106。 接著，請參照第3C圖，在每一埋入式溝槽電容的上電 極112上形成一埋入帶層116，例如摻雜的複晶矽層。請 96-064/0492-A41265-TW/final 11 200947669 參照第3D圖，藉由習知微影及蝕刻技術，在深溝槽陣列 的列方向上兩相鄰的深溝槽對101a及l〇lb之間定義出主 動區’而在每一深溝槽對101a及l〇ib上方定義出淺溝槽 隔離（shallow trench isolation, STI)區。接著，在主動區 的基底上方形成一絕緣材料（未繪示），例如氧化；5夕，並 填入淺溝槽隔離區。之後，可藉由化學機械研磨（cheinical mechanicpolishing，CMP) ’去除多餘的絕緣材料及由氮化 矽層104與墊氧化矽層1〇2所構成的罩幕層，而在每一深 ❹溝槽對101 a及101b的上半部形成一隔離絕緣層Π8。 請參照第4A至4F圖，其繪示出根據本發明實施例之 字元線及位元線的製造剖面示意圖。如第4A圖所示，在 深溝槽陣列的列方向上每兩相鄰的深溝槽對1〇1&及1〇lb 之間的基底1〇〇内（即，主動區）形成與深溝槽1〇la/1〇lb 彼此隔離的一開口 120’以提供製作垂直電晶體結構之用。 如第4B圖所示，可藉由離子佈植製程，在開口 120 ❹底部的基底1〇〇内形成—隔離摻雜區121。可對基底1〇〇 實施-熱處理’使埋入帶層116因受熱而擴散至主動區的 基底100内，而在開口 120兩側的基底謂内且鄰近開口 12〇底部處形成與隔轉_ 121相鄰的擴散區。此處， 擴散區係作為垂直電晶體結構的汲極區122，其導電型 (即’ N/P型）不同於隔離摻雜區丨21的導電型。 如第4C圖所不’在每—開π —的側壁及底部形成一 間極介電層124 ’例如氣化石夕層。接著，在基底及隔 離絕緣層118上形成一導電層126,例如摻雜的複晶石夕層’ 96-064/0492-A41265-TW/fmal 12 200947669 並填入每一開口 120内。接著，在導電層126上依序形成 一導電層128及一絕緣層130。導電層128可由金屬或金 屬石夕化物所構成，而絕緣層13 0可由氧化石夕、氣化石夕、或 其組合所構成。 如第4D圖所示，藉由習知微影及蝕刻技術，圖案化絕 緣層130,以形成具有字元線圖案的複數上蓋層131。接 著，以上蓋層131作為蝕刻罩幕，依序蝕刻下方的導電層 128及導電層126，以形成閘極電極127及第二閘極電極 ❹ 129。此處，閘極電極127及第二閘極電極129係作為記憶 裝置的字元線。接著，以上蓋層131作為佈植罩幕來進行 源極離子佈植，以在開口 120兩側的基底100内且鄰近開 口 120頂部處形成源極區132，其導電型相同於，汲極區 122的導電型。 接著，如第4E圖所示，在每一字元線的側壁形成絕緣 間隙壁134。絕緣間隙壁134可由氧化矽或氮化矽所構成。 如此一來，便完成垂直電晶體結構的製作。之後，在間隙 壁134之間形成内層介電（interlayer dielectric, ILD)層 13 6，例如氧化石夕層。 接著，如第4F圖所示，在源極區132上方的内層介電 層136内形成二位元線導電插塞138a及138b，以與源極 區132電性連接。之後，在内層介電層136上，沿深溝槽 陣列的列方向形成平行排列且電性連接至位元線導電插塞 138a及138b的複數位元線140,如第5圖所示。如此一來， 便完成本實施例的記憶裝置製作。位元線140與導電插塞 96-064/0492-A41265-TW/fmal 13 200947669 138a及138b可由相同的材料所構成，例如鎢金屬，且可 藉由鑲嵌製程製作而成。另外，位元線140與導電插塞138a 及138b也可分別製作且可使用不同的金屬材料。須注意的 是導電插塞138a及138b分別電性連接至兩相鄰的位元線 140。因此，每一記憶單元由一垂直電晶體結構以及位於其 兩側的二埋入式溝槽電容。而每一記憶單元的埋入式溝槽 電容可藉由二位元線140寫入 根據本發明，每一記憶單元由一垂直電晶體結構以及 ® 位於其兩側的二埋入式溝槽電容。而每一記憶單元的埋入 式溝槽電容可藉由二位元線140儲存互補的資料信號來有 效降低漏電流對儲存資料的影響，進而增加資料保留時 間。再者，儲存的資料由深溝槽電容器對分，可有效縮短 寫入及讀取的時間，進而提高記憶體的速度並降低工作電 壓。另外，由於每一記憶單元中二埋入式溝槽電容係共用 一字元線，因此相較於傳統雙單元記憶裝置而言，本實施 ©例之記憶裝置可具有較小的裝置尺寸而改善記憶體積集 度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1A圖係繪示出根據本發明實施例之具有用於記憶 裝置的深溝槽陣列的基底平面示意圖； 96-064/0492-A41265-TW/final 14 200947669 第1B圖係繪示出沿第1A圖中l-Γ線的剖面示意圖； 第2Α至2C圖係繪示出根據本發明實施例之埋入式溝 槽電容的製造剖面示意圖； 第3Α圖係繪示出根據本發明實施例之定義埋入帶層 區的平面示意圖； 第3Β至3D圖係繪示出根據本發明實施例之埋入帶製 造及主動區定義的製造剖面示意圖； 第4Α至4F圖係繪示出根據本發明實施例之字元線及 ® 位元線的製造剖面示意圖；以及 第5圖係繪示出根據本發明實施例之具有雙重溝槽電 容的記憶裝置平面示意圖。 【主要元件符號說明】 100〜基底；l〇la、101b〜深溝槽；102〜墊氧化矽層； 104〜氮化矽層；106〜領型絕緣層；108〜埋入式下電極；110〜 電容介電層；112〜上電極；114〜罩幕圖案層；116〜埋入帶 ❹ 層；118〜隔離絕緣層；120〜開口； 121〜隔離摻雜區；122〜 汲極區；124〜閘極介電層；126、128〜導電層；130〜絕緣 層；127~閘極電極；129〜第二閘極電極；131〜上蓋層；132〜 源極區；134〜絕緣間隙壁；136〜内層介電層；138a、138b〜 位元線導電插塞；140〜位元線。 96-064/0492-A41265-TW/fmal 15Then, as shown in FIG. 2, a capacitor dielectric layer 110 is formed on the sidewall material portion of the lower half of the deep trench pair 101a and 101b, which is a nitrogen (tetra) layer, an oxide-nitride (ON) layer. A laminated structure or a laminated structure of an oxide-nitride-oxide. Next, as shown in FIG. 2C, a doped polysilicon layer (not shown) is filled in each deep trench pair i〇ia and i〇ib, and the doped polysilicon layer is etched back. The fabrication of the upper electrode 112 of the buried trench capacitor is completed to a predetermined depth. Referring to FIGS. 3A to 3D, FIG. 3A is a plan view showing the definition of a buried band in accordance with an embodiment of the present invention, and FIG. 3D is a view showing the manufacture of a buried tape according to an embodiment of the present invention. And a schematic diagram of the manufacturing profile defined by the active zone. As shown in FIGS. 3A and 3B, a plurality of parallel-arranged mask pattern layers 114, such as photoresist layers, are formed along the row direction of the array of deep desert trenches to partially cover each deep trench pair l〇la and l〇ib. . Next, etch back is performed to partially remove the collar-type insulating layer 106 which is not covered by the mask pattern layer 114. Next, referring to FIG. 3C, a buried strap layer 116, such as a doped polysilicon layer, is formed on the upper electrode 112 of each buried trench capacitor. Please refer to FIG. 3D for the two adjacent deep trench pairs 101a and 10b in the column direction of the deep trench array by conventional lithography and etching techniques, please refer to FIG. 3D. A shallow trench isolation (STI) region is defined over each of the deep trench pairs 101a and 10B. Next, an insulating material (not shown) is formed over the substrate of the active region, for example, oxidized; and the shallow trench isolation region is filled. Thereafter, the excess insulating material and the mask layer composed of the tantalum nitride layer 104 and the pad oxide layer 1〇2 may be removed by chemical mechanical polishing (CMP), and in each deep trench An isolation insulating layer 8 is formed on the upper portions of 101a and 101b. Referring to Figures 4A through 4F, there are shown schematic cross-sectional views of the fabrication of word lines and bit lines in accordance with an embodiment of the present invention. As shown in FIG. 4A, each of two adjacent deep trench pairs in the column direction of the deep trench array is formed in the substrate 1〇〇 (ie, the active region) between 1〇1& and 1〇lb and the deep trench 1开口la/1〇lb is an opening 120' that is isolated from each other to provide a vertical transistor structure. As shown in Fig. 4B, the doped region 121 can be formed in the substrate 1〇〇 at the bottom of the opening 120 by an ion implantation process. The substrate 1〇〇 can be subjected to a heat treatment to diffuse the buried belt layer 116 into the substrate 100 of the active region by heat, and is formed in the substrate on both sides of the opening 120 and adjacent to the bottom of the opening 12〇. 121 adjacent diffusion zones. Here, the diffusion region serves as the drain region 122 of the vertical transistor structure, and its conductivity type (i.e., 'N/P type) is different from that of the isolation doping region 丨21. As shown in Fig. 4C, a pole dielectric layer 124' such as a gasification layer is formed on the side walls and the bottom of each opening. Next, a conductive layer 126, such as a doped polytecrous layer '96-064/0492-A41265-TW/fmal 12 200947669, is formed over the substrate and isolation insulating layer 118 and filled into each opening 120. Next, a conductive layer 128 and an insulating layer 130 are sequentially formed on the conductive layer 126. The conductive layer 128 may be composed of a metal or a metal stellite, and the insulating layer 130 may be composed of oxidized stone, gas fossil, or a combination thereof. As shown in Fig. 4D, the insulating layer 130 is patterned by conventional lithography and etching techniques to form a plurality of cap layers 131 having a word line pattern. Then, the upper cap layer 131 serves as an etching mask, and sequentially etches the underlying conductive layer 128 and the conductive layer 126 to form the gate electrode 127 and the second gate electrode 129. Here, the gate electrode 127 and the second gate electrode 129 serve as word lines of the memory device. Next, the upper cap layer 131 is used as an implantation mask to perform source ion implantation to form a source region 132 in the substrate 100 on both sides of the opening 120 and adjacent to the top of the opening 120, and the conductivity type is the same as that of the bungee region. Conductive type of 122. Next, as shown in Fig. 4E, insulating spacers 134 are formed on the sidewalls of each of the word lines. The insulating spacer 134 may be composed of tantalum oxide or tantalum nitride. In this way, the fabrication of the vertical transistor structure is completed. Thereafter, an interlayer dielectric (ILD) layer 13, such as an oxidized layer, is formed between the spacers 134. Next, as shown in FIG. 4F, two bit line conductive plugs 138a and 138b are formed in the inner dielectric layer 136 above the source region 132 to be electrically connected to the source region 132. Thereafter, on the inner dielectric layer 136, a plurality of bit lines 140 arranged in parallel and electrically connected to the bit line conductive plugs 138a and 138b are formed along the column direction of the deep trench array, as shown in FIG. In this way, the memory device fabrication of the embodiment is completed. The bit line 140 and the conductive plug 96-064/0492-A41265-TW/fmal 13 200947669 138a and 138b may be composed of the same material, such as tungsten metal, and may be fabricated by a damascene process. In addition, the bit line 140 and the conductive plugs 138a and 138b can also be fabricated separately and different metal materials can be used. It should be noted that the conductive plugs 138a and 138b are electrically connected to two adjacent bit lines 140, respectively. Therefore, each memory cell consists of a vertical transistor structure and two buried trench capacitors on either side of it. The buried trench capacitor of each memory cell can be written by the two bit line 140 according to the invention, each memory cell consisting of a vertical transistor structure and two buried trench capacitors on both sides thereof. . The buried trench capacitor of each memory cell can store the complementary data signal by the two bit line 140 to effectively reduce the influence of the leakage current on the stored data, thereby increasing the data retention time. Furthermore, the stored data is divided by deep trench capacitors, which can shorten the writing and reading time, thereby increasing the speed of the memory and reducing the operating voltage. In addition, since the two buried trench capacitors share a word line in each memory cell, the memory device of the present embodiment can be improved with a smaller device size than the conventional dual cell memory device. Memory volume set. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic plan view of a substrate having a deep trench array for a memory device according to an embodiment of the present invention; 96-064/0492-A41265-TW/final 14 200947669 1B FIG. 2A to 2C are schematic cross-sectional views showing the manufacturing of the buried trench capacitor according to the embodiment of the present invention; FIG. 3 is a schematic diagram showing The schematic diagram of the embodiment of the present invention is a schematic plan view of the buried layer zone; the third to third 3D drawings illustrate the manufacturing section of the buried tape manufacturing and the active zone definition according to the embodiment of the present invention; the fourth to fourth 4F drawings A schematic cross-sectional view of a word line and a bit line in accordance with an embodiment of the present invention is shown; and FIG. 5 is a plan view of a memory device having a dual trench capacitor in accordance with an embodiment of the present invention. [Main component symbol description] 100~substrate; l〇la, 101b~deep trench; 102~pad oxide layer; 104~ tantalum nitride layer; 106~ collar type insulating layer; 108~buried lower electrode; 110~ Capacitor dielectric layer; 112~ upper electrode; 114~ mask pattern layer; 116~ buried layer ❹ layer; 118~ isolation insulating layer; 120~ opening; 121~ isolation doped region; 122~ bungee region; Gate dielectric layer; 126, 128~ conductive layer; 130~ insulating layer; 127~ gate electrode; 129~ second gate electrode; 131~ upper cap layer; 132~ source region; 134~ insulating spacer; ~ inner dielectric layer; 138a, 138b ~ bit line conductive plug; 140 ~ bit line. 96-064/0492-A41265-TW/fmal 15