TW200945468A - Semiconductor device test system, test handler, test head, interface block of semiconductor device tester, method for sorting tested semiconductor devices, and method to support semiconductor device test - Google Patents
Semiconductor device test system, test handler, test head, interface block of semiconductor device tester, method for sorting tested semiconductor devices, and method to support semiconductor device test Download PDFInfo
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200945468 六、發明說明： 【發明所屬之技術領域】 本發明涉及一半導體裝置測試系統和—測試處理器， 一 尤相關於使用一測試板之半導體裝置測試技術，其中該測 試板係安裝到執行半導體裝置之測試之一測試頭的一界面 區塊。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test system and a test processor, and more particularly to a semiconductor device test technique using a test board, wherein the test board is mounted to an execution semiconductor One of the interface blocks of the test head of the test of the device.
❹ 【先前技術】 一狱而$，一半導體裝置測試系統包括··一測試控制 設備、一測試頭、-測試處理器和—賴頭支樓設備。根 據測試控制裝置的控制’測試頭測試半導體裝置。測試處 理器將多個半導體裝置提供給測試頭，使它們能夠電子接 觸測試頭和進行測試。該測試頭支撐設備支撺該測試頭，. 以使該測試頭可以穩定地連接到 支撐設備在本發明的技術領域中 該測試處理器。該測試頭 也被稱為•控制器，。 圓1是一個平面圖，說明 頭200相互連接的情況，以及 面的說明中，詳細解釋測試處 其中的連接。 一測試處理器100和一測試 圖2是圖1的側視圖。在下 理器器100和測試頭2〇〇及 如圖 一測試室 1所示，測試處理器器100 120、和一卸裁設備13〇。 包括一裝載裝置 110、 裝卸設備110用 於裝載位於裝載站LP之半導體裝置至 3 200945468 承載板CB。 測試室120從裝載站Lp接收到裝有半導體裝置之承載 板CB，並允許對裝載在承載板CB的半導體裝置進行電子 測試。 卸載設備1 3 0根據等級排列受測試的半導體裝置，並 •在卸載站LP將它們從承載板卸載下來，在卸載站Lp中， 承載受測試的半導體裝置之承載板係是由承載板被承載至 © 裝載站UP。 習知的測試處理器i 00已經被揭示於韓國專利第 i〇-〇7〇9m號，發明名稱為「測試處理器」，所以本案將省 略它的詳細說明。 如圖1和圖2所示’測試頭2〇〇包括一界面區塊21〇 和頭主體220界面區塊21〇在本發明的技術領域中也 被稱為也被稱為'HiFixboard '或，界面板I。 界面區塊210包括複數測試插座211，其分別與由測 試處理器HM)提供的複數半導體裝置電器接觸。如圖” 圖2所示’如果測試處理器⑽和測試頭2⑽彼此連接， 部分界面區塊被插人和放在測試處理器⑽的測試室12〇 的裡面。 頭主體220藉由下述方式測試半導體裝置：根據一測 試控制設備的控制（未圖示），藉由界面區塊2iq之測試插 座211’料導體裝置施加一電子信號，然後藉由界面區 4 200945468 塊210從半導體裝置讀出電子信號。 如圖1所示，承載板⑶沿著虛線C的-循環路徑移 動。如圖2所示，測試頭係由—支揮設備从所支撐。 近年來，隨著半導體裝置的需求不斷增加，測試處理 器在性能上已得到改進’使得一次能夠測試更多的半導體 裝置’或一次提供更多料導體裝置給測試頭。 因此，如果測試處理器打算-次提供更多半導體裝置 ㈣Μ ’測試頭也應提高其容量和性能’以測試相同數 目的半導體裝置’以達成對測試處理器的加強。 然而，難以提高測試主體的容量和性能。因此，測試 主體在能力和性能上不匹配測試處理器。此外為了提高 頭主體的能力和表現，需要花費大量的開發成本。 ❹ 雄然測試頭的能力可藉由下列方式增加··分支為施加 電子信號至半導體裝置的通道，然而測試頭仍未能達成與 這種能力的增加相對應的表現。因此，必須增加測試期間。 另一方面，即使在測試頭的能力和表現可以得到改 善，整個測試頭都該換新，這樣浪費了資源和產生了巨大 的更換費用。 為了解決這些問題，最近有人建構一種可以從半導體 裝置讀出電子信號的技術，其不藉由頭主體，而是藉由一 可更換界面區塊來處理，從而使界面區塊能發揮與測試處 理器相對應的性能。在這種情況下，半導體裝置測試系統 5 200945468 可以提高其測試性能，而不用提高頭主體的性能。 根據上述建構的技術，界面區塊應配備一測試晶片， 其可從半導體裝置讀出和處理電子信號。 然而’如圖1所示’部分界面模塊應被插入和放置在 1^1 測試室。因此’界面區塊的測試晶片會受到測試室溫度的 - 影響。 如果半導體裝置在高溫下進行測試，測試室的内部溫 © 度往往接近15〇eC。在這種情況下，測試室的熱狀態影響 測試晶片，因此’測試晶片可能過熱。 一般來說，測試晶片正常操作於60。C以下。如果一測 試晶片的工作溫度超過6〇°C時，它可能導致故障。因此， 不能在高溫下進行半導體裝置的可靠性測試。 【發明内容】 ® 本發明解決了上述問題，並提供了 一技術，其可以消 除從一半導體裝置測試系統的一界面區塊產生的熱量，其 中該半導體裝置測試系統擴大其測試功能至界面區塊。 本發明進一步提供能夠使用冷卻器冷卻空氣之一技 • 術。 . 本發明還提供一技術，其可以平均地分別冷卻安裝在 一界面區塊的測試晶片。 依據本發明之一示例性實施例，本發明提供了 一種半 6 200945468 導體裝置測試系統，包括：一測試頭，其用於依據一測試 控制設備，測試半導體裝置；一測試處理器，其搞接該測 試頭，用以提供該半導體裝置給該測試頭，以使它們能夠 與該測試頭電子連接，並進行測試；—設備，用以支撐該 測試頭，以使該測試頭可以穩定地連接到該測試處理器； 及一溫度控制設備，用以控制該測試頭的溫度， 該測試頭包括一界面區塊和一頭主體。該界面區塊包 ® 括·複數測試插座，其分別與由該測試處理器提供之該半 導體裝置電子接觸；及一測試板，其用以藉由從該界面板 讀出電子信號來執行該半導體裝置的一測試.該頭主體輸 出該半導體裝置測試所需要的一控制信號給該測試板。及 該溫度控制設備移除在該測試板中產生的熱量。 較佳地’該界面區塊更包括一頭連接板，用以電子連 接該測試板與該頭主體。該溫度控制設備在該測試板和該 頭連接電路板間供應溫度控制氣體。 較佳地，該溫度控制設備包括：一空氣供應設備，用 以在該測試板和該頭連接電路板之間供應空氣；及一空氣 抽吸Ιχ備’用以抽吸在該測試板和該頭連接電路板間的空 氣，及將它排出到外面。 較佳地，該空氣供應設備包括一冷卻器。該冷卻器冷 卻空氣，該冷卻空氣被一空氣壓縮機壓縮到大於大氣壓力 的高壓，並提供到該測試板和該頭連接板。 7 200945468 較佳地被供給到該測試板和該頭連接板間的空氣有 一壓力’其可以接觸到被包含在該測試板的所有測試晶 片，然後被排放到外面。 較佳地，該溫度控制設備被安裝到下列之任何一者： ” 該測試處理器、測試頭、及測試頭支撐設備。 • 依據本發明之另一示例性實施例，本發明提供了一種 測試頭，用以測試半導體裝置，包括：一界面區塊，用以 © 測試該半導體裝置，該界面區塊有複數測試插槽，其分別 電子接觸由一測試處理器提供的該半導體裝置；及一頭主 體，用以輸出半導體裝置測試所需之一控制信號。 該界面區塊包括：該界面區塊包括：一界面板，其具 有複數測試插座；一測試板，用以藉由從該界面讀出電子 信號，執行該半導體裝置的一測試；一封閉板，其相對於 該測試板，配置在該界面板的對面；及一封閉框架，用以 ® 在該測試板和該封閉板間形成一封閉空間；該控制信號從 該頭主體被傳送到該測試板；及該封閉板或該關閉框架 具有至少一或多流入孔，其使空氣將在該測試板產生的熱 篁移除流入該封閉空間’及至少一或多排出孔，其使該空 氣自該封閉空間排出。 較佳地’該界面區塊排列在該封閉空間，及該界面區 塊更包括：-導管，用以喷射空氣，使其流入在該測試板 上的該至少一或多流入孔。 200945468 較佳地，該封閉框架係一頭連接板，用以電子連接該 測式板至該頭主體。 較佳地，該至少一或多排出孔係形成於該封閉板。該 界面區塊更包括一外殼。該外殼形成一流出空間，該流出 空間相對於該封閉板在該封閉空間對面。該外殼具有流出 • 孔’其允許空氣從該流出空間流出。 較佳地，該至少一或多流入孔係形成在該封閉板。 © 依據本發明之另一示例性實施例，本發明提供了一種 測試器之一種界面區塊，其用於測試半導體裝置，包括： 一界面板，其具有複數測試插槽，其分別與從一測試處理 器提供的該半導體裝置電子連接；一測試板，其具有至少 一或多測試晶片，用以藉由從該界面板讀出電子信號來執 行該半導體裝置的一測試，及用以偵測該測試晶片本身的 溫度；一封閉板，其相對於該測試板，配置在該界面板的 ® 對面，及一封閉框架，用以在該測試板和該封閉板間形成 一封閉空間。該測試晶片係暴露在該封閉空間中。 較佳地，界面區塊更包括一溫度感應器，用以偵測在 該封閉空間中的溫度。 依據本發明之另一示例性實施例，本發明提供了一種 . 測試器之一種界面區塊，其用於測試半導體裝置，包括： 一界面板，其具有複數測試插槽，其分別與從一測試處理 器提供的該半導體裝置電子連接；一測試板，其具有至少 9 200945468 一或多測試晶片，用以藉由從該界面板讀出電子信號，以 執行該半導體裝置的一測試；一封閉板，其相對於該測試 板，配置在該界面板的對面；一封閉框架’用以在該測試 板和該封閉板間形成一封閉空間；及一溫度感應器，用以 偵測在該封閉空間中的溫度。該測試晶片係暴露在該封閉 • 空間中。 依據本發明之另一示例性實施例，本發明提供了一種 ® 用於分類受測試的半導體裝置的方法，包括：在一測試頭 的一界面區塊偵測一測試晶片的溫度，以讀出並處理在一 測試點測試的該半導體裝置的電子信號；確定是否該偵測 溫度係位在一所需的溫度範圍内；如果該偵測溫度是在該 所需的溫度範圍内，則根據一第一分類方式，依據測試結 果’刀類在該所需的溫度範圍内測試的至少一或多半導體 裝置，及如果該偵測溫度偏離該所需的溫度範圍，則根據 ® 相異於該第一分類方式之一第二分類方式，分類在偏離該 所需的溫度範圍的一溫度中所測試的至少一或多半導體裝 置。 較佳地，該第二分類方式係將在偏離該所需的溫度範 園的一溫度測試的至少一或多半導體裝置分類為一再測試 ' 批次。 依據本發明之另一示例性實施例，本發明提供了一種 用於分類受測試的半導體裝置的方法，包括：在一測試頭 200945468 的一界面區塊偵測複數測試晶片的個別溫度，以讀出並處 理在一測試點測試的該半導體裝置的電子信號；碟定是否 該個別的偵測溫度係位在一所需的溫度範圍内；如果該測 試晶片之每一者的該個別的偵測溫度是在一所需的溫度範 圍内，則根據一第一分類方式，依據測試結果，分類在該 所需的溫度範圍内測試的至少一或多半導體裝置；及如果 該測試晶片之每一者的該個別的偵測溫度偏離該所需的温 © 度範圍，則根據相異於該第一分類方式之一第二分類方 式’分類在偏離該所需的溫度範圍的一溫度中所測試的至 少一或多半導體裝置。 依據本發明之另一示例性實施例，本發明提供了一種 用於支援半導體裝置之測試的方法，包括下列步驟：偵測 在一封閉空間中的溫度，在該密閉空間中，安襞在一測試❹ [Prior Art] A prison device, a semiconductor device test system includes a test control device, a test head, a test processor, and a Laitou branch device. The semiconductor device is tested according to the control 'test head' of the test control device. The test processor provides multiple semiconductor devices to the test heads to enable them to electronically contact the test head and perform tests. The test head supporting device supports the test head so that the test head can be stably connected to the supporting device in the technical field of the present invention. This test head is also called a controller. The circle 1 is a plan view showing the case where the heads 200 are connected to each other, and the description of the faces explains the connections in the test place in detail. A test processor 100 and a test Fig. 2 is a side view of Fig. 1. In the processor 100 and the test head 2, and as shown in the test room 1 of Fig. 1, the processor 100 120 and a unloading device 13 are tested. A loading device 110 is included, and a handling device 110 is used to load the semiconductor device at the loading station LP to 3 200945468 carrier CB. The test chamber 120 receives the carrier board CB containing the semiconductor device from the loading station Lp and allows electronic testing of the semiconductor device mounted on the carrier board CB. The unloading device 130 sorts the semiconductor devices under test according to the rank, and • unloads them from the carrier plate at the unloading station LP, in which the carrier board carrying the semiconductor device under test is carried by the carrier board To © loading station UP. The conventional test processor i 00 has been disclosed in Korean Patent No. i〇-〇7〇9m, and the invention name is "test processor", so the detailed description thereof will be omitted in this case. As shown in FIGS. 1 and 2, the 'test head 2' includes an interface block 21A and the head body 220 interface block 21, also referred to as 'HiFixboard' or in the technical field of the present invention. Interface board I. Interface block 210 includes a plurality of test sockets 211 that are in contact with a plurality of semiconductor device appliances provided by test processor HM), respectively. As shown in Fig. 2, if the test processor (10) and the test head 2 (10) are connected to each other, part of the interface block is inserted and placed inside the test chamber 12A of the test processor (10). The head body 220 is by the following means Testing the semiconductor device: according to the control (not shown) of a test control device, an electronic signal is applied through the test socket 211' material conductor device of the interface block 2iq, and then read out from the semiconductor device through the interface region 4 200945468 block 210 Electronic signal. As shown in Fig. 1, the carrier board (3) moves along the -circulation path of the broken line C. As shown in Fig. 2, the test head is supported by the support device. In recent years, with the demand for semiconductor devices In addition, the test processor has been improved in performance 'making it possible to test more semiconductor devices at a time' or to provide more material conductor devices to the test head at one time. Therefore, if the test processor intends to provide more semiconductor devices (four) Μ ' The test head should also increase its capacity and performance 'to test the same number of semiconductor devices' to achieve enhancements to the test processor. However, it is difficult to improve the test The capacity and performance of the main body. Therefore, the test subject does not match the test processor in terms of capability and performance. In addition, in order to improve the capability and performance of the head main body, it takes a lot of development cost. ❹ The ability to test the head can be obtained by the following methods The addition is a channel for applying an electronic signal to the semiconductor device, but the test head still fails to achieve the performance corresponding to the increase in this capability. Therefore, the test period must be increased. On the other hand, even in the ability of the test head and Performance can be improved, the entire test head should be replaced, which wastes resources and generates huge replacement costs. In order to solve these problems, a technique for reading electronic signals from semiconductor devices has recently been constructed, which does not rely on the head. The main body is processed by a replaceable interface block so that the interface block can perform the performance corresponding to the test processor. In this case, the semiconductor device test system 5 200945468 can improve its test performance, and There is no need to improve the performance of the head body. According to the above constructed technology, the interface block should be equipped A test wafer is prepared which can read and process electronic signals from the semiconductor device. However, the 'partial interface module' should be inserted and placed in the 1^1 test chamber as shown in Fig. 1. Therefore, the test wafer of the interface block is subject to Test chamber temperature - effect. If the semiconductor device is tested at high temperatures, the internal temperature of the test chamber is often close to 15 〇eC. In this case, the thermal state of the test chamber affects the test wafer, so the test wafer may overheat Generally, the test wafer is normally operated below 60 ° C. If the operating temperature of a test wafer exceeds 6 ° C, it may cause a malfunction. Therefore, the reliability test of the semiconductor device cannot be performed at a high temperature. The present invention addresses the above problems and provides a technique that eliminates heat generated from an interface block of a semiconductor device test system that expands its test function to the interface block. The invention further provides a technique that is capable of cooling air using a chiller. The present invention also provides a technique for equally cooling the test wafers mounted on an interface block, respectively. According to an exemplary embodiment of the present invention, the present invention provides a half 6 200945468 conductor device test system, comprising: a test head for testing a semiconductor device according to a test control device; and a test processor The test head is configured to provide the semiconductor device to the test head so that they can be electrically connected to the test head and tested; and the device supports the test head so that the test head can be stably connected to The test processor; and a temperature control device for controlling the temperature of the test head, the test head comprising an interface block and a body. The interface block includes: a plurality of test sockets respectively in electrical contact with the semiconductor device provided by the test processor; and a test board for performing the semiconductor by reading an electronic signal from the interface board A test of the device. The head body outputs a control signal required for testing the semiconductor device to the test board. And the temperature control device removes heat generated in the test board. Preferably, the interface block further includes a connecting plate for electronically connecting the test board to the head body. The temperature control device supplies a temperature control gas between the test board and the head connection board. Preferably, the temperature control device comprises: an air supply device for supplying air between the test board and the head connection circuit board; and an air suction device for sucking on the test board and the The head connects the air between the boards and discharges it to the outside. Preferably, the air supply device comprises a cooler. The cooler cools the air, which is compressed by an air compressor to a high pressure greater than atmospheric pressure and supplied to the test board and the head connection plate. 7 200945468 Preferably, the air supplied between the test board and the head connection plate has a pressure 'which can contact all of the test wafers contained in the test board and then be discharged to the outside. Preferably, the temperature control device is mounted to any one of: "" the test processor, the test head, and the test head support device. • According to another exemplary embodiment of the present invention, the present invention provides a test a head for testing a semiconductor device, comprising: an interface block for testing the semiconductor device, the interface block having a plurality of test sockets respectively electrically contacting the semiconductor device provided by a test processor; and a head The main body is configured to output a control signal required for testing the semiconductor device. The interface block includes: the interface block includes: an interface board having a plurality of test sockets; and a test board for reading from the interface An electronic signal, performing a test of the semiconductor device; a closing plate disposed opposite the interface plate relative to the test plate; and a closed frame for forming a closure between the test plate and the closing plate Space; the control signal is transmitted from the head body to the test panel; and the closure panel or the closure frame has at least one or more inflow apertures that are empty Removing the heat generated in the test plate into the enclosed space' and at least one or more exhaust holes that discharge the air from the enclosed space. Preferably, the interface block is arranged in the closed space, and the The interface block further includes: a conduit for injecting air into the at least one or more inflow holes on the test board. 200945468 Preferably, the closed frame is a connecting plate for electronically connecting the test. Preferably, the at least one or more discharge holes are formed in the closing plate. The interface block further comprises an outer casing. The outer casing forms a first-class space, and the outflow space is opposite to the closing plate. The enclosed space is opposite. The outer casing has an outflow hole that allows air to flow out of the outflow space. Preferably, the at least one or more inflow holes are formed in the closing plate. © According to another exemplary embodiment of the present invention The present invention provides an interface block for testing a semiconductor device, comprising: an interface board having a plurality of test slots respectively associated with a test processor Providing the semiconductor device with an electronic connection; a test board having at least one or more test wafers for performing a test of the semiconductor device by reading an electronic signal from the interface plate, and for detecting the test chip a temperature of its own; a closed plate disposed opposite the test plate, opposite to the test plate, and a closed frame for forming a closed space between the test plate and the closed plate. The test wafer is exposed Preferably, the interface block further includes a temperature sensor for detecting the temperature in the enclosed space. According to another exemplary embodiment of the present invention, the present invention provides a test. An interface block for testing a semiconductor device, comprising: an interface board having a plurality of test sockets respectively electrically connected to the semiconductor device provided from a test processor; a test board having at least 9 200945468 one or more test wafers for performing a test of the semiconductor device by reading an electronic signal from the interface board; a closed plate, the opposite The test plate is disposed opposite the interface plate; a closure frame "is used between the test plate and the closing plate is formed a closed space; and a temperature sensor for detecting the temperature of the enclosed space. The test wafer is exposed to the enclosed space. In accordance with another exemplary embodiment of the present invention, the present invention provides a method for classifying a semiconductor device under test, comprising: detecting a temperature of a test wafer at an interface block of a test head to read And processing the electronic signal of the semiconductor device tested at a test point; determining whether the detected temperature is within a desired temperature range; if the detected temperature is within the desired temperature range, according to The first classification method according to the test result 'at least one or more semiconductor devices tested by the knife in the required temperature range, and if the detected temperature deviates from the required temperature range, One of the classification methods, the second classification method, classifies at least one or more semiconductor devices tested in a temperature that deviates from the desired temperature range. Preferably, the second classification mode classifies at least one or more semiconductor devices tested at a temperature deviation from the desired temperature range into a retest 'batch. In accordance with another exemplary embodiment of the present invention, a method for classifying a semiconductor device under test includes: detecting an individual temperature of a plurality of test wafers at an interface block of a test head 200945468 to read And processing an electronic signal of the semiconductor device tested at a test point; determining whether the individual detected temperature is within a desired temperature range; if the individual detection of each of the test chips The temperature is within a desired temperature range, and according to a first classification method, classifying at least one or more semiconductor devices tested within the required temperature range according to the test result; and if each of the test wafers The individual detected temperature deviates from the required temperature range, and is classified according to a second classification method different from the first classification method, in a temperature deviating from the required temperature range. At least one or more semiconductor devices. According to another exemplary embodiment of the present invention, there is provided a method for supporting testing of a semiconductor device, comprising the steps of: detecting a temperature in an enclosed space in which an ampoule is mounted in a closed space test
頭的一界面區塊的一測試晶片被曝露；確定是否該偵測溫 度係位在一所需的溫度範圍内；如果該偵測到的溫度係在 該所需的溫度範圍内’則以一正常狀態操作一 半導體裝置 測試系統；及如果該偵測到的溫度偏離該所需的溫度範 圍，則以一緊急狀態操作該半導體裝置測試系统❶ ^L·. 一 作為 種自 較佳地，以一緊急狀態操作該半導體裴置蜊試系統係 測試處理器上是產生一聲音警報或顯示一 H覺信號。 該半導體裝置測試系統之一元件的該測試 〇〇 Λζ. 動化設備’其支援該半導體裝置的測試。 11 200945468 較佳地，在以-緊急狀態操作該半導體裝置測試系統 之步驟中，作為該半導體裝置測試系統之-元件的該剛試 處理器是一種自動化兮杂傲 甘 °備，、支挺該半導體裝置的測試、 將在偏離該所需的溫度範圍的—溫度測試的至少一或多丰 導體裝置分類為-再測試批次。作為該半導體裝置測試系 統之-元件㈣測試處理器是—種自動化設備，其支援該 半導體裝置的測試。 人 較佳地，在-緊急狀態操作該半導體裝置測試系統更 包括：控制一溫度控制設備，以將該封閉空間的溫度保持 在該所需的溫度範圍内。該溫度控制設備係該半導體 測試系統之一元件。 【實施方式】 下文中將參照附圖，詳述本發明之示例性實施例。在 所有圖式中’相同的元件符號代表相同或相似部分。可能 省略本文中引用之習知函式和結構之詳細說明，以避免模 糊本發明之重點。 <測試頭之界面區塊> 如圖3所示，應用至一半導體裝置測試系统之一界面 區塊310包括一界面板311、一測試板312、和一頭連接板 313。 12 200945468 該界面板311係部署為一電路板311a，其側邊有複數 測試插座3 1 lb，其係電子接觸由測試處理器提供之複數半 導體裝置’及該電路板311a之對面側有界面板端連接器 3 11 c，其係電子連接到測試板3 12。 • 測試電路板3 1 2係以一電路板3 1 2a部署，該電路板 • 3 12a的一侧有第一測試板端連揍器3 12b，其係電子連接到 界面板端連接器3 11 c ’及該電路板3 1 2a對面側有第二測試 ® 板端連接器312d’其係電子連接到頭連接板.313，及一測 試晶片312c藉由通過界面板311從半導體裝置讀出電子信 號’來測試半導體裝置。應當明白，測試板3 12可被佈署 為包含複數測試晶片。 頭連接板313係以一電路板313a部署，該電路板3Ua 之一側有一頭連接板端連接器3 13b，其電子連接到第二測 試板端連接器31 2d，及該電路板313a之對面通過連接電 境CC電子連接至頭主體。 圖4是圖3之界面區塊31〇之組裝視圖；界面區塊31〇 可更包括一封閉框架3 14，以在組裝時，在測試板3 12和 • 頭連接板313間形成-封閉板S。另夕卜，頭連接板312和 封閉框架3 14用來在界面板3丨丨和測試板3 12之間形成另 一封閉空間。從這個觀點看來，頭連接板313也可以被界 定為-封閉板。這個封閉框架314有一空氣流入孔3Ma， 其允許空氣流人封閉空間8和—空氣流出孔3Ub，其允許 13 200945468 空氣流出，從而消除從測試板312特別是測試晶片312c產 生的熱量。 圖5之拆解視圖繪示作為圖3界面區塊310之一應用 實例之一界面區塊510，及圖6是圖5之界面區塊510之 ‘组裝視圖； 如圖5和圖6所示，該界面區塊包括510包括一界面 板511、一測試板512、和GFG連接器515。GFG連接器 © 515之每一者在兩側具有接觸導線T，其電子連接到界面板 511和測試板512。界面板511和測試板512藉由耦合元件 (例如，螺栓5 16)互相耦合。界面區塊5 1 0係配置如上述， 因為在界面板5 11和測試板5 12間的空間可被最小化，從 而使界面區塊5 1 0之全部長度減少。 <半導體裝置測試系統> ® 根據本發明之半導體裝置測試系統包括界面區塊310 或510。因為在界面區塊31〇或510之測試板312或512 上’電子信號被熱電阻產生的熱所扭曲’所以測得的可能 不是半導體裝置，。 -4 為了解決這問題，如圖7所示’半導體裝置測試系統 還包括一溫度控制設備7〇〇。 溫度控制設備700包括一外殼710、一風扇720、一風 扇驅動設備730、一氣體供應設備74〇、一空氣供應線750、 14 200945468 及一空氣流入線760。 風扇外殼710在其一側形成一空氣排出孔711，以及 在另一側形成一空氣流入孔7 12。 風扇720是放在風扇外殼710中。它通過空氣流入孔 712吸收空氣，及通過空氣排出孔711排放》 風扇驅動設備730驅動風扇720。在本發明之實施例 中，風扇驅動裝置730是以一馬達部署。 〇A test wafer of an interface block of the head is exposed; determining whether the detected temperature is within a desired temperature range; if the detected temperature is within the desired temperature range, then Operating the semiconductor device test system in a normal state; and operating the semiconductor device test system in an emergency state if the detected temperature deviates from the desired temperature range 一L. An emergency state operation of the semiconductor system is to generate an audible alarm or display an H-signal on the test processor. The test of one of the components of the semiconductor device test system, the device, supports the test of the semiconductor device. 11 200945468 Preferably, in the step of operating the semiconductor device test system in an emergency state, the test processor as an element of the semiconductor device test system is an automated noisy, and the support is The testing of the semiconductor device classifies at least one or more conductor devices that are temperature tested from the desired temperature range as - retest the batch. As the semiconductor device test system - the component (four) test processor is an automation device that supports the test of the semiconductor device. Preferably, operating the semiconductor device test system in an emergency state further comprises: controlling a temperature control device to maintain the temperature of the enclosed space within the desired temperature range. The temperature control device is an element of the semiconductor test system. [Embodiment] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same element symbols in the drawings represent the same or similar parts. Detailed descriptions of the conventional functions and structures referred to herein may be omitted to avoid obscuring the focus of the present invention. <Interface Block of Test Head> As shown in FIG. 3, an interface block 310 applied to a semiconductor device test system includes an interface board 311, a test board 312, and a header board 313. 12 200945468 The interface board 311 is deployed as a circuit board 311a having a plurality of test sockets 31 1 lb on the side thereof, which are in electronic contact with a plurality of semiconductor devices provided by the test processor and an interface board on the opposite side of the circuit board 311a. The end connector 3 11 c is electronically connected to the test board 3 12 . • The test board 3 1 2 is deployed in a circuit board 3 1 2a having a first test board end porter 3 12b on one side of the board 12 3a that is electronically connected to the interface board end connector 3 11 And a second test® board end connector 312d' on the opposite side of the circuit board 3 1 2a is electrically connected to the head connection board .313, and a test chip 312c reads the electrons from the semiconductor device through the interface board 311. The signal 'to test the semiconductor device. It should be understood that the test board 3 12 can be deployed to include a plurality of test wafers. The head connecting plate 313 is disposed on a circuit board 313a, and one side of the circuit board 3Ua has a connecting board end connector 3 13b electrically connected to the second test board end connector 31 2d and opposite to the circuit board 313a. Electronically connected to the head body by connecting the electrical CC. 4 is an assembled view of the interface block 31A of FIG. 3; the interface block 31 can further include a closed frame 314 to form a -closed plate between the test board 3 12 and the head connecting plate 313 during assembly. S. In addition, the head connecting plate 312 and the closing frame 314 are used to form another closed space between the interface plate 3A and the test plate 312. From this point of view, the head connecting plate 313 can also be defined as a - closed plate. This closed frame 314 has an air inflow hole 3Ma which allows air to flow into the space 8 and the air outflow hole 3Ub, which allows 13 200945468 air to flow out, thereby eliminating heat generated from the test board 312, particularly the test wafer 312c. The disassembled view of FIG. 5 illustrates an interface block 510 as one of the application examples of the interface block 310 of FIG. 3, and FIG. 6 is an 'assembled view of the interface block 510 of FIG. 5; FIG. 5 and FIG. The interface block includes 510 including an interface board 511, a test board 512, and a GFG connector 515. Each of the GFG connectors © 515 has a contact wire T on both sides that is electronically coupled to the interface plate 511 and the test board 512. The interface board 511 and the test board 512 are coupled to each other by a coupling element (e.g., bolts 5 16). The interface block 5 10 configuration is as described above because the space between the interface board 5 11 and the test board 5 12 can be minimized, thereby reducing the overall length of the interface block 5 10 . <Semiconductor Device Test System> The semiconductor device test system according to the present invention includes an interface block 310 or 510. Since the 'electronic signal is distorted by the heat generated by the thermal resistance' on the test board 312 or 512 of the interface block 31 or 510, it may not be a semiconductor device. -4 In order to solve this problem, the semiconductor device test system shown in Fig. 7 further includes a temperature control device 7A. The temperature control device 700 includes a housing 710, a fan 720, a fan drive device 730, a gas supply device 74, an air supply line 750, 14 200945468, and an air inflow line 760. The fan casing 710 has an air discharge hole 711 formed on one side thereof and an air inflow hole 712 on the other side. Fan 720 is placed in fan housing 710. It absorbs air through the air inflow hole 712 and discharges through the air discharge hole 711. The fan driving device 730 drives the fan 720. In an embodiment of the invention, fan drive 730 is deployed as a motor. 〇
氣體供應設備740在低溫下供應氣體至風扇外殼71〇 的内側，以有效地消除產生的熱量。 空中供應線750連接空氣排出孔711至封閉框架314 的流入孔314a’從而將通過空氣排出孔7U從風扇外殼71〇 排放的空氣引入至界面區塊310的封閉空間s。 空氣供應線760連接封閉框架314的排出孔31朴至風 扇外殼71〇之空氣流入孔712 ’從而允許通過排出孔31朴 從封閉空間S排放空氣至空氣流入孔712的風扇外殼71〇。 因此，在測試半導體裝置期間，藉由循環空氣，採用 溫度控制設備的半導體裝置” ^亦允許在測試板 312上累積產生的熱量。也就是說，測試系統可以繼續消 除其中產生的熱量。 3 12維持在室溫下，也可以避 真如圖7所示，溫度控制 ^而，如圖8所示，也可以實 另一方面，如果測試板 免起因於熱量之電子特性的 設備700被用來循環空氣。 15 200945468 以這種方式通過 施溫度控制設備7 0 0為不循環空氣類型， 風扇外殼810的空氣流入孔812來抽吸外部空氣通，以及 通過封閉框架814的排出孔814b ’從封閉空間§排放空氣 到外部。因此’如圖8示，可以部署溫度控制設備，而無 需如圖7所示之氣體供應設備74〇和空氣流入線76〇。 ❹ 較佳地，溫度控制設備700被安裝至測試處理器9〇〇， 如圖9所示。較佳地，溫度控制設備7〇〇被安裝至測試頭 1000(如圖10所示），或被安裝至支撐設備11〇〇(如圖u所 示）。然而，由於界面區塊310係部分插入並置於測試處理 器之測試室中，將溫度控制設備7〇〇安裝至測試處理器是 最好的。 <應用1> 如圖4所示，在封閉框架314形成流入孔3l4a和排出 © 孔314b，以此方式部署半導體裝置測試系統，在應用i中， 如圖12所示，在頭連接板1213形成流入孔121乜和排出 孔1214b，亦可以此方式部署半導體裝置測試系統，應當 明白’流入孔1214a和排出孔1214b之一者係形成在封閉 ' 框架1214，而另一則是形成在頭連接板1213。尤其是，如 ’ 果流入孔12 14a係形成於頭連接板1213，流入封閉空間的 空氣被喷灑在測試板上。也就是說，空中避免從流入孔至 排出孔的繞路’從而增加測試板的冷卻效率。 16 200945468 〈應用2> 备低溫測試完成，測試插座的電線被測試插座所導入 冷卻所壓縮’從而導致測試錯誤^為了防止這種凝結現 象，傳統的半導體裝置測試系統包括一乾燥裝置，其可強 制喷灑乾燥空氣。 在應用2，如圖13所示，根據本發明之半導體裝置測 ©試系統還包括-喷麗設備13〇〇,其可噴麗乾燥空氣至一封 閉空間V。封閉空間v係使用封閉框帛i3i5形成在一界面 板13 11和一測試板丨3丨2之間。 <應用3> ❹ 在應用3中，如圖14所示，半導體裝置測試系統係配 置為包括-導管1416’其形成通向—封閉空間s之測試板 ⑷2之複數喷孔⑷6a ’所以經由一流入孔""a流動之 空氣通過噴灑洞⑷6a直接喷在測試板、化上，從而消 除來自測^ 1412之熱。因為它去除效率高，故該測試系 統是有利的。冑當明白，測試系統之佈署可以利用至少一 或多導管⑷6,其中導管1416可形成為一桿狀。 <應用4> 用示例4之半導體裝置測試系 圖15繪不依據本發明應 17 200945468 統之一主要部分。 如圖15所示，測試系統包含一溫度控制設備。溫度控 制設備700被配置為包括一空氣供應設備ιμ〇 ,用以供應 空氣至封閉空間S，及一抽吸設備，用以自封閉空間吸出 空氣，其中空氣是依箭頭方向流動。 為了另外安裝抽吸設備1 520至溫度控制設備，一測試 頭的-界面區塊1500具有一外殼1515,其形成相對於頭 ©連接板1513 ’位於封閉空間s對面的一流出空間f。 頭連接板1513被配置為：二流入孔1513&形成於板 1513兩相對邊界側和複數排出孔151%形成於其中心部 分。外殼1515形成一流出孔1515&，抽吸設備152〇藉以 將從封閉空間S經由複數排出孔i 5 i 3b流動至流出空間f 之空氣抽出。 在應用4，如圈】$所； . 固所不’頭連接板1513被部署為有 二流入孔1513a v但是，應明白，它可能包括三或二以上 的流入孔。如果頭連接板1513是部署為具有複數流入孔， 從而允許空氣供應設備經由它供應空氣至封閉空間，空氣 可以均勻地分散在封閉空間的整個位置從而使測試板的 冷卻效率可以最大化。 在應用4中，流動在封閉空間§的整體位置的空氣& P測試板1511 ’特別是，―測試晶片1川&，然後藉由形 成在頭連接板1513中位部分的排出孔151%排放至流出空 18 200945468 抓^呀，空氣被強制經由流出孔 間F。當抽吸設備 1515a從流出空間F流出’其中空氣沿箭頭方向流動 另一方面，因為連接電纜堵塞流出空間f，它們阻止 氣流或造成空氣渦流，從而使空氣不能順利從流出空間F 排出。可利用抽吸設備1520強制空氣流動解決這個=題。 在應用4，測試系統是有利的，因為它不循環空氣， 也沒有增加冷卻空氣的溫度。 ❹ 在應用4 ’根據冷卻條件下，測試系統可以操作為： 供應室溫空氣或如如上文章節「半導體裝置測試系統」所 述之使用空氣供應設備，藉由低溫氣體冷卻之空氣。 〈應用5> 圖16繪示依據本發明應用示例5之半導體裝置測試系 統之一主要部分。 如圖1 6所示，依據應用5之測試系統利用在應用4中 使用之界面區塊。但在這種情況下，在應用4的界面區塊 之測試板上因為電阻而產生熱量，從而使來自半導體裝置 之電子信號被扭曲。因此，測試系統無法正確測試半導體 裝置。 為了解決這問題，如圖16所示，根據應用5之測試系 統更包括一溫度控制設備1610、空氣壓縮機1620、以及抽 吸設備1630 » 19 200945468 溫度控制故備包括一冷卻器1610和一空氣供應線 1612。 冷卻器1611是一空氣供應設備。它冷卻被空氣壓縮機 1620所壓縮的空氣，及供應被冷卻壓縮的空氣至一封閉空 • 間。一般情況下，一測試處理器使用用於冷卻氣體之液氮 • (LN2)。液氮是昂貴的且係耗材’從而導致測試處理器的維 修費用增加。根據應用5的測試系統使用一冷卻器來冷卻 0 空氣，而不是使用液氮。 空氣壓縮機1620提供高於大氣壓力之達3.5〜5 Kgf/cm2高壓之空氣。如果一測試外殼、用於測試半導體裝 置之工廠已裝備了壓縮線，該壓縮線可被連接到冷卻器。 因此’測試系統不需要空氣壓縮機。 為了防止水冷凝在封閉空間的每一表面，最好從空氣 移除水份和供應不包含水份的乾燥空氣。 Ο 下文將參照圖1 7說明根據本發明之一種供應冷卻空 · · . 氣給半導體裝置測試系統之測試頭的方法。 1.冷卻高壓空氣（S1710 ) - 當空氣壓縮機1620以3.5〜5Kgf/cm2的壓力壓縮空 - 氣，並且將它供應給冷卻器1611，冷卻器1611冷卻高壓空 氣（S1710 )。3.5〜5Kgf/cm2的高壓空氣經由流入孔1513a 流入一定容量的封閉空間S，然後體積迅速擴大，所以空 20 200945468 氣充分和均勻地抵達封閉空間S的複數測試晶片1511a-1 〜151 la-4。 如果封閉空間S的體積被設計為相較於本實施例來得 小或大’或者如果排出扎丨5丨3b的大小是設計為相較於本 實施例來得小或大，則應減少或增加氣壓以符合設計。 ’ 在本發明的實施例中，界面區塊被設計為具有體積85 (寬）X320(長）xll (高）立方毫米的封閉空間。當有 © 這樣一封閉空間S的測試處理器的測試點是90。(：時，如 果被冷卻到約1 C和壓縮至3.5〜5 Kgf/cm2的空氣被提供 給封閉空間S，則封閉空間S的溫度能被控制在低於3〇。 C(大約為室溫），因此’測試晶片也可以順利操作。 2.供應冷高壓空氣至封閉空間（S1720 ) 在步驟S1710中，被冷卻器1611冷卻的高壓空氣被供 Φ 應給封閉空間s，其中暴露複數測試晶片1511 a-1〜1511 a-4 (S1720)〇 冷卻高壓空氣沿著空氣供應線1612從冷卻器16U通 過流入孔1 5 13 a流動至封閉空間s。由於冷卻的高壓空氣 - 立即擴展，並迅速蔓延在封閉空間S，冷卻空氣可以迅速 - 達到··測試晶片l511^1和151U-4,其位置相對接近流入 孔1513a ;及測試晶片i51ia-2和15lu_3，其位置相對逮 離流入孔1513a。因此，能均勻冷卻暴露在封閉空間s的 21 200945468 所有測試晶片151 la-1〜151 la-4。 另一方面，如果未經過空氣壓縮機1620壓縮之冷卻的 常壓空氣被供應至封閉空間S ’則在它抵達位置相對遠離 流入孔1513a之測試晶片1511a - 2和1511a — 3之前經由 排出孔1 5 1 3 b排放’如圖1 8所示。也就是說，測試晶片 1 5 11 a - 2和1 5 11 a - 3受到相對少量的冷卻空氣的影響。 因此’在位置相對接近流入孔l513a之測試晶片mia_丄 和15 11 a - 4及位置相對遠離流入孔15丨3a之測試晶片 1511a- 2和1511a _ 3之間發生溫度偏差。特別是，如果一 抽吸設備1630強烈抽吸封閉空間s中的空氣，則溫度偏差 變大。因此，如果半導體裝置測試系統未部署有一空氣壓 縮機，則不易準備和控制複數測試晶片i5iia _丨〜 1511a-4之均勻溫度。The gas supply device 740 supplies the gas to the inner side of the fan casing 71A at a low temperature to effectively eliminate the generated heat. The air supply line 750 connects the air discharge hole 711 to the inflow hole 314a' of the closing frame 314 to introduce the air discharged from the fan casing 71A through the air discharge hole 7U to the closed space s of the interface block 310. The air supply line 760 connects the discharge hole 31 of the closing frame 314 to the air inflow hole 712' of the fan casing 71 to allow the air to be discharged from the closed space S to the fan casing 71A of the air inflow hole 712 through the discharge hole 31. Therefore, during the testing of the semiconductor device, the semiconductor device using the temperature control device "by circulating air" also allows the generated heat to be accumulated on the test board 312. That is, the test system can continue to eliminate the heat generated therein. Maintaining at room temperature can also avoid the truth as shown in Figure 7, temperature control ^, as shown in Figure 8, can also be on the other hand, if the test board is free from the electronic properties of the device 700 is used to cycle 15 200945468 In this way, by applying the temperature control device 700 as a non-circulating air type, the air inflow hole 812 of the fan casing 810 draws the outside air passage, and through the discharge hole 814b' of the closed frame 814 from the enclosed space § Ejecting air to the outside. Therefore, as shown in Fig. 8, the temperature control device can be deployed without the gas supply device 74 and the air inflow line 76 as shown in Fig. 7. 较佳 Preferably, the temperature control device 700 is installed. To the test processor 9, as shown in Figure 9. Preferably, the temperature control device 7 is mounted to the test head 1000 (as shown in Figure 10), or is To the support device 11 (as shown in Figure u). However, since the interface block 310 is partially inserted and placed in the test chamber of the test processor, it is best to install the temperature control device 7 to the test processor. <Application 1> As shown in Fig. 4, an inflow hole 314a and a bleed_hole 314b are formed in the closed frame 314, and the semiconductor device test system is deployed in this manner, in the application i, as shown in Fig. 12, at the head connection plate 1213 forms an inflow hole 121 and a discharge hole 1214b. The semiconductor device test system can also be deployed in this manner. It should be understood that 'one of the inflow hole 1214a and the discharge hole 1214b is formed in the closed 'frame 1214, and the other is formed in the head connection. The plate 1213. In particular, if the 'inflow hole 12 14a is formed in the head connecting plate 1213, the air flowing into the closed space is sprayed on the test board. That is, the air path from the inflow hole to the discharge hole is avoided in the air' Thereby increasing the cooling efficiency of the test board. 16 200945468 <Application 2> After the low temperature test is completed, the wires of the test socket are compressed by the cooling of the test socket, resulting in a test error ^ To prevent such condensation, the conventional semiconductor device test system includes a drying device that can forcibly spray dry air. In the application 2, as shown in FIG. 13, the semiconductor device test system according to the present invention further includes - spray The device 13 is configured to spray dry air to a closed space V. The closed space v is formed between the interface plate 13 11 and a test plate 丨3丨2 using the closed frame 帛i3i5. <Application 3> In application 3, as shown in FIG. 14, the semiconductor device test system is configured to include a conduit 1416' which forms a plurality of orifices (4) 6a' of the test plate (4) 2 leading to the closed space s, so via an inflow orifice "" a flowing air is directly sprayed on the test board through the spray hole (4) 6a, thereby eliminating heat from the test 1412. This test system is advantageous because of its high removal efficiency. It is understood that the deployment of the test system can utilize at least one or more conduits (4) 6, wherein the conduit 1416 can be formed as a rod. <Application 4> Test apparatus using the semiconductor device of Example 4 Fig. 15 depicts a main part which is not in accordance with the present invention 17 200945468. As shown in Figure 15, the test system includes a temperature control device. The temperature control device 700 is configured to include an air supply device ιμ〇 for supplying air to the enclosed space S, and a suction device for drawing air from the enclosed space, wherein the air flows in the direction of the arrow. In order to additionally install the suction device 1 520 to the temperature control device, a test head-interface block 1500 has a housing 1515 that forms a first-class outlet space f opposite the closed space s with respect to the head © connection plate 1513'. The head connecting plate 1513 is configured such that two inflow holes 1513 & are formed on the opposite boundary sides of the plate 1513 and a plurality of discharge holes 151% are formed in the central portion thereof. The outer casing 1515 forms a first-class outlet 1515&, and the suction device 152 extracts air flowing from the closed space S through the plurality of discharge holes i 5 i 3b to the outflow space f. In the application 4, such as the circle], the solid connector 1513 is deployed to have two inflow holes 1513a. However, it should be understood that it may include three or more inflow holes. If the head connecting plate 1513 is deployed to have a plurality of inflow holes, thereby allowing the air supply device to supply air to the enclosed space therethrough, the air can be uniformly dispersed throughout the entire position of the enclosed space so that the cooling efficiency of the test board can be maximized. In the application 4, the air & P test plate 1511' flowing in the overall position of the closed space § 'in particular, the test wafer 1 & and then the venting hole 151% formed in the middle portion of the head connecting plate 1513 Discharge to the outflow 18 200945468 Grab the air, the air is forced through the outflow hole F. When the suction device 1515a flows out from the outflow space F, in which the air flows in the direction of the arrow, on the other hand, since the connecting cable blocks the outflow space f, they block the airflow or cause the air to vortex, so that the air cannot be smoothly discharged from the outflow space F. The suction device 1520 can be used to force air flow to solve this problem. In application 4, the test system is advantageous because it does not circulate air nor increase the temperature of the cooling air. ❹ In Application 4 ‘Under cooling conditions, the test system can operate as: Supply room temperature air or air cooled by a cryogenic gas, as described in the “Semiconductor Device Test System” section of the previous section. <Application 5> Fig. 16 is a view showing an essential part of a semiconductor device test system according to Application Example 5 of the present invention. As shown in Fig. 16, the test system according to the application 5 utilizes the interface block used in the application 4. In this case, however, heat is generated on the test board of the interface block of the application 4 due to the electric resistance, so that the electronic signal from the semiconductor device is distorted. Therefore, the test system cannot properly test the semiconductor device. In order to solve this problem, as shown in FIG. 16, the test system according to the application 5 further includes a temperature control device 1610, an air compressor 1620, and a suction device 1630 » 19 200945468 The temperature control device includes a cooler 1610 and an air. Supply line 1612. The cooler 1611 is an air supply device. It cools the air compressed by the air compressor 1620 and supplies the cooled compressed air to a closed space. In general, a test processor uses liquid nitrogen (LN2) for cooling gases. Liquid nitrogen is expensive and is a consumable' resulting in increased maintenance costs for the test processor. A tester according to Application 5 uses a cooler to cool 0 air instead of using liquid nitrogen. The air compressor 1620 provides air at a pressure of 3.5 to 5 Kgf/cm2 above atmospheric pressure. If a test enclosure, the factory for testing the semiconductor device, is equipped with a compression line, the compression line can be connected to the cooler. Therefore, the test system does not require an air compressor. In order to prevent water from condensing on each surface of the enclosed space, it is preferable to remove moisture from the air and supply dry air containing no moisture. BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method of supplying a cooling head to a test head of a semiconductor device test system according to the present invention will be described with reference to FIG. 1. Cooling of high-pressure air (S1710) - When the air compressor 1620 compresses the air-gas at a pressure of 3.5 to 5 Kgf/cm2 and supplies it to the cooler 1611, the cooler 1611 cools the high-pressure air (S1710). The high-pressure air of 3.5 to 5 Kgf/cm2 flows into the closed space S of a certain volume through the inflow hole 1513a, and then the volume is rapidly expanded, so that the air 20 200945468 gas sufficiently and uniformly reaches the plurality of test wafers 1511a-1 to 151 la-4 of the closed space S. . If the volume of the closed space S is designed to be smaller or larger than in the present embodiment or if the size of the discharge shackle 5 丨 3b is designed to be smaller or larger than in the present embodiment, the air pressure should be reduced or increased. In order to meet the design. In an embodiment of the invention, the interface block is designed to have an enclosed space of volume 85 (width) X 320 (length) x 11 (height) cubic millimeters. When there is © such a closed space S, the test point of the test processor is 90. (: When the air cooled to about 1 C and compressed to 3.5 to 5 Kgf/cm 2 is supplied to the closed space S, the temperature of the closed space S can be controlled to be less than 3 〇 C (about room temperature) Therefore, the test wafer can also be operated smoothly. 2. Supply cold high-pressure air to the enclosed space (S1720). In step S1710, the high-pressure air cooled by the cooler 1611 is supplied to the enclosed space s, wherein the plurality of test wafers are exposed. 1511 a-1 to 1511 a-4 (S1720) 〇 Cooling high-pressure air flows from the cooler 16U through the inflow hole 1 5 13 a to the enclosed space s along the air supply line 1612. Due to the cooled high-pressure air - immediately expands and rapidly Spreading in the enclosed space S, the cooling air can be quickly reached - the test wafers l511^1 and 151U-4 are positioned relatively close to the inflow hole 1513a; and the test wafers i51ia-2 and 15lu_3 are positioned relatively close to the inflow hole 1513a. Therefore, it is possible to uniformly cool all of the test wafers 151 la-1 to 151 la-4 exposed to the closed space s. On the other hand, if the atmospheric air that has not been compressed by the air compressor 1620 is supplied to the closed space S 'then It is discharged via the discharge holes 1 5 1 3 b before it reaches the test wafers 1511a - 2 and 1511a - 3 which are relatively far from the inflow hole 1513a as shown in Fig. 18. That is, the test wafer 1 5 11 a - 2 and 1 5 11 a - 3 is affected by a relatively small amount of cooling air. Therefore, the test wafers mia_丄 and 15 11 a - 4 in a position relatively close to the inflow hole l513a and the test wafer 1511a in a position relatively far from the inflow hole 15丨3a are - A temperature deviation occurs between 2 and 1511a _ 3. In particular, if a suction device 1630 strongly draws air in the enclosed space s, the temperature deviation becomes large. Therefore, if the semiconductor device test system does not have an air compressor deployed, It is not easy to prepare and control the uniform temperature of the complex test wafer i5iia _丨~ 1511a-4.
相反地，本應用實例被配置為，高遷空氣可通過流, 孔1513a提供給封心間s，從而可以均句地到達所有萍 試晶片 1511a-i 〜 因此，它可以大比率地^ 低測試晶片⑸la]〜1511“間的溫度偏差，從㈣ 夠準備一均句溫度的測試晶片⑸心！〜15Ua_ 試晶片1511a _ i〜 ^ 1 4如此測試半導體裝置，因ώ 能提供一相對較高可靠性的測試結果。 從封閉空間排出空氣（S 1 73 0 ) 22 200945468 藉由 1511a- 1 抽吸設備1630的抽吸力的作用，冷卻測試晶片 〜 1511a-4的空氣通過排出孔1513b從封閉空 間s排出（S1730 )。 • 〈應用6> 圖19之視圖繪示一種依據圖16之應用6之半導體裝 置測試系統之界面區塊191〇。 〇 如圖19所示’界面區塊1910包括：一界面板1911， 其具有一測試插槽1911a; —測試板1912; —封閉板1913 ; 一封閉框架1914 ;及一溫度感應器i915。 如圖20所示’測試板1912包括複數測試晶片1912a。 較佳地’測試晶片1 912a是以由Altera公司所生產的晶片 所部署’其可以偵測到的晶片本身的溫度。測試晶片1912 可以讀出並處理來自複數（例如，四個）半導體裝置的電子 ❹信號。 測試板1912、封閉板1913和封閉框架1914共同形成 一封閉空間S。該測試晶片1912a係暴露在該封閉空間S 中。 溫度感應器1 9 1 5偵測封閉空間§的内部溫度。 如圖2 1所不’封閉空間s和暴露在其中的測試晶片 1912a可被從一溫度控制設備192〇供應的冷卻空氣所冷 卻。也就是說，冷卻空氣從溫度控制設備192〇經由流入孔 23 200945468 1913a被引入至封閉空間s，以冷卻測試晶片1912a和封閉 空間S ’然後通過排出孔丨9〗3 ^排出。 使用界面區塊1 91 〇的測試系統可藉由溫度控制設備 1 920冷卻測試晶片1912a和封閉空間S，從而可以防止測 * 試晶片1912a過熱。 然而，由於測試晶片1912a係在高溫下通過電導線連 接至半導體裝置’它們可能會過熱，即使封閉空間S係經 〇 適當降溫的。在這種情況下，由測試晶片1912自半導體裝 置讀取的信號可能有錯誤。特別是，如果測試晶片l912a 過熱超過要求的溫度範圍’並在這種狀態下執行對半導體 的測試，受測試的半導體裝置必須分別管理。 如果封閉空間S中的溫度升高，則難以冷卻測試晶片 1912a’因而導致測試晶片1912a過熱。當封閉空間§中的 溫度偏離出一所需溫度範圍内，應告知使用者，應自動降 ® 低封閉空間S的溫度。此外，在封閉空間S過熱時測試的 半導體裝置必須分別管理。如果有必要，應該停止測試半 導體裝置。 重要的是’溫度控制設備1920能操作，測試晶片1912a 和封閉空間S能保持在一所需的温度範圍，例如，低於6〇 ' 。C。但是，測試晶片1912a和/或封閉空間s可能是無意 間過熱，意即’偏離要求的溫度範圍°因此，在這種狀態 下測試的半導體裝置應按下面的方法分類。下文亦將描述 24 200945468 一種用於支援半導體裝置之測試的方法β ι·用於分類受測試的半導體裝置的方法 圖22是一流程圖，其描述一種根據本發明之分類受測 試的半導體裝置之方法。 1)偵測測試晶片的溫度（S22 10 ) © #測試系統進行對半導體裝置的測試，複數測試晶片On the contrary, the application example is configured such that the high-migration air can be supplied to the core s through the flow, and the hole 1513a can be uniformly reached to all the test chips 1511a-i~ Therefore, it can be tested at a large ratio Wafer (5) la] ~ 1511 "temperature deviation between, from (four) enough to prepare a test temperature of the test wafer (5) heart! ~ 15Ua_ test wafer 1511a _ i ~ ^ 1 4 test semiconductor device, because it can provide a relatively high reliability Sexual test results. Exhaust air from the enclosed space (S 1 73 0 ) 22 200945468 By the suction force of the 1511a-1 suction device 1630, the air of the test wafer ~ 1511a-4 is cooled through the discharge hole 1513b from the enclosed space s discharge (S1730). <Application 6> FIG. 19 is a view showing an interface block 191 of the semiconductor device test system according to the application 6 of FIG. 16. As shown in FIG. 19, the interface block 1910 includes: The interface board 1911 has a test slot 1911a; a test board 1912; a closing board 1913; a closed frame 1914; and a temperature sensor i915. As shown in Fig. 20, the test board 1912 includes a plurality of test wafers 1912a. The ground test wafer 1 912a is a temperature that can be detected by a wafer produced by Altera Corporation. The test wafer 1912 can read and process electrons from a plurality of (for example, four) semiconductor devices. The test board 1912, the closing plate 1913 and the closing frame 1914 together form a closed space S. The test wafer 1912a is exposed in the closed space S. The temperature sensor 1 9 15 detects the internal temperature of the closed space §. The non-closed space s of FIG. 21 and the test wafer 1912a exposed therein can be cooled by the cooling air supplied from a temperature control device 192. That is, the cooling air is passed from the temperature control device 192 via the inflow hole 23 200945468 1913a is introduced into the enclosed space s to cool the test wafer 1912a and the enclosed space S' and then discharged through the discharge port 〗9. 3 ^ The test system using the interface block 1 91 冷却 can cool the test wafer by the temperature control device 1 920 1912a and the enclosed space S, thereby preventing the test wafer 1912a from being overheated. However, since the test wafer 1912a is passed through the electric wire at a high temperature Connected to the semiconductor device 'they may overheat even if the enclosed space S is properly cooled. In this case, the signal read from the semiconductor device by the test wafer 1912 may be erroneous. In particular, if the test wafer l912a is overheated Exceeding the required temperature range 'and performing semiconductor testing in this state, the semiconductor devices under test must be separately managed. If the temperature in the enclosed space S rises, it is difficult to cool the test wafer 1912a' and thus cause the test wafer 1912a to overheat. When the temperature in the enclosed space § deviates from a desired temperature range, the user should be informed that the temperature of the low enclosed space S should be automatically reduced. In addition, the semiconductor devices tested when the enclosed space S is overheated must be separately managed. If necessary, stop testing the semiconductor device. It is important that the temperature control device 1920 is operable to maintain the test wafer 1912a and the enclosed space S at a desired temperature range, for example, below 6 〇 '. C. However, the test wafer 1912a and/or the enclosed space s may be unintentionally overheated, meaning that it deviates from the required temperature range. Therefore, the semiconductor devices tested in this state should be classified as follows. 24 200945468 A method for supporting testing of a semiconductor device. FIG. 1 is a method for classifying a semiconductor device under test. FIG. 22 is a flowchart depicting a semiconductor device tested according to the classification of the present invention. method. 1) Detecting the temperature of the test chip (S22 10 ) © #Test system for testing semiconductor devices, multiple test wafers
溫度摘測操作可以即時歧期進行。溫度债測操作也可能 只在半導體裝置在測試站進行測試時執行。 2)決定測試晶片的溫度（S222〇 ) 端疋在S22 1 0偵測的測試晶片丄92丨a之個別溫度是否 例如’低於60 t ( S2220)。本文Temperature sampling operations can be performed in a timely manner. Temperature debt testing operations may also be performed only when the semiconductor device is tested at the test station. 2) Determine the temperature of the test wafer (S222〇). Whether the individual temperature of the test wafer 丄92丨a detected at S22 10 is, for example, 'below 60 t (S2220). This article
〇 在一所需的溫度範圍 3)分類半導體裝置（S2: 在S2220中，當測試晶片 (S2231、S2232) 晶片192 1 a個別的溫度在一所需 25 200945468 的溫度範圍内，至少一或多測試半導體裝置係根據測試等 級來分類（S223 1)’即所謂的第一分類方法，其作為一正 吊的分類方法。相反地，如果在在S222〇中測試晶片i92ia 個別的溫度偏離一所需溫度範圍，或例如大於6〇它，則 對這種在一偏離的溫度範圍内測試的半導體裝置進行分 類’即所謂的第二分類方法（S2232)。 第二分類方法指的是一種以一再測試批次將在測試晶 © 片1912a偏離所需溫度範圍時測量的半導體裝置進行分類 的方法。以一再測試批次分類意指以一欲再次測試的批 次，分類受測試的半導體裝置。相關於半導體裝置再測試 的技術已公開於韓國專利申請號第1〇_〇792488號，發明名 稱為 “TEST HANDLER AND METHOD FOR SUPP0RTING THE TEST HANDLER to perform testing- 〇 #果複數測試晶片1912a之一部分係處於-所需的溫 度範園内，而另-部分是偏離該所需的溫度範圍，則只有 其電子信號係由偏離溫度範圍之複數受測試晶片1912&之 部分所讀取之受測試半導體裝置是按第二分類方法分類。 較佳地，在測試處理器自動分類受測試半導體裝置。 -在這種情況下，測試處理器的卸載設備執行半導體裝置的 '分類。 2.支援半導體裝置之測試的方法 26 200945468 圖23是一流程圖，其描述一種根據本發明用於支援半 導體裝置之測試的方法。 1) 镇測封閉空間的溫度（S23 1 〇 ) 溫度感應器1915偵測封閉空間S的内部溫度 (S23 1 0)。溫度感應器丨9丨5所進行的溫度偵測操作可以即 時或定期執行。溫度偵測操作也可能只在半導體裝置在測 G 試站進行測試時執行。 2) 決定封閉空間的溫度（S2320 ) 確定在S23 10偵測的封閉空間s之内部溫度是否在一 所需的溫度範圍，例如，低於60 t (S2220)e本文中， 基於在S2310偵測到的資訊，S232〇的決定可能在測試器 或測試處理器中執行。如果確定S232〇在測試器執行，則 ©冑定結果或控制測試處理器的指令應傳送至測試處理器， 從而使測試處理器執行一對應的操作。 3 )根據決定結果操作測試系統（S233 1， S2332 ) 在S2320中，若封閉空間s的内部溫度是在一所需的 恤度範圍内，則測試系統正常操作（Μ”丨）。相反地，在 S2320中，若内部溫度的封閉空間§偏離要求的溫度範圍， 則測試系統執行一緊急操作（S2332 )。 27 200945468 下文將敘述S2332的緊急操作的示例。 測試系統之緊急操作的示例 Α.示例 該測試系統可以實施為，通過測試處理- n 不封閉处 ❹ ❾ 間S為過熱。指示方法可部署為，藉由測試處理器之： 器產生聲音警報或顯示一視覺信號。 顯不 B.示例2 該測試系統可以實施為，暫時停止測試處理器。 地’測試系統係部署為，在封閉空間8的溫度返 溫度範圍内之後，自動解除測試處理器的停止操作。 C ·示例3 測試系統可以部署為： 間S過熱時測試的半導體裝 以一再測試批次， 置予以分類。 將在封閉空 D·示例4 測試系統可以部署為：如果溫度控制設備議已停止 操作，則操作溫度控制裝置192〇,以使封閉空間s的溫度 降低】所需的溫度範圍；或如果溫度控制設備係以相 28 200945468 對較小的冷卻能力操作，則控制溫度控制設備mu提高 溫度控制設備1920的冷卻能力。 應明白’測試系統可以實施為，執 别1仃不例1〜4之一或 全部。 〆 應極易理解，測試系# *5!*以音：&备 戎糸統了以實施為，使用分類半導體分类 classifying the semiconductor device in a desired temperature range 3) (S2: in S2220, when the test wafer (S2231, S2232) wafer 192 1 a individual temperature is within a required temperature range of 25 200945468, at least one or more The test semiconductor device is classified according to the test level (S223 1)', the so-called first classification method, which is used as a positive hanging method. Conversely, if the temperature of the wafer i92ia is tested in S222, the individual temperature deviation is required. The temperature range, or for example greater than 6 ,, classifies such semiconductor devices tested in a deviated temperature range, the so-called second classification method (S2232). The second classification method refers to a test with repeated The method by which the batch will be classified by the semiconductor device measured when the test wafer 1912a deviates from the desired temperature range. The repeated test batch classification means classifying the semiconductor device under test in a batch to be tested again. The technology for retesting a semiconductor device has been disclosed in Korean Patent Application No. 1〇_792488, entitled "TEST HANDLER AND METHOD FOR SUPP0RTING T HE TEST HANDLER to perform testing- 〇#One of the plurality of test wafers 1912a is in the desired temperature range, while the other part is deviated from the required temperature range, and only its electronic signal is deviated from the temperature range. The tested semiconductor devices read by the plurality of tested wafers 1912 & are classified according to a second classification method. Preferably, the test processor automatically classifies the tested semiconductor devices. - In this case, the test processor The unloading device performs the 'classification of the semiconductor device. 2. The method for supporting the test of the semiconductor device 26 200945468 FIG. 23 is a flowchart describing a method for supporting the test of the semiconductor device according to the present invention. Temperature (S23 1 〇) The temperature sensor 1915 detects the internal temperature of the enclosed space S (S23 1 0). The temperature detection operation performed by the temperature sensor 丨9丨5 can be performed immediately or periodically. The temperature detection operation may also be performed. Only performed when the semiconductor device is tested at the G test station. 2) Determine the temperature of the enclosed space (S2320) Determine the closed detection at S23 10 Whether the internal temperature of s is within a desired temperature range, for example, less than 60 t (S2220)e. Based on the information detected at S2310, the S232〇 decision may be performed in the tester or test processor. If it is determined that S232〇 is executed by the tester, the ©determination result or the instruction of the control test processor should be transmitted to the test processor, so that the test processor performs a corresponding operation. 3) The test system is operated according to the decision result (S233) 1, S2332) In S2320, if the internal temperature of the enclosed space s is within a desired range of degrees, the test system operates normally (Μ"丨). Conversely, in S2320, if the enclosed space of the internal temperature § deviates from the required temperature range, the test system performs an emergency operation (S2332). 27 200945468 An example of the emergency operation of S2332 will be described below. Example of emergency operation of the test system Α. Example The test system can be implemented to pass the test - n is not closed ❾ S S is overheated. The indication method can be deployed by the test processor to generate an audible alarm or display a visual signal. Show B. Example 2 The test system can be implemented to temporarily stop testing the processor. The ground test system is deployed to automatically deactivate the test processor after the temperature of the enclosed space 8 has returned to the temperature range. C • Example 3 The test system can be deployed as: The semiconductors tested during the S overheating are loaded with repeated test batches and classified. Will be in the closed space D. Example 4 test system can be deployed: if the temperature control device has stopped operating, then operate the temperature control device 192 〇 to reduce the temperature of the enclosed space s] the required temperature range; or if the temperature control The equipment is operated with phase 28 200945468 for smaller cooling capacity, and then the temperature control device mu is controlled to increase the cooling capacity of the temperature control device 1920. It should be understood that the test system can be implemented to perform one or all of the examples 1 to 4. 〆 It should be easy to understand, test system # *5!* by sound: &
置 的方法和/或支援半導體裝置測試的方法。 如上所述’根據本發明之半導㈣置測試系統可以消 除從一界面區塊’（即，測試板）產生的熱量，那裡的熱量 可能會扭曲電子特性，因此產生測試錯誤。因&，它可以 精確地測試半導體裝置。此外，它可以均勾地冷卻被包含 在界面區塊的個別測試晶片，從而可以達成半導體裝置的 測試可靠性。 雖然本文已經詳細描述了本發明之示例性實施例，應 ❹㈣解，對於習知該項技藝者而言，如后附申請專利範圍 界定般，本文所描述的基本發明概念可以有許多的變化和 修改，匕們仍然歸屬本發明示例性實施例的精神和範圍之 内。 【圖式簡單說明】 可藉由本發明之下述内容及附圖明白本發明之上述和 其他目的、特徵和優點，其中： 圖1是一平面圖，其繪示一般半導體裝置測試系統之 29 200945468 一主要部分； 圖2是一側視圖’其繪示圖i之半導體裝置測試系統； 圖3是一爆炸圖，其繪示依據本發明之一實施例，用 於一半導體裝置測試系統之一界面區塊； 圖4是圖3之界面區塊之組裝視圖； 圖5之拆解視圖繪示作為圖3界面區塊之一應用實例 之一界面區塊； 圖6是圖5之界面區塊之組裝視圖； 圖7是一爆炸圖，其繪示依據本發明之一實施例，應 用一溫度控制設備之一半導體裝置測試系統之一主要部 分； 圖8是一側視圖，其繪示圖7之主要部分之一應用； 圖9至圖11之圖式說明一種用於配置如圖7所示之溫 度控制設備之方法； 圖12至圖16是爆炸圖，其繪示依據本發明，一半導 體裝置測試系統之各種應用； 圖17是一流程圖，其說明根據本發明，一種提供冷卻 空氣給半導體裝置測試系統之測試頭的方法； 圖18之圖式說明一種不藉由空氣壓縮機將冷卻空氣 i、應、σ |導體裝置測試系統之一封閉空間之方法； 圖19之視圖繪示一種依據圖之應用6之半導體裝 置測試系統之界面區塊； 30 200945468 圖2〇之圖式繪示圖丨9之界面區塊之一測試板； 圖21之圖式繪示依據本發明之應用6之半導體裝置測 試系統之主要部分； . 圖22是一流程圖’其描述一種根據本發明之分類受測 試的半導體裝置之方法； 圖23是一流程圖’其描述一種根據本發明用於支援半 導體裝置之測試的方法； ❹ 【主要元件符號說明】 〇 100 測試處理器 312 一測試板 110 裝載裝置 312a 電路板 120 測試室 312b 測試板端連接器 130 卸載設備 312c 測試晶片 200 測試頭 313 頭連接板 210 界面區塊 313a 電路板 211 測試插座 313b 頭連接板端連接器 220 頭主體 314 封閉框架 310 界面區塊 314a 空氣流入孔 311 界面板 314b 空氣流出孔 311a 電路板 510 界面區塊 311b 測試插座 511 界面板 311c 界面板端連接器 512 測試板 31 200945468The method of setting and/or the method of supporting semiconductor device testing. As described above, the semi-conductive (four) test system according to the present invention can eliminate heat generated from an interface block ' (i.e., test board), where heat may distort electronic characteristics, thus causing test errors. Because of &, it can accurately test semiconductor devices. In addition, it can cool the individual test wafers contained in the interface block, so that the test reliability of the semiconductor device can be achieved. Although the exemplary embodiments of the present invention have been described in detail herein, it should be understood that the basic inventive concept described herein can be varied and varied as defined by the appended claims. Modifications are still within the spirit and scope of the exemplary embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become apparent from FIG. 2 is a side view of the semiconductor device test system of FIG. 1; FIG. 3 is an exploded view showing an interface region of a semiconductor device test system according to an embodiment of the present invention. Figure 4 is an assembled view of the interface block of Figure 3; Figure 3 is a disassembled view showing one of the application blocks of one of the interface blocks of Figure 3; Figure 6 is an assembly of the interface block of Figure 5. Figure 7 is an exploded view showing one main portion of a semiconductor device test system using a temperature control device in accordance with an embodiment of the present invention; Figure 8 is a side view showing the main portion of Figure 7 One of the applications; FIG. 9 to FIG. 11 illustrate a method for configuring the temperature control device shown in FIG. 7. FIG. 12 to FIG. 16 are exploded views showing a semiconductor device test according to the present invention. system Figure 17 is a flow chart illustrating a method of providing cooling air to a test head of a semiconductor device test system in accordance with the present invention; Figure 18 is a diagram illustrating a cooling air i, not by an air compressor, A method for enclosing a space in a σ | conductor device test system; FIG. 19 is a view showing an interface block of a semiconductor device test system according to application 6 of the figure; 30 200945468 FIG. One of the interface blocks is a test board; FIG. 21 is a diagram showing a main part of a semiconductor device test system according to application 6 of the present invention; FIG. 22 is a flow chart describing a classification according to the present invention. FIG. 23 is a flowchart depicting a method for supporting testing of a semiconductor device in accordance with the present invention; ❹ [Major component symbol description] 〇100 test processor 312, test board 110, loading device 312a, circuit board 120 test chamber 312b test board end connector 130 unloading device 312c test wafer 200 test head 313 head connection plate 210 interface block 313a Circuit board 211 test socket 313b head connection board end connector 220 head body 314 closed frame 310 interface block 314a air inflow hole 311 interface board 314b air outflow hole 311a circuit board 510 interface block 311b test socket 511 interface board 311c interface board end Connector 512 Test Board 31 200945468
515 GFG連接器 1312 測試板 516 螺栓 1315 封閉框架 700 溫度控制設備 1416 導管 710 外殼 1412 測試板 720 風扇 1416 喷孔 730 風扇驅動設備 1414a流入孔 740 一氣體供應設備 1500 界面區塊 750 一空氣供應線 1510 空氣供應設備 760 一空氣流入線 1511 測試板 810 風扇外殼 1 5 11 a測試晶片 812 空氣流入孔 1513 頭連接板 814 封閉框架 1513a流入孔 814b 排出孔 15 13b排出孔 900 處理器 1515 外殼 1000 測試頭 1520 抽吸設備 1100 支撐設備 1610 溫度控制設備 1213 頭連接板 1611 冷卻器 1214a流入孔 1612 空氣供應線 1214b排出孔 1620 空氣壓縮機 1300 喷灑設備 1630 抽吸設備 1315 封閉框架 1911 界面板 1311 界面板 1911 a測試插槽 32 200945468515 GFG connector 1312 test board 516 bolt 1315 closed frame 700 temperature control device 1416 conduit 710 housing 1412 test board 720 fan 1416 nozzle 730 fan drive device 1414a inflow hole 740 a gas supply device 1500 interface block 750 an air supply line 1510 Air supply device 760 - Air inflow line 1511 Test board 810 Fan housing 1 5 11 a Test wafer 812 Air inflow hole 1513 Head connection plate 814 Closed frame 1513a Inflow hole 814b Discharge hole 15 13b Discharge hole 900 Processor 1515 Housing 1000 Test head 1520 Suction device 1100 support device 1610 temperature control device 1213 head connection plate 1611 cooler 1214a inflow hole 1612 air supply line 1214b discharge hole 1620 air compressor 1300 spray device 1630 suction device 1315 closed frame 1911 interface plate 1311 interface plate 1911 a Test slot 32 200945468
1912 測試板 1915 1912a測試晶片 1920 1913 封閉板 CC 1913a ί流入孔 S 1913b排出孔 SA 1914 封閉框架 V 溫度感應器 溫度控制設備 連接電纜 封閉空間 支撐設備 封閉空間1912 Test Board 1915 1912a Test Wafer 1920 1913 Closing Plate CC 1913a ί Inlet Hole S 1913b Vent Hole SA 1914 Closed Frame V Temperature Sensor Temperature Control Equipment Connecting Cable Enclosed Space Supporting Equipment Enclosed Space
3333
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| KR1020080042821A KR100981165B1 (en) | 2008-03-15 | 2008-05-08 | Semiconductor device test system and test handler |
| KR1020080072879A KR100950332B1 (en) | 2008-07-25 | 2008-07-25 | Sorting method of tested semiconductor device and supporting method for testing semicondutor device |
| KR2020080010388U KR200464551Y1 (en) | 2008-03-15 | 2008-08-04 | Semiconductor device test system |
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| US10197621B2 (en) | 2013-06-07 | 2019-02-05 | Kingston Digital, Inc. | Testing device |
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| CN105307458B (en) * | 2015-11-06 | 2018-01-30 | 上海斐讯数据通信技术有限公司 | A kind of measurement jig and heat dissipating method with heat sinking function |
| KR102393040B1 (en) * | 2015-11-27 | 2022-05-03 | (주)테크윙 | Docking apparatus for testing electronic devices |
| CN110133469A (en) * | 2019-05-31 | 2019-08-16 | 德淮半导体有限公司 | Semiconductor testing apparatus and its working method |
| CN112802536B (en) * | 2019-11-13 | 2024-09-13 | 第一检测有限公司 | Chip testing device and chip testing system |
| CN111289877B (en) * | 2020-03-03 | 2022-07-19 | 武汉精鸿电子技术有限公司 | Aging test equipment |
| CN112684320B (en) * | 2020-12-17 | 2023-01-31 | 海光信息技术股份有限公司 | Chip low-temperature testing environment bin and chip testing machine |
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| US6091062A (en) * | 1998-01-27 | 2000-07-18 | Kinetrix, Inc. | Method and apparatus for temperature control of a semiconductor electrical-test contractor assembly |
| WO2003007007A1 (en) * | 2001-07-12 | 2003-01-23 | Advantest Corporation | Electronic parts handling device, and electronic parts temperature control method |
| JP2003028924A (en) * | 2001-07-13 | 2003-01-29 | Advantest Corp | Electronic component handling device and method of controlling temperature of the electronic component |
| KR100824128B1 (en) * | 2006-09-07 | 2008-04-21 | 가부시키가이샤 어드밴티스트 | Insert for electronic component handling apparatus, and electronic component handling apparatus |
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