TW200943513A - Package substrate and method for fabricating the same - Google Patents

Package substrate and method for fabricating the same

Info

Publication number
TW200943513A
TW200943513A TW97113564A TW97113564A TW200943513A TW 200943513 A TW200943513 A TW 200943513A TW 97113564 A TW97113564 A TW 97113564A TW 97113564 A TW97113564 A TW 97113564A TW 200943513 A TW200943513 A TW 200943513A
Authority
TW
Taiwan
Prior art keywords
layer
forming
metal
metal layer
resist
Prior art date
Application number
TW97113564A
Other languages
Chinese (zh)
Other versions
TWI360214B (en
Inventor
Chao-Wen Shih
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW97113564A priority Critical patent/TWI360214B/en
Publication of TW200943513A publication Critical patent/TW200943513A/en
Application granted granted Critical
Publication of TWI360214B publication Critical patent/TWI360214B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A package substrate and a method for fabricating the same are provided. The method includes: forming an adhesive layer and a metal layer on at least one surface of a core board; forming a first resist layer on the metal layer; forming a first opening region in the first resist layer and the metal layer by penetrating the first resist layer and removing a portion of the metal layer so as to expose the metal layer from the first opening region, wherein scope of removing the metal layer is greater than scope of removing the first resist layer; forming a metal post within the first opening region; removing the first resist layer; forming a first solder mask layer to replace the removed first resist layer; forming a first circuit layer on the metal post to provide electrical connection; forming a built-up structure on the first circuit layer and the first solder mask layer; removing the core board, the adhesive layer, and the metal layer, to allow the metal post to protrude outward and expose from the first solder mask layer. Accordingly, a package structure free of a core board, provided with fine-circuit structure, and characterized by a simple process can be fabricated.
TW97113564A 2008-04-15 2008-04-15 Package substrate and method for fabricating the s TWI360214B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97113564A TWI360214B (en) 2008-04-15 2008-04-15 Package substrate and method for fabricating the s

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97113564A TWI360214B (en) 2008-04-15 2008-04-15 Package substrate and method for fabricating the s

Publications (2)

Publication Number Publication Date
TW200943513A true TW200943513A (en) 2009-10-16
TWI360214B TWI360214B (en) 2012-03-11

Family

ID=44869029

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97113564A TWI360214B (en) 2008-04-15 2008-04-15 Package substrate and method for fabricating the s

Country Status (1)

Country Link
TW (1) TWI360214B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515487A (en) * 2012-06-21 2014-01-15 位速科技股份有限公司 Method for manufacturing ceramic package substrate used in light-emitting wafers
TWI451826B (en) * 2012-05-28 2014-09-01 Zhen Ding Technology Co Ltd Multilayer printed circuit board and method for manufacturing same
TWI615936B (en) * 2016-09-20 2018-02-21 矽品精密工業股份有限公司 Substrate structure and the manufacture thereof
CN112103194A (en) * 2020-08-27 2020-12-18 珠海越亚半导体股份有限公司 Switching substrate, manufacturing method thereof and device packaging structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451826B (en) * 2012-05-28 2014-09-01 Zhen Ding Technology Co Ltd Multilayer printed circuit board and method for manufacturing same
CN103515487A (en) * 2012-06-21 2014-01-15 位速科技股份有限公司 Method for manufacturing ceramic package substrate used in light-emitting wafers
TWI615936B (en) * 2016-09-20 2018-02-21 矽品精密工業股份有限公司 Substrate structure and the manufacture thereof
CN112103194A (en) * 2020-08-27 2020-12-18 珠海越亚半导体股份有限公司 Switching substrate, manufacturing method thereof and device packaging structure

Also Published As

Publication number Publication date
TWI360214B (en) 2012-03-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees