CN112103194A - Switching substrate, manufacturing method thereof and device packaging structure - Google Patents
Switching substrate, manufacturing method thereof and device packaging structure Download PDFInfo
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- CN112103194A CN112103194A CN202010876464.4A CN202010876464A CN112103194A CN 112103194 A CN112103194 A CN 112103194A CN 202010876464 A CN202010876464 A CN 202010876464A CN 112103194 A CN112103194 A CN 112103194A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application discloses a switching substrate and a manufacturing method thereof, and a device packaging structure, wherein the manufacturing method of the switching substrate comprises the following steps: providing a carrier plate, wherein the carrier plate is of a symmetrical structure, and metal layers are respectively arranged on the upper surface and the lower surface of the carrier plate; manufacturing metal columns and hole metals on the upper surface and/or the lower surface of the carrier plate, wherein the metal columns and the hole metals are connected with the metal layers arranged on the upper surface and/or the lower surface of the carrier plate; laminating a dielectric layer on the upper surface and/or the lower surface of the carrier plate, wherein the dielectric layer covers the metal column and the hole metal; polishing the dielectric layer to enable the dielectric layer to be flush with the metal columns and the hole metal, wherein the dielectric layer, the metal columns and the hole metal form a switching bottom plate; etching the metal layer on the upper surface and/or the lower surface of the carrier plate to separate the carrier plate from the transfer base plate, and performing graphic manufacturing on the upper surface and the lower surface of the transfer base plate to form a plurality of upper circuit layers and a plurality of lower circuit layers; and etching the hole metal to form a through hole structure. The routing distance can be shortened, and the signal quality of a circuit and the reliability of a product are improved.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a switching substrate, a manufacturing method thereof and a device packaging structure.
Technical Field
With the continuous development of microelectronic technology, electronic components and circuit board substrate circuits are more and more complex, and the performance of electronic products is more and more high, so that higher requirements are put forward on the packaging forms of the electronic components and the circuit board substrates of the complex circuits.
The Wire Bonding packaging technology is to utilize heat, pressure and ultrasonic energy to tightly weld a metal lead and a substrate Bonding pad to realize electrical interconnection between chips and a substrate and information intercommunication between chips, has the advantages of being capable of precisely controlling Bonding parameters, mature in matching system and the like, is widely applied, but the metal lead can cause impurities on the surface of a circuit during Wire Bonding packaging, and is not beneficial to application of complex circuits and light and thin products.
Content of application
The present application is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the application provides a switching substrate, a manufacturing method thereof and a device packaging structure, which can shorten the routing distance and improve the signal quality of a circuit and the reliability of a product. The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a method for manufacturing an interposer substrate, including:
providing a carrier plate, wherein the carrier plate is of a symmetrical structure, and metal layers are respectively arranged on the upper surface and the lower surface of the carrier plate;
manufacturing metal columns and hole metals on the upper surface and/or the lower surface of the carrier plate, wherein the metal columns and the hole metals are connected with the metal layers arranged on the upper surface and/or the lower surface of the carrier plate;
laminating a dielectric layer on the upper surface and/or the lower surface of the carrier plate, wherein the dielectric layer covers the metal column and the hole metal;
polishing the dielectric layer to enable the dielectric layer to be flush with the metal columns and the hole metal, wherein the dielectric layer, the metal columns and the hole metal form a switching bottom plate;
etching the metal layer on the upper surface and/or the lower surface of the carrier plate to separate the carrier plate from the transfer base plate, and performing graphic manufacturing on the upper surface and the lower surface of the transfer base plate to form a plurality of upper circuit layers and a plurality of lower circuit layers;
and etching the hole metal to form a through hole structure.
According to the manufacturing method of the switching substrate in the embodiment of the first aspect of the application, at least the following beneficial effects are achieved: on the first hand, the switching substrate manufactured according to the method for manufacturing the switching substrate comprises a through hole structure for mounting a chip, and the pin position of the chip positioned in the through hole structure is closer to the horizontal distance of a routing pad of the switching substrate, so that the transverse distance of routing is shortened, and the problem of avoiding positions of the routing pad and a circuit loop is reduced; the second aspect, shorten routing distance and can reduce parasitic inductance and resistance that the circuit produced, improve the signal quality of circuit, the third aspect, shorten routing distance and can reduce the encapsulation welding cost.
Optionally, in an embodiment of the present application, the method further includes forming solder masks on the upper surface and the lower surface of the adapter substrate, windowing the solder masks, and forming pads of an upper circuit layer and a lower circuit layer corresponding to the adapter substrate.
Optionally, in an embodiment of the present application, the method further includes forming a protective layer on the surface of the pad.
Optionally, in one embodiment of the present application, the protective layer material comprises nickel gold, nickel palladium gold, tin, silver or an organic solderability preservative film.
Optionally, in an embodiment of the present application, the method further includes depositing a metal seed layer, and etching the metal seed layer to attach the metal seed layer to the lower surface of the upper circuit layer and the upper surface of the lower circuit layer.
Optionally, in an embodiment of the present application, the metal layers disposed on the upper surface and the lower surface of the carrier include a first metal layer and a second metal layer, and the first metal layer and the second metal layer may be separated by physical stripping.
In a second aspect, an embodiment of the present application provides a interposer substrate, including:
a dielectric layer;
the metal column is arranged in the dielectric layer and is flush with the dielectric layer;
the circuit layer comprises an upper circuit layer and a lower circuit layer which are respectively arranged on the upper surface and the lower surface of the dielectric layer, and two ends of the metal column are respectively communicated with the upper circuit layer and the lower circuit layer;
and the through hole structure is arranged in the dielectric layer in a penetrating way.
According to the transit substrate of the embodiment of the second aspect of the application, at least the following beneficial effects are achieved: on the first hand, the switching substrate provided by the application comprises a through hole structure for mounting a chip, and the pin position of the chip in the through hole structure is closer to the horizontal distance of a routing pad of the switching substrate, so that the transverse distance of routing is shortened, and the problem of avoiding positions of the routing pad and a circuit loop is reduced; the second aspect, shorten routing distance and can reduce parasitic inductance and resistance that the circuit produced, improve the signal quality of circuit, the third aspect, shorten routing distance and can reduce the encapsulation welding cost.
Optionally, in an embodiment of the present application, the printed circuit board further includes a solder mask layer disposed on the surface of the circuit layer, the solder mask layer is provided with a pad, and the pad is connected to the upper circuit layer and the lower circuit layer.
Optionally, in an embodiment of the present application, a protective layer is further included and is disposed on the upper surface of the pad.
Optionally, in one embodiment of the present application, the protective layer material comprises nickel gold, nickel palladium gold, tin, silver or an organic solderability preservative film.
Optionally, in an embodiment of the present application, a metal seed layer is further included, and the metal seed layer is attached to the lower surface of the upper circuit layer and the upper surface of the lower circuit layer.
In a third aspect, an embodiment of the present application provides a device package structure, including:
the switching substrate comprises a dielectric layer, a metal column, a through hole structure and a circuit layer, wherein the circuit layer comprises an upper circuit layer and a lower circuit layer which are respectively arranged on the upper surface and the lower surface of the dielectric layer and communicated with the metal column;
an electronic device disposed at the via structure, the electronic device being in communication with the upper line layer or the lower line layer;
the surface of the printed circuit board is provided with a welding point;
the first substrate is arranged between the adapter substrate and the printed circuit board and is communicated with the lower circuit layer or the upper circuit layer and the welding points so that the electronic device is electrically communicated with the printed circuit board;
and the plastic packaging layer covers the surface of the electronic device.
According to the device packaging structure of the embodiment of the third aspect of the application, at least the following beneficial effects are achieved: on the first hand, the device packaging structure provided by the application comprises a through hole structure for mounting a chip, wherein the pin position of the chip positioned in the through hole structure is closer to the horizontal distance of a routing pad of a switching substrate, so that the transverse distance of routing is shortened, and the problem of avoiding positions of the routing pad and a circuit loop is reduced; the second aspect, shorten routing distance and can reduce parasitic inductance and resistance that the circuit produced, improve the signal quality of circuit, the third aspect, shorten routing distance and can reduce the encapsulation welding cost.
Optionally, in an embodiment of the present application, the printed circuit board further includes a solder mask layer disposed on the upper circuit layer and the lower circuit layer, the solder mask layer is provided with a pad, and the pad is connected to the circuit layer.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.
Fig. 1 is a flowchart illustrating steps of a method for manufacturing a interposer substrate according to an embodiment of the present disclosure;
fig. 2 to 14 are cross-sectional views corresponding to steps of a method for manufacturing a interposer substrate according to another embodiment of the present application;
fig. 15 to 19 are cross-sectional views corresponding to steps of a method for manufacturing a interposer substrate according to another embodiment of the present application;
fig. 20-23 are cross-sectional views corresponding to method steps of a device packaging structure according to another embodiment of the present application.
Reference numerals:
the printed circuit board comprises a carrier plate 10, a first metal layer 11, a second metal layer 12, a third metal layer 13, a fourth metal layer 14, a photosensitive dry film 20, a metal column pattern 21, a hole pattern 22, a metal column 121, a hole metal 122, a through hole structure 123, a dielectric layer 110, an upper circuit layer 161, a lower circuit layer 162, a photosensitive barrier layer 30, a transfer substrate 100, a solder resist layer 130, a pad 131, a protective layer 140, a metal seed layer 150, an electronic device 200, a printed circuit board 300, a first substrate 400 and a plastic package layer 500.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are merely illustrative and not restrictive, and therefore do not represent any changes in the technical spirit, structure, proportion, or size which may occur or which may not affect the performance or objectives achieved thereby, and are intended to be covered by the teachings herein.
Reference will now be made in detail to the present embodiments of the present application, preferred embodiments of which are illustrated in the accompanying drawings, which are for the purpose of visually supplementing the description with figures and detailed description, so as to enable a person skilled in the art to visually and visually understand each and every feature and technical solution of the present application, but not to limit the scope of the present application.
In the description of the present application, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and larger, smaller, larger, etc. are understood as excluding the present number, and larger, smaller, inner, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
Referring to fig. 1, a method for manufacturing a interposer substrate according to an embodiment of the present application includes the following steps:
s100, providing a carrier plate 10, where the carrier plate 10 is a symmetrical structure, and metal layers are respectively disposed on an upper surface and a lower surface of the carrier plate 10, specifically, as shown in fig. 2, first preparing a carrier plate 10, where the carrier plate 10 includes a middle carrier and initial metal layers symmetrically disposed on the upper surface and the lower surface of the middle carrier, where the initial metal layers include a first metal layer 11 and a second metal layer 12, the first metal layer 11 is disposed between the middle carrier and the second metal layer 12, specifically a copper foil layer with a thickness of 18um, and the second metal layer 12 is specifically a copper foil layer with a thickness of 3um, and in subsequent steps, the first metal layer 11 and the second metal layer 12 can be directly peeled off for board separation; as shown in fig. 3, form third metal layer 13 and fourth metal layer 14 on the initial metal layer of the upper surface or the lower surface of symmetrical carrier plate 10 in proper order, specifically be at the surface nickel plating and the copper facing in proper order of thickness 3 um's copper foil layer, the effect is that can etch 3um copper after the follow-up minute board, the nickel layer can protect the metal structure that the follow-up technology generated when 3um copper etches, reduce the etching speed, prevent excessive etching, third layer metal 13 nickel layer thickness is about 3um usually, fourth layer metal 14 copper layer thickness is about 3um usually, nickel, copper thickness can be defined according to actual need.
It should be noted that, in the manufacturing process, the carrier 10 is used as an initial layer, the carrier 10 is in a vertically symmetric structure, the double-sided interposer substrate 100 may be manufactured on the basis of the carrier 10, and the single-sided interposer substrate 100 may also be manufactured on the upper surface or the lower surface of the carrier 10.
S200, manufacturing metal posts 121 and hole metals 122 on the upper surface and/or the lower surface of the carrier plate 10, wherein the metal posts 121 and the hole metals 122 are connected with metal layers arranged on the upper surface and/or the lower surface of the carrier plate 10, specifically, as shown in fig. 4, the photosensitive dry film 20 is attached to the upper surface and the lower surface of the carrier plate 10 at the same time, the photosensitive dry film 20 is used for shielding and protecting the carrier plate 10, and the photosensitive dry film 20 is subjected to photolithography process according to design requirements, specifically, the photosensitive dry film 20 is exposed first, and then the exposed photosensitive dry film 20 is subjected to development process to form a shielding pattern, and the shielding pattern includes metal post patterns 21 and hole patterns 22; as shown in fig. 5, after the development, the substrate is chemically plated to form metal pillars 121 and via metal 122 at the corresponding positions of the metal pillar patterns 21 and the via patterns 22, in an embodiment, the plated metal material is specifically copper, and the thickness of the plated metal can be adjusted according to the actual thickness of the photosensitive dry film 20; as shown in fig. 6, the photosensitive dry film 20 is removed with a chemical.
It should be noted that the photosensitive dry film 20 is a high molecular compound, and it can generate a polymerization reaction after being irradiated by the ultraviolet ray to form a stable substance attached to the board surface, thereby achieving the function of blocking the electroplating and etching, in some embodiments of the present application, the position to be shielded is subjected to a local exposure treatment, the positions of the metal pillar patterns 21 and the hole patterns 22 to be exposed are subjected to a non-exposure treatment, and then the unexposed photosensitive dry film 20 is removed through a development treatment, so as to expose the required metal pillar patterns 21 and the hole patterns 22.
S300, laminating a dielectric layer 110 on the upper surface and/or the lower surface of the carrier 10, wherein the dielectric layer 110 covers the metal posts 121 and the hole metals 122, specifically, as shown in fig. 7, laminating the dielectric layer 110 on the upper surface and the lower surface, so that the dielectric layer 110 covers the metal posts 121 and the hole metals 122, and an epoxy resin prepreg with glass fiber is usually used.
S400, polishing the dielectric layer 110 to make the dielectric layer 110 flush with the metal pillar 121 and the hole metal 122, and forming a transfer backplane by the dielectric layer 110, the metal pillar 121 and the hole metal 122, specifically, polishing the dielectric layer 110 to make the dielectric layer 110 flush with the metal pillar 121 and the hole metal 122, and forming a transfer backplane by the dielectric layer 110, the metal pillar 121 and the hole metal 122, as shown in fig. 8, performing thinning polishing on the dielectric layer 110 to expose top surfaces of the metal pillar 121 and the hole metal 122, so as to make the dielectric layer 110 flush with the metal pillar 121 and the hole metal 122, and simultaneously controlling the thickness of the dielectric layer 110. Dielectric layer 110 fixes metal post 121 and via metal 122 to form an integrated interposer substrate.
S500, etching the metal layer on the upper surface and/or the lower surface of the carrier 10 to separate the carrier 10 from the interposer, patterning the upper surface and the lower surface of the interposer to form a plurality of upper circuit layers 161 and a plurality of lower circuit layers 162, specifically, as shown in fig. 8, performing a board separation process on the first metal layer 11 and the second metal layer 12 on the upper surface and/or the lower surface of the carrier 10 to separate the interposer from the carrier 10, removing the middle carrier and the first metal layer 11 as a whole, adhering the copper foil layer of the second metal layer 12, the nickel layer of the third metal layer 13, and the copper layer of the fourth metal layer 14 to one side surface of the interposer, performing an etching process on one side surface of the interposer, removing the second metal layer 12, the third metal layer 13, and the fourth metal layer 14 adhered to the surface of the interposer, and exposing the interposer composed of the dielectric layer 110, the metal posts 121, and the via metal 122, as shown in fig. 9; as shown in fig. 10, attaching the photosensitive barrier layer 30 on the upper and lower surfaces of the interposer substrate, and performing a photolithography process on the photosensitive barrier layer 30 to form patterns corresponding to the upper circuit layer 161 and the lower circuit layer 162 on the upper and lower surfaces of the interposer substrate, respectively; as shown in fig. 11, metal is deposited on the corresponding pattern of the upper circuit layer 161 and the lower circuit layer 162, specifically, metal copper is electroplated by using an electroplating process to form the upper circuit layer 161 and the lower circuit layer 162, and the photosensitive barrier layer 30 is removed.
It should be noted that the interposer substrate on the upper surface and the lower surface of the carrier 10 can be separated at the same time, and in some embodiments of the present application, the interposer substrate on the upper surface of the carrier 10 is separated from the carrier 10 as an example.
S600, etching the hole metal 122 to form a via structure 123, specifically, as shown in fig. 12, attaching the photosensitive barrier layer 30 to two sides of the adapter backplane with the circuit layer again, and performing exposure and development (photolithography process) on the photosensitive barrier layer 30 to shield the circuit layer, exposing the hole metal 122 region; as shown in fig. 13, an etching process is used to remove the via metal 122 to form a via structure 123 in the interposer substrate, and remove the photosensitive barrier layer 30, thereby completing the manufacture of the interposer substrate 100, where the via structure 123 is used to embed electronic components, the electronic components are wire-bonded to the circuit layer on one side of the interposer substrate 100, and the electronic components are connected to the desired printed circuit board 300 (PCB) through the circuit layer on the other side of the interposer substrate 100.
As shown in fig. 14, the method for manufacturing a relay substrate further includes forming a solder resist layer 130 on the surfaces of the upper circuit layer 161 and the lower circuit layer 162, and windowing the solder resist layer 130 to form pads 131 corresponding to the upper circuit layer 161 and the lower circuit layer 162 of the relay substrate, specifically, manufacturing an outer solder resist layer 130 on the surfaces of the upper circuit layer 161 and the lower circuit layer 162 and exposing the pads 131. The solder mask layer 130 can protect the circuit layer inside the transfer substrate, the pad 131 is used for electrical connection of the transfer substrate, the surface of the pad 131 is a metal circuit layer, and the metal circuit layer is easily oxidized in the storage and use processes, so that the surface of the pad 131 is further subjected to anti-oxidation treatment, specifically, a protective layer 140 is formed on the surface of the pad 131, and the protective layer 140 can be subjected to surface treatment by depositing chemically stable metals such as nickel-palladium-gold, nickel-gold, tin, silver and the like, and further comprises covering with an organic solder mask.
Referring to fig. 15 to 19, in some embodiments of the present application, a metal seed layer 150 is further deposited, and the metal seed layer 150 is etched, so that the metal seed layer 150 is attached to the lower surface of the upper circuit layer 161 and the upper surface of the lower circuit layer 162, specifically, as shown in fig. 15, the metal seed layer 150 is deposited on the upper surface and the lower surface of the interposer substrate structure shown in fig. 14, specifically, the metal seed layer 150 is formed on the upper surface and the lower surface of the interposer substrate structure respectively by using a physical sputtering method, and the metal seed layer 150 can increase adhesion between metal and metal, and in addition, when a metal circuit layer is plated on the basis of the metal seed layer 150, the plating quality of the circuit layer can be; attaching the photosensitive barrier layer 30 to the upper and lower surfaces of the metal seed layer 150, and performing photolithography processing on the photosensitive barrier layer 30 to form patterns corresponding to the upper circuit layer 161 and the lower circuit layer 162 on the upper and lower surfaces of the adapter substrate, respectively; as shown in fig. 16, depositing metal on the corresponding pattern of the upper circuit layer 161 and the lower circuit layer 162, specifically, electroplating copper by using an electroplating process to form the upper circuit layer 161 and the lower circuit layer 162, removing the photosensitive barrier layer 30, and etching away the metal seed layer 150 outside the position of the circuit layer to make the metal seed layer 150 consistent with the circuit layer; as shown in fig. 17, the photosensitive barrier layer 30 is attached to both sides of the adapter substrate with the circuit layer again, and the photosensitive barrier layer 30 is exposed and developed (photolithography process) to shield the circuit layer and expose the metal outlet 122 region; as shown in fig. 18, an etching process is used to remove the via metal 122 to form a via structure 123 in the interposer substrate, and remove the photosensitive barrier layer 30, the via structure 123 divides the interposer substrate into a plurality of independent interposer substrates 100, and due to the shielding protection of the photosensitive barrier layer 30, the upper surface and the lower surface of the interposer substrate 100 respectively retain an upper circuit layer 161, a lower circuit layer 162 and a metal seed layer 150; as shown in fig. 19, the solder resist layer 130 is formed on the surfaces of the upper wiring layer 161 and the lower wiring layer 162, and the solder resist layer 130 is windowed to form the pads 131 with the upper wiring layer 161 and the lower wiring layer 162 of the relay substrate, specifically, the outer solder resist layer 130 is formed on the upper and lower surfaces of the relay substrate to expose the pads 131. The solder mask layer 130 can protect an internal circuit layer of the transfer substrate, the position of the pad 131 is used for electrical connection of the transfer substrate, the surface of the pad 131 is a metal circuit layer, and the metal circuit layer is easily oxidized in the storage and use processes, so that the surface of the pad 131 is further subjected to anti-oxidation treatment, specifically, a protective layer 140 is formed on the surface of the pad 131, the protective layer 140 can be subjected to surface treatment by depositing chemically stable metals such as nickel-palladium-gold, nickel-gold, tin, silver and the like, and the surface treatment is further performed by covering an organic solder mask.
Referring to fig. 13, the present application provides an interposer substrate including a dielectric layer 110; metal column 121, set up inside dielectric layer 110, level with dielectric layer 110; the circuit layer comprises an upper circuit layer 161 and a lower circuit layer 162 which are respectively arranged on the upper surface and the lower surface of the dielectric layer 110, and two ends of the metal column 121 are respectively communicated with the upper circuit layer 161 and the lower circuit layer 162; and the through hole structure 123 penetrates through the dielectric layer 110.
In one embodiment, the interposer substrate is composed of a dielectric layer 110, metal pillars 121, a circuit layer and a via structure 123, the metal pillars 121 are embedded in the dielectric layer 110, the circuit layer includes an upper circuit layer 161 and a lower circuit layer 162 respectively disposed on the upper surface and the lower surface of the metal pillars 121, the via structure 123 is disposed through the dielectric layer 110 to divide the interposer substrate into a plurality of interposer substrate sub-structures, each interposer substrate sub-structure includes at least one metal pillar 121 and at least one upper circuit layer 161 and one lower circuit layer 162 connected to the metal pillar 121, the via structure 123 is used for embedding electronic components, the electronic components are connected to the circuit layer on one surface of the interposer substrate sub-structure by wire bonding, the electronic components are connected to a desired printed circuit board 300 through the circuit layer on the other surface of the interposer substrate, and compared with the conventional connection method of direct wire bonding between the electronic components and the printed circuit board 300, the routing distance can be shortened through the switching substrate, and the transmission quality of circuit signals is improved.
Referring to fig. 14, in some embodiments of the present application, the interposer further includes a solder resist layer 130 disposed on the surfaces of the upper circuit layer 161 and the lower circuit layer 162, the solder resist layer 130 is provided with a pad 131, the pad 131 is connected to the circuit layer, the solder resist layer 130 can protect the inner circuit layer of the interposer, and the pad 131 is used for electrical connection of the interposer.
In an embodiment, the surface of the pad 131 is a metal circuit layer, and the metal circuit layer is easily oxidized during storage and use, so that the surface of the pad 131 is further subjected to an anti-oxidation treatment, specifically, a protective layer 140 is formed on the surface of the pad 131, and the protective layer 140 can be subjected to a surface treatment by depositing chemically stable metals such as ni-pd-au, ni-au, sn, and ag, and further including covering with an organic solderability preservative film.
Referring to fig. 18 or 19, in some embodiments of the present application, a metal seed layer 150 is further included, and the metal seed layer 150 is attached to a lower surface of the upper line layer 161 and an upper surface of the lower line layer 162.
In one embodiment, the metal seed layer 150 can increase the adhesion between metals, and can improve the plating quality of the circuit layer when the metal circuit layer is plated on the metal seed layer 150.
Referring to fig. 23, the present application provides a device package structure, including the interposer substrate 100 in the above embodiments, the interposer substrate 100; an electronic device 200 disposed at the via structure 123, the electronic device 200 being in communication with the upper wiring layer 161 or the lower wiring layer 162 of the relay substrate 100; a printed circuit board 300 having a surface provided with a solder joint; a first substrate 400 disposed between the relay substrate 100 and the printed circuit board 300, for electrically connecting the electronic device 200 and the printed circuit board 300 by communicating with the lower wiring layer 162 or the upper wiring layer 161 and the soldering points; and a molding layer 500 covering the surface of the electronic device 200 for insulating and protecting the electronic device 200.
The application provides a device packaging structure, still includes solder mask 130, sets up on circuit layer 161 and circuit layer 162 surface down, and solder mask 130 is provided with pad 131, and pad 131 is connected with circuit layer 161 and circuit layer 162 down.
Referring to fig. 20 to 23, in an embodiment, the device package structure includes a printed circuit board 300, a first substrate 400, an electronic device 200, an interposer substrate 100, and a plastic package layer 500, where the interposer substrate 100 is connected to the first substrate 400 by a bonding pad 131, the electronic device 200 such as a chip and an inductor resistor is soldered on the interposer substrate 100 by a wire bonding method of metal bonding, after the electronic device 200 is bonded to the interposer substrate 100, the electronic device 200 is first encapsulated and protected by the plastic package layer 500, and after the encapsulated electronic device 200, the interposer substrate 100, and the first substrate 400 are soldered on the printed circuit board 300, specifically, as shown in fig. 20, the interposer substrate 100 shown in fig. 14 is soldered on the first substrate 400; as shown in fig. 21, the electronic device 200 is attached to the relay substrate 100 at the position of the via structure 123; wire bonding the electronic device 200 and the relay substrate 100; as shown in fig. 22, after the electronic device 200 and the interposer substrate 100 are bonded, mold encapsulation is performed through the encapsulation layer 500, and the encapsulation layer 500 can perform insulating and protecting functions; as shown in fig. 23, after the molding is completed, the package is soldered to a printed circuit board 500, i.e., a PCB main board.
It should be noted that the electronic device 200 includes, but is not limited to, a device and a chip, and may be an active device, a passive device, an independent chip or device, or a combination of multiple chips or devices, and may be different power devices according to the classification of the application, or may be a radio frequency or logic chip, and the type and number of the chips or devices may be a combination of multiple chips stacked back to back according to 3D requirements, or may be a combined design of an upper, lower, left, and right single-layer array. Compared with the traditional packaging mode of directly bonding the electronic components on the PCB mainboard, the lead bonding mode of connecting through the switching substrate 100 can shorten the packaging lead length of the electronic components, the reduction of the packaging lead length can not only improve the reliability of a product circuit, but also reduce the parasitic inductance resistance generated by overlong lead length, and simultaneously, the routing distance is shortened, and the cost can also be reduced.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are included in the scope of the present invention defined by the claims.
Claims (13)
1. A manufacturing method of an adapter substrate is characterized by comprising the following steps:
providing a carrier plate, wherein the carrier plate is of a symmetrical structure, and metal layers are respectively arranged on the upper surface and the lower surface of the carrier plate;
manufacturing metal columns and hole metals on the upper surface and/or the lower surface of the carrier plate, wherein the metal columns and the hole metals are connected with the metal layers arranged on the upper surface and/or the lower surface of the carrier plate;
laminating a dielectric layer on the upper surface and/or the lower surface of the carrier plate, wherein the dielectric layer covers the metal column and the hole metal;
polishing the dielectric layer to enable the dielectric layer to be flush with the metal columns and the hole metal, wherein the dielectric layer, the metal columns and the hole metal form a switching bottom plate;
etching the metal layer on the upper surface and/or the lower surface of the carrier plate to separate the carrier plate from the transfer base plate, and performing graphic manufacturing on the upper surface and the lower surface of the transfer base plate to form a plurality of upper circuit layers and a plurality of lower circuit layers;
and etching the hole metal to form a through hole structure.
2. The interposer substrate manufacturing method according to claim 1, further comprising: and forming a solder mask on the surfaces of the upper circuit layer and the lower circuit layer, windowing the solder mask, and forming a welding pad corresponding to the upper circuit layer and the lower circuit layer.
3. The method according to claim 2, further comprising forming a protective layer on the surface of the bonding pad.
4. The interposer substrate fabrication method of claim 3, wherein the protective layer material comprises Ni-Au, NiPdAu, Sn, Ag or organic solderability preservative.
5. The method for manufacturing the interposer substrate according to any one of claims 1 to 4, further comprising depositing a metal seed layer, and etching the metal seed layer to attach the metal seed layer to the lower surface of the upper circuit layer and the upper surface of the lower circuit layer.
6. The method for manufacturing a relay substrate according to claim 1, wherein the metal layers disposed on the upper surface and the lower surface of the carrier include a first metal layer and a second metal layer, and the first metal layer and the second metal layer can be separated by physical peeling.
7. An interposer substrate, comprising:
a dielectric layer;
the metal column is arranged in the dielectric layer and is flush with the dielectric layer;
the circuit layer comprises an upper circuit layer and a lower circuit layer which are respectively arranged on the upper surface and the lower surface of the dielectric layer, and two ends of the metal column are respectively communicated with the upper circuit layer and the lower circuit layer;
the through hole structure is arranged in the dielectric layer in a penetrating mode.
8. The interposer substrate of claim 7, further comprising a solder mask disposed on the upper and lower circuit layers, the solder mask having a pad connected to the upper and lower circuit layers.
9. The interposer substrate of claim 8, further comprising a protective layer disposed on the upper surface of the bonding pad.
10. The interposer substrate of claim 9, wherein the protective layer material comprises nickel-gold, nickel-palladium-gold, tin, silver, or an organic soldermask.
11. The interposer substrate of any one of claims 7-10, further comprising a metal seed layer attached to the lower surface of the upper circuit layer and the upper surface of the lower circuit layer.
12. A device packaging structure, comprising:
the switching substrate comprises a dielectric layer, a metal column, a through hole structure and a circuit layer, wherein the circuit layer comprises an upper circuit layer and a lower circuit layer which are respectively arranged on the upper surface and the lower surface of the dielectric layer and communicated with the metal column;
an electronic device disposed at the via structure, the electronic device being in communication with the upper line layer or the lower line layer;
the surface of the printed circuit board is provided with a welding point;
the first substrate is arranged between the adapter substrate and the printed circuit board and is communicated with the lower circuit layer or the upper circuit layer and the welding points so that the electronic device is electrically communicated with the printed circuit board;
and the plastic packaging layer covers the surface of the electronic device.
13. The device package structure of claim 12, further comprising a solder mask disposed on the upper and lower circuit layers, the solder mask being provided with pads connected to the upper and lower circuit layers.
Priority Applications (1)
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| CN202010876464.4A CN112103194A (en) | 2020-08-27 | 2020-08-27 | Switching substrate, manufacturing method thereof and device packaging structure |
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| CN202010876464.4A CN112103194A (en) | 2020-08-27 | 2020-08-27 | Switching substrate, manufacturing method thereof and device packaging structure |
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Application publication date: 20201218 |