TW200933587A - Scanning signal line driving circuit and display device - Google Patents

Abstract

It is possible to realize a scan signal line drive circuit having a high resistance against a noise which fluctuates the level to the High side and hardly causing a display trouble. A gate driver (4) to be arranged on a TFT liquid crystal panel includes a shift register (10d) to which a D-FF (11) is cascade-connected. A signal is outputted from a data output terminal (Q) of the D-FF (11). Here, the data output terminal (Q) of the D-FF (11) is connected to a pull-down resistor (Rd). Accordingly, even if a noise fluctuating the level to the High side is received, it is possible to prevent the level fluctuation of the signal from the data output terminal of the D-FF. This prevents generation of a display trouble caused by a noise which turns ON a gate line which does not perform display.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning signal line driving circuit for applying a scanning signal to a scanning signal line of a display screen, and a display device using the scanning signal line driving circuit. • [Prior Art] In recent years, a large number of electromagnetic wave generating sources such as electronic equipment, electric machines, and wireless devices have been around the side. Electromagnetic waves from these electromagnetic wave generating sources may have various effects on the surrounding electromagnetic environment, and electronic devices that are sources of electromagnetic waves may themselves be affected by electromagnetic waves from other electromagnetic wave generating sources. Therefore, for an electronic device or the like, it is necessary to prevent electromagnetic waves from being released to the outside of the machine, and it is necessary to have resistance to the surrounding electromagnetic environment. The evaluation specifications of electromagnetic waves with respect to such electronic devices and the like have been established, and in particular, as a specification for analog electrostatic discharge, there is IEC 61〇〇〇_4_2. On the other hand, the test corresponding to the IEC6100 (M-2 specification is performed by a pulse generation device called ESD (Electr〇 static discharge). For the display device such as a liquid crystal display, as described above, By electrostatically simulating and testing the ESD, it is confirmed that there is no influence on the display. Further, a technique for improving the resistance to electromagnetic waves such as electronic equipment has been developed (for example, 'Patent Document 丨). The structure of the semiconductor wafer 91 disclosed in Patent Document 1 is shown. A plurality of peripheral portion pads 92, I35476.doc 200933587, are provided on the outer peripheral portion of the semiconductor wafer 91, and are connected to the outside by wires 93. Further, in the semiconductor On the wafer surface other than the peripheral pad 92 of the wafer 91, a plurality of central portion pads 94 are provided in a linear and lattice-like manner. A top φ μ & The wire 95 is continuously connected by wire bonding. With the above configuration, the voltage drop due to the resistance can be reduced, and the potential of the wiring can be reduced, and the temperature can be reduced. Lt; can prevent malfunction due to power supply noise, etc. [Patent Document 1]

曰 公开 公开 日本 日本 日本 日本 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 2005 The noise to the l〇w side is slightly improved, but when the noise is changed to the high side, a problem that the malfunction is likely to occur is generated. In particular, in a display device such as a TFT (Thin FUm Transistor) liquid crystal panel, when the gate line is unintentionally turned on by causing the level to be changed to the noise on the High side, there is a possibility that the gate line may be generated. The display of the horizontal line is abnormal. The following 'will be explained in detail. Fig. 13 is a schematic view showing the configuration of a conventional representative TFT liquid crystal panel 101. The TFT liquid crystal panel 1〇1 includes a glass substrate 1〇2, a source driver 1〇3, and a gate driver 104. A TFT 107 is formed on the glass substrate 1〇2, and a pixel 108 in which liquid crystal is sandwiched between the pixel electrodes is connected to the drain of the TFT 107. Also, Ding? A source line 1〇5 is connected to the source of 1'107, and the source line 105 is connected to the driving output of the source driver 1〇3. The gate of TFT1〇7 is connected to 135476.doc 200933587. The interpole line 106' is connected to the driving output of the gate driver ι4. The TFT 107 is turned on by applying a signal of the gate line 1〇6 to the gate, and a signal of the source line 105 is applied to the pixel 1〇8. The signal that has been given to the pixel ι8 is accumulated in the pixel 1〇8 as a voltage between the counter electrode 1〇9, and the transmittance level of the liquid crystal in the pixel 1〇8 is determined by the voltage. And thus enter the line display. Fig. 14 is a circuit diagram showing the configuration of the gate driver 丨〇4. The gate drive © 〇4 has a shift register 11A, a level shifter circuit ι2, an output buffer 113, and an output terminal 114. The shift register 11 is composed of seven 1) 汴 17 (〇 flip-flops) U1, and signals from the outputs Q1 to Q7 of the D-FF (1) are input to the level shifter circuit 112, and the signal level is Converted. The signal from the level shifter circuit 112 is output from the output terminal 113 to the gate line via the output buffer 112. In the shift register 11 各, each D_FF 动 is operated by the operation clock clk, and the signals input from the input IN are sequentially output to Q1 to Q7 at the timing of the operation clock cLK. The gate driver 1 〇 4 is mounted such that one output corresponds to one gate line 106, and the gate line 1 〇 6 is sequentially driven for the display of the TFT liquid crystal panel ι 〇. The outputs Q1 to Q7 of the shift register 110 are normally low, and the high pulse is input to the input ... to indicate the start timing of the display, and the extension pulse is sequentially shifted. The shifted High pulse in the shift register 110 sequentially turns the gate line 106 to High, and turns on the TFT 107, thereby performing a facet display. 135476.doc 200933587 Here, the semiconductor integrated circuit like the gate driver 104 is supplied with a source of t from a power supply terminal 位于 located at the periphery thereof. The tendency of miniaturization or wafer size increase by 9 recent processes, as described in the background art of the patent document, increases the resistance of the power supply wiring from the source region + the source to the active region of the wafer β until it cannot be ignored. The degree, & is the cause of malfunction caused by power noise. The above-mentioned line resistance affects not only the power supply but also the signal wiring.

Specifically, when the test for the simulated electrostatic discharge disclosed in the background art is performed on the TFT liquid crystal panel 1〇1 shown in Fig. 13, an abnormality of the horizontal bright line may occur on the display surface. When the cause of the display abnormality is analyzed, it is found that the gate driver 104 is inadvertently caused by the level change caused by the noise of the level shift to the mgh side on the input side of the D_FF 111 and the input buffer 113. The gate line 1〇6 is turned on, so the display t produces a horizontal bright line. In this way, the level of each output of the #shift register 110 is changed to the high side by the noise, and the output of the gate driver 104 is in the High state except when the original timing of the High pulse is output, which causes the original not to be performed. ^ The gate line 106 is turned "on" to cause a display abnormality. And, when the output of D_FF1U of one part of the shift register 110 is in a High state by noise, and the input of D_FFU1 of the next stage is read into the High level, in the shift register 11? In addition to the two pulses of the normal shift, the High pulse generated by the noise also shifts, causing the display to be abnormal continuously from §. Thus, the noise that causes the level to shift to the High side, as disclosed in the patent document 135476.doc 200933587, cannot improve the noise tolerance by reducing the voltage drop of the wiring resistance. The present invention has been made in view of the above problems, and an object thereof is to realize a scanning signal line drive circuit and a display device which are highly resistant to noise which causes the level to shift to the exit side and which are less likely to cause display abnormality. 10 ❹ In order to solve the above problem, the scanning signal line drive circuit of the present invention includes a second shift register in which M (M is an integer of 2 or more) flip-flops are connected in series. The first shift register The input signal from the external input is sequentially transmitted to the forward and reverse inverters in synchronization with the clock signal, and the output is output from the data output terminals of the respective flip-flops! The shift pulse is used to drive the scanning signal line of the display surface, wherein the pull-down resistor is connected to the data output terminal of at least one of the flip-flops. According to the above configuration, the M flip-flops of the first shift register sequentially output the input signal to sequentially output the first shift pulse for driving the scanning signal line. Here, the pull-down resistor is connected to the data output terminal ' of at least one of the flip-flops, and when the noise that causes the level to shift to the High side is received from the outside, the pull-down resistor functions to cancel the first! The level of shifting changes. As a result, it is possible to prevent the display from being abnormal due to the unintended timing, the first shift pulse being High and the display being abnormal. Therefore, the effect of the scan line circuit as described below can be realized by the pole line conduction, that is, the scanning chip drive circuit drives the circuit to increase the level of noise to the side of the piano. It is not easy to produce display abnormalities. The scanning signal line_circuit t of the present invention is preferably connected to the second shifting of the flip-flops, the serial-level bit register and the logic circuit, and the J35476.doc 200933587 2 shift The register transmits the domain input signal inversion and the synchronously to the flip-flop in the subsequent stage, and outputs the second shift pulse from the private output. The pull-up resistor is connected to the second shift register. At least __ of the flip-flops of the data output terminal of the flip-flop, the logic circuit respectively receives the nth (n is an integer of (1) upper than the integer) of the first register from the first register The old bit pulse, and the inverted pulse of the second shift pulse from the flip-flop of the second stage of the above-mentioned register

The logical sum is output as the third shift pulse, and the scanning signal line is driven by the third shift pulse. According to the above configuration, in addition to the correction shift register, the second shift register H is further provided, and the flip-flop system constituting the second shift register is sequentially transferred in reverse to the first shift register. The inverted signal of the input signal is output and the (3)th pulse is extracted. Here, the pull-up resistor is connected to the data output terminal of at least one of the flip-flops of the second shift register, and the pull-up resistor functions when the external level is changed to the noise of the Low side. The level shift of the second shift pulse to the Low side is cancelled. Further, the logic circuit acquires the inversion pulse of the second shift pulse and the second shift pulse from the flip-flops of the second stage of the second shift register and the second shift register, and the The logical sum is output as the third shift pulse, and the scanning signal line is driven. Therefore, even if the level shifts to the noise on the Low side, the shift of the first shift register is interrupted, and the first shift pulse disappears. The inverted pulse of the second shift pulse can also be used as the third shift. The bit pulse is output. Here, the 'second shift pulse is output by shifting the inverted signal of the input signal. Therefore, the waveform of the inverted pulse of the second shift pulse is shifted to the first shift when the normal shift is 135476.doc 200933587 The waveform of the pulse is the same. Therefore, even when the noise is received from the outside to change the level to the Low side, the first! When the shift pulse disappears, and the second shift pulse does not disappear, the waveform of the third shift pulse is the same as the waveform of the first shift pulse when it is normally shifted. As described above, since the second shift pulse is less likely to cause level fluctuation with respect to the noise that causes the level to shift to the L〇w side, the third shift pulse is not only opposite to the level shifting to the high side noise. Level fluctuations are less likely to occur, and level fluctuations are less likely to occur with respect to noise that causes the level to shift to the Low side. Therefore, it is possible to realize the scanning signal line driving circuit 0 which is highly resistant to both the noise which changes the level to the High side and the noise which changes the level to the Low side. In order to solve the above problem, the scanning of the present invention The signal line driving circuit has a second shift register in which M (M is an integer of 2 or more) flip-flops are connected in series, and the first shift register synchronizes the input signal from the external input with the clock signal. The ground is sequentially transmitted to the flip-flops of the rear stage, and the first shift pulse is outputted from the data output terminals of the respective flip-flops to drive the scanning signal lines of the display surface, which is characterized by At least one of the flip-flops of the device has the first input of the material input terminal of the flip-flop! Transmission gate, first! An inverter, a second transmission interpole, a second inverter, and a first buffer circuit constituting a data output terminal, the data input terminal, the first transmission gate, the i-th inverter, and the second transmission idler, The second inverter and the m-thrush circuit are connected in this order, and a first pull-up resistor is disposed at the second connection point between the phaser and the second transfer gate. A first pull-down resistor is provided at a point 2 of the second connection I35476.doc 200933587 between the nth and the ith buffer circuits. According to the configuration, the M flip-flops of the i-th shift register sequentially transmit the ^ number, thereby outputting the first shift pulse S for driving the scan signal line to be in at least one flip-flop. A pull-up resistor is disposed at a first connection point between the first inverter and the second transmission idler, and the second inverter is provided.

Like the 1st buffer circuit. The second pull-down resistor is set at the second connection point between A and A, so that the inside of the rain/reactor can be lifted relative to the side that causes the level to change to the side.

Ifl's resistance to H is such that the "second shift pulse" does not easily cause level fluctuation even if it receives noise that causes the level to shift to the High side. As a result, it is possible to prevent display abnormality caused by the first shift pulse being turned to High and the gate line being turned on by the unintended timing. Therefore, there is an effect that the scanning signal line drive circuit can be realized, and the scanning signal circuit is more resistant to noise that causes the level to shift to the High side, and display abnormality is less likely to occur. In the scanning signal line drive circuit A of the present invention, the first pull-up resistor may be provided instead of the above-mentioned first! a connection point is provided at a third connection point between the second transmission closing pole and the second inverter, and the first pull-down resistor may be provided in the second connection point instead of the second connection point The fourth connection point between the transmission gate and the first inverter described above. According to the above configuration, the first pull-up resistor is provided at the third connection point between the second transfer gate and the second inverter, and is! The pull-down resistor is provided at the fourth connection point between the second transfer gate and the first inverter, so that the resistance of the inside of the flip-flop to the noise on the high side can be improved. Therefore, even if the first shift pulse is received, the level shift is not easily caused by the level shifting to the high side 135476.doc 12 200933587. In the scanning signal line driving circuit of the present invention, the fi inverter may be composed of a first transistor that outputs a high level signal and a signal that outputs a low level: a second transistor, and the second inverter may be The output of the third transistor is formed by the third transistor of the signal and the fourth transistor that outputs the signal of the low level. Alternatively, the first pull-up resistor and the pull-down resistor may be provided instead of the first transistor. The driving ability is set higher than the driving ability of the second transistor described above, and the driving ability of the fourth transistor can be set higher than the driving ability of the third transistor. According to the above configuration, since the driving ability of the first transistor of the signal of the high level of the output of the first inverter is higher than the second transistor of the signal of the output low level, the pull-up resistor is set to be inverted. The same state as at the first connection point between the second transmission idler and the second transmission idler. &, because the driving ability of the fourth transistor of the signal of the low level of the output of the second inverter is higher than that of the third transistor of the signal of the second high level, the sigh of the pull-down resistor is placed at the second The second connection point between the inverter and the first buffer circuit is the same as n, so that the tolerance of the inside of the flip-flop can be improved with respect to the noise that causes the level to shift to the High side. The configuration is such that even if the noise that causes the level to shift to the High side is received, the first shift pulse is not easily generated - a level shift occurs. In the scanning signal line driving circuit of the present invention, it is preferable to further include a second shift register and a plurality of logic circuits in which a flip-flop is connected in series, and the second shift register inputs the input. The signal inversion signal is sequentially transmitted to the rear-stage flip-flop in synchronization with the above-mentioned clock signal, and the data is output from each flip-flop 135476.doc 200933587 terminal output second shift pulse 'the above-mentioned p-shift register At least one of the flip-flops includes a third transmission gate, a third inverter, a fourth transmission gate, a fourth inverter, and a constituent data output that constitute the data input terminal of the flip-flop t a second buffer circuit of the terminal, wherein the data input terminal, the third transfer gate, the third inverter, the fourth transfer gate, the fourth inverter, and the second buffer circuit are sequentially connected to the third counter A second pull-down resistor is provided at a fifth connection point between the phase detector and the fourth transmission gate, and a second connection point is provided at a sixth connection point between the fourth inverter and the second buffer circuit. Pulling the resistance, the logic circuit described above is the first >^" from the first shift register a logical sum of a first shift pulse of the flip-flop of the upper and lower integers and an inverted pulse of the second shift pulse of the flip-flop from the Nth stage of the second shift register; The third shift pulse is output, and the scanning signal line is driven by the third shift pulse. According to the above configuration, in addition to the first shift register, a second shift register is further provided. The flip-flop constituting the second shift register sequentially transmits the inverted signal of the input signal in reverse to the second shift register φ, and outputs the second shift pulse. Here, the second shift In at least one of the flip-flops of the register, a second lower pull resistance is provided at the fifth connection point between the third inverter and the fourth transfer gate to the fourth inverter and the second buffer Since the second pull-up resistor is provided at the sixth connection point between the circuits, the tolerance of the inside of the flip-flop to the noise that causes the level to shift to the Low side can be improved. Therefore, even the second shift pulse Receiving the noise that causes the level to change to the Low side, the level change is not easy to occur. Further, the logic circuit obtains the first shift from the temporary storage. And the second shift temporary storage 135476.doc -14- 200933587 ^r^i catches the logical sum of the first shift pulse of the flip-flop and the reverse pulse of the second shift pulse and 'puts the logic And outputting the scanning signal line as the third shift pulse, whereby even if the level shifts to the noise on the Low side, the shift of the shift register is interrupted and the first shift pulse is made/ The second shift pulse inversion pulse can also be output as the third shift pulse, and the second shift pulse is output by shifting the inverted signal of the input signal. Therefore, the second shift is performed. The waveform of the inversion pulse of the bit pulse is the same as the waveform of the first shift pulse at the time of the positive shift. Therefore, even if the noise is changed to the side of the L〇W side, the first time is received. When the shift pulse disappears, the waveform of the third shift pulse is the same as the waveform of the third shift pulse at the time of normal shift as long as the second shift pulse does not disappear. As described above, since the second shift pulse is less likely to cause a level fluctuation with respect to the noise that causes the level to shift to the L〇w side, the third shift pulse is not easily changed not only to the noise that causes the level to shift to the High side. A level change occurs, and level fluctuations are less likely to occur with respect to noise that causes the level to shift to the Low side. Therefore, it is possible to realize a scanning signal line drive circuit which is highly resistant to both the level shifting noise to the High side and the level shifting noise to the Low side. In the scanning signal line drive circuit of the present invention, the second pull-down resistor may be provided at the seventh connection point between the fourth transmission gate and the fourth inverter instead of the fifth connection point. The second pull-up resistor may be provided at the eighth connection point between the third transfer gate and the third inverter instead of being disposed at the sixth connection point. According to the above configuration, the second pull-down resistor is provided at the seventh connection point between the fourth transmission gate and the fourth 135476.doc 15-200933587 inverter, and the second pull-up resistor is disposed at the third gate and the third At the 8th connection point between the inverters, the inside of the flip-flop can be increased.卩 is relative to the tolerance of the noise that causes the level to change to the L〇w side. Therefore, even if the second shift pulse receives noise that causes the level to shift to the side, the level shift is less likely to occur. In the scanning signal line driving circuit of the present invention, the third inverter may be composed of a fifth transistor that outputs a signal of a high level and a sixth electrode that outputs a signal of a low level, the fourth inversion. The device may also be formed by a seventh transistor that outputs a high-order nickname and an eighth transistor that outputs a signal with a low level. Alternatively, instead of providing the second pull-up resistor and the second pull-down resistor, the sixth The driving ability of the transistor is set higher than the driving ability of the fifth transistor, and the driving ability of the seventh transistor can be set higher than the driving ability of the eighth transistor. According to the above configuration, the driving ability of the sixth electric solar cell of the signal of the output of the low level of the third inverter is still at the $th transistor of the signal of the high level, so that the pull-down resistor is set to the third counter. The same state as in the case of the fifth connection point between the phaser and the fourth transmission gate. Further, the driving ability of the seventh transistor of the signal of the high-level output of the fourth inverter is higher than the eighth transistor of the output low level, so that the pull-up resistor is set to the fourth inverter. The same state as in the case of the sixth connection point between the second buffer circuits. Therefore, it is possible to improve the tolerance of the inside of the flip-flop with respect to the noise that causes the level to shift to the side, and the Sunstar is succinct and sighs as follows: even if the level is changed to the Low side The miscellaneous, 筮, & , / < miscellaneous a second shift pulse is also less prone to level change 0 135476.doc 200933587; to solve the above problem, the scanning signal line driver circuit of the present invention has a string The stage is connected with M (M is an integer of 2 or more). The flip-flops are small (1) the first shift register, the cascade is connected to the flip-flops, and the second shift register and the Μ In the majority of the circuits, the number of the first shift register and the number of the second shift registers is an odd number of three or more. The first shift register inputs an input signal from the outside. The clock (4) is synchronously transmitted to the front and back of the forward and reverse, and from the respective forward and reverse devices

The material output terminal outputs a first shift pulse, and the pull-down resistor is connected to a data output terminal of at least one of the flip-flops of the first shift register, and the second shift register inputs the input signal The inversion signal is sequentially transmitted to the front and back H in synchronization with the clock signal, and the second shift pulse is output from the data output terminal of each flip-flop, and the pull-up resistor is connected to the second shift register. The data output terminal of at least one of the flip-flops of the flip-flop is 'the first shift register from the first shift register is one or more integers below the slave's second shift pulse, and An inversion pulse of the second shift pulse from the flip-flop of the second stage of the second shift register is input to each of the plurality of circuits, and the multi-turn circuit selects the input pulse The pulse having a large number of pulses outputs the result of the selection as the third shift pulse, and the scanning signal line of the display screen is driven by the third shift pulse. According to the above configuration, the first shift register and the second shift register are collectively set to an odd number of three or more. Here, as described above, with the pull-down resistor, the tolerance of the first shift register to the noise that causes the level to shift to the High side is improved, and the second shift is temporarily stored by the pull-up resistor. The tolerance of the device is improved relative to the noise of the 135476.doc -17-200933587 quasi-variable to the Low side. & Further' will be the same from the same segment of the first shift register and the second shift register! The inversion pulse of the shift pulse and the second shift pulse is input to a plurality of circuits, and most of the circuits select a pulse of a larger number of the input pulses and transmit the I as the third shift pulse to all the shift registers. When the shift operation is performed, the first shift pulse and the inverted pulse of the second shift pulse have the same waveform. Here, even when the noise is shifted to the Hggh side from the external level, or the level is changed to the L〇w side of the miscellaneous: 'The shift portion of the - part is malfunctioning, thereby making the input pulse &quot When the boring tool becomes a different waveform, since the majority of the circuits select a large number of pulses, the waveform of the third shift pulse is not different from the normal time. Therefore, it is possible to realize a scanning signal line driving circuit which is highly resistant to both the noise which changes the level to the ¥ side and the noise which causes the level fluctuation bw side to be high. Preferably, in the case where the plurality of upper mi shift registers or the second shift register are set, the plurality of first shift registers or the second shift registers are not arranged in phase with each other. 'Do not share the power supply wiring and GND wiring. The shift temporary storage 1^ is resistant to the noise of the material changing to the _ side - the higher the sensitivity, on the contrary, the phase recognition & Also, Chu; the resistance of the noise to the L〇W side of the '^ 2 shift register relative to the level shifting to the Low side of the δί (* tolerance to the age of the ancient side of the noise resistance Responsibility = the cause of the cause, relative to the level change to the device, set more third: such as 'when the second shift is temporarily stored in the multi-bit register, if the level changes to 135476. Doc •18· 200933587 The noise on the W side causes all the first shift registers to malfunction, and the third shift pulse from most circuits also becomes the error W number.] In view of this, according to the above configuration, The first shift register or the second shift register is not close to each other, and the second shift is disposed. The power supply wiring and the GND are not used. Therefore, the level shift can be reduced to just Side noise,

: The person moves the level to the noise on the L〇W side to cause a risk of malfunction of all of the first or second shift register. Therefore, the influence of the noise on the third shift pulse can be further reduced. A display device of the present invention includes the above-described scanning signal line drive circuit. According to the above configuration, the scanning signal line drive circuit is resistant to the level shifting to the noise on the High side, or the level shifting to the noise side of the coffee side and the level shifting to the noise side of the Low side. Since the average effect is '@', it is possible to realize a display device which is highly resistant to noise in which at least the level is shifted to the High side and which is less likely to cause display abnormality. As described above, in the scanning signal line driving circuit of the present invention, the pull-down resistor is connected to the data output terminal of at least one of the flip-flops, and thus the effect is that the level can be changed. The noise of the noise on the side of the (4) side is high, and it is difficult to generate a scanning signal line drive circuit that displays an abnormality. Still other objects, features, and advantages of the present invention will be apparent from the appended claims. Further, the benefits of the present invention can be made clear by reference to the following description in the accompanying drawings. [Embodiment] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings in 135476.doc -19-200933587. Further, in the following description, various limitations are set forth in the technical aspects of the invention, but the scope of the invention is not limited to the embodiments and the drawings below. [Embodiment 1] A first embodiment of the present invention will be described with reference to Fig. 1 and Fig. 2, and Fig. 2 is a schematic view showing a configuration of a TFT liquid crystal panel 1 of the present embodiment. The TFT liquid crystal panel 1 includes a glass substrate 2, a source driver 3, and a gate driver 4. The source substrate 5 and the gate line 6 are provided on the glass substrate 2, and the TFTs 7 and the pixels 8 are provided at the intersections of the source line 5 and the gate line 6, and the ends of the pixels 8 are connected to the counter electrode 9. Here, the glass substrate 2, the source driver 3, the source line 5, the gate line 6, the TFT 7, the pixel 8, and the counter electrode 9' of the TFT liquid crystal panel 1 are respectively connected to the TFT liquid crystal panel shown in FIG. The glass substrate 1〇2, the source driver 103, the source line 105, the gate line 1〇6, the TFT1〇7, the pixel 108, and the counter electrode 1〇9 of 1 are substantially the same, and thus detailed description thereof will be omitted. In the present embodiment, in order to enhance the resistance of the TFT liquid crystal panel to electromagnetic wave noise, the gate driver 4 is constructed as follows. Fig. 1 is a circuit diagram showing the configuration of the gate driver 4. The gate driver 4 is provided with a shift register 10d, 7 level shifter circuits 12, 7 output buffers 13 and 7 output terminals 14. The shift register 1〇d has 7 cascade connections. D-FF11. The D-FF 11, the level shifter circuit 12, the output buffer 13, and the output terminal 14 are substantially the same as the d_ffui, the level shifter circuit 112, the output buffer 113, and the output terminal ι4 shown in Fig. 14. Further, the number of the level shifter circuit 12 or the output buffer 13 is not limited to 7 135476.doc 200933587 ' can be appropriately set according to the number of gate lines to be scanned. The shift register l〇d has seven 〇_1?1711 connected in series, and the input signal D of the gate driver 4 is input to the data input terminal D of the D_FF1 of the initial stage of the shift register. When the D_FF11 of the shift register 1 〇d is shifted, the pulse terminal has the operation clock CLK, and the data output terminal Q of each D-FF 11 outputs the signals Qld to Q7d.

Further, in the shift register, the pull-down resistor is not connected to the data output terminal Q of each D_FFU. More specifically, one end of the pull-down resistor Rd is connected to the data output terminal Q of the DFF 11, and the other end of the pull-down resistor is grounded. Therefore, when the electromagnetic wave noise is received from the outside, the signals Qld to Q7d of the d_ffi 1 are changed to the High side, and the effect of canceling the level fluctuation is obtained. Therefore, it is possible to prevent the gate line which is not originally displayed from being turned on due to the level fluctuation to the noise on the mgh side, thereby causing an abnormal display. Further, the smaller the resistance value of the pull-down resistor Rd, the more the resistance to the noise on the high side can be improved, and conversely, the drive capability of the shift register Wd to output the High pulse is lowered. If the driving ability of the shift register i 〇 d is lowered, the normally shifted High pulse sometimes disappears when a noise that causes the level to shift to the Low side is received. Further, the resistance value of the pull-down resistor Rd becomes a relative value to the buffering capacity of each D_FF11, and the buffering capacity of each D-FFU differs depending on the circuit scale or the operating speed of the driving. Therefore, the pull-down resistor Rdi resistance value is set in consideration of the assumed noise, the buffering capability of the D-FF 11, and the like. 135476.doc -21 - 200933587 In the present embodiment, the pull-down resistors are provided in the respective data output terminals Q, but even if the pull-down resistor RdS is placed in the lean output terminal Q of at least one D-FF 11, Compared with the previous configuration, the noise tolerance can also be improved. Also, D-FFli can be other positive and negative devices such as JK type. [Embodiment 2] When the second embodiment of the present invention is described with reference to Figs. 3 to 6 , the gate driver 4 of the first embodiment described above is improved in the level shift to the High side. The noise is tolerated, but the resistance of the noise that causes the level to change to the L〇w side is lowered due to the provision of the pull-down resistor Rd'. Therefore, in the present embodiment, the following configuration will be described, and the configuration can improve the tolerance with respect to the noise that causes the level to shift to the L〇w side. Fig. 3 is a circuit diagram showing the configuration of the gate driver 24 of the present embodiment. The gate driver 24 is provided with two shift registers 10d, 10u, seven level shifter circuits 12, seven output buffers 13, seven output terminals 14, and seven 10 OR circuits 15. That is, the gate driver 24 is provided in the gate driver 4 shown in Fig. 1 and further includes shift register 1〇u and 〇R circuits. The composition. Similarly to the shift register 1〇d, the shift register l〇u also has seven D-FFs 11 connected in series, and the input signal IN of the gate driver 4 is input to the shift via the inverter INV1. The data input terminal D of D_FF11 at the beginning of the bit register 1〇11. Further, an operation clock CLK is also input to the clock terminal CK of each of the D-FFs 11 of the shift register l〇u, and signals Qlu to Q7u are output from the data output terminals Q of the respective D-FFs 11. Further, the data output terminal q of each D_FF11 of the shift register 10u is 135476.doc •22·200933587 The pull-up resistor Ru is connected. More specifically, one end of the pull-up resistor RU

The data connected to D-FF11 outputs her; η I Bayer® Chiss Q, and the other end of the pull-up resistor Ru is connected to the power supply potential. The self-shift register stores each of the D 1 outputs Xinqing d~Q7d, and the D_FF11 output signals of the self-shifted register 1〇U are called ~Q7u. signal

Qld to Q7d are input to one of the input terminals of each of the OR circuits 15 respectively. On the other hand, the signals Q1U to Q7u are input to the other of the input terminals of the respective OR circuits 15 via the inversion (four) ν. Thereby, in each of the NR circuits 15, the signal Qmd and the signal gamma are made to be embossed? The logic of the inverted signal of the integer) and the signal (4) is an integer of 1 to 7 and is rotated to the quasi-offset circuit 12. Each of the signals Q1 to Q7 is converted to a signal level by the level shifter circuit 12, and is output from the output terminal 14 to the closed line via the output buffer 13. Thus, the gate driver 24 of the present embodiment includes the shift register _ and the shift register 1 〇 U, the shift register, the shift register _ at each (four) 11 of the data output terminal Q A pull-down resistor Rd is disposed on the shift register Is H)U, and a pull-up resistor Ru is disposed on each D_FF11<f material output terminal Q, and the logic value and the shift register i〇d are shifted. The signal with the opposite signal produces a shift. The shift register 1 〇d has the effect of canceling the level change when receiving the electromagnetic noise from the outside and the position of the signal Qld to Q7d of the D-FFU is changed to the chat side. On the other hand, when the shift register 10u receives the electromagnetic wave noise from the outside, and the signal Q:~Q7u of the signal is changed to the L〇w side, the shift register 10u cancels the level change. effect. Further, the signal from the shift register 10d is "integer" I35476.doc • 23- 200933587 ” The signal training (9) from the shift register 1〇u is 卜? The integer number is inverted. The L number is input to the C) R circuit. The '10' circuit converts the logical sum of these signals as the signal Qm (m is an integer from 1 to 7). Therefore, even when the output of one of the shift registers 1 〇d · 1〇u disappears by the noise from the outside = 'the signals Q1 to Q7 do not disappear. Thus, the gate driver 4 can not only improve the resistance to the noise that causes the level to shift to the High side, but also improve the resistance to the noise that causes the level to shift to the L〇w side. ° ', the timing of the output k number from the shift register 1〇d. 1〇U&〇R circuit I5 will be described. Fig. 4 is a timing chart showing signal waveforms of signals Qld to Q7d, signals Qlu to Q7u, and signals Q1 to Q7 which are not normally received. When the input signal IN is input, in the shift register 1〇d, each D_FF1U&integration action clock CLK rises to shift the input signal IN, and outputs a signal.

Qld~Q7d. On the other hand, in the shift register 10u, each D-FF 11 shifts the inverted signal of the input signal IN in response to the rise of the operation clock CLK, and outputs signals Qlu to Q7u. The inverted signal of the signal Qmd and the signal Qmu (an integer of mg i to 7) is input to the OR circuit 15, and the 〇R circuit 15 outputs a signal Qm (m is an integer of 1 to 7) as the logical sum. Fig. 5 is a timing chart showing signal waveforms of signals Qld to Q7d, signals Qlu to Q7u, and signals Q1 to Q7 when the level shift is received to the noise on the l〇w side. In the shift register l〇d, the signal Q3diHigh pulse disappears due to the influence of noise, so the signals Q4d to Q7d are not output. On the other hand, in the shift register 10u, since the pull-up resistor Ru is provided on the data output terminal q of each D-FF 11, the signals Qlu to Q7u are not easily changed to the Low side. Since 135476.doc -24- 200933587, the shift register 1 〇u is not susceptible to the noise that causes the signal to change to the Low side, so that the signal Q3u$ disappears when the noise is generated. Therefore, the signals Qlu to Q7u are outputted in the same manner as usual in the absence of noise, and the inverted signals of the signals Qlu to Q7u are input to the 〇R circuit 15. Therefore, the output signals Q1 to Q7 from the OR circuit I5 become the same waveform as in the normal case.

Conversely, 'when receiving the noise that causes the signal to shift to the High side', even if the shift in the shift register 10u is interrupted, the shift register is less susceptible to the noise that causes the signal to shift to the High side. The effect, therefore, from the shift temporary storage benefits lOdi^fs wave Q1 d~Q7d will not disappear. Therefore, no influence of noise occurs in the output signals Q1 to Q7 from the circuit 15. As described above, the gate driver 4 can output the same signal as usual when receiving any of the noise that causes the signal to shift to the Low side and the noise that causes the signal to shift to the side. . Therefore, the TF liquid crystal panel including the gate driver 24 of the present embodiment is less likely to cause display abnormality even if electromagnetic wave noise is received from the outside. Further, in the 'gate driver 24, the signal Qmd from the shift register 1 is an integer of 1 to 7) and the signal from the bit register i〇u (m is an integer of 7) The circuit of the logical sum of the inverted signal is not limited to the OR circuit 15'. It can also be composed of the AND Relais „ 电路 circuit. That is, as shown in FIG. 6 , the inverted signal of the signal Qmd can also be transmitted to the viewer. The Qmu is input to the AND circuit 16, and the inversion of the output of the AND circuit 16 is outputted as the signal Qm to the level shifter circuit 12. [Embodiment 3] 135476.doc •25· 200933587

A third embodiment of the present invention will be described with reference to Figs. 7 to 9 as follows. In the second embodiment, a configuration in which a pull-down resistor or a pull-up resistor is connected between the data input terminals of the D_FF of the data output terminal = the lower stage is described. Thereby, the noise tolerance between the D-FFs can be improved, but since the internal circuit of the D-FF is affected by the noise, there is a variation in the output signal from the D-FF. In the present embodiment, the configuration in which the noise resistance of the gate driver is improved by the pull-down resistor and the pull-up resistor provided in the D_FF will be described. Fig. 7 is a circuit diagram showing the configuration of the gate driver 34 of the present embodiment. The gate driver 34 has the same configuration as that of the flip-flop driver 24 shown in Fig. 3, in which the shift register 30d·30U is provided instead of the shift register HM·l〇u. The shifting temporary device is configured as follows, that is, in the shift register i〇d shown in FIG. 3, the pull-down resistor Rd is not provided between the IFFs, but is instead set to replace the dffu, and each DFF3id output signal Qlld~Q17d. Moreover, the shift register 3〇U is configured as follows. In the shift register l〇u shown in FIG. 3, the pull-up resistor Ru is not provided between the D-FFs, but D_FF31u is set instead. , each D_ FF3U output signal qUu~Q17u. The same components as those of the gate driver 24 shown in Fig. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. Both D FF31d and D-FF3 1u have pull-down resistors and pull-up resistors internally. The D-FF 31d is configured to strengthen the text resistance with respect to the noise that causes the signal to shift to the mgh side. On the other hand, d_FF3u is a configuration for enhancing the resistance to noise that causes the signal to shift to the Low side. 135476.doc • 26 - 200933587 Therefore, the signals Q11 d~Q 17d are not easily affected by the noise that changes to the High side, and the signals Ql 1 u~Q 1 7u are not susceptible to noise that changes to the Low side. Further, an inverted signal of the signal Qnd (n is an integer of 11 to 17) and the signal Qnu (where n is an integer of 11 to 17) is input to the OR circuit 15, and the OR circuit 15 uses the logical sum of the signals as the signal Qm ( m is an integer from 1 to 7 and is output. Therefore, even when the output of one of the shift registers 30d · 30u disappears by noise from the outside, the signals Q1 to Q7 do not disappear.继 Next, the specific configuration of D-FF3 1 d · 3 1 u will be described. ❹ Fig. 8 is a circuit diagram showing the detailed configuration of the D-FF3 Id. D-FF3 Id has eight P-channel MOS (Metal Oxide Semiconductor) transistors P1 to P8 (hereinafter, transistors P1 to P8) and eight 1^ channels! ^〇8 Electric body N1~ N8 (hereinafter, transistors N1 to N8), three inverters INV3, and a buffer BUFF. One of the operation clocks CLK input to the clock input terminal CK becomes the signal CKD via the two inverters INV3. Further, the other one of the operation clocks Clk input to the clock input terminal CK becomes the signal CKDB via one inverter INV3. The two transistors P1 · N1 form the transmission gate (the third transmission gate), and the signal from the data input terminal D is input to the transmission gate. Electrode (4)

The signal input CKD is input to the middle, and the signal CKDB is input to the gate of the transistor N1. " J 2 transistors Ρ2· N2 constitute an inverter (first inverter). Further, * transistors P5' Ρ 6 · Ν 6 · N5 are connected in series. Specifically, the source of the transistor P5 is connected to the power supply potential, and the terminal of the transistor p5 is connected to the source of the transistor P6. The pole of 6 is connected to the transistor, and the source of the body N6 is connected to the pole of the transistor N5, and the source of the body N5 is grounded. A signal (10) is input to the gate of the transistor P5, and a signal CKDB is input to the opening of the transistor milk. The output of the magic transmission gate formed by the transistors P1 · N1 is input to the ?! inverter composed of the transistors P2 · N2, the drain of the transistor ?6, and the gate of the transistor N6. Two transistors P3. N3 also constitute the transmission gate (second transmission gate), the drain of transistor P2, the gate of transistor N2, the gate of transistor p6, the gate of transistor N6 And the inputs of the second transmission gate are connected to each other. A signal CKDB is input to the gate of the transistor P3, and a signal CKD is input to the gate of the transistor. Two transistors P4 · N4 constitute an inverter (second inverter). Further, four transistors P7 · P8 · N8 · N7 are connected in series. Specifically, the source of the transistor P7 is connected to the power supply potential, and the drain of the transistor p7 is connected to the source of the transistor P8. The drain of the transistor P8 is connected to the drain of the transistor N8, and the gate of the transistor N8 The source is connected to the drain of the transistor N7, and the source of the transistor is grounded. A signal CKDB is input to the gate of the transistor P7, and a signal CKD is input to the gate of the transistor. The output of the second transmission gate composed of the transistors P3 and N3 is input to the second inverter and the transistor composed of the transistors P4 and N4. The bungee of 8 and the crystal N8 are not. The drain of transistor P4, the drain of transistor N4, and the transistor? The gate of 8 and the gate of transistor N8 are both connected to the input terminal of the buffer BUFF. The output terminal of the buffer BUFF becomes the data output terminal q of D-FF3 1 d. 135476.doc • 28 - 200933587 Here, the connection point between the first transmission gate composed of the transistor P1 · N1 and the first inverter composed of the transistor P2 · N2 is taken as the point a ^ The connection point between the inverter composed of the electric bb body P2 and N2 and the transmission gate composed of the transistor ρ3·Ν3 serves as a point b. Further, a connection point between the transmission gate composed of the transistors P3 and N3 and the inverter composed of the transistors p4 and N4 is referred to as a point c. Further, the connection point between the inverter composed of the transistors ·4 · N4 and the buffer BUFF is taken as the point d. In the D-FF 31d, a pull-up eRu1 is further provided at the point b, and a pull-down resistor Rd1 is provided at the point d. Thereby, even if the noise that causes the level to shift to the High side is received, the buffer bUFF is received. The output signal, that is, the level of the output signal from the D-FF 3 Id is also not easily changed. That is, the pull-up resistor Ru 1 and the pull-down resistor Rd 1 increase the tolerance of the internal D-FF3 1 d to make the level change to the noise of the High side, and further replace the pull-up resistor Rul and pull-down. The resistor Rd1 increases the gate width of the transistor P2 and the transistor N4, or shortens the gate length, thereby increasing the driving ability of the transistor P2 and the transistor N4, so that the inside of the D-FF 31d can be improved in the same manner as described above. It is tolerant to the level of noise that changes the level to the High side. Further, the pull-down resistor Rd1 is provided at the point a, and the pull-up resistor Rui is provided at the point c. Thereby, the tolerance of the noise within the D_FF 31d to the high side can be similarly improved. Fig. 9 is a circuit diagram showing the detailed configuration of the D-FF 31U. D_FF3] u is constructed as follows. In the D-FF3 Id shown in FIG. 8, 'the pull-up resistor Ru1 is set instead of the point b, and the pull-down resistor Rd1 is set at the point d, and the lower 135476 is set at the point b. Doc -29- 200933587 Pull resistor Rd2, set pull-up resistor Ru2 at point d. Therefore, contrary to the D-FF 31d, the d-FF 31u receives the output signal from the buffer BUFF even if the noise is changed to the Low side, that is, the level of the output signal from the D-FF 31U is not easily changed. . That is, the pull-up resistor Ru2& pull-down resistor Rd2 can be used to improve the tolerance of the inside of the D-FF 31U for the noise level shifting to the Low side.

Furthermore, instead of providing the pull-up resistor RU2 and the pull-down resistor Rd2, the gate width of the transistor N2 and the transistor P4 is increased, or the gate length is shortened to improve the driving ability of the transistor N2 and the transistor P4. Similarly to the above, the tolerance of the inside of the D-FF3 1 u to the level of the noise on the L〇w side can be improved. Also, set the pull-up resistor at point a! ^12 ′Set pull-down resistor at point ^

Rd2, by this, can also similarly improve the tolerance of the inside of D_FF31u for making the level change to the noise on the Low side. Also, it can be configured as follows: In the gate driver 4 shown, the D-FF 11 is replaced with D_FF 31d. Further, in this case, a configuration in which the pull-down resistor Rd is not provided may be employed. The above-described configuration can improve the tolerance for the noise that causes the level to change to the exit pupil as compared with the previous configuration. [Fourth embodiment] A fourth embodiment will be described. The present invention will be described below with reference to Fig. 10 and Fig. 1.圑1 〇 indicates this fact _ · ~ 啊战1 The two-question driver 44 is configured as follows: In the 24 shown in Fig. 3, the shift register W is further provided, and s 135476 is provided instead of the ceramic road 15. Doc •30· 200933587 Number circuit 25 » The shift register 10e has seven D-FFns connected in series, similar to the shift register 1〇d, in the initial stage of the shift register 10e. The input signal ΙΝβ of the gate driver 44 is input to the data input terminal D of the FF11, and the action clock CLK is also input to the clock terminal CK of each D-FF11 of the shift register 10e, and each D_FF1 ^ The data output terminal q outputs signals Q1 e to Q7e 〇 and further 'like the shift register l 〇 d', the pull-down resistor is connected to the data output terminal q of each D-FF 11 of the shift register 〇e Specifically, one end of the pull-down resistor Rd is connected to the D_FF11i data output terminal Q, and the other end of the pull-down resistor Rd is grounded. The majority of the circuits 25 have three input terminals a to C and an output terminal q. When two or more of the input terminals A to C are High, the output becomes

When the input terminals a to C are two or more Low, the output becomes Low. The input terminals A to C of each of the plurality of circuits 25 are inputted with a signal Qmd (m is an integer from 1 to 7) from the shift register 10d, a twist signal from the signal Qmu of the shift register 10u, and The signal Qme of the shift register l〇e. Most of the circuits 25 output signals of the same waveform of two or more of the input signals as the signal Qm (m is an integer). Thereby, the signal Qmd, the signal Qmu, and the signal Qme are all in the same waveform without receiving noise from the outside. Here, even if any one of the shift registers 10d. 1〇u · 1〇e is malfunction due to noise, 'in the signal input to the majority circuit 25, the signal of the normal waveform 135476.doc -31 · 200933587 Occupy the majority' so the signal Qm from most circuits 25 is no different from the state in which no noise is received. As such, the resistance of the gate driver 44 to noise can also be improved. Further, it is preferable that the shift register 10d and the shift register 1〇e are disposed at separate positions of the integrated circuit, and the power supply or the GND wiring are also separated from each other. Therefore, when the gate driver 44 receives the noise that causes the level to shift to the side of the l〇w side, the risk of malfunction of the shift register 10 (1·i〇e) can be reduced. A circuit diagram showing a specific configuration of a plurality of circuits 25. The plurality of circuits 25 are provided with two AND circuits 25a. 25b. 25c and an OR circuit 25d. Signals from the input terminal A are input to the AND circuit 25a and the AND circuit 25b, and signals from the input terminal B. The input from the input circuit 25b and the AND circuit 25c, the signal from the input terminal C is input to the AND circuit 2A and the AND circuit 25c. The output from each of the AND circuits 25a, 25b, 25c is input to the 〇R circuit 25d, and the output of the OR circuit 25d. The terminal is a majority of the circuit and the output terminal Q. Further, the configuration shown in Fig. 11 is an example of a plurality of circuits, and other well-known circuits may be used. Alternatively, a plurality of circuits may be provided instead of the OR circuit, and the QR circuit may be provided. It may be configured as a logical sum of the output signal (4), the signal Qmu, and the signal Qme (m is an integer of the data 7.) In the present embodiment, the number of systems of the shift register is three, but the following may be Composition, ie A shift register of five or more odd-numbered systems is provided to acquire a majority of signals from the respective shift registers. [Summary of Embodiments] 135476.doc -32- 200933587 The present invention is not limited to the above In the embodiment, various modifications can be made within the scope of the claims, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the present invention. [Industrial Applicability] The present invention is preferably applied to a display device such as a liquid crystal display. The specific embodiments or examples set forth in the preferred embodiments of the invention are merely intended to clarify the invention. The technical content of the product is not limited to the above specific examples and is interpreted in a narrow sense. It can be implemented in various ways within the spirit of the present invention and the scope of the patents as set forth below. Fig. 1 is a circuit diagram showing a configuration of a gate driver of a first embodiment. Fig. 2 is a schematic view showing a configuration of a TFT liquid crystal panel according to a first embodiment. 2 is a circuit diagram showing a configuration of a gate driver of the embodiment. Fig. 4 is a timing chart showing signal waveforms from respective flip-flops and ER circuits when the gate driver shown in Fig. 3 does not receive noise. 5 is a timing chart showing signal waveforms from the respective flip-flops and OR circuits when the gate driver shown by the circle 3 receives the noise that causes the level to shift to the L〇W side. FIG. 6 shows the present invention. Fig. 7 is a circuit diagram showing a configuration of a gate driver according to a third embodiment. Fig. 8 is a diagram showing a shift of one of the gate drivers shown in Fig. 7. 135476.doc • 33 · 200933587 Circuit diagram of the details of the flip-flop of the register. Fig. 9 is a circuit diagram showing the details of the flip-flops constituting the other shift register of the gate driver shown in Fig. 7. Fig. 10 is a circuit diagram showing the configuration of a gate driver of a fourth embodiment. Figure U is a circuit diagram showing details of a plurality of circuits provided on the gate driver shown in Figure 10 . Wide Path ❹ Figure 12 is a schematic view showing the configuration of a conventional semiconductor wafer. Fig. 13 is a schematic view showing the configuration of a conventional TFT liquid crystal panel. [Description of Main Element Symbols] Fig. 14 is a circuit diagram showing the configuration of the prior gate driver. 1 TFT liquid crystal panel (display device) 4, 24' 34, 44 gate driver (scanning signal line drive 6 gate line (scanning signal line) 10d ' 1〇e shift register (first shift register) L〇d, l〇u, 10e shift register lOu shift register (2nd shift register) 11 d_FF (reverse) 12-bit shift circuit 15 OR circuit (logic circuit) 16 and circuit (logic circuit) 25 Most circuits 30d Shift register (1st shift register) 30u Shift register (2nd shift register) Φ 135476.doc -34- 200933587 31d ' 31u D-FF (reactor) a point (fourth connection point, eighth connection point) b point (first connection point, fifth connection point) BUFF buffer (first buffer circuit, second buffer circuit) Point c (3rd connection point, 7th connection point) CLK Operation clock (clock signal) D Data input terminal d ❹ IN point (2nd connection point, 6th connection point) Input signal N2 Transistor (2nd electric) Crystal, 6th transistor) N4 transistor (4th transistor, 8th transistor) P2 transistor (1st transistor, 5th transistor) P4 Body (3rd transistor, 7th transistor) Q Data output terminal Q1 to Q7 signal (3rd shift pulse) Qlld to Q17d signal (1st shift pulse) Q11 u~Q1 7u (2nd shift pulse Qld~Q7d signal wave (first shift pulse) 'Qle~Q7e k number (first shift pulse) Qlu~Q7u signal (second shift pulse) Rd pull-down resistor Rd1 pull-down resistor (first pull-down resistor) Rd2 Pull-down resistor (2nd pull-down resistor) Ru Pull-up resistor 135476.doc •35- 200933587

Rul pull-up resistor (1st pull-up resistor)

Ru2 pull-up resistor (2nd pull-up resistor)

-36- 135476.doc

Claims (1)

200933587 X. Patent application: A scanning signal line driver circuit having a first shift register with M (M is an integer of 2 or more) flip-flops connected in series ’! The shift temporary storage system transmits the input signal from the external input in synchronization with the clock signal in sequence: to the flip-flop of the latter stage, and outputs a shift pulse from the data output terminal of each flip-flop to thereby display The scan signal line of the face is driven. The feature is that: ❹ A pull-down resistor is connected to the data output terminal of at least one of the above-mentioned flip-flops. 2. The scanning signal line driving circuit of claim 1, wherein the second shift register and the m logic circuits are connected in series with a flip-flop, and the fourth shift register is The inversion signal of the input signal is synchronized with the clock of the clock, and the second shift pulse is output from the data output terminal of the positive/negative device, and the pull-up resistor is connected to the second shift. The data output terminal of at least one of the positive and negative of the bit register, the logic circuit respectively is positive from the Nth (N is an integer of 1 or more and Μ) from the first shift register The counter! The logical sum of the shift pulse and the inverted pulse of the (9)th pulse from the flip-flop of the (fourth) segment of the second shift register is output as the third shift pulse, and the third is performed by the third The scanning signal line is driven by shifting the pulse. 7 kinds of scanning signal line driving circuits, which have the first shift register which is connected in series with an integer of 2 Τ), and the old bit register is to be input from the outside. The input signal and the clock signal are sequentially transmitted in sequence 135476.doc 200933587 to the rear of the forward and reverse device' and output the first shift pulse from the data output terminals of the respective flip-flops, thereby scanning the signal line of the display screen Driving, wherein at least one of the flip-flops includes a first transmission gate, a second inverter, and a second transmission gate that constitute a data input terminal of the flip-flop 2 inverter and a 丨 snubber circuit constituting the data output terminal, • the above data input terminal, the first transmission gate, the first inverter, the second transmission gate, the second inverter, and the second buffer circuit Connected in this order, the first pull-up resistor is disposed at a second connection point between the first inverter and the second transmission gate, and the second inverter and the second buffer circuit are The first pull-down resistor is provided at the second connection point. 4. If the request is a scanning signal line driving circuit of the third, wherein the first pull-up resistor is provided at the third connection point between the second transmission gate and the second inverter instead of being disposed at the second connection point; Q: The first pull-down resistor is provided at the second connection point instead of the second connection point, and is provided at a fourth connection point between the first transmission gate and the third inverter. The scanning signal line driving circuit, wherein the second inverter is composed of a first transistor that outputs a high level signal and a second transistor that outputs a low level signal, and the second inverter is output. A third transistor having a high level signal and a fourth transistor outputting a low level signal, instead of providing the first pull-up resistor and the first pull-down resistor, the 135476.doc 200933587 first transistor The driving capability is set higher than the driving capability of the second transistor described above and the driving ability of the fourth transistor is set higher than the driving capability of the third transistor. 6. The scanning signal line of claim 3 or 4 Drive circuit, which includes The second shift register and the μ logic circuit are connected to the flip-flop, and the second shift register sequentially transmits the inverted signal of the input signal to the clock signal in synchronization with the clock signal. a second-stage shift pulse is outputted from the data output terminal of each of the flip-flops, and at least one of the flip-flops of the second shift register is provided with the flip-flop a third transmission gate of the data input terminal, a third inverter, a fourth transmission gate, a fourth inverter, and a second buffer circuit constituting the data output terminal, the data input terminal, the third transmission gate, and the The inverter, the fourth transmission gate, the fourth inverter, and the second buffer circuit are connected in this order, and are disposed at a fifth connection point between the third inverter and the fourth transmission gate. a second pull-down resistor is provided at a sixth connection point between the fourth inverter and the second buffer circuit, and the logic circuit is respectively provided from the second shift register The ith shift pulse of the flip-flop of the Ν (Ν is an integer below 1) The logical sum of the inversion pulse of the second shift pulse from the flip-flop of the first segment of the second shift register is output as the third shift pulse, and the third shift pulse is used. The above scanning signal line is driven. 7. The scanning signal line driving circuit of claim 6, wherein the second pull-down power 135476.doc 200933587 is provided instead of the fifth connection point, and is disposed at the fourth transmission gate and the fourth inverter. The seventh pull-up resistor is provided at the eighth connection point between the third transfer gate and the third inverter instead of the sixth connection point. 8. The scanning signal line driving circuit of claim 6, wherein the third inverter is composed of a fifth transistor that outputs a signal of a high level and a sixth transistor that outputs a signal of a low level, ❹ The fourth inverter is composed of a seventh transistor that outputs a high-level signal and an eighth transistor that outputs a signal having a low level, instead of providing the second pull-up resistor and the second pull-down resistor. The driving ability of the solar cell on the sixth electric day is set higher than the driving month b force of the above-mentioned first transistor, and the driving ability of the seventh transistor is set higher than the driving ability of the eighth transistor. A scanning signal line driving circuit, comprising: at least one first shift register in which M (M is an integer of 2 or more) flip-flops are connected in series, and the cascade connection has one positive and negative At least one second shift register and one of a plurality of circuits, the number of which is the number of the above-mentioned _bit register, the first shift register is input from the external input ..... 〜调八'|§ Now the ja pulse f is synchronously transmitted to the positive and negative n of the latter stage, and outputs the first shift pulse from the output terminal of each positive ^, and the pull-down resistor is connected to the above-mentioned first shift register In the flip-flop of the device, the 135476.doc 200933587 data output terminal of the nine flip-flops, the second shift register transmits the inverted signal of the input signal to the subsequent segment in synchronization with the clock signal. a flip-flop device, and outputting a second shift pulse from a data output terminal of each of the flip-flops, wherein the pull-up resistor is connected to a data output terminal of at least one of the flip-flops of the second shift register, The positive and negative of the segment from the above-mentioned i-th shift register The first shift pulse and the inversion pulse of the second shift pulse from the flip-flop of the second stage of the second shift register are input to each of the plurality of circuits, and the circuit is Selecting a larger number of pulses in the pulse of the input person and outputting the selected junction (4) as the third shift pulse, and performing the scanning signal line on the display surface by the third shift pulse of the Hei 10. The scan signal line drive circuit of claim 9, wherein the plurality of first shift registers or the plurality of first shift registers are provided in the case where the plurality of first shift registers or the second shift registers are provided on the plurality of parameters The two shift registers are not close to each other and do not share the power supply wiring and the GND wiring. The device does not have a scanning signal line driving circuit, and the scanning signal line driving circuit has a first shift temporary crying which is connected in series with an integer of 2 or more integers, and the first shift is performed. The register is transmitted from the external input (4) and the clock signal to the front and back of the inverter, and the first shift pulse is output from the front and back of each of the forward and reverse devices. Thereby, the scanning signal line of the display screen is driven, and the pull-down resistor system 135476.doc 200933587 is connected to the data output terminal of at least one of the above-mentioned flip-flops. 135476.doc