JPH0667209A - Circuit for driving display device - Google Patents

Abstract

PURPOSE:To eliminate the influence of static electricity generated at an electrode for inspection and to improve the yield of manufacture by connecting the output of a register block to the electrode for inspection through an FET for inspection or inverter circuit for inspection. CONSTITUTION:Shift registers 1 and 2 are provided with a series circuit of a NOR circuit 3 and a NOT circuit 4 between register blocks 11 and 21 which are paired at the same stage position and register blocks 11 and 21 which are paired at a stage position behind them. The register blocks 11 and 21 are provided with FETs for inspection or inverter circuits 8 for inspection and electrodes 6 for inspection corresponding to them. Consequently, even if an internal circuit element is destroyed owing to static electricity generated at an electrode for inspection, the destruction only extends frequently to a defect such as a leakage between the terminals of the FETs for inspection or inverter circuits 8 for inspection. Therefore, the possibility that the shift registers 1 and 2, NOR circuit 3, etc., are destroyed, is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit used in a display device using liquid crystal or the like.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device used in a liquid crystal television or the like is provided with scanning signal lines corresponding to the number of scanning lines of a liquid crystal panel and display signal lines corresponding to the number of pixels of one scanning line, A display signal for one scanning line is sent to the liquid crystal panel by activating one scanning signal line while applying the display signal to each display signal line. Then, while applying the display signals of the corresponding scanning lines to the respective display signal lines, by sequentially activating the respective scanning signal lines, it is possible to display an image for one screen on the liquid crystal panel.

The drive circuits for driving the scanning signal lines and the display signal lines of the liquid crystal display device are each composed of a shift register. The shift register is a circuit in which a plurality of registers (flip-flop circuits, etc.) are connected in series, and shifts the data input to the register at the front stage to the register at the rear stage based on the clock signal. The data held in the registers of the stages can be output in parallel. Then, in the drive circuit which drives the scanning signal line, when the output of the register of each stage is connected to the scanning signal line and a scanning signal consisting of one active data is input to the register of the front stage, the scanning signal is supplied for each clock signal. Scanning can be performed by sequentially activating the lines one by one. In the drive circuit which drives the display signal line, the output of the register of each stage is input to the sample hold circuit, and the display signal for one scanning line is sequentially written to each display signal line.

The drive circuit for driving the scanning signal lines and the display signal lines often employs a redundant structure for improving the yield, especially when integrally formed on a glass substrate or the like with a liquid crystal panel. However, simply connecting, for example, two shift registers in parallel makes repair impossible if both shift registers have a defect even at one location. Therefore, the shift register is divided into a plurality of register blocks, all the outputs of the corresponding register blocks are once input to the gate circuit at the same stage position, and the outputs of the gate circuit are respectively connected to the rear adjacent register blocks. A configuration has been conventionally used in which the shift signal is crossed for each register block by sending the shift signal to each register block. According to such a redundant configuration, even if all the shift registers connected in parallel have one or more defects, there is a normal one in any one of the corresponding register blocks at the same stage position. As long as it can be repaired, the efficiency of the redundant configuration will be improved.

FIG. 4 shows a conventional drive circuit having the above redundant structure.

In the drive circuit of FIG. 4, a case where two shift registers 1 and 2 are connected in parallel to form a redundant configuration will be described. Each shift register 1 is divided into a plurality of register blocks 11 or register blocks 21, respectively. Each of the register blocks 11 and 21 is formed by connecting a plurality of registers 11a or 21a each of which is a D-type flip-flop circuit in series. Therefore, the data input to each of the register blocks 11 and 21 is based on the clock signal.
From a and 21a, the registers 11a and 21a of the next stage are sequentially shifted.

In the above two shift registers 1 and 2, paired register blocks 11 and 21 are arranged at the same stage position.
And a register block 11 that forms a pair at the stage position behind it,
21 between the NOR circuit 3 and the NOT circuit 4 respectively.
A series circuit of is provided. Then, each NOR circuit 3
The two inputs of the
Are connected to each other, and the output of each NOT circuit 4 is
The outputs are branched and connected to the inputs of the rear register blocks 11 and 21, respectively. The two inputs of each NOR circuit 3 are grounded via pull-down resistors R, respectively. Further, the inspection electrodes 6 are connected to the outputs of the register blocks 11 and 21, respectively.

Further, in the above two shift registers 1 and 2, the inverted outputs of the respective registers 11a and 21a forming a pair at the same stage are connected to the two inputs of the NOR circuit 7, respectively. The two inputs of each NOR circuit 7 are also grounded via the pull-down resistor R, as in the NOR circuit 3. Each output of these NOR circuits 7 is connected to a scanning signal line via a suitable buffer when the driving circuit is a scanning signal line driving circuit, and as a control signal when it is a display signal line driving circuit. Connected to the sample hold circuit.

The above-mentioned conventional drive circuit inputs test serial data to the two shift registers 1 and 2 and causes the shift operation to be performed by the clock signal, and monitors the potential of each inspection electrode 6. Malfunctions can be inspected for each of the register blocks 11 and 21. When any one of the register blocks 11 or 21 is found to be defective, the output of the register block 11 or 21 is cut by a laser beam or the like at a portion indicated by X in the figure.
Then, one input of the NOR circuit 3 is always fixed to the GND level via the pull-down resistor R, so that this NO
The output of the R circuit 3 will depend only on the output of the normal register block 21 or 11 to which the other input is connected. Then, the pair of register blocks 11 in the next stage
Only the data output from the normal register block 21 or 11 is sent to 21 via the NOT circuit 4 as it is, and it is possible to prevent the defective register block 11 or 21 from affecting the subsequent stages. it can. However, when the defect of the register block 11 or 21 always outputs only the high impedance or GND level, the output of the NOT circuit 4 is always normal without disconnecting the output of the register block 11 or 21. It will depend on the output of the register block 21 or 11. Therefore, in this case, the subsequent register blocks 11 and 21 can operate normally without any change, so that cutting work by a laser beam or the like becomes unnecessary.

Further, when any one of the register blocks 11 or 21 is found to be defective, the laser is also provided between the inverted output of each register 11a, 21a in the register block 11 or 21 and one input of the NOR circuit 7. Cut with a beam or the like at the portion marked X in the figure. Then NO
Since one input of the R circuit 7 is always fixed to the GND level via the pull-down resistor R, the output of the NOR circuit 7 depends only on the inverted output of each register 11a, 21a in the normal register block 21 or 11. However, only correct data can be output in parallel to the scanning signal line or the display signal line. However, also in this case, the defect of the register block 11 or 21 is always caused by the register 11a,
When only the high impedance or GND level is output from the inverted output of 1a, it is not necessary to disconnect the inverted output of these registers 11a and 21a.

[0011]

However, when the inspection electrode 6 as described above is provided in the integrated circuit, the internal circuit element connected to the inspection electrode 6 is easily destroyed by the static electricity generated in the inspection electrode 6. . In addition, particularly in a liquid crystal display device, since rubbing treatment needs to be performed to align the liquid crystal, the elements such as the NOR circuit 3 connected to the inspection electrode 6 are easily destroyed by the extremely large static electricity generated at this time. Become.

Therefore, in the conventional drive circuit, the inspection electrode 6 provided for inspecting the register blocks 11 and 21 having the redundant configuration rather increases the risk of destroying the elements such as the NOR circuit 3 and the like. There is a problem that it becomes a major factor that hinders the improvement of the yield.

If the inspection electrode 6 is not provided, the risk of the internal NOT circuit 4 and other elements being destroyed by static electricity is reduced. However, if the inspection electrode 6 is not provided, when an abnormality occurs in the operation of the drive circuit, it is necessary to disconnect the outputs of the register blocks 11 and 21 by trial and error to identify the defective portion. Therefore, a new problem arises that the repair work becomes extremely troublesome.

In view of the above situation, the present invention connects the outputs of the register blocks 11 and 21 to the inspection electrode 6 through the inspection FET, thereby preventing the influence of static electricity from reaching the inside. The purpose is to provide.

[0015]

In a drive circuit for a display device of the present invention, a plurality of shift registers are connected in parallel, each shift register is divided into a plurality of register blocks, and In the drive circuit of the display device in which the gate circuit is arranged between each stage, the output of the register block of the previous stage is connected to the input of each gate circuit, and the output of each gate circuit is connected to the input of the register block of the next stage, The output of each register block is connected to the gate terminal of the inspection FET, and the inspection electrodes are connected to the source terminal and the drain terminal of the inspection FET, respectively, thereby achieving the above object. .

In the drive circuit of the display device of the present invention, a plurality of shift registers are connected in parallel, each shift register is divided into a plurality of register blocks, and a gate circuit is provided between each stage of the register blocks. The output of each register block is connected to the input of each gate circuit and the output of each register block is connected to the output of each register block of the previous stage, and the output of each gate circuit is connected to the input of the register block of the next stage. Is connected to the input of the inverter circuit or the buffer circuit, and the output of the inverter circuit or the buffer circuit is connected to the inspection electrode, respectively, whereby the above object is achieved.

[0017]

According to the first aspect of the invention, the output of each register block is input to the gate terminal of the corresponding inspection FET. Therefore, if a weak current is passed between the two inspection electrodes connected to the source terminal and the drain terminal of this inspection FET to measure the channel resistance, the output state of the register block is inspected at any time as in the conventional case. be able to. Further, the output state of the register block can be inspected at any time by connecting the inspection FETs so as to form a source follower (drain ground) circuit and monitoring the voltage of the inspection electrode connected to the source terminal.

With the structure in which the inspection electrodes are connected via the inspection FETs, even if the internal circuit is destroyed by the static electricity generated in the inspection electrodes, this destruction occurs. Is limited to a defect such as a leak between terminals of the inspection FET, and there is almost no influence on the internal gate circuit or register block.

As a result, according to the first aspect of the present invention, the static electricity generated in the inspection electrode may damage the shift register or the gate circuit while forming the inspection electrode to identify the defective portion. Can be reduced.

According to the invention of claim 2, the output of each shift register is input to the corresponding inverter circuit or buffer circuit. Therefore, by monitoring the potential of the inspection electrode connected to the output of the inverter circuit or the buffer circuit, the output state of the register block can be inspected at any time as in the conventional case. The power supply for the inverter circuit or the buffer circuit may be provided from the outside at the time of inspection by providing a test electrode for power supply, or may be supplied from an internal power supply circuit.

When the inspection electrodes are connected via the inverter circuit or the buffer circuit in this manner, even if the internal circuit is destroyed by the static electricity generated on the inspection electrodes, this destruction is caused. Is a failure of the inverter circuit or the buffer circuit, and there is almost no influence on the internal gate circuit or register block. Moreover, when a buffer circuit composed of a plurality of stages of inverter circuits is used, the plurality of stages of inverter circuits double or triple prevent the influence of static electricity, so that the internal circuit can be surely protected. become.

As a result, also in the case of the second aspect of the invention, the static electricity generated in the inspection electrode may damage the shift register or the gate circuit while enabling the identification of the defective portion by forming the inspection electrode. Can be reduced.

[0023]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention and is a block diagram showing a drive circuit of a liquid crystal display device.
Incidentally, the same numbers are added to the constituent members having the same functions as those of the conventional example shown in FIG.

In this embodiment, a driving circuit for driving the scanning signal lines or the display signal lines in the active matrix type liquid crystal display device will be described.

This drive circuit employs a redundant configuration in which two shift registers 1 and 2 are connected in parallel. Each shift register 1 has a plurality of register blocks 1
1 or register block 21. Also,
Each register block 11 and 21 has a register 1
1a or a plurality of registers 21a are connected in series. The registers 11a and 21a latch the data input to the data input by a clock signal, and output the latched data from the non-inverted output and the inverted output, respectively.
Form a flip-flop circuit, and by connecting the non-inverting output of the previous stage to the data input of the next stage, a plurality of registers are connected in series to form the register blocks 11 and 21. And the register 1 at the frontmost stage in this series connection
The data input of 1a, 21a is the register block 11,
21 becomes an input, and the non-inverted outputs of the last stage registers 11a, 21a become the outputs of the respective register blocks 11, 21. Therefore, the data input to the register blocks 11 and 21 is stored in the register 1 of the frontmost stage based on the clock signal.
1a and 21a are sequentially shifted to the registers 11a and 21a of the next stage. In addition, each register 11a, 2
The FET constituting 1a is formed of a TFT (thin film transistor) like the FET of the liquid crystal panel.

In the above two shift registers 1 and 2, paired register blocks 11 and 21 are arranged at the same stage position.
And a register block 11 that forms a pair at the stage position behind it,
21 between the NOR circuit 3 and the NOT circuit 4 respectively.
A series circuit of is provided. Then, each NOR circuit 3
The two inputs of the
Of the NOR circuit 3 and the output of the NOT circuit 4 which inverts the output of the NOR circuit 3 is branched and connected to the inputs of the rear register blocks 11 and 21. The two inputs of each NOR circuit 3 are grounded via pull-down resistors R, respectively.

Each of the register blocks 11 and 21 has
One inspection FET 5 and two inspection electrodes 6 are provided corresponding to each. The inspection FET 5 is a TFT
FET formed by the corresponding register 1
The outputs of 1a and 21a are connected to the gate terminals,
The inspection electrode 6 is connected to the source terminal and the drain terminal.

In the shift registers 1 and 2, the inverted outputs of the registers 11a and 21a which form a pair in the same stage are connected to the two inputs of the NOR circuit 7, respectively. The two inputs of each NOR circuit 7 are also grounded via the pull-down resistor R, as in the NOR circuit 3. Each output of the NOR circuit 7 is connected to a scanning signal line when the driving circuit is a scanning signal line driving circuit, and is connected to a sample hold circuit as a control signal when the driving circuit is a display signal line driving circuit. It

When inspecting the drive circuit having the above configuration, first, the power supply voltage Vcc of the shift registers 1 and 2 is set to 10V.
As a degree, a voltage of 5 V is applied to the inspection electrode 6 connected to the source terminal of each inspection FET 5, and a voltage of 5.1 V is applied to the inspection electrode 6 connected to the drain terminal. Then, when the test serial data is input to the shift registers 1 and 2 and the shift operation is performed by the clock signal, when the output potentials of the register blocks 11 and 21 are at the Vcc level, the test is input to the gate terminals. FET5 for inspection is turned on, and when the output potential is at the GND level, FET5 for inspection
Turns off. Therefore, when the channel resistance is obtained by measuring the current flowing between the inspection electrodes 6 and 6 connected to the source terminal and the drain terminal of the inspection FET 5, the output states of the register blocks 11 and 21 can be detected at any time. Will be able to. Further, by connecting a power source and a resistor via the inspection electrode 6 so that each inspection FET 5 constitutes a source follower circuit, the inspection FET 5 is connected.
Of the register blocks 11, 21 depending on the potential of the inspection electrode 6 connected to the source terminal.
You can also monitor the output status of. In this way, when any one of the register blocks 11 or 21 is found defective, the register block 11 or 21 is defective.
And the inverted output of each of the registers 11a and 21a are appropriately cut by a laser beam or the like at the portion marked by X in the figure, so that the defect is repaired as in the conventional case.

Further, when the inspection electrode 6 is connected through the inspection FET 5 as in the above structure, even if the internal circuit element is destroyed by the static electricity generated in the inspection electrode 6, this destruction is caused. Often results in a defect such as a leak between terminals of the inspection FET 5 that is not related to the shift operation of the shift registers 1 and 2. Therefore, this inspection FE
When T5 is destroyed by static electricity, the malfunction of each register block 11, 21 cannot be correctly detected, but the static electricity reduces the possibility that the shift registers 1, 2 themselves malfunction. ,
As a whole, the yield of the drive circuit can be improved.

As a result, according to the present embodiment, by forming the inspection electrode 6, it is possible to identify the defective portion, but the static electricity generated in the inspection electrode 6 is applied to the shift registers 1 and 2 and the NOT circuit 4. It becomes possible to eliminate the risk of destroying etc.

FIG. 2 shows another embodiment of the present invention and is a block diagram showing a drive circuit of a liquid crystal display device. The constituent members having the same functions as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, a case will be described in which the inspection FET 5 in the first embodiment shown in FIG. 1 is replaced with an inspection inverter circuit 8.

Each register block 11, 21 of this embodiment
The inspection electrodes 6 are connected to the respective outputs via the inspection inverter circuit 8. The inspection inverter circuit 8 is a circuit in which the source terminals of a CMOS N-channel FET 8a and a P-channel FET 8b are connected to each other.
These N-channel FET 8a and P-channel FET 8
The signal input to the gate terminal of b is inverted and output from the source terminal. The outputs of the register blocks 11 and 21 are commonly connected to the gate terminals of the N-channel FET 8a and the P-channel FET 8b, which are the inputs of the inspection inverter circuit 8, and the output of the inspection inverter circuit 8 is the N-channel. FET 8a
The drain terminal of the P-channel FET 8b is connected to the inspection electrode 6. Also, these N-channel FETs
The inspection electrodes 6 are also connected to the source terminals of 8a and the P-channel FET 8b, respectively.

When inspecting the drive circuit having the above configuration, the P channel FE in the inspection inverter circuit 8 is used.
The power source V is applied to the inspection electrode 6 connected to the source terminal of T8b.
While the CC is connected, the inspection electrode 6 connected to the source terminal of the N-channel FET 8a is grounded, and the potential of the inspection electrode 6 connected to the drain terminals of the N-channel FET 8a and the P-channel FET 8b is monitored. When the test serial data is input to the shift registers 1 and 2 and the shift operation is performed by the clock signal,
The data obtained by inverting the outputs of the register blocks 11 and 21 is monitored at any time.
The malfunctions 1 and 21 can be detected.

Further, in this way, the inspection inverter circuit 8 is also provided.
Even when the inspection electrodes 6 are connected via the shift electrodes 1, 2
Can be prevented from affecting the operation. Moreover,
By connecting the inspection electrodes 6 via a buffer circuit in which two or more inspection inverter circuits 8 are connected in series, the influence of static electricity can be shielded more reliably.

The drive circuit shown in FIG. 3 is adapted to supply internal power to the inspection inverter circuit 8 of the second embodiment shown in FIG. Therefore, in this case, the Vcc power supply line for supplying power to the shift registers 1 and 2 and the NOT circuit 4 is also connected to the source terminal of the P-channel FET 8b in each inspection inverter circuit 8 and the GND power supply. The line is also connected to the source terminal of N-channel FET 8a. In addition, the inspection electrode 6
Is formed for each of the register blocks 11 and 21, and the N-channel F in the inspection inverter circuit 8 is formed.
The drain terminals of the ET 8a and the P-channel FET 8b are commonly connected.

If the internal power supply is supplied to the inspection inverter circuit 8 as described above, it is not necessary to supply power to the inspection electrode 6 from the outside when the drive circuit is inspected, and the inspection inverter circuit 8 is not required. Circuit 8 and inspection electrode 6
It is also possible to make the formation area of the as small as possible. However, in this case, if a defect occurs in the N-channel FET 8a or the P-channel FET 8b of the inspection inverter circuit 8, the input of the NOR circuit 3 may be affected. When such an influence appears, it is necessary to cut the portion of the wiring connecting the inspection inverter circuit 8 and the Vcc power supply line and the GND power supply line with the mark x by a laser beam or the like.

[0040]

As is apparent from the above description, according to the drive circuit of the display device of the present invention, the influence of static electricity generated in the inspection electrodes is surely prevented from reaching the shift register and the gate circuit. As a result, it is possible to contribute to an improvement in manufacturing yield.

[Brief description of drawings]

FIG. 1 is a block diagram showing a driving circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 shows another embodiment of the present invention and is a block diagram showing a drive circuit of a liquid crystal display device.

FIG. 3 shows still another embodiment of the present invention and is a block diagram showing a drive circuit of a liquid crystal display device.

FIG. 4 is a block diagram showing a drive circuit of a liquid crystal display device, showing a conventional example.

[Explanation of symbols]

 1 shift register 2 shift register 11 register block 21 register block 3 NOR circuit 4 NOT circuit 5 inspection FET 6 inspection electrode 8 inspection inverter circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shiro Toichi, 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Within Sharp Co., Ltd. No.22 Sharp Co., Ltd.

Claims (2)

[Claims] 1. A plurality of shift registers are connected in parallel, each shift register is divided into a plurality of register blocks, and a gate circuit is arranged between each stage of the register blocks. In the drive circuit of the display device in which the output of the register block of the previous stage is connected to the input and the output of each gate circuit is connected to the input of the register block of the next stage, the output of each register block is connected to the gate terminal of the inspection FET. A drive circuit for a display device, which is connected to the inspection FET and has source and drain terminals respectively connected to the inspection electrode. 2. A plurality of shift registers are connected in parallel, each shift register is divided into a plurality of register blocks, and a gate circuit is arranged between each stage of the register blocks. In the drive circuit of the display device in which the output of the register block of the previous stage is connected to the input and the output of each gate circuit is connected to the input of the register block of the next stage, the output of each register block is input to the inverter circuit or the buffer circuit. And a drive circuit of a display device, which is connected to the inspection electrode and the output of the inverter circuit or each buffer circuit.