200929482 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於封裝晶片之承載帶及其晶片封裝結構； 特別是一種沿承載帶之橫向方向上設置有複數封裝單元之承載帶 及其晶片封裝結構。 【先前技術】 隨著科技及製程技術之發展，各式電子產品皆走向小型化、方 © 便攜帶等趨勢。由於可撓性電路板具有厚度薄、引腳間距小、且 腳數高等優點，當液晶螢幕為了節省空間，或是電子產品設計具 有折疊功能時，可撓性電路板便成為不可或缺的元件。 一般而言，可撓性電路板係利用晶片封裝技術，將半導體晶片 接合於其上。其中，捲帶自動接合封裝（Tape Automatic Bonding, TAB)技術係將晶片接合於承載帶上，為目前最常見的晶片封裝 技術之一。其又可分成捲帶承載封裝（Tape Carrier Package, TCP ) 及薄膜覆晶封裝（Chip-On-Film，COF)二種封裝型式。應用此技 ◎ 術所製造之可撓性電路板廣泛地應用於各種液晶螢幕、手機、電 腦及各式電子產品中。 習知之晶片封裝結構1及其承載帶10如第1圖所示，為方便說 明，可定義第一方向X及第二方向Y，其中第一方向X係承載帶 10之輸送方向，而第二方向Y係為其橫向方向。承載帶10上沿 二側邊101順序分佈有複數定位孔110,用以在製程中輸送及定位 承載帶10。承載帶10上更包含有封裝單元120以供晶片20設置 及接合，且於封裝單元120上更分佈有引腳130,引腳130與晶片 5 200929482 20電性連接，其中晶片2Q透過其主動面上之銲墊或設置於鲜塾上 之凸塊與引腳130接合以電性連接。 ❹ Ο 然而’習知承載帶Π)上之複數封裝單元12〇係單純沿第一方向 x順序分佈，而在承載帶10之第二方向y上，同-位置僅設有單 一封裝早凡⑽。更明破而言，習知配置方式中，不論承載帶10 在第一方向γ上的寬度尺寸為何，封裝單元⑽（或晶片扣）僅 沿=方向以序配置，使得承载㈣之可洲面積未能充分使 用。舉例而言’當配置寬度之承載帶1Q上的晶片尺寸較小 導致承載帶H)上未使用面積過多，最後裁切丢棄，導致材 倍習知承載帶10係為長條捲帶，並配合於製程設備中輸送 =，並—分別對封裝單元120進行各個封裝步驟。換言之，承載 2之母個封農單元120在進行每個製程步驟前，皆需要針對單 :=Γ2。進行一次輸送及定位之動作。可想見地，頻 =送與疋位動作，以及製程設備的反覆操作，將耗費過多的 時間，導致製造效率不高，進而增加製造成本。 载二提供一種可充分利用配置面積且提昇製造效率之承 、阳封震結構，乃為此一業界亟待解決的問題。 【發明内容】 封之—目的在於提供—種詩«日日日片之承«及盆曰片 封裝、，、。構，承解在與輸送㈣ ，、“ 封裝單元，用以沾入 杈甸方向上，設置有複數 片。藉此，提高承载帶面積之使用率， 進而達到節省承載帶成本之目的。 償便用羊 6 200929482 本發明之另-目的在於提供一種用 片封裝結構，由於承載帶在同一掃向二之承載帶及其晶 在部分製程中，可針對同一橫向方向上_ =裝單：， 或加工，有效提升生產效率。 5時進仃疋位 =達上述目的，本發明所揭露之承载帶具有—表面及— ，=二該表面包含有二傳輸區域及複數封裝單元。”， “專傳輸區域分別定義於該承載帶之二側邊，且沿該第—方 ❹ ❹ 伸’該圖案化金屬線路層係分佈於該等封裝單元上，該等封裝；： :第一方向實質上垂直之該第二方向，鄰接地分佈二 表，俾供複數晶片分別設置於各該封裝單元内，並與該圖案 化金屬線路層電性連接。 ’、° 本發明更揭露一種晶片封裝結構’包含上述承載帶及複數曰 ，該4晶片適可分別設置於該㈣裝單元内，與 線路層電性連接。 ㈣金屬 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂 文係以較佳實施細&合職圖式進行詳細說明。 【實施方式】 "月 > 考第2圖’本發明之第_實施例揭露—種用於封裝晶片之 承載帶3 ’其具有—表面及—圖案化金屬線路層。承载帶3之表面 上可定義有二傳輸區域31及複數㈣單元，圖案化金屬線路層 77佈於料封裝單元上。本實施例之承載帶3適可沿第—方向χ 輸送’或沿第—方向Χ捲繞為—承載帶捲，以方便儲存及運送。 其中—傳輪區域31係分別定義於承載帶3之二側邊3〇卜且广 7 ❹ Ο 200929482 第一方向χ延伸，於本實施 成有複數定位孔31G，巧―^ _ 3於二傳魅域3】上形 合進行輸送與定位。。向Χ順序配置’以與製程設備配 本發明之特徵在於，複數 首之繁-方6 ν , (早70係〜與第-方向X實質上垂 ° ’鄰接地分佈於承” 3之表自上 晶片分別設置於内，並盥該 俾（、複數 施例中，複數封裝單元至少於本只 元322，且於第二方向m以封農早疋切及第二封裝單 s D上彼此鄰設’如第2圖所示。須說明的 χ本貫㈣«取承_ 3之局部料例示，封裝單元當然可200929482 IX. The invention relates to a carrier tape for packaging a wafer and a chip package structure thereof; in particular, a carrier tape provided with a plurality of package units in a lateral direction of the carrier tape and Its chip package structure. [Prior Art] With the development of technology and process technology, all kinds of electronic products are moving toward miniaturization, and the use of portable tapes. Since the flexible circuit board has the advantages of thin thickness, small pin pitch, and high number of pins, the flexible circuit board becomes an indispensable component when the liquid crystal screen is used for space saving or when the electronic product design has a folding function. . In general, a flexible circuit board utilizes a wafer packaging technique to bond a semiconductor wafer thereto. Among them, Tape Automatic Bonding (TAB) technology is one of the most common chip packaging technologies for bonding wafers to tape. It can be divided into two types: Tape Carrier Package (TCP) and Chip-On-Film (COF). Applying this technology ◎ The flexible circuit board manufactured by the company is widely used in various LCD screens, mobile phones, computers and various electronic products. The conventional chip package structure 1 and its carrier tape 10 are as shown in FIG. 1. For convenience of explanation, a first direction X and a second direction Y may be defined, wherein the first direction X is the conveying direction of the carrier tape 10, and the second direction The direction Y is its lateral direction. A plurality of positioning holes 110 are sequentially disposed on the carrier tape 10 along the two side edges 101 for transporting and positioning the carrier tape 10 during the manufacturing process. The carrier tape 10 further includes a package unit 120 for the wafer 20 to be disposed and bonded, and a pin 130 is further disposed on the package unit 120. The pin 130 is electrically connected to the wafer 5 200929482 20 , wherein the wafer 2Q passes through the active surface thereof. The upper pad or the bump disposed on the squeegee is joined to the pin 130 for electrical connection. ❹ Ο However, the plurality of package units 12 on the conventional carrier tape are simply distributed in the first direction x, and in the second direction y of the carrier tape 10, the same position is only provided with a single package (10) . More clearly, in the conventional configuration, regardless of the width dimension of the carrier tape 10 in the first direction γ, the package unit (10) (or wafer buckle) is only arranged in the direction of the = direction, so that the area of the carrier (4) can be Not fully utilized. For example, 'when the size of the wafer on the carrier tape 1Q of the configuration width is small, the unused area on the carrier tape H is too large, and finally the cutting is discarded, resulting in the material-bearing carrier tape 10 being a long tape, and Cooperating with the processing equipment, the packaging unit 120 performs respective packaging steps. In other words, the parenting unit 120 of the bearer 2 needs to be directed to a single :=Γ2 before performing each process step. Perform a transport and positioning operation. Conceivably, the frequency = send and clamp operations, as well as the repeated operation of the process equipment, will take too much time, resulting in inefficient manufacturing, thereby increasing manufacturing costs. It is an urgent problem to be solved in the industry to provide a bearing structure that can fully utilize the configuration area and improve the manufacturing efficiency. [Summary of the Invention] The purpose of the seal is to provide a poem «Day of the Japanese and Japanese films" and the packaging of the pots and pans. The structure, the entrainment and the transport (4), and the "packaging unit, which are used to penetrate into the direction of Fudian, are provided with a plurality of sheets. Thereby, the utilization rate of the belt area is increased, thereby achieving the purpose of saving the cost of the belt. Use Sheep 6 200929482 Another object of the present invention is to provide a sheet package structure in which the carrier tape can be placed in the same lateral direction as the carrier tape in the same scanning direction and its crystal in part process, or Processing, effectively improving production efficiency. 5 o'clock into the position = for the above purpose, the carrier tape disclosed in the present invention has - surface and -, = two the surface contains two transmission areas and a plurality of package units.", "special transmission The regions are respectively defined on two sides of the carrier tape, and the patterned metal circuit layer is distributed on the package units along the first-party , ,, the packages; the first direction is substantially vertical The second direction is adjacently distributed with two tables, and the plurality of wafers are respectively disposed in each of the package units and electrically connected to the patterned metal circuit layer. ', ° The present invention further discloses a crystal The package structure 'includes the above-mentioned carrier tape and a plurality of wires, and the four chips are respectively disposed in the (four) package unit and electrically connected to the circuit layer. (4) The metal can make the above objects, technical features and advantages of the present invention more obvious. The easy-to-understand text is described in detail in the preferred embodiment of the present invention. [Embodiment] "Month> Test 2: The first embodiment of the present invention discloses a carrier tape for packaging a wafer 3' has a surface and a patterned metal circuit layer. The surface of the carrier tape 3 may define two transmission regions 31 and a plurality of (four) cells, and the patterned metal circuit layer 77 is disposed on the material packaging unit. The belt 3 is suitable for transporting along the first direction 或 or winding along the first direction as a carrier tape for convenient storage and transportation. The transmission zone 31 is defined on the two sides of the carrier tape 3 respectively.卜和广7 ❹ Ο 200929482 The first direction χ extension, in this implementation has a plurality of positioning holes 31G, Qiao _ _ 3 on the second transmission charm domain 3] on the shape of transport and positioning. Having the features of the invention with the process equipment In the first, the number of the first one is -6 ν , (the early 70 series ~ is substantially perpendicular to the first direction X - 'is distributed adjacent to the bearing" 3 table is set in the upper wafer, and the 俾 (, plural In the embodiment, the plurality of package units are at least in the second element 322, and are adjacent to each other in the second direction m, and are arranged adjacent to each other on the second package list s D as shown in Fig. 2. According to the partial material of (4) «Receiving _ 3, the package unit can of course be
方向X佈滿整條承載帶3，·此外，若承载帶3於第二方向Y t、向尺寸允許叹置更多個封裝單元，則可包含更多個封裝單 凡，本實施例僅以二封裝單元作為例示，非用以限定本發明。 本發月之承载可3沿第二方向γ之橫向尺寸（即承載帶寬度） 可輕易地應用目前習知之承載帶尺寸，例如35、48、7〇«米寬度， 而不而要使用特殊尺寸之承載帶。 2清楚說明本實施例之技術特徵，可將㈣化金屬線路層區分 包含第-引腳331及第二引腳说其中第一引腳如實質上沿第 向X，形成於第一封襞單元321上，而第二引腳332實質上 &第-方向X ’形成於第二封裝單元322上。詳細言之，第—引 腳331更包含第一輸入引腳331&及第一輸出引腳331b，而第二引 32更包含第二輸入引腳332a及第二輸出引腳332b。於第—實 也例中，第一輸入引腳33h與第二輸入引腳332a係分別自第一 士裝單7L 321之晶片接合區321a與第二封裝單元322之晶片接合 8 200929482 區322a，朝同—方向延伸， 332b則朝另-方向延伸’換^引腳咖與第二輪出引卿 於同-側，且輸出引咖’輸人引_對各^接合區位 明之第㈣位於各“接合區之另U於样 明之弟—貫施例中， …、於本發 則可與第二_腳32 ”_3’之第—輸人引腳咖 322a朝同—方向延伸’換=自日日片接合區321a與晶片接合區 配置為何，皆可實施本發明。。，不論輸入引腳及輸出引腳之方向 ❹ Ο 須說明的是，前述實施例所定義之承载帶3 3,，伟在 域31間，、、凡铉_士人 J秋可J，J ’係在一傳輸區 n ’口 — °Y上具有複數個封裝單元。換言之，封裝單 凡之間不具備其㈣輸_或定位孔m 面積充分利用。 文用The direction X is covered with the entire carrier tape 3. In addition, if the carrier tape 3 is in the second direction Y t and the size is allowed to slap more package units, more packages may be included. This embodiment only uses The two package units are illustrative and are not intended to limit the invention. The carrying capacity of the present month 3 can be easily applied to the lateral dimensions of the second direction γ (ie the width of the carrier tape), such as 35, 48, 7 〇 «m width, instead of special dimensions. Carrying belt. 2 clearly illustrating the technical features of the embodiment, the (four) metal circuit layer can be divided into a first pin 331 and a second pin, wherein the first pin is substantially along the first direction X, formed in the first sealing unit The second pin 332 is substantially & the first direction X ' is formed on the second package unit 322. In detail, the first pin 331 further includes a first input pin 331 & and a first output pin 331b, and the second lead 32 further includes a second input pin 332a and a second output pin 332b. In the first embodiment, the first input pin 33h and the second input pin 332a are respectively bonded from the wafer bonding region 321a of the first package 7L 321 to the wafer bonding portion 8 200929482 region 322a of the second package unit 322. In the same direction, the direction is extended, and the 332b is extended in the other direction. 'Change the pin coffee and the second round to the same side, and the output is the same as the side, and the output is the same as the first (the fourth). "The other part of the junction area is the same as the younger brother of the sample - in the example, ..., in this issue, it can be extended with the second _ foot 32 _3' - the input pin coffee 322a is the same direction - change = from The present invention can be implemented by the arrangement of the day-to-day sheet bonding region 321a and the wafer bonding region. . Regardless of the direction of the input pin and the output pin, 须 须 须 须 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 , , , It has a plurality of package units on a transmission area n 'port - °Y. In other words, the package unit does not have its (4) transmission or locating hole m area. Text use
前述實施例中，承載帶3 v 7 * A A 戰帶3’ 3可更包含一靜電防護線路333，環 繞封裝單元321、322，以楹徂、^ 耠仏適§之靜電防護，避免電路間之干 擾。第2圖所示之實施例中，各封裝單元皆個別由—靜電防護線 路333環繞’然於其他的實施樣態中，—靜電防護線路扣亦可 以同時環繞多個封裝單元，皆可達到預期之效果。 本發明之第三實施例係一種晶片封裝結構4,如第4圖所示，其 包含上述第-實施例之承載帶3及複數晶片，為方便說明，第4 圖中僅繪示第-晶片4i及第二晶片42，而第一晶片似第二晶 片42係分別設置於第2圖所示之晶片接合區32^及322&上且 於承載帶3之二傳輸區域31間。第一晶片41及第二晶片42各包 含一輸入端及相對於輸入端之一輸出端，其中第一晶片41之輸入 端與第-輸入引腳33U電性連接，第一晶片41之輸出端與第一 9 ❹ ❹ 200929482 輸出引腳331b電性遠垃，I & 而第二晶片42之輸入端與第二輪引 腳332a電性連接，鈐山山 m 輪出鹌與第二輸出引腳332b電性連接。曰H 封裝結構4所使用之承 W連接曰曰片 水载τ 3之結構如同上述之承载帶3,在此不 另賢述。 第㈤片41及第二晶片42之輸入端或輸出端可位於同 側或相反側，白可實施本發明。詳言之，於第三實施例中，第 —晶片41及第二晶片42之輪入端或輸出端係位於同一側，如第4 圖所不；然於本發明第 杳 一 貫e例中，如第5圖所示，晶片封裝結 構4之弟—晶片4] β勞—。 第二曰曰片42係封裝於第二實施例之承载帶 3’上’且第-晶片41與第二晶片42之輸入端或輪出端係位於相 反側。再者’上述第—晶片41與第二晶片42可為相同之晶片， 或者為相異之晶片’所有可應用晶片承載帶封裝技術之晶片皆可 \ ;本發明之日日片封裝結構4及，並且皆屬於本發明之專 利範圍所主張之範疇。 \料見把例之承载帶及晶片封裝結構，可改善傳統承載 '晶片封裝結構之各項缺點。其中，承載帶沿第二方向上設置 數ΐ裝單元，、而此等封裝單元及設置於其上之複數晶片，適 °日由置於承載帶二側之傳輸區域同時定位或輸送，可充分運 二承載帶之可用面積，達到節省承載帶成本之目的，且於輸送或 心位作業時，可同時處理〉VL笛__., #曰g Q ^ —方向上設置之複數封裝單元及複 数日日片，可有效提升生產效率。 上述之實施例僅用來例舉本發明之實施態樣，以及閣釋本發明 之技術特徵，並非絲限制本發明之保護㈣。任何熟悉此技術 200929482 於本發明所主張之範 圍為準。 者可輕易完成之改變或均等性之安排均屬 圍，本發明之權利保護範圍應以中請專利範 【圖式簡單說明】 第1圖係習知日日日片封裝結構之示意圖； 第2圖係本發明第一實施例之承载帶之示意圖； :3圖係本發明第二實施例之承載帶之示意圖；In the foregoing embodiment, the carrier tape 3 v 7 * AA battle zone 3' 3 may further include an electrostatic protection circuit 333 surrounding the package units 321, 322 to protect against static electricity between the circuits and the circuit. interference. In the embodiment shown in FIG. 2, each package unit is individually surrounded by an ESD protection line 333. In other embodiments, the ESD protection line buckle can also surround a plurality of package units at the same time, which can achieve the expected The effect. A third embodiment of the present invention is a chip package structure 4, as shown in FIG. 4, which includes the carrier tape 3 and the plurality of wafers of the above-described first embodiment. For convenience of explanation, only the first wafer is shown in FIG. 4i and the second wafer 42, and the first wafer-like second wafers 42 are respectively disposed on the wafer bonding regions 32 and 322 & shown in FIG. 2 and between the two transfer regions 31 of the carrier tape 3. The first chip 41 and the second chip 42 each include an input end and an output end opposite to the input end, wherein the input end of the first chip 41 is electrically connected to the first input pin 33U, and the output end of the first chip 41 The output pin 331b is electrically distant from the first 9 ❹ ❹ 200929482, and the input end of the second chip 42 is electrically connected to the second pin 332a, and the output of the 钤山山 m wheel and the second output lead The foot 332b is electrically connected. The 曰曰H package structure 4 is used for the W-connecting slab. The structure of the water-carrying τ 3 is the same as that of the above-mentioned carrier tape 3, and is not described here. The input or output of the (f)th sheet 41 and the second wafer 42 may be on the same side or on the opposite side, and the present invention may be practiced. In detail, in the third embodiment, the wheel end or the output end of the first wafer 41 and the second wafer 42 are on the same side, as shown in FIG. 4; however, in the third example of the present invention, As shown in FIG. 5, the chip package structure 4 is the same as the wafer 4]. The second cymbal piece 42 is packaged on the carrier tape 3' of the second embodiment and the input end or the wheel end of the first wafer 41 and the second wafer 42 are located on opposite sides. Furthermore, the above-mentioned first wafer 41 and the second wafer 42 may be the same wafer, or different wafers may be used for all wafers with applicable wafer carrier tape packaging technology; And all of them fall within the scope of the patent scope of the present invention. It is expected that the carrier tape and the chip package structure of the example can improve the shortcomings of the conventional carrier chip package structure. Wherein, the carrying belt is provided with a plurality of armoring units in the second direction, and the packaging units and the plurality of wafers disposed thereon are simultaneously positioned or transported by the transmission area disposed on the two sides of the carrying belt, which is sufficient The available area of the carrier tape can save the cost of the carrier tape, and can handle the VL flute __., #曰g Q ^ - the plurality of package units and plurals set in the direction during the transport or heart position operation. Japanese and Japanese films can effectively improve production efficiency. The above embodiments are merely illustrative of the embodiments of the present invention, as well as the technical features of the present invention, and do not limit the protection of the present invention (4). Any familiarity with this technique 200929482 is subject to the scope of the invention. The change or equalization arrangement that can be easily accomplished is within the scope of the invention. The scope of protection of the present invention should be described in the patent specification [Simplified description of the drawing]. Figure 1 is a schematic diagram of the conventional Japanese and Japanese package structure; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic view of a carrier tape according to a first embodiment of the present invention; FIG. 3 is a schematic view of a carrier tape according to a second embodiment of the present invention;
第4圖係本發明第二每 ;以及 第片封裝結構之示意圖 %發明第四實施例之晶片封裝結構之示意圖 【主要元件符號說明】 1 封裝結構 101 側邊 120 封裝單元 20 晶片 3， 承载帶 31 傳輸區域 321 第一封裝單元 322 第二封裝單元 331 第一引腳 331b 第一輸出引腳 332a 第一輸入引腳 333 靜電防護線路 4， 晶片封裝結構 10 承載帶 110 定位孔 130 引腳 3 承載帶 301 側邊 310 定位孔 321a 晶片接合區 322a 晶片接合區 331a 第一輸入引腳 332 第二引腳 332b 第二輸出引腳 4 晶片封裝結構 41 第一晶片 11 200929482 42 第二晶片 X 第一方向 Y 第二方向 ❹4 is a schematic view of a second package of the present invention; and a schematic view of a package structure of a first package; a schematic diagram of a package structure of a fourth embodiment of the invention [Description of main components] 1 package structure 101 side 120 package unit 20 wafer 3, carrier tape 31 transfer area 321 first package unit 322 second package unit 331 first pin 331b first output pin 332a first input pin 333 electrostatic protection line 4, chip package structure 10 carrier tape 110 positioning hole 130 pin 3 bearing Tape 301 Side 310 Positioning Hole 321a Wafer Bonding Area 322a Wafer Bonding Area 331a First Input Pin 332 Second Lead 332b Second Output Pin 4 Wafer Mounting Structure 41 First Wafer 11 200929482 42 Second Wafer X First Direction Y second direction❹
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