CN212010939U

CN212010939U - Semiconductor packaging structure

Info

Publication number: CN212010939U
Application number: CN202020966495.4U
Authority: CN
Inventors: 吴斌
Original assignee: Nantong Xinjing Electronic Technology Co ltd
Current assignee: Nantong Xinjing Electronic Technology Co ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2020-11-24
Anticipated expiration: 2030-06-01

Abstract

The utility model provides a semiconductor packaging structure, including chip, adhesive material layer, lead wire frame and packaging body, the chip is the polygon, the side of a plurality of sides of chip is through adhesive material layer and lead wire frame fixed connection, the packaging body has the side the same with the chip limit number, chip, adhesive material layer, lead wire and lead wire frame are sealed through the packaging body and become an organic whole, the outer end of lead wire frame that exposes outside the packaging body is equipped with the solder joint; the chip at least comprises three edges, wherein one edge is arranged corresponding to one end of the input end and the output end with less pin number requirement, the other edges are arranged corresponding to the other end of the input end and the output end with more pin number requirement, and each pin is respectively connected with the lead frame through a lead. The utility model discloses a polygonal chip and packaging body provide sufficient space for the more pin of figure, corresponding volume that reduces semiconductor package structure to avoid producing bridging, electromigration scheduling problem, small, with low costs, production cycle is short.

Description

Semiconductor packaging structure

Technical Field

The utility model relates to the field of semiconductor technology, concretely relates to semiconductor packaging structure.

Background

With the continuous development of semiconductor technology, electronic products tend to be developed in a large-scale, small-volume and high-speed direction, and the reduction of the volume of semiconductor chips and integrated circuits including the semiconductor chips leads to the increase of the layout and wiring density of the integrated circuits, which also puts higher and higher requirements on the packaging technology and the packaging structure of the semiconductor chips.

In the prior art, a wafer level packaging process is adopted for a micro-packaged integrated circuit, as shown in fig. 1, the package mainly comprises a surface protection layer 11, a chip 12 and a pin 13, wherein the surface protection layer 11 is generally made of a polyimide material; the chip 12 is made of silicon material; the pins 13 are generally metal balls with high tin content.

The wafer level packaging process has the following disadvantages: (1) the cost is high: in order to match a welding pad matrix on the mainboard of various conventional portable electronic products, the product requires that a matched internal integrated circuit must have a corresponding size, and crystal grains with the same area size must be used at present due to structural limitation, so that the product cost is greatly increased; (2) the production period is long: the existing product uses a similar wafer manufacturing technology, a photomask and a metal sputtering process are mostly adopted to connect a circuit of a crystal grain and peripheral pins, and the production flow is complicated; (3) the product has strict requirements on the use environment: as shown in fig. 1, since the chip 12 is directly exposed, the silicon material is brittle, and edge chipping, surface circuit scratch, ball dropping, and the like are easily generated in the actual use process.

In order to solve the above technical problems, it is desirable to provide a semiconductor package structure with small size, low cost, short production cycle, and less damage to chips, pins, etc.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to provide a semiconductor packaging structure, it is small, with low costs, production cycle is short, and chip, pin etc. are not fragile.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor package structure, including a chip, a bonding material layer, a lead frame and a package body, wherein the chip is polygonal, the side of a plurality of sides of the chip is fixedly connected with the lead frame through the bonding material layer, the lead is connected with the chip and the lead frame, the package body has a side surface with the same number as the chip sides, the chip, the bonding material layer, the lead and the lead frame are sealed into a whole through the package body, and the outer end of the lead frame exposed outside the package body is provided with a solder joint;

the chip at least comprises three edges, wherein one or more edges are arranged corresponding to one end of the input end and the output end with less pin number requirement, the other edges are arranged corresponding to the other end of the input end and the output end with more pin number requirement, and each pin is respectively connected with the lead frame through a lead.

The chip is a trilateral shape, the packaging body correspondingly has three side surfaces, one side of the chip is arranged corresponding to one end of the input end and the output end with less pin number requirement, and the pins on the side are connected with the lead frame arranged on the corresponding side surface of the packaging body through leads; the other two edges of the chip are arranged corresponding to the other ends of the input end and the output end with more pin number requirements, and the pins on the two edges are connected with lead frames arranged on two corresponding side surfaces of the packaging body through leads.

The chip can also be a pentagon, the packaging body correspondingly has five side faces, one or two sides of the chip are arranged corresponding to one end of the input end and the output end with less pin number requirement, and the pins on the one or two sides are connected with the lead frame arranged on the corresponding side face of the packaging body through leads; the other sides of the chip are arranged corresponding to the other ends of the input end and the output end with more pin number requirements, and the pins on the other sides are connected with lead frames arranged on the other sides of the packaging body through leads.

The shape of the chip is not limited to the three-sided and five-sided shapes described above, and can be adjusted according to the number of pins and the volume required by the product.

Wherein, the outer end of the welding spot is provided with a welding-assistant coating.

Preferably, the soldering assistant plating layer is a tin plating layer, and the thickness of the soldering assistant plating layer is 0.01-0.1 mm.

The welding points on the outer side of the same side face of the packaging body comprise pin welding points and heat dissipation welding points, and the heat dissipation welding points are connected with one pin welding point through a lead.

The pin welding points are regular or irregular, and the heat dissipation welding points are regular or irregular.

The pin welding points are circular, square, oval or polygonal, and the heat dissipation welding points are circular, square, oval or polygonal.

Preferably, one of the pin pads has a different shape than the remaining pin pads.

The utility model discloses an above-mentioned technical scheme's beneficial effect as follows:

1. the utility model discloses a polygonal chip and packaging body provide sufficient space for the more pin of figure, corresponding volume that reduces semiconductor package structure to avoid producing bridging, electromigration scheduling problem, small, with low costs, production cycle is short.

2. The utility model discloses a do not have pin, little packaging technology, chip and pin do not expose outside, and chip, pin etc. are not fragile.

Drawings

Fig. 1 is a schematic diagram of a conventional semiconductor package structure in the background art of the present invention;

fig. 2 is a schematic structural diagram of a first embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a distribution of solder points according to an embodiment;

fig. 4 is a top view of a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a solder joint in the second embodiment.

Description of reference numerals:

11. a surface protection layer; 12. a chip; 13. a pin;

1. a chip; 2. a layer of bonding material; 3. a lead wire; 4. a lead frame; 5. a package body; 6. welding spots; 7. welding-assistant plating; 8. a pin welding spot; 9. radiating welding spots;

21. a chip; 24. a lead frame; 25. a package body; 28. a pin welding spot; 29. and (4) radiating welding spots.

Detailed Description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.

Example 1

An embodiment of the utility model provides a semiconductor package structure, including chip 1, adhesive material layer 2, lead wire 3, lead wire frame 4 and packaging body 5, chip 1 is the polygon, adhesive material layer 2 and lead wire frame 4 fixed connection are passed through to the side on a plurality of limits of chip 1, lead wire 3 connects chip 1 and lead wire frame 4, packaging body 5 has the side the same with 1 limit number of chip, chip 1, adhesive material layer 2, lead wire 3 and lead wire frame 4 are sealed into an organic whole through packaging body 5, the outer end that exposes in the packaging body 5 outside of lead wire frame 4 is equipped with solder joint 6, and semiconductor package structure corresponds the welding through the input/output end of solder joint and drive circuit.

And the outer end of the welding spot 6 is provided with a welding-assistant plating layer 7.

Preferably, the soldering assistant plating layer 7 is a tin plating layer, and the thickness is 0.01-0.1 mm.

The welding points on the outer side of the same side face of the packaging body 5 comprise pin welding points 8 and heat dissipation welding points 9, and the heat dissipation welding points 9 are connected with one pin welding point 8 through a lead.

The pin pads 8 may be regular in shape, such as circular, square, oval or polygonal; and may be irregularly shaped.

The heat dissipation welding spots 9 can be in a regular shape, such as a circle, a square, an ellipse or a polygon; and may be irregularly shaped.

The chip 1 at least comprises three edges, wherein one or more edges are arranged corresponding to one end of the input end and the output end with less pin number requirement, the other edges are arranged corresponding to the other end of the input end and the output end with more pin number requirement, and each pin is respectively connected with the lead frame 4 through a lead 3.

The technical solution of the present invention will be further explained with reference to the following specific examples.

Example 1

As shown in fig. 2, in this embodiment, the chip 1 is a trilateral, the package body 5 correspondingly has three side surfaces, one of the edges of the chip 1 is disposed corresponding to one of the input and output terminals with less pin count, and the pins on the edge are connected to the lead frame 4 disposed on the corresponding side surface of the package body 5 through the leads 3; the other two edges of the chip 1 are arranged corresponding to the other ends of the input and output ends with more pin count requirements, and the pins on the two edges are connected with lead frames 4 arranged on two corresponding side surfaces of the packaging body 5 through leads 3.

As shown in fig. 3, in the present embodiment, the pin pads 8 are circular and are arranged in a row on the side surface of the package body 5, and the heat dissipation pad 9 is arranged in the middle of the row of pads and is connected to the adjacent pin pad 8 through a wire.

Example 2

As shown in fig. 4, in this embodiment, the chip 21 is pentagonal, the package body 25 correspondingly has five side surfaces, one or two sides of the chip 21 are disposed corresponding to one end of the input and output terminals with less pin count, and the pins on the one or two sides are connected to the lead frame 24 disposed on the corresponding side surface of the package body 25 through leads; the other sides of the chip 21 are disposed corresponding to the other ends of the input and output terminals requiring a large number of pins, and the pins on the other sides are connected to lead frames 24 disposed on the other sides of the package body 25 through leads.

As shown in fig. 5, in the present embodiment, a heat dissipation pad 29 is disposed in the middle of the side surface of the package body 25, the plurality of pin pads 28 are uniformly distributed on the outer side of the heat dissipation pad 29 along the circumferential direction, and the heat dissipation pad 29 is connected to one of the pin pads 28 through a wire.

Of the plurality of pin pads 28, one of the pin pads 28 has a different shape than the remaining pin pads.

Compare in prior art and adopt rectangle chip package structure to and the conventional technique of pin is laid on the both sides of adoption rectangle, the utility model discloses an adopt trilateral or pentagonal chip, lay the pin on trilateral or the five sides of chip, provide sufficient space of laying for intensive pin. The utility model discloses a do not have pin, little packaging technology, the encapsulation back solder joint exposes outside, and not the pin, avoids among the packaging process chip, pin etc. damaged problem.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A semiconductor packaging structure is characterized by comprising a chip, an adhesive material layer, a lead frame and a packaging body, wherein the chip is polygonal, the side of a plurality of sides of the chip is fixedly connected with the lead frame through the adhesive material layer, the lead is connected with the chip and the lead frame, the packaging body is provided with the side faces with the same number as the sides of the chip, the adhesive material layer, the lead and the lead frame are sealed into a whole through the packaging body, and the outer end of the lead frame, which is exposed outside the packaging body, is provided with a welding spot;

2. The semiconductor package structure according to claim 1, wherein the chip is triangular, the package body correspondingly has three side surfaces, one of the side surfaces of the chip is disposed corresponding to one of the input and output terminals requiring less number of pins, and the pins on the side surface are connected to lead frames disposed on the corresponding side surface of the package body through leads; the other two edges of the chip are arranged corresponding to the other ends of the input end and the output end with more pin number requirements, and the pins on the two edges are connected with lead frames arranged on two corresponding side surfaces of the packaging body through leads.

3. The semiconductor package structure of claim 1, wherein the chip is pentagonal, the package body correspondingly has five side surfaces, one or two of the side surfaces of the chip are disposed corresponding to one of the input and output terminals requiring less number of pins, and the pins on the one or two side surfaces are connected to lead frames disposed on the corresponding side surfaces of the package body through leads; the other sides of the chip are arranged corresponding to the other ends of the input end and the output end with more pin number requirements, and the pins on the other sides are connected with lead frames arranged on the other sides of the packaging body through leads.

4. The semiconductor package structure of claim 1, wherein an outer end of the solder joint is provided with a solder-assist plating layer.

5. The semiconductor package structure of claim 4, wherein the solder-assist plating layer is a tin plating layer with a thickness of 0.01-0.1 mm.

6. The semiconductor package structure of claim 1, wherein the solder joints on the outer side of the same side of the package body comprise a pin solder joint and a heat dissipation solder joint, and the heat dissipation solder joint is connected with one of the pin solder joints through a wire.

7. The semiconductor package structure of claim 6, wherein the pin pad is circular, square, oval or polygonal, and the heat sink pad is circular, square, oval or polygonal.

8. The semiconductor package structure of claim 6, wherein one of the pin pads has a different shape than the remaining pin pads.