Ϊ244176 13589twf.d〇 九、發明說明： 【發明所屬之技術領域】 有關封f:件與f程方法，且特別是 之銲軍層剝離的方法Ep型封裝基板與避免接腳間 【先前技術】 近年來’隨著電子技術的 的相繼問世，使得則，、w科技電子產業 推陳出^二L 功能更佳的電子產品不斷地 =二ΠΓ、薄、短、小的趨勢設計。目前在半 經常載器（灿_咖啦腊）是 n ·的構衣兀*件之一，其主要分為堆疊壓合式 (I:ated)及積層s (bu細p)二大麵。—式 7載=之基材（Substmte)主要係 又° 點，作為連接晶片或外部電路 承#哭且古心“ 2 輸出媒介。由於基板型 裝緊湊以及性能良好等優點，因 此已成為封衣（paekage)製財何或_縣元件之一。 方面’在高度情報化的今曰’為符合電子裝置 南速處理化、多功能化、積集化及小型輕量化等多方面的 要求，半導體製程技術也不斷朝向微型化及高密 展，而基板型承載器之線路設計也隨著晶片功能之二展^ 封裝之需求而日亦複雜。然而，隨著基板型承載器^ 化及其線路的複雜化’也連帶使得現有的基板 二 製程上遭遇許多新的問題。 戰时在 1244176 13589twf.doc Μ同時參考圖1八與1B，其中圖1A繪示為習知之一 種平面格狀陣列（Land Grid Array，LGA)型態之矩陣型封 裝基板的局部示意圖，而圖1B繪示為圖1A之矩陣型封裝 基板進行切割（sawing)後所形成之單一承載器的局部示 意圖。矩陣型封裝基板1〇〇係由一封裝基材11〇以及配置 於封衣基材110表面之一銲罩層（s〇lder mask) ^加所構 成，並可劃分為多個承載單元102以及介於相鄰之承載單 兀=2之間的一邊條區1〇4。此外，每一承載單元1⑽之 封裝基材no的外圍具有多個接腳112，其係與承 1〇2之邊緣切齊，且鮮罩層12〇具有多個開口 用以暴 ^接腳U2以及接聊112兩側之部分封褒紐ι ^ 面。 今 明再參考圖1A與1B’習知可對上述之矩陣型 割’以藉由刀具移除邊條:銲= 。:及，才Π。，進而分離出多個獨立之= 106。值件注意的是，由 切割面上造成一側向鹿力邊條區104時，會在 便可能受到此侧向應力的作用，== (Peeing) (crack) 〇 能經由鮮軍層12G的剝離處進人解 封裝基材之内部線路遭受破 土 中，而使付 銲料等)進行接腳與外部電‘卜：欲藉由導電材(如 的剝離或斷裂，使得導嘗1^接亦可能因銲罩層120 1244176 13589twf.doc 【發明内容】 有於此本發明的目的就是在提供一種<避免接腳 間之銲罩層剝離的晶片封裝結構，其接腳間之錄罩層與封 裝基材之間可具有較佳之接合強度，以提高切割製程之良 率〇 本發明的又一目的就是在提供一種可避免接腳間之 銲罩層剝離的矩陣型封裝基板，其接腳間之鲜罩層與封裝 基材之間可具有杈佳之接合強度，以提高切割製程之良率。 ^發明的另-目的是在提供—種避免接腳間之鲜罩 二摩的方法，用以提㊄接腳間之銲罩層與縣基材之接 5強度，進而改善切割製程的良率。 構，述ί其他目的’本發明提出-種晶片封裝結 夂二2 器、一晶片以及一封裳膠體，其中承載 ;= 封裝基材、至少-間隔條以及-輝罩層。ί 裝基材例如具有多個接腳，其係位於封褒 間隔條係配置於縣基材之外圍， 卜圍’而 之接腳之間。此外，a⑺條係位於兩相鄰 罩層係覆蓋間裝基材上，其中辉 二用《暴_腳。 接腳，而封裝=置 材上且封裝膠體係覆蓋晶片。 承載=其更=:=型：^基板’其例如具有多個 隔條以及—鲜ΐ::::包括一封裝基材、至少-間 曰封裝基材例如具有多個接腳，其係位 1244176 i3589twf.doc 園’且間隔:::於置基材之外 配置於封裝基材上，苴 日1另外，銲罩層係 具有=接腳的多個開:心暴覆：::。’且㈣ ♦，開心之:如=封=㈣型封裝基板 圍之部分封装基材的表面。此外開：=露，周 層例如係内縮於封裝基材之、募缝才目闕口間之部分輝罩 之材質例如是銅$ _且間隔條之材質與接腳 齊。 糾接_如可與縣歸之邊緣切 之二:=目=更：-種避免接腳間 圍例如具有多個接腳，且二 緣切背。接著，形成多個間隔條才邊 ，接腳相互間隔排列。然後， 接腳的多個開口，用以暴露出接腳。料層具有對應於 在本發明之避免接腳間之銲罩層剝離的 條例如可㈣裝基材之接腳同時形成。此外，形 =方式例如可先形成-銲罩材料層於封餘 ^匕此料材料層，以於轉罩材料層上形朗口=圖 ==時’例如可使開口暴露出接腳周圍之部分封裝 基於上述’本發明之晶片封裳結構、矩陣型封裝基板 1244176 13589twf.doc /、避免接腳間之銲罩層剝離的方法係於接腳間之銲罩層的 下方开/成間條’以藉由間隔條與銲罩層之結合來提高 銲罩層之接合強度，進而提供較佳之切割良率與可靠度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 ，同時參考圖2A與2B ’其中圖2A㈣為本發明之 較佳實施例之-種矩_封裝基板的局部示意圖，而圖2β 緣不，圖2A之矩陣型封裝基板進行切難所形成之單一 承載器的局部示意g。轉型封裝基板細例如包括一封 裝基材21G、-銲罩層22〇以及多個間隔條23()，其中封裝 基材210例如是由多個圖案化線路層（未綠示）以及至少 -介電層（未繪示）交替疊合所構成之—多層板，且封褒 基材210之表面線路層例如延伸多個長形之接腳212至封 裝基材210的外圍’以料域基材21()與外部電路之輸 出入媒71。此外，間隔條230係配置於封裝基材21〇上， 並與接腳212相互間隔排列。在一較佳實施例中，間隔條 230與接腳212例如可以是由同—線路層所構成，亦即在 形成封裝基材210表面之圖案化線路層（未緣示）的時候， 便同時形成間隔條230與接腳212，且其材f例如是銅。 田然，在不考慮製程成本的情形下，間隔條與接腳 亦可以是藉由不同之製程步驟所形成，而間隔條23〇之材 質的選擇例如是與㈣層23G具核佳之接合特性的材 1244176 13589twf.doc 於封裝基材2〗0上，並覆蓋間隔條23〇， ^ 212及其兩侧之部分封裝基材21〇的表面，換言 (Non-Solder Mask Defined, NSMD) ^ 上开/点/)成鲜罩層220的方式例如是先在封裝基材210 =:_層(未緣示），之後再對此銲罩材料層 矩陣i二ΪΓ*圖案化的動作’以形成開口 222。此外， ί衣基板200例如可劃分為多個承載單元2 "於相鄰之承載單元202之間的一邊條區2〇4，並中= 具切割邊條區綱，可使承載單元202相互分離，^ ===之承載器2〇6。值得一提的是，經過切割後: 之鲜罩層220係與其下方之間隔條230接 :罢Ϊ 將可承受刀具形成的剪應力，而有效避免 、干罩層220發生剝離或斷裂之問題。 截哭二ί考圖3，其繪示本發明之較佳實施例之另一種承 32=^示意圖。承載器3〇6之鮮罩層320係藉由開。 2 =出封裝基材31〇上的多個接腳312，並覆蓋相鄰接 ==咖條330。值雜意的是，本實齡!之接腳 ^之間隔條33〇與銲罩層no係自封裝基材训之邊 、毒内‘距離d，因此可在切割時減輕銲罩層32〇可能受 I244176twf_d〇c 施例中=:’進而提高切割之良率。此外，在-實 隔條•輝罩間隔條330之寬度w，以增強間 條33〇不Ϊ義之接合效果。惟需注意的是間隔 接合時，相i接腳=外，以免承載器與外界電路 的現象。 腳12之間藉由間隔條330而發生誤導通 載器音4圖其ΪΓ發明之較佳實施例之又一種承 422a a ""圖八中，銲罩層42〇之開口 422的角落 割時應力口 是弧形角’因此可有效避免切 jf"。當然，在本發明之其他實施例中，開口 422之 角洛更可以是折角或其他可改善結構強度之形狀。 述之’ 5t參考圖5A與5B ’其中圖5A繚示為應用上 所得到之—種晶片封裝結構的剖面示意圖，而 圖5】:示為圖5A之晶片封裝結構的下視示意圖。如圖 恭所不，晶片封裝結構5〇〇係由一晶片510、一承 其Γ J Μ及一封裝膠體Μ0所構成。7氣載器520之封裝 i： * I 2例如具有承載表面522a以及相對之背面522b， 個Γΐϊ表面522a上係配置有—晶片承載區5施以及多 526 L m而背面522b之外圍係配置有多個接腳 ，且接㈣遍係透蝴懿材522㈣至接腳伽。 述實施例所示’承載器520之兩相鄰接腳526 52 、=隔條526a，且銲罩層528係覆蓋於間隔條 a ，並藉由開口 528a暴露出接腳526。然而，關於接 1244176 13589twf.doc 腳526、間隔條526a以及銲罩層528等相關元件的配置關 係與麦化’凊參考上述實施例，在此不再重複贅述。 凊再參考圖5B，晶片510例如具有主動表面510a以 及相對之背面51〇b，且晶片510係以背面510b朝向承載 态520而配置於晶片承載區524a上，其中晶片承載區524a 有助於晶片510之散熱。此外，晶片510之主動表面510a 你|如具有多個銲墊514，其中銲墊514係以打線的方式而 分別透過多條導線54〇耦接至封裝基材522之接合墊 524b。另外，封裝膠體530係配置於封裝基材522之承載 表面522a，並覆蓋晶片51〇。 值得一提的是，除了上述之晶片封裝結構之外，本發 明之承載ϋ更可應用於其他更多類型之日日日片封裝結構，而 依據不同種類之晶片與設計需求，本發明之晶片與承載器 之間更例如可藉由覆晶技術或其他封裝技術進行接合。 $上所述，本發明係於接腳間形成間隔條，並使接腳 間之詳罩層覆蓋闕隔條上，以改善胃知銲罩層與封聚基 材間之接合不佳的情形。值得_提的是，上述實施例所緣 不之承載裔僅為舉例之用，其並非用以限定本發明，其中 ^接腳以及鮮罩層之開口的形狀、尺寸，以及間隔條之 ^、尺相及配置方式當可隨製程參數與設計需求而有 4之變化。藉由本發明之晶片封裝結構、矩陣型封裝基 接腳間之銲罩層剝離的方法可有效避免切割時銲 曰4離或斷裂之問題，因而可提昇切割製程之良率，且 由於銲罩層與封裝基材間具有良好的接合效果，更有助於 12 1244176 13589twf.doc 改善承載器與晶片封裝結構的可靠度。 雖然本發明已以較佳實施例揭露如上，铁苴並非用以 蚊本發明，任何_此技藝者，在不脫離本發明之 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A緣示為習知之一種平面格狀陣列型態之矩陣型 封裝基板的局部示意圖。 …圖1B纷示為圖^之矩陣型封裝基板進行士刀割後所形 成之單一承載器的局部示意圖。 圖2A繪不為本發明之較佳實施例之一種矩陣型 基板的局部示意圖。 又 圖_為圖2a之轉型封裝基板進行切割後所形 成之早一承載器的局部示意圖。 ，3繪示為本發明之較佳實施例之另一種承載器的 部示意圖。 ，4、會不為本發明之較佳實施例之又一種承載器的局 部不思圖。 圖。 圖5A纟會示為本發明之一種晶片封裝結構的剖面示意 ，5B繪示為圖5人之晶片封裝結構的下視示意圖 【主要元件符號說明】 100 :矩陣型封裝基板 110 :封裝基材 13 1244176 13589twf.doc 102 ··承載單元 104 ··邊條區 106 :承載器 112 :接腳 120 :銲罩層 122 ··開口 200 :矩陣型封裝基板 202 :承載單元 204 :邊條區 206 :承載器 210 :封裝基材 212 :接腳 220 :銲罩層 222 :開口 230 :間隔條 306 :承載器 310 :封裝基材 312 :接腳 320 :銲罩層 322 ··開口 330 :間隔條 420 :銲罩層 422 :開口 422a :角落 14 1244176 13589twf.doc d :距離 w :寬度 500 :晶片封裝結構 510 :晶片 510a :主動表面 510b :背面 514 :銲墊 520 :承載器 522 :封裝基材 522a ··承載表面 522b :背面 524a :晶片承載區 524b :接合墊 526 :接腳 526a ··間隔條 528 :銲罩層 528a :開口 530 :封裝膠體 540 :導線 15Ϊ244176 13589twf.d.9. Description of the invention: [Technical field to which the invention belongs] Related methods of sealing f: pieces and f-processes, and especially the method of peeling the solder layer Ep-type package substrate and avoiding pins [prior art] In recent years, with the successive advent of electronic technology, the electronic industry with better and better functions has been introduced, and electronic products with better functions have been continuously designed with two thinner, thinner, shorter, and smaller trends. At present, the semi-regular loader (Chan_Calara) is one of the n * garments, which is mainly divided into two types: stacked and laminated (I: ated) and laminated s (bu thin p). —Substmte of 7 type = is mainly used as connecting point or external circuit bearing. Cry and old-fashioned "2 output medium. Due to the compactness of the substrate and good performance, it has become a seal. (Paekage) One of the components of the financial system or the county. In terms of high-informatization today, semiconductors are in line with the requirements of the South Korean electronics processing, multifunctionalization, accumulation, and miniaturization. The process technology also continues to be miniaturized and high-density, and the circuit design of the substrate type carrier is also becoming more complicated with the development of the second function of the chip ^ packaging requirements. However, as the substrate type carrier and its circuit "Complication" also caused many new problems in the existing substrate two process. At wartime, 1244176 13589twf.doc MU will refer to Figures 18 and 1B at the same time, where Figure 1A shows a conventional planar grid array (Land Grid Array (LGA), a partial schematic diagram of a matrix-type package substrate, and FIG. 1B is a partial schematic diagram of a single carrier formed after the matrix-type package substrate of FIG. 1A is sawing The matrix packaging substrate 100 is composed of a packaging substrate 110 and a solder mask layer disposed on the surface of the sealing substrate 110, and can be divided into a plurality of bearing units 102. And a side strip area 104 between adjacent load cells = 2. In addition, the periphery of the packaging substrate no of each load cell 1⑽ has a plurality of pins 112, which are connected to the load 102. The edges are aligned, and the fresh cover layer 120 has a plurality of openings to expose pins U2 and part of the sealing surfaces on both sides of the chat 112. Now referring to FIGS. 1A and 1B, the conventional method can be used for the above. Matrix cut to remove the edges by the tool: Weld =.: And, only Π., And then separate a number of independent = 106. It is important to note that the side of the cutting surface causes a deer edge When the strip area is 104, it may be affected by this lateral stress. == (Peeing) (crack) 〇 The internal circuit of the decapsulated substrate can be broken through the peeling point of the fresh military layer 12G, which will cause the ground to be broken. (For example, soldering, etc.) are used to connect the pins to the external electrical source. If the conductive material (such as peeling or breaking) is used, it may be caused by soldering. 120 1244176 13589twf.doc [Summary of the Invention] The purpose of the present invention is to provide a chip packaging structure < avoiding the peeling of the solder mask layer between the pins, between the mask layer between the pins and the packaging substrate It can have better bonding strength to improve the yield of the cutting process. Another object of the present invention is to provide a matrix-type package substrate that can avoid the peeling of the solder mask layer between the pins. The packaging substrates can have good joint strength to improve the yield rate of the cutting process. ^ Another purpose of the invention is to provide a method to avoid fresh cover between the pins, which can be used to improve the joints. The strength of the welding mask layer and the base material is 5 to improve the yield of the cutting process. Structure, and other purposes. The present invention proposes a chip packaging device, a chip, and a colloid, which carry; = a packaging substrate, at least a spacer, and a glow mask. The mounting substrate has, for example, a plurality of pins, which are located between the sealing spacers and the periphery of the county substrate, and between the pins. In addition, the a purlin is located on two adjacent cover systems covering the interlayer substrate, of which Hui Er uses "violet feet." Pins, and the package = on the material and the encapsulant system covers the chip. Carrying = its more =: = type: ^ substrate 'which, for example, has a plurality of spacers, and-fresh: ::: includes a packaging substrate, at least-the packaging substrate has, for example, a plurality of pins, its position 1244176 i3589twf.doc Park 'and the interval :: is placed on the packaging substrate outside the substrate, the next day 1 In addition, the solder mask layer has multiple openings with = pins: Heartburst :::. ’And ㈣ ♦, happy: such as = encapsulation = encapsulation substrate surface around a part of the encapsulation substrate. In addition: = exposed, the peripheral layer is, for example, the material of the part of the shroud, which is retracted inside the packaging substrate, and the seam is between the mouth and the mouth. The material of the spacer is, for example, copper. Twist_If it can be cut with the edge of the county, the second one: = 目 = 更:-to avoid a pin interval, for example, there are multiple pins, and the two edges are cut back. Next, a plurality of spacers are formed, and the pins are spaced from each other. Then, multiple openings of the pins are used to expose the pins. The material layer has strips corresponding to the stripping of the solder mask layer between the pins of the present invention, for example, the pins of the base material can be mounted simultaneously. In addition, the shape = method can be formed, for example,-a welding mask material layer is formed on the sealing material layer, so that the mouth of the hood material layer is shaped like a mouth = Figure = = When 'for example, the opening can be exposed around the pins. Part of the package is based on the wafer sealing structure of the present invention, the matrix package substrate 1244176 13589twf.doc /, and the method of avoiding the peeling of the solder mask layer between the pins is to open / form the strip below the solder mask layer between the pins. 'In order to improve the bonding strength of the welding mask layer through the combination of the spacer and the welding mask layer, thereby providing better cutting yield and reliability. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with reference to the accompanying drawings, as follows. [Embodiment] Referring to FIGS. 2A and 2B together, FIG. 2A is a partial schematic diagram of a kind of moment_package substrate, which is a preferred embodiment of the present invention, and FIG. 2β has a margin. The matrix package substrate of FIG. 2A is difficult to solve. Schematic g of a single carrier formed. The transformation package substrate includes, for example, a packaging substrate 21G, a solder mask layer 22, and a plurality of spacers 23 (). The packaging substrate 210 is, for example, composed of a plurality of patterned circuit layers (not shown in green) and at least- An electrical layer (not shown) is alternately stacked to form a multilayer board, and the surface circuit layer of the sealing substrate 210 extends, for example, a plurality of elongated pins 212 to the periphery of the packaging substrate 210. 21 () and the input / output medium 71 of the external circuit. In addition, the spacer 230 is disposed on the packaging substrate 21 and is spaced apart from the pins 212. In a preferred embodiment, the spacers 230 and the pins 212 may be composed of the same circuit layer, that is, when a patterned circuit layer (not shown) on the surface of the packaging substrate 210 is formed, they are simultaneously The spacers 230 and the pins 212 are formed, and the material f is, for example, copper. Tian Ran, without considering the cost of the process, the spacers and pins can also be formed by different process steps, and the material selection of the spacer 23 is, for example, a material with good bonding characteristics with the sacrificial layer 23G Material 1244176 13589twf.doc on the sealing substrate 2 and covering the surface of the spacer 23 °, ^ 212 and part of the sealing substrate 21 on both sides, in other words (Non-Solder Mask Defined, NSMD) ^ / Dot /) The method of forming the fresh cover layer 220 is, for example, firstly encapsulating the substrate 210 =: _ layer (not shown), and then performing a patterning operation on the material layer matrix i of the solder cover to form an opening. 222. In addition, the clothing substrate 200 can be divided into a plurality of load bearing units 2 " one side strip area 204 between adjacent load bearing units 202, for example, with a cutting edge strip outline, which can make the load bearing units 202 mutually Separated, ^ === of the carrier 206. It is worth mentioning that after cutting: the fresh cover layer 220 is connected to the spacer 230 below it: it will be able to withstand the shear stress formed by the cutter, and effectively avoid the problems of peeling or breaking of the dry cover layer 220. Interrupted Cry 2 and FIG. 3, which illustrates another schematic diagram of another embodiment of the present invention. The fresh cover layer 320 of the carrier 306 is opened. 2 = The multiple pins 312 on the packaging substrate 31 are output, and the adjacent pins are covered. What is strange is that the space 33 of the pin ^ of the current age! And the solder mask layer no are the distance d from the edge of the package substrate, and therefore the solder mask layer 32 can be reduced during cutting. May be affected by I244176twf_d〇c == 'in the example to improve the yield of cutting. In addition, the width w of the in-real spacer and the mask spacer 330 is increased to enhance the unambiguous joining effect of the spacer 33. However, it should be noted that the phase i pin = outside when the interval is connected, so as to avoid the phenomenon of the carrier and the external circuit. A misalignment of the carrier sound occurs between the feet 12 through the spacer 330. FIG. 8 shows another corner of the opening 422 of the solder mask layer 42 in the preferred embodiment of the invention. When cutting, the stress port is an arc angle, so it can effectively avoid cutting jf ". Of course, in other embodiments of the present invention, the corners of the opening 422 may be chamfered or other shapes that can improve the structural strength. 5 'is referred to FIGS. 5A and 5B. Among them, FIG. 5A is a schematic cross-sectional view of a chip packaging structure obtained in the application, and FIG. 5] is a schematic bottom view of the chip packaging structure of FIG. 5A. As shown in the figure, the chip package structure 500 is composed of a chip 510, a substrate Γ J M, and a packaging colloid M0. 7 Package i of air carrier 520: * I 2 has, for example, a bearing surface 522a and an opposite back surface 522b. The Γΐϊ surface 522a is provided with a wafer bearing area of 5 μm and more than 526 L m. Multiple pins are connected through the transparent material 522 to the pins. The two adjacent pins 526 52 and the spacer 526a of the carrier 520 shown in the embodiment described above, and the solder mask layer 528 covers the spacer a, and the pins 526 are exposed through the opening 528a. However, regarding the configuration relationship of the related components such as 1244176 13589twf.doc pin 526, spacer 526a, and solder mask layer 528, etc., refer to the above embodiment, and will not be repeated here. 5B, the wafer 510 has, for example, an active surface 510a and an opposite back surface 51b, and the wafer 510 is disposed on the wafer carrying area 524a with the back surface 510b facing the carrying state 520, where the wafer carrying area 524a helps the wafer 510 heat dissipation. In addition, the active surface 510a of the chip 510 may have a plurality of bonding pads 514, wherein the bonding pads 514 are coupled to the bonding pads 524b of the packaging substrate 522 through a plurality of wires 540 respectively. In addition, the encapsulating gel 530 is disposed on the bearing surface 522a of the encapsulating substrate 522 and covers the wafer 51. It is worth mentioning that in addition to the above-mentioned chip packaging structure, the carrier of the present invention can also be applied to other more types of day-to-day chip packaging structures. According to different types of wafers and design requirements, the wafers of the present invention It can be bonded to the carrier by, for example, flip-chip technology or other packaging technology. As mentioned above, the present invention is to form a spacer between the pins, and to cover the 阙 spacer with a detailed mask layer between the pins to improve the poor connection between the welding mask layer and the sealing substrate. . It is worth mentioning that the bearing examples described in the above embodiments are only examples, and are not intended to limit the present invention. The shape and size of the openings of the ^ pins and the fresh cover layer, and the spacers ^, The size, phase and configuration method can be changed according to the process parameters and design requirements. The method for peeling the solder mask layer between the chip packaging structure and the matrix-type package base pins of the present invention can effectively avoid the problem of solder separation or breakage during cutting, thereby improving the yield of the cutting process, and because the solder mask layer It has a good bonding effect with the packaging substrate, which helps 12 1244176 13589twf.doc to improve the reliability of the carrier and chip packaging structure. Although the present invention has been disclosed as above with a preferred embodiment, the iron cricket is not used to mosquito the invention. Anyone skilled in the art can make some modifications and retouching without departing from the scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. [Brief description of the figure] FIG. 1A is a partial schematic diagram of a conventional matrix package substrate of a planar grid array type. … FIG. 1B is a partial schematic diagram of a single carrier formed by the matrix-type package substrate of FIG. ^ After cutting with a knife. FIG. 2A is a partial schematic diagram of a matrix substrate according to a preferred embodiment of the present invention. And Figure_ is a partial schematic diagram of an early carrier formed by cutting the transformation package substrate of Figure 2a. 3 is a schematic diagram of another carrier according to a preferred embodiment of the present invention. 4. It may not be a local plan of another carrier of the preferred embodiment of the present invention. Illustration. FIG. 5A is a schematic cross-sectional view of a chip packaging structure of the present invention, and FIG. 5B is a schematic bottom view of the chip packaging structure of FIG. 5 [Description of main component symbols] 100: Matrix packaging substrate 110: Packaging substrate 13 1244176 13589twf.doc 102 ··························································· Device 210: encapsulation substrate 212: pin 220: solder mask layer 222: opening 230: spacer bar 306: carrier 310: encapsulation substrate 312: pin 320: solder mask layer 322 ·· opening 330: spacer bar 420: Solder mask layer 422: opening 422a: corner 14 1244176 13589twf.doc d: distance w: width 500: chip package structure 510: wafer 510a: active surface 510b: back surface 514: pad 520: carrier 522: packaging substrate 522a Carrying surface 522b: Back surface 524a: Wafer carrying area 524b: Bonding pad 526: Pin 526a. Spacer 528: Solder mask layer 528a: Opening 530: Encapsulant 540: Wire 15