TW200921788A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TW200921788A
TW200921788A TW097130523A TW97130523A TW200921788A TW 200921788 A TW200921788 A TW 200921788A TW 097130523 A TW097130523 A TW 097130523A TW 97130523 A TW97130523 A TW 97130523A TW 200921788 A TW200921788 A TW 200921788A
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TW
Taiwan
Prior art keywords
insulating layer
layer
wiring
semiconductor device
compound
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Application number
TW097130523A
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Chinese (zh)
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TWI375274B (en
Inventor
Yoshihiro Nakata
Tadahiro Imada
Shirou Ozaki
Yasushi Kobayashi
Kohta Yoshikawa
Ei Yano
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Fujitsu Ltd
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Publication of TWI375274B publication Critical patent/TWI375274B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming an insulating layer comprising silica-based insulating material, processing the insulating layer, hydrophobizing the insulating layer by applying a silane compound to act on the insulating layer; and irradiating the insulating layer with light or an electron beam.

Description

200921788 九、發明說明： 【發明所屬之技術領域3 背景 本發明係有關於一種包括一乾蝕刻一二氧化矽基絕緣 5 層之半導體裝置之製造方法的技術。 【先前技術3 半導體積體電路之積體化與裝置密度的增加使多層半 導體裝置之需求增加。積體化增加導致配線距離之減少， 因此，它會造成在配線間之電容增加並造成配線延遲。 10 配線延遲受到配線之電阻與在該等配線間之電容的影 響，且由以下公式產生：BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for fabricating a semiconductor device including a dry etching-cerium oxide-based insulating 5 layer. [Prior Art 3 The integration of semiconductor integrated circuits and the increase in device density have increased the demand for multilayer semiconductor devices. The increase in integration leads to a reduction in the wiring distance, and therefore, it causes an increase in capacitance between wirings and causes wiring delay. 10 Wiring delay is affected by the resistance of the wiring and the capacitance between the wirings and is generated by the following formula:

T OC CR 其中T表示配線延遲，R表示配線電阻，且C表示在該 等配線間之電容且由以下公式產生： 15 C = 8〇8rS/d 其中d表示在該等配線間之距離，S表示電極面積（該等 配線之相對側表面積），Sr表示一設置在該等配線間之絕緣 材料的介電常數，且ε〇表示真空之介電常數。因此，減少 該絕緣材料之介電常數對於減少該配線延遲是有效的。 20 所使用之習知絕緣材料是如二氧化矽（Si02)、氮化矽 (SiN)、磷矽酸鹽玻璃（PSG)之無機材料及如聚醯亞胺之有機 材料。在半導體裝置中最常使用之CVD Si02層具有大約4 之介電常數，而為低介電常數CVD層且正在研究中之SiOF 層具有大約3.3至3.5之介電常數。但是，該SiOF層具高吸水 200921788 性；因此，其介電常數會隨著吸收水份而增加。 近年來，多孔質絕緣層，即，具有低介電常數之絕緣 材料吸引許多注意。該等多孔質絕緣層之形成方式是將可 藉熱蒸發或分解有機樹脂添加至用以形成低介電常數塗層 5 之材料中，且接著在形成該多孔質絕緣層時因加熱而蒸發 或分解。 二氧化矽基絕緣層，特別是多孔質絕緣層，在形成多 層配線之步驟中會受到工作破壞且因此會增加有效介電常 數。因此，有人提出以下方法：一種以利用一矽氮烷化合 10 物對乾蝕刻層間絕緣層進行表面處理且接著真空乾燥之方 徑，修復一被破壞層之方法。此外，亦有人提出以下方法： 一種以一如矽氮烷、一烷氧矽烷或一乙醯氧矽烷等矽烷化 合物處理一絕緣層，以修復一被破壞層之方法。 【發明内容3 15 概要 依據一實施例之一方面，一種半導體裝置之製造方法 具有：形成一包含二氧化矽基絕緣材料之絕緣層；加工該 絕緣層；藉塗布一矽烷化合物以在該絕緣層上作用，使該 絕緣層疏水化；及以光或一電子束照射該絕緣層。 20 圖式簡單說明 第1圖是一流程圖，顯示第一實施例之半導體裝置之製 造方法； 第2A至2C圖是截面圖，顯示第一實施例之方法的步 驟； 6 200921788 第3A至3C圖是截面圖，顯示第一實施例之方法的步 驟； 第4A至4C圖是截面圖，顯示第二實施例之方法的步 驟； 5 第5A與5B圖是截面圖，顯示第二實施例之方法的步 . 驟； 第6A與6B圖是載面圖，顯示第二實施例之方法的步 驟； 第7A與7B圖是截面圖，顯示第二實施例之方法的步 10 驟； - 第8A與8B圖是截面圖，顯示第二實施例之方法的步 驟； 第9圖是一戴面圖，顯示第二實施例之方法的一步驟； 第10圖是一截面圖，顯示第二實施例之方法的一步驟； 15 第11圖是一截面圖，顯示第二實施例之方法的一步驟； 第12圖是一載面圖，顯示第二實施例之方法的一步驟； 第13圖是一截面圖，顯示第二實施例之方法的一步驟； 第14圖是一截面圖，顯示第二實施例之方法的一步驟； 第15圖是一流程圖，顯示第三實施例之方法的步驟； ' 20 第16A至16D圖是截面圖，顯示第三實施例之方法的步 驟； 第17A與17B圖是截面圖，顯示第四實施例之方法的步 驟； 第18A與18B圖是截面圖，顯示第四實施例之方法的步 7 200921788 驟； 第19圖是一截面圖，顯示第四實施例之方法的一步驟； 第20圖是一截面圖，顯示第四實施例之方法的一步驟； 第21圖是一截面圖，顯示第四實施例之方法的一步驟； 5 第22A與22B圖是截面圖，顯示第五實施例之方法的一 步驟； 第23A與23B圖是截面圖，顯示第五實施例之方法的一 步驟； 第2 4圖是一截面圖，顯示第五實施例之方法的一步驟； 10 第25圖是一截面圖，顯示第五實施例之方法的一步驟； 第26圖是一截面圖，顯示第五實施例之方法的一步驟； 第27A至27D圖是截面圖，顯示用以製備一用以說明此 方法優點之評價樣本之方法的步驟。 C實施方式3 15 較佳實施例之說明 [第一實施例] 以下將參照第1、2A至2C與3A至3C圖說明一第一實施 例之半導體裝置之製造方法。 第1圖是一顯示該方法之流程圖，且第2A至2C圖是顯 20 示該方法之步驟的截面圖。 請參閱第1圖，該方法包括一沈積一二氧化矽基絕緣層 之步驟（步驟S11)、一使該二氧化矽基絕緣層圖案化之步驟 (步驟S12)、一藉電漿處理去除壁沈積物之步驟(步驟S13)、 一以矽烷化合物修復乾蝕刻破壞之步驟（步驟S14)、及一藉 200921788 光或一電子束照射縮合Si-OH基之步驟(步驟si5)。 以下將參照第2 A至2C與3 A至3 C圖詳細說明這些步驟。 該二氧化矽基絕緣層1〇2沈積在一底基板1〇〇(步驟S11) 上，且該底基板1〇〇包含如矽基板之包括MIS電晶體、一或 5 多數配線層等的半導體基板。 該二氧化石夕基絕緣層102之例包括：如電聚§丨〇2層、電 漿SiN層、電漿SiC : Η層、電漿SiC : 0 : Η層、電漿SiC : H : N層、及電漿SiOC層之電漿-CVD層；如有機SOG層與 多孔質二氧化矽層之塗層型絕緣層；及類似層。在此之用 10語“SiC : Η層”表示一含有氧(〇)與氳(H)之Sic層，且在此之 用語“SiC : H : N層”表示一含有氫(η)與氮(N)之SiC層。特 別地，如多孔質二氧化矽層之塗層型絕緣層是較佳的，因 為它們具有低介電常數。 多孔質二氧化矽包括一模板型多孔質二氧化矽材料及 15 一非模板型多孔質二氧化矽材料，且該模板型多孔質二氧 化矽材料具有多數藉分解一混合有機S0G之熱分解樹脂而 形成之孔隙，並且該非模板型多孔質二氧化矽材料具有多 數由粒子形成之孔隙。 該非模板型多孔質二氧化矽材料之例包括可由 20 Catalysts & Chemicals Ind· Co., Ltd.取得之NCS系列、及可 由JSR Corporation取得之LKD系列。 該非模板型多孔質二氧化矽材料之其他較佳例包括含 有一藉在四烷基氫氧化銨(TAA0H)存在下水解而獲得之有 機矽化合物的液體組成物，且該液體組成物製成之材料具 200921788 5 10 15 有等於或大於瓣a之彈性模數、等於或大於霞a之硬 度、及-在低介電常數與高強度狀良好平衡。該有機石夕 化合物之例包括：四燒氧錢、三烧氧傾、甲基三炫氧 石夕烧、乙基三糾魏H綠㈣、祕三烧氧石夕 烧乙稀基一烧氧石夕燒、稀丙基三烧氧石夕烧、縮水甘油基 三烷氧矽烷、二烷氧矽烷、二甲基二烷氧矽烷、二乙基二 烧氧魏、二丙基L規、二苯基二⑨氧雜、二乙 ㈣二&氧魏、二烯丙基二院氧魏、二縮水甘油基二 烧乳石夕燒、苯曱基二燒氧靴、苯乙基二烧氧雜、苯丙 基一烧氧#院、笨乙烯基二烧氧《浅、笨烯丙基二烧氧石夕 院、苯縮水甘絲二⑥切院、甲基乙烯基二烧氧石夕烧、 乙基乙烯基二燒氧魏、及丙基乙稀基二絲石夕烧。 一用以形成—塗布型多孔質二氧化㈣之塗布溶劑可 '浴解作為夕孔質二氡化石夕前驅物之石夕氧烧樹脂且並 不疋特殊的。忒塗布溶劑之例包括：如甲醇、乙醇、正丙 醇 '異丙醇、JL 丁醇、異丁醇、特丁醇之醇類；如紛、甲 酚'一乙酚、二乙酚、丙酚、壬酚、乙烯酚、及烯丙酚之 盼類，如壞已_ '甲基異丁酮、及甲乙酮之酮類；如甲基 賽路蘇及乙基赛路蘇之赛路蘇；如己烧、丙烧及癸烧之烴 類’及如丙二醇、丙二醇單曱基醚、丙二醇單甲基醚乙酸 酯之二醇類。 由塗布型絕緣材料製成之絕緣層可以透過，例 如’一將該絕緣材料塗布於一底基板之步驟、一在80。(:至 350°C之溫度下加熱該底基板之步驟T OC CR where T represents the wiring delay, R represents the wiring resistance, and C represents the capacitance between the wirings and is generated by the following formula: 15 C = 8 〇 8rS / d where d represents the distance between the wirings, S Indicates the electrode area (the opposite side surface area of the wiring), Sr represents the dielectric constant of an insulating material disposed between the wiring lines, and ε 〇 represents the dielectric constant of the vacuum. Therefore, reducing the dielectric constant of the insulating material is effective for reducing the wiring delay. 20 Conventional insulating materials used are inorganic materials such as cerium oxide (SiO 2 ), cerium nitride (SiN), phosphoric acid silicate glass (PSG), and organic materials such as polyimide. The CVD SiO 2 layer most commonly used in semiconductor devices has a dielectric constant of about 4, and is a low dielectric constant CVD layer and the SiOF layer under study has a dielectric constant of about 3.3 to 3.5. However, the SiOF layer has a high water absorption of 200921788; therefore, its dielectric constant increases as it absorbs moisture. In recent years, porous insulating layers, i.e., insulating materials having a low dielectric constant, have attracted much attention. The porous insulating layer is formed by adding a thermally fusible or decomposable organic resin to a material for forming the low dielectric constant coating 5, and then evaporating by heating when the porous insulating layer is formed or break down. The ceria-based insulating layer, particularly the porous insulating layer, is subjected to work failure in the step of forming the multi-layer wiring and thus increases the effective dielectric constant. Therefore, a method has been proposed in which a damaged layer is repaired by surface-treating a dry etching interlayer insulating layer with a monoazane compound and then vacuum drying. Further, the following method has also been proposed: A method of treating an insulating layer by treating a insulating layer with a decane compound such as decane, alkoxy oxane or ethoxy decane to repair a damaged layer. SUMMARY OF THE INVENTION According to an aspect of an embodiment, a method of fabricating a semiconductor device includes: forming an insulating layer comprising a cerium oxide-based insulating material; processing the insulating layer; coating the insulating layer by applying a decane compound Acting to hydrophobize the insulating layer; and illuminating the insulating layer with light or an electron beam. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of fabricating a semiconductor device of a first embodiment; Figs. 2A to 2C are cross-sectional views showing steps of a method of the first embodiment; 6 200921788 3A to 3C Figure 5 is a cross-sectional view showing the steps of the method of the first embodiment; Figures 4A to 4C are cross-sectional views showing the steps of the method of the second embodiment; 5 Figures 5A and 5B are cross-sectional views showing the second embodiment 6A and 6B are carrier views showing steps of the method of the second embodiment; FIGS. 7A and 7B are cross-sectional views showing step 10 of the method of the second embodiment; - 8A And FIG. 8B is a cross-sectional view showing the steps of the method of the second embodiment; FIG. 9 is a front view showing a step of the method of the second embodiment; FIG. 10 is a cross-sectional view showing the second embodiment a step of the method; 15 Fig. 11 is a cross-sectional view showing a step of the method of the second embodiment; Fig. 12 is a plan view showing a step of the method of the second embodiment; a cross-sectional view showing a step of the method of the second embodiment; Is a cross-sectional view showing a step of the method of the second embodiment; FIG. 15 is a flowchart showing the steps of the method of the third embodiment; '20 FIGS. 16A to 16D are cross-sectional views showing the third embodiment 17A and 17B are cross-sectional views showing the steps of the method of the fourth embodiment; FIGS. 18A and 18B are cross-sectional views showing step 7 of the method of the fourth embodiment; 200921788; a cross-sectional view showing a step of the method of the fourth embodiment; FIG. 20 is a cross-sectional view showing a step of the method of the fourth embodiment; and FIG. 21 is a cross-sectional view showing the method of the fourth embodiment a step; 5 FIGS. 22A and 22B are cross-sectional views showing a step of the method of the fifth embodiment; FIGS. 23A and 23B are cross-sectional views showing a step of the method of the fifth embodiment; 1 is a cross-sectional view showing a step of the method of the fifth embodiment; and FIG. 26 is a cross-sectional view showing the method of the fifth embodiment One step; the 27A to 27D are sectional views, For the preparation of a step for explaining a method of evaluation of the advantages of this method of sample. C. Embodiment 3 15 Description of Preferred Embodiments [First Embodiment] A method of manufacturing a semiconductor device according to a first embodiment will be described below with reference to Figs. 1, 2A to 2C and 3A to 3C. Fig. 1 is a flow chart showing the method, and Figs. 2A to 2C are cross-sectional views showing the steps of the method. Referring to FIG. 1, the method includes a step of depositing a germanium dioxide-based insulating layer (step S11), a step of patterning the germanium dioxide-based insulating layer (step S12), and removing the wall by plasma treatment. a step of depositing (step S13), a step of repairing dry etching damage with a decane compound (step S14), and a step of condensing the Si-OH group by irradiation with 200921788 light or an electron beam (step si5). These steps will be described in detail below with reference to Figs. 2A to 2C and 3A to 3C. The ceria-based insulating layer 1〇2 is deposited on a base substrate 1〇〇 (step S11), and the base substrate 1〇〇 includes a semiconductor including a MIS transistor, one or a plurality of wiring layers, such as a germanium substrate. Substrate. Examples of the carbon dioxide base insulating layer 102 include: an electropolymer layer, a plasma SiN layer, a plasma SiC: a germanium layer, a plasma SiC: 0: germanium layer, and a plasma SiC: H: N a plasma-CVD layer of the layer and the plasma SiOC layer; a coating-type insulating layer such as an organic SOG layer and a porous ceria layer; and the like. As used herein, the phrase "SiC: Η layer" means a Sic layer containing oxygen (〇) and 氲 (H), and the term "SiC : H : N layer" as used herein means a hydrogen (η) and nitrogen. (N) SiC layer. In particular, a coating type insulating layer such as a porous ceria layer is preferable because they have a low dielectric constant. The porous ceria comprises a template type porous ceria material and a non-template type porous ceria material, and the template type porous ceria material has a plurality of thermal decomposition resins which are decomposed into a mixed organic SOG. The pores are formed, and the non-template type porous ceria material has a plurality of pores formed by particles. Examples of the non-template type porous ceria material include the NCS series available from 20 Catalysts & Chemicals Ind. Co., Ltd., and the LKD series available from JSR Corporation. Other preferred examples of the non-template type porous ceria material include a liquid composition containing an organic hydrazine compound obtained by hydrolysis in the presence of tetraalkylammonium hydroxide (TAA0H), and the liquid composition is prepared. The material has a modulus of elasticity equal to or greater than the a-valve a, a hardness equal to or greater than the a, and a good balance between the low dielectric constant and the high strength. Examples of the organic stone compound include: four oxygen-burning oxygen, three-burning oxygen, methyl tris-oxygen stone, ethyl three-correction H green (four), secret three-burning oxygen-stone-burning ethylene-burning oxygen Shi Xizhuo, Dilyl propyl trioxide, Sodium decyl oxane, Dialkyl oxane, Dimethyldioxane, Diethyl sulphur, Wei, Dipropyl L, II Phenyl bis 9 oxa, di(tetra) bis & oxy Wei, diallyl dioxirane, diglycidyl sinter calcined sulphur, benzoquinone sulphuric acid boots, phenethyl sulphide Miscellaneous, phenylpropyl-burning oxygen #院, stupid vinyl two-burning oxygen "shallow, stupidyl bis-Oxygen stone Xiyuan, benzene-shrinking stalks 6 sputum, methyl vinyl sinter , ethyl vinyl di-oxygenated Wei, and propylethylene di-silica. A coating solvent for forming a coating type porous dioxide (4) can be 'bathed out' as a cerium oxide resin which is a fumatous bismuth fossil precursor and is not particularly special. Examples of the ruthenium coating solvent include: alcohols such as methanol, ethanol, n-propanol 'isopropanol, JL butanol, isobutanol, and butanol; such as cresol, cresol'-ethylphenol, diethylphenol, and propylene Phenol, indophenol, vinylphenol, and allylphenol, such as bad _ 'methyl isobutyl ketone, and ketones of methyl ethyl ketone; such as methyl 赛苏苏 and ethyl 赛路苏赛赛苏; For example, hydrocarbons such as hexane, propylene and teriyaki, and diols such as propylene glycol, propylene glycol monodecyl ether, and propylene glycol monomethyl ether acetate. The insulating layer made of a coating type insulating material can be permeable, for example, a step of applying the insulating material to a base substrate, and a step at 80. (: the step of heating the base substrate at a temperature of 350 ° C

、及一在 350°C 至 450°C 20 200921788 之溫度下使該底基板石更化之步驟來形成。豸加熱步驟與該 硬化步驟最好在一惰性氣體環境氣體中以等於或小於 lOOppm之氧含量執行，這是因為該絕緣層之耐水氣性可不 因氧化而被破壞。 5 如第2A圖所示，一由例如⑽製成之硬遮單104藉例如 一 CVD製程而形成在該二氧化矽基絕緣層1〇2上。 一光阻層106形成在該硬遮罩104上，且該光阻層1〇6 具有一藉光刻法(photolithography)形成在一預定區域中之 第一開口 108。 10 如第2B圖所示，該硬遮罩1〇4以使用該光阻層1〇6作為 一遮罩的方式被乾蝕刻，藉此該第一開口 1〇8被轉移至該硬 遮罩104上。 該光阻層106係藉利用例如氧電漿進行灰化(ashing)來 移除。 15 該二氧化矽基絕緣層1〇2透過該已圖案化硬遮罩忉斗被 乾蝕刻，藉此在該二氧化矽基絕緣層102中形成一第二開口 110(步驟S12)。一用以乾蝕刻該二氧化矽基絕緣層102之製 程可以形成配線溝槽及/或通孔且未特別受到限制，該二氧 化矽基絕緣層102可以在一真空室中被乾蝕刻，而以下之氣 20 體或混合物在該真空室中以例如，50mTorr之壓力及200W 之功率被電漿化：一或多數如CF4、CHF3、C2F6、C3F8、及 C4F1()之氣體氟烴或含有至少一該氟烴及氬(Ar)、氮(N2)、氧 (〇2)、及氫(H2)之至少一者的氣體混合物。 在前述乾蝕刻步驟中，多數被破壞層112形成在該第二 11 200921788 開口 110之壁中，如第2圖中之又號所示。該等被破壞層112 係鍵結由於電漿破壞而斷裂之區域且可能會吸收水份，並 且該等被破壞層112含有&-OH基。 在該乾蝕刻步驟中產生之副產物係沈積在該第二開口 5 110之壁上，藉此壁沈積物U4形成在其壁上，如第2C圖所 示。當該二氧化絲絕緣層102以例如H餘刻氣體乾钱 刻時，該等壁沈積物114含有〇?<聚合物。 該已圖案化二氧化矽基絕緣層102以由依需要含氧、 1、氫、及氮之-或多個之氣體所產生的電漿來處理(步驟 1〇 S13)。這使該等壁沈積物114可以由該第二開口 11〇之壁上 移除，如第3A圖所示。 前述電漿處理是要移除該等壁沈積物114。如果該等壁 沈積物114仍留在該第二開口 U〇之壁上，則下述修復該破 壞之效果將會不足。因此，當以-含氟餘刻氣體乾敍刻該 15二氧化石夕基絕緣層時，最好實施該電漿處理。 湘該硬遮罩U)4使該二氧切基絕緣層1〇2圖案化， 且該硬遮罩104具有一如前述般由該光阻層1〇6轉印之圖 案。該二氧化矽基絕緣層102可以使用該光阻層1〇6作為一 遮罩而非該硬遮罩104之方式圖案化，此時，在完成該第二 20 % 口 110後將鼓阻層觸移除。該光阻層1Q6itf藉利用氧 電聚灰化來移除’這提供與由步驟S13所獲得者相同之效 果。如果該等壁沈積物114可以藉灰化與該光阻層刚一起 被充份地移除，則步驟sl3之電浆處理不必要實施。步驟阳 之電衆處理可以在氧《灰化以外附帶實施。 12 200921788 該等壁沈積物lu 以一如氫氟酸、氟化銨、或磷化銨 之化學樂品來移除，=^ = ’、而非實施步驟S13之電漿處理。 以氧化夕基絕緣層102由於實施乾姓刻以形成該第 二開口 11〇所造成 破裱係利用一矽烷化合物來修復（步驟 S14)，這使得料 ^ 寻破破壞層112可以被修復，藉此形成多數 已修復層116，如第3B圖所示。 在這操作中，蕤私士 稽孝刻產生之Si_〇H基可以與該矽烷化 口物反應帛以使該等Si-ΟΗ基可與該石夕院化合物反應之 方法並未特別X限且可使用任何方法，最好使用以下方 1〇法.其中以該石夕燒化合物之處理係在大氣壓或在真空下實 施之旋塗法或-蒸錢法。特別地，該蒸鑛法特別適合， 因為5亥蒸鑛法不受表面張力影響。 在该洛鍍法中，該底基板100最好被加熱至邓乂至 350°C之溫度，使得财院化合物在該三氧化⑪基絕緣層 15 ι〇2中擴散且補強已修復部份。在該旋塗法中，該二氧化矽 基絕緣層102係在室溫下以旋塗機處理，且接著被烘烤使 得該等已修復部份被補強。此時，該二氧化矽基絕緣層1〇2 最好在一或多數由5〇°C至350〇C之範圍内之溫度下烘烤。 該一氧化碎基絕緣層102之處理溫度最好依據該石夕烧 20 化合物之種類，在一由50°C至350oC之範圍内選擇。其處理 溫度之上限依據該妙烧化合物之沸點來決定，且因此設定 為低於或等於該矽烷化合物之沸點。其下限設定為如义的 原因是該二氧化矽基絕緣層102之破壞無法在—低於5〇〇c 之溫度下以該矽烷化合物充份地修復。 13 200921788 用以修復該二氧化矽基絕緣層102之破壞的矽烷化合 物具有可與Si-OH基反應之官能基，且並未特別受限。該矽 烷化合物之例包括如二曱基二矽氮烷、四甲基二矽氮烷、 及六甲基二矽氮烷之矽氮烷；如雙（三甲基矽基）乙醯胺及雙 5 (三乙基矽基）乙醯胺之矽醯胺類；如三甲氧矽烷、三乙氧矽 烷、曱基三曱氧矽烷、甲基三乙氧矽烷、二甲基三甲氧矽 烷、二甲基三乙氧矽烷、三曱基三甲氧矽烷、三甲基三乙 氧矽烷、乙基三甲氧矽烷、乙基三乙氧矽烷、二乙基三甲 氧矽烷、二乙基三乙氧矽烷、三乙基三曱氧矽烷、三乙基 1〇 三乙氧矽烷、丙基三曱氧矽烷、丙基三乙氧矽烷、二丙基 三甲氧矽烷、二丙基三乙氧矽烷、三丙基三甲氧矽烷、三 丙基三乙氧矽烷、苯基三甲氧矽烷、笨基三乙氧矽烷、二 苯基三甲氧矽烷、二笨基三乙氧矽烷、三苯基三甲氧矽烷、 二笨基三乙氧矽烷、苯甲基甲氧矽烷、笨甲基乙氧矽烷、 —甲苯基曱氧矽烷、二甲苯基乙氧矽烷、二苯甲基甲氧矽 、Ώ, _ 命+ 疋、 笨甲基乙氧矽烷之烷氧矽烷類；及如三乙醯氧矽 烷、三乙氧矽烷、曱基三乙氧矽烷、二曱基乙醯氧矽烷、 一甲基乙醯氧矽烷、乙基乙醯氧矽烷、二乙基乙醯氧矽烷、 二乙基乙醯氧矽烷、二丙基乙醯氧矽烷、三丙基乙醯氧矽 院、笨其二 一 土二乙醯氧矽烷、二苯基乙醯氧矽烷、三苯基乙醯 笨甲義本甲基乙醯氧矽烷、二甲苯基乙醯氧矽烷、及二 土二乙醯氧矽烷之乙醯氧矽烷類。 可以^破壞之修復使存在於該等被破壞層112中之Si_〇H基 蔓成Si-CH3基，使疏水性增強。但是，因為該石夕 14 200921788 烷化合物具有大分子量且因此具有空間位阻性，所以難以 將所有Si-〇H基轉變成Si_CH3基。如果該二氧化矽基絕緣層 102暴露在空氣中，則剩餘之Si-OH基將會吸收水份，而這 會造成該二氧化矽基絕緣層1〇2之介電常數增加。 5 依據這實施例之方法，在該破壞修復後，該等剩餘之And forming a step of refining the base substrate at a temperature of 350 ° C to 450 ° C 20 200921788. The crucible heating step and the hardening step are preferably performed at an oxygen content of equal to or less than 100 ppm in an inert gas atmosphere because the water vapor resistance of the insulating layer is not destroyed by oxidation. As shown in Fig. 2A, a hard mask 104 made of, for example, (10) is formed on the ceria-based insulating layer 1'2 by, for example, a CVD process. A photoresist layer 106 is formed on the hard mask 104, and the photoresist layer 〇6 has a first opening 108 formed in a predetermined area by photolithography. 10, as shown in FIG. 2B, the hard mask 1〇4 is dry etched by using the photoresist layer 1〇6 as a mask, whereby the first opening 1〇8 is transferred to the hard mask. 104 on. The photoresist layer 106 is removed by ashing using, for example, oxygen plasma. The erbium oxide-based insulating layer 1 2 is dry etched through the patterned hard mask hopper to form a second opening 110 in the ruthenium oxide-based insulating layer 102 (step S12). A process for dry etching the ceria-based insulating layer 102 may form wiring trenches and/or via holes, which are not particularly limited, and the ceria-based insulating layer 102 may be dry etched in a vacuum chamber. The following gas or mixture is plasmad in the vacuum chamber at a pressure of, for example, 50 mTorr and a power of 200 W: one or more gaseous fluorocarbons such as CF4, CHF3, C2F6, C3F8, and C4F1 () or at least A gas mixture of at least one of a fluorocarbon and argon (Ar), nitrogen (N2), oxygen (〇2), and hydrogen (H2). In the foregoing dry etching step, a majority of the damaged layer 112 is formed in the wall of the opening 11 of the second 11 200921788, as shown by the symbol in Fig. 2. The damaged layers 112 are bonded to regions that are broken due to plasma destruction and may absorb moisture, and the damaged layers 112 contain &-OH groups. The by-product produced in the dry etching step is deposited on the wall of the second opening 5110, whereby the wall deposit U4 is formed on the wall thereof as shown in Fig. 2C. When the silicon dioxide insulating layer 102 is dry, for example, with H residual gas, the wall deposits 114 contain ruthenium <polymer. The patterned ceria-based insulating layer 102 is treated with a plasma generated by a gas containing oxygen, 1, hydrogen, and nitrogen as needed (step 1 〇 S13). This allows the wall deposits 114 to be removed from the wall of the second opening 11 as shown in Figure 3A. The aforementioned plasma treatment is to remove the wall deposits 114. If the wall deposits 114 remain on the wall of the second opening U, the effect of repairing the damage described below will be insufficient. Therefore, when the 15 SiO 2 etched layer is dry-etched with a fluorine-containing residual gas, the plasma treatment is preferably carried out. The hard mask U) 4 pattern the dioxin insulating layer 1 〇 2, and the hard mask 104 has a pattern transferred from the photoresist layer 1 〇 6 as described above. The ceria-based insulating layer 102 can be patterned using the photoresist layer 1〇6 as a mask instead of the hard mask 104. At this time, the drum resist layer is formed after the second 20% port 110 is completed. Touch to remove. The photoresist layer 1Q6itf is removed by utilizing oxygen ashing. This provides the same effect as that obtained by the step S13. If the wall deposits 114 can be sufficiently removed by ashing together with the photoresist layer, the plasma treatment of step s13 is not necessary. Step Yang's electricity treatment can be carried out in addition to oxygen "ashing." 12 200921788 The wall deposits lu are removed by a chemical such as hydrofluoric acid, ammonium fluoride, or ammonium phosphide, =^ = ' instead of the plasma treatment of step S13. The ruthenium-based insulating layer 102 is repaired by using a decane compound due to the implementation of the dry-end etching to form the second opening 11 ( (step S14), which allows the material-breaking damage layer 112 to be repaired. This forms a majority of the repaired layer 116, as shown in Figure 3B. In this operation, the method in which the Si_〇H group produced by the smugglers can react with the decylated oxime to make the Si- thiol group react with the shixi compound is not particularly limited. Any method may be used, and it is preferred to use the following method. The treatment with the zephyr compound is a spin coating method or a steaming method which is carried out at atmospheric pressure or under vacuum. In particular, the steaming method is particularly suitable because the 5th steaming method is not affected by the surface tension. In the Luo plating method, the base substrate 100 is preferably heated to a temperature of from Deng to 350 ° C, so that the compound of the compound diffuses in the trioxide 11 -based insulating layer 15 ι 2 and reinforces the repaired portion. In the spin coating method, the ceria-based insulating layer 102 is treated by a spin coater at room temperature, and then baked so that the repaired portions are reinforced. At this time, the ceria-based insulating layer 1〇2 is preferably baked at one or a plurality of temperatures ranging from 5 ° C to 350 ° C. The treatment temperature of the oxidized ground-based insulating layer 102 is preferably selected in the range of 50 ° C to 350 ° C depending on the type of the compound. The upper limit of the treatment temperature is determined depending on the boiling point of the inventive compound, and is therefore set to be lower than or equal to the boiling point of the decane compound. The reason why the lower limit is set to be correct is that the destruction of the ceria-based insulating layer 102 cannot be sufficiently repaired with the decane compound at a temperature lower than 5 〇〇c. 13 200921788 The decane compound for repairing the destruction of the ceria-based insulating layer 102 has a functional group reactive with the Si-OH group, and is not particularly limited. Examples of the decane compound include decazinones such as dinonyldiazepine, tetramethyldiazepine, and hexamethyldiazepine; such as bis(trimethyldecyl)acetamide and double 5 (triethyl decyl) acetamamine amides; such as trimethoxy decane, triethoxy decane, decyl trioxoxane, methyl triethoxy decane, dimethyl trimethoxy decane, dimethyl Triethoxy oxane, trimethyl methoxy decane, trimethyl triethoxy decane, ethyl trimethoxy decane, ethyl triethoxy decane, diethyl trimethoxy decane, diethyl triethoxy decane, three Ethyl trioxoxane, triethyl 1 〇 triethoxy decane, propyl trioxoxane, propyl triethoxy decane, dipropyl trimethoxy decane, dipropyl triethoxy decane, tripropyl trimethyl Oxane, tripropyltriethoxydecane, phenyltrimethoxydecane, stupyltriethoxydecane, diphenyltrimethoxydecane, dipyridyltriethoxydecane, triphenyltrimethoxydecane, dipyridyl Ethoxy decane, benzyl methoxy decane, stupid methyl ethoxy decane, —tolyl oxoxane, xylyl ethoxy decane, diphenyl Alkoxy oxane, hydrazine, hydrazine, hydrazine, methyl ethoxy oxane, and alkoxy oxane such as triethoxy decane, triethoxy decane, decyl triethoxy decane Decane, monomethyl methoxy decane, ethyl ethoxy oxane, diethyl ethoxy oxane, diethyl ethoxy oxane, dipropyl ethoxy oxane, tripropyl ethoxy oxime, Stupid Erdioxane, Diphenyl Ethoxy Oxane, Triphenyl Ethyl Oxime, Methyl Ethyl Ox Oxane, Xylphenyl Ethoxy Oxane, and Di-Ethylene Dioxane Oxane oxane of decane. The repair of the damage can cause the Si_〇H group present in the damaged layer 112 to form a Si-CH3 group to enhance hydrophobicity. However, since the Shihe 14 200921788 alkane compound has a large molecular weight and thus has steric hindrance, it is difficult to convert all Si-〇H groups into Si_CH3 groups. If the ceria-based insulating layer 102 is exposed to the air, the remaining Si-OH groups will absorb moisture, which causes an increase in the dielectric constant of the ceria-based insulating layer 1〇2. 5 according to the method of this embodiment, after the damage is repaired, the remaining

Sl-〇H基被縮合(脫氫縮合)成Si-0-Si基，以防止吸收水份(步 驟S15)。該等剩餘之Si_〇H基可以光或一電子束照射該二氧 化矽基絕緣層102且以3 〇°C至400°C加熱該底基板100之方 式加以縮合’如第3C圖所示。 10 一用以縮合該等剩餘之Si-OH基之燈可以170至700nm 之波長發射光且並沒有特別之限制，該燈之例包括準分子 燈、水銀燈、及金屬齒素燈。在照射光時，該底基板1〇〇之 溫度最好是3〇°C至400°C。 用以縮合該等剩餘之S i _ 〇 η基之環境氣體最好具有等 15於或小於150PPm之氧含量且可包含氮、氦(He)及氬之一或 多種。或者’一真空環境可用於其縮合。若為這種真空環 境，則可將氮、氦(He)及氬之一或多種導入一真空室中， 使得s亥真空室中之壓力以一或多個質量流量計調整至一預 定值。 20 在藉電子束縮合&_^^基時，該二氧化矽基絕緣層1〇2 最好以一在真空中具有1至15kV之加速電壓的電子束加以 照射。當該電子束小於lkV時，無法得到充分的效果。當其 加速電壓大於15kV時，該二氧化矽基絕緣層丨〇2會被破壞。 在照射光或電子束時的處理溫度最好依據該二氧化矽 15 200921788 基絕緣層102之種類’在由3〇°C至400°C之範圍内選擇。該 處理溫度之上限依據該二氧化矽基絕緣層102之溫度上限 來決定，且係小於其溫度上限。該處理溫度之下限設定於 30°C的原因是縮合反應在低於3〇°C時不會發生。 5 由於該等Si-OH基係在如前所述地以矽烷化合物修復 破壞後才被縮合，所以可以大幅減少該二氧化矽基絕緣層 102之吸水性。即使該二氧化矽基絕緣層102暴露於空氣 中，這亦可防止該二氧化石夕基絕緣層102吸收水份，亦即， 這防止該二氧化矽基絕緣層102之介電常數會由於吸收在 ίο 該二氧化石夕基絕緣層102上之水份而增加。 依據這實施例’即使該二氧化矽基絕緣層102暴露在空 氣中，亦可防止該二氧化矽基絕緣層102之介電常數因乾蝕 刻所造成之破壞而增加。 [第二實施例] 15 以下將參照第4A至14圖說明一第二實施例之半導體裝 置的製造方法。在這些圖中，與用以說明第1至3C圖所示之 第一實施例之半導體裝置之製造方法的相同構件具有相同 符號且將簡短地說明或將不加以說明。 第4A至14圖係顯示這實施例之方法之步驟的截面圖。 20 這實施例之方法比第一實施例之方法更為特定。 一用以界定一元件區域14之隔離層12係藉一例如矽局 部氧化(LOCOS)製程形成在一如矽基板之半導體基板10， 且該隔離層12可以藉一淺槽隔離製程形成。 一M0S電晶體24藉一類似於製造一般M0S電晶體之製 16 200921788 程的製程形成在該元件區域14上，如第4A圖所示，該M〇s 電晶體24包括一設置在該半導體基板10上方之閘電極18， 且一閘絕緣層16位於其間，並且該MOS電晶體24亦包括設 置在該半導體基板10中且置於該閘電極18兩側上之源極/ 5 >及極區域22。 例如’一二氧化矽（Si〇2)層係藉例如一CVD製程，形成 在該半導體基板10與該MOS電晶體24上。 該二氧化矽層之表面係藉例如一化學機械拋光(CMp) 製程平坦化，藉此形成一由二氧化矽製成且具有一平坦表 10 面之第一層間絕緣層26。 氮化矽（SiN)藉例如一電漿加強CVD製程沈積在該第 一層間絕緣層26上’藉此形成一播止層28。該擋止層28係 由氮化矽製成且具有例如50nm之厚度，該擋止層28作為在 一後續步驟中於CMP時之拋光擋止且作為在另一後續步驟 15中於一第二層間絕緣層38中形成第一配線溝槽46時之蝕刻 擋止。除了氮化矽以外，該擋止層28可由SiC: H、SiC : 〇 : Η、SiC : H : N製成。 如第4Β圖所示’多數接觸孔3〇藉光刻與乾蝕刻形成， 以延伸通過該擋止層2 8與該第一層間絕緣層2 6而到達該等 20 源極/汲極區域22。 氮化鈦（TiN)藉例如一濺鍍製程沈積在該擋止層28 上，藉此形成一第一障壁金屬層32。該第一障壁金屬層32 係由TiN製成’且具有例如5〇nm之厚度。 藉例如一 CVD製程，一具有例如1μιγι之厚度的鎢（W) 17 200921788 層34形成在該第一障壁金屬層32上。 如第4C圖所示，該鎢層34與該第一障壁金屬層32係藉 例如一 CMP製程拋光，使得該擋止層28暴露出來，藉此各 包括該第一障壁金屬層32之一部份及該鎢層34之一部份的 5多數第一接觸栓塞35形成在該等接觸孔3〇中。 藉例如一電漿加強CVD製程，SiC : 〇 : H沈積在其中 配置有該等第一接觸栓塞35之擋止層28上，藉此形成一第 一絕緣層36。該第一絕緣層36係由SiC : Ο : Η製成，且具 有例如30nm之厚度。該第一絕緣層36是一含有氧與氫之緻 10密SiC膜，且作為用以防止水份等擴散之障壁層。 如第5A圖所示，該第二層間絕緣層38形成在該第一絕 緣層36上。該第二層間絕緣層38是一多孔質二氧化矽材 料，且具有例如大160nm之厚度。以下材料與製程可用來氷 成該第二層間絕緣層38 :在第一實施例之方法中用以形成 15該二氧化矽基絕緣層102的其中一多孔質二氧化矽材料與 製程。 ~ 如第5B圖所示，藉例如—電漿加強CVD製程，二氧化 矽(Si〇2)沈積在該第二層間絕緣層38上，藉此形成一 ^〜絕 緣層40。該第二絕緣層40是二氧化矽，且具有例如 20 厚度。 如第6A圖所示，一第一光阻層42形成在該第二絕緣層 40上。該第一光阻層42具有藉光刻形成之第一開口私，且 透過該等第一開口 44,暴露出多數區域，而該等區域係用 以形成具有大約lOOnm之寬度且分開大約1〇〇11111之距離之 18 200921788 第一配線51。 如第6B圖所示，以該第一光阻層42與該擋止層28分別 被用來作為一遮罩及一擋止之方式，以例如一ch氣體與一 CHF3氣體依序乾蝕刻該第二絕緣層4〇、該第二層間絕緣層 5 38、及該第一絕緣層36，藉此形成用以形成該等第一配線 51之第一配線溝槽46。該等第一配線51延伸通過該第二絕 緣層40、該第二層間絕緣層38、及該第一絕緣層36。在這 乾餘刻步驟中’含有Si-OH基之被破壞層112形成在該等第 一配線溝槽46之壁中，如第6B圖中之叉號所示。 10 該第一光阻層42係藉例如氧電漿灰化來移除，即使壁 沈積物在形成該等第一配線溝槽46時因乾蝕刻而形成在該 等第一配線溝槽46之壁中，亦可在這灰化步驟中移除該等 壁沈積物。 在將3cc之例如六曱基二矽氮烷之矽烷化合物滴在該 15 第二絕緣層40上且接著以l，〇〇〇rpm對該第二絕緣層40進行 旋塗60秒後，在例如120°C下將該半導體基板10烘烤60秒且 再以一熱板在250°C下烘烤6〇秒。這使由在形成該等第一配 線溝槽46時因乾蝕刻產生之si_0H基可以轉變成Si-CH3 基，藉此可修復存在該等第一配線溝槽46之壁中的被破壞 20層112。結果，形成已修復層I16，如第7A圖所示。 在這步驟中，可以使用在第一實施例中所述之用以修 復該被破壞層112的相同矽烷化合物與製程。 如第7B圖所示，以該半導體基板在一氮環境氣體中 被加熱至例如400〇C之方式，利用一由Ushio Inc.取得之 19 200921788 UVL-7000 H4-N高壓水銀燈，以具有例如200至600nm之波 長之紫外線照射該第二絕緣層40十分鐘。這使得剩餘之 Si-OH基可藉縮合轉變成Si-O-Si基，因此可防止因該等剩餘 之Si-OH基吸收水份。 5 在這步驟中，可使用與用以縮合在第一實施例中所示 之Si-OH基者相同之製程與條件。在這步驟中可進行電子束 照射，而不是以與在第一實施例中所示者相同之方式進行 光照射。 藉例如一濺鍍製程，將氮化钽(TaN)沈積在該第二絕緣 10 層40上，藉此形成一第二障壁金屬層48。該第二障壁金屬 層48是氮化钽，且具有例如10nm之厚度。該第二障壁金屬 層4 8防止銅由在一後續步驟中形成之銅線擴散至該等絕緣 層中。 藉例如一電鍍製程，將銅沈積在該第二障壁金屬層48 15 上，藉此形成一第一晶種層（圖未示）。該第一晶種層是銅， 且具有例如1 〇nm之厚度。 藉例如一電鍍製程，將一第一銅塗層沈積在該第一晶 種層上，藉此形成一第一銅層50。該第一銅層50包括該第 一晶種層與該第一銅塗層，且具有例如600nm之厚度。 20 該第二障壁金屬層48位在該第二絕緣層40上之一部份 及該第一銅層50位在該第二絕緣層40上方之一部份係藉一 CMP製程移除，藉此在該等第一配線溝槽46中形成該等第 一配線51。該等第一配線51包括該等第二障壁金屬層48留 在該等第一配線溝槽46中之多數部份及該第一銅層50留在 20 200921788 其中之多數部份，且一用以如前述般形成該等第一配線51 之製程被稱為一單一金屬鑲嵌製程。 如第8A圖所示，藉例如一 CVD製程，將SiC : Ο : Η沈 積在該第二絕緣層40上，藉此形成一第三絕緣層52。該第 5 三絕緣層52是SiC : Ο : Η，且具有例如30nm之厚度。該第 三絕緣層52作為一用以防止水份擴散及銅由該等第一配線 51擴散出來之障壁層。 利用一多孔質二氧化矽材料，在該第三絕緣層52上形 成一第三層間絕緣層54。該第三層間絕緣層54可以與用以 10 形成該第二層間絕緣層38者相同之方式形成，且該第三層 間絕緣層54具有例如180nm之厚度。 如第8B圖所示，藉一電漿加強CVD製程，在該第三層 間絕緣層5 4上沈積二氧化矽（S i Ο 2 )，藉此形成一第四絕緣層 56。該第四絕緣層56係由二氧化矽製成，且具有例如30nm 15 之厚度。 利用一多孔質二氧化矽材料，在該第四絕緣層56上形 成一第五層間絕緣層58。一用以形成該第五層間絕緣層58 之製程可與用以形成該第二層間絕緣層38者相同，且該第 一銅層50具有一例如16nm之厚度。 20 如第9圖所示，藉例如一電漿加強CVD製程，將二氧化 矽（Si02)沈積在該第五層間絕緣層58上，藉此形成一第五絕 緣層60。該第五絕緣層60係由二氧化矽製成，且具有一例 如30nm之厚度。 一第二光阻層62形成在該第五絕緣層60上，且該第二 21 200921788 光阻層62具有多數藉光刻形成之第二開口 64。透過該等第 二開口 64，將多數區域暴露出來，且該等區域係用以形成 多數延伸至a亥專第一配線51之通孔。The Sl-〇H group is condensed (dehydrogenated) to form a Si-0-Si group to prevent absorption of moisture (step S15). The remaining Si_〇H groups may be condensed by irradiating the ceria-based insulating layer 102 with light or an electron beam and heating the base substrate 100 at 3 ° C to 400 ° C as shown in FIG. 3C . A lamp for condensing the remaining Si-OH groups can emit light at a wavelength of 170 to 700 nm without particular limitation, and examples of the lamp include an excimer lamp, a mercury lamp, and a metal dentate lamp. When the light is irradiated, the temperature of the base substrate 1 is preferably from 3 ° C to 400 ° C. The ambient gas for condensing the remaining S i _ 〇 η groups preferably has an oxygen content of 15 or less and may include one or more of nitrogen, helium (He) and argon. Or 'a vacuum environment can be used for its condensation. In the case of such a vacuum environment, one or more of nitrogen, helium (He) and argon may be introduced into a vacuum chamber such that the pressure in the vacuum chamber is adjusted to a predetermined value by one or more mass flow meters. The ruthenium oxide-based insulating layer 1 〇 2 is preferably irradiated with an electron beam having an acceleration voltage of 1 to 15 kV in a vacuum by electron beam condensation & When the electron beam is smaller than lkV, a sufficient effect cannot be obtained. When the accelerating voltage is greater than 15 kV, the ceria-based insulating layer 丨〇2 is destroyed. The treatment temperature at the time of irradiating light or electron beam is preferably selected in the range of from 3 ° C to 400 ° C depending on the type of the ruthenium oxide 15 200921788-based insulating layer 102. The upper limit of the treatment temperature is determined by the upper limit of the temperature of the ceria-based insulating layer 102 and is less than the upper limit of its temperature. The reason why the lower limit of the treatment temperature is set at 30 ° C is that the condensation reaction does not occur below 3 ° C. (5) Since the Si-OH groups are condensed after being repaired and destroyed by the decane compound as described above, the water absorption of the cerium oxide-based insulating layer 102 can be drastically reduced. Even if the ceria-based insulating layer 102 is exposed to the air, this prevents the dioxide-based insulating layer 102 from absorbing moisture, that is, the dielectric constant of the ceria-based insulating layer 102 is prevented from being The absorption is increased by the moisture on the SiO 2 base insulating layer 102. According to this embodiment, even if the ceria-based insulating layer 102 is exposed to the air, the dielectric constant of the ceria-based insulating layer 102 can be prevented from increasing due to damage caused by dry etching. [Second Embodiment] 15 A method of manufacturing a semiconductor device according to a second embodiment will be described below with reference to Figs. 4A to 14 . In the drawings, the same members as those for explaining the manufacturing method of the semiconductor device of the first embodiment shown in Figs. 1 to 3C have the same reference numerals and will be briefly described or will not be described. 4A through 14 are cross-sectional views showing the steps of the method of this embodiment. The method of this embodiment is more specific than the method of the first embodiment. An isolation layer 12 for defining an element region 14 is formed on a semiconductor substrate 10 such as a germanium substrate by a LOCOS process, and the isolation layer 12 can be formed by a shallow trench isolation process. A MOS transistor 24 is formed on the device region 14 by a process similar to that of a conventional MOS transistor. As shown in FIG. 4A, the M 〇 transistor 24 includes a semiconductor substrate. a gate electrode 18 above 10, and a gate insulating layer 16 therebetween, and the MOS transistor 24 also includes a source/5 > and a pole disposed in the semiconductor substrate 10 and placed on both sides of the gate electrode 18. Area 22. For example, a layer of germanium dioxide (Si 2 ) is formed on the semiconductor substrate 10 and the MOS transistor 24 by, for example, a CVD process. The surface of the ceria layer is planarized by, for example, a chemical mechanical polishing (CMp) process, thereby forming a first interlayer insulating layer 26 made of cerium oxide and having a flat surface. Niobium nitride (SiN) is deposited on the first interlayer insulating layer 26 by, for example, a plasma enhanced CVD process, thereby forming a stop layer 28. The stop layer 28 is made of tantalum nitride and has a thickness of, for example, 50 nm, the stop layer 28 acts as a polishing stop at CMP in a subsequent step and as a second in another subsequent step 15. The etching stopper when the first wiring trench 46 is formed in the interlayer insulating layer 38. The stopper layer 28 may be made of SiC:H, SiC : 〇 : Η, SiC : H : N, in addition to tantalum nitride. As shown in FIG. 4, a plurality of contact holes 3 are formed by photolithography and dry etching to extend through the stop layer 28 and the first interlayer insulating layer 26 to reach the 20 source/drain regions. twenty two. Titanium nitride (TiN) is deposited on the stop layer 28 by, for example, a sputtering process, thereby forming a first barrier metal layer 32. The first barrier metal layer 32 is made of TiN and has a thickness of, for example, 5 Å. A layer of tungsten (W) 17 200921788 having a thickness of, for example, 1 μm is formed on the first barrier metal layer 32 by, for example, a CVD process. As shown in FIG. 4C, the tungsten layer 34 and the first barrier metal layer 32 are polished by, for example, a CMP process, so that the stopper layer 28 is exposed, thereby including one portion of the first barrier metal layer 32. A plurality of first contact plugs 35 of a portion of the tungsten layer 34 are formed in the contact holes 3A. SiC: 〇: H is deposited on the stop layer 28 in which the first contact plugs 35 are disposed, for example, by a plasma-enhanced CVD process, thereby forming a first insulating layer 36. The first insulating layer 36 is made of SiC : Ο : Η and has a thickness of, for example, 30 nm. The first insulating layer 36 is a 10 SiC film containing oxygen and hydrogen, and serves as a barrier layer for preventing diffusion of moisture or the like. As shown in Fig. 5A, the second interlayer insulating layer 38 is formed on the first insulating layer 36. The second interlayer insulating layer 38 is a porous ceria material and has a thickness of, for example, 160 nm. The following materials and processes can be used to form the second interlayer insulating layer 38: one of the porous ceria materials and processes used to form the ceria-based insulating layer 102 in the method of the first embodiment. ~ As shown in Fig. 5B, ruthenium dioxide (Si 〇 2) is deposited on the second interlayer insulating layer 38 by, for example, a plasma enhanced CVD process, thereby forming an insulating layer 40. The second insulating layer 40 is hafnium oxide and has a thickness of, for example, 20. As shown in Fig. 6A, a first photoresist layer 42 is formed on the second insulating layer 40. The first photoresist layer 42 has a first opening formed by photolithography, and through the first openings 44, a plurality of regions are exposed, and the regions are formed to have a width of about 100 nm and are separated by about 1 〇. 〇11111 distance of 18 200921788 first wiring 51. As shown in FIG. 6B, the first photoresist layer 42 and the blocking layer 28 are used as a mask and a blocking method, respectively, for example, a CH gas and a CHF3 gas are sequentially etched. The second insulating layer 4, the second interlayer insulating layer 538, and the first insulating layer 36, thereby forming the first wiring trenches 46 for forming the first wirings 51. The first wirings 51 extend through the second insulating layer 40, the second interlayer insulating layer 38, and the first insulating layer 36. In this dry step, the damaged layer 112 containing Si-OH groups is formed in the walls of the first wiring trenches 46 as indicated by the crosses in Fig. 6B. 10 the first photoresist layer 42 is removed by, for example, oxygen plasma ashing, even if the wall deposits are formed in the first wiring trenches 46 by dry etching when the first wiring trenches 46 are formed. In the wall, the wall deposits may also be removed during this ashing step. After 3 cc of a decane compound such as hexakisodiazane is dropped on the 15 second insulating layer 40 and then the second insulating layer 40 is spin-coated at 1, rpm for 60 seconds, for example, The semiconductor substrate 10 was baked at 120 ° C for 60 seconds and then baked at 250 ° C for 6 seconds with a hot plate. This allows the si_0H group generated by dry etching in forming the first wiring trenches 46 to be converted into Si-CH3 groups, whereby the damaged 20 layers in the walls of the first wiring trenches 46 can be repaired. 112. As a result, the repaired layer I16 is formed as shown in Fig. 7A. In this step, the same decane compound and process as described in the first embodiment for repairing the damaged layer 112 can be used. As shown in FIG. 7B, a 19 200921788 UVL-7000 H4-N high-pressure mercury lamp obtained by Ushio Inc. is used in a manner that the semiconductor substrate is heated to, for example, 400 〇C in a nitrogen atmosphere to have, for example, 200. The second insulating layer 40 was irradiated with ultraviolet rays having a wavelength of 600 nm for ten minutes. This allows the remaining Si-OH groups to be converted into Si-O-Si groups by condensation, thereby preventing absorption of moisture by the remaining Si-OH groups. 5 In this step, the same processes and conditions as those used to condense the Si-OH group shown in the first embodiment can be used. In this step, electron beam irradiation can be performed instead of performing light irradiation in the same manner as that shown in the first embodiment. A tantalum nitride (TaN) is deposited on the second insulating layer 10 by, for example, a sputtering process, thereby forming a second barrier metal layer 48. The second barrier metal layer 48 is tantalum nitride and has a thickness of, for example, 10 nm. The second barrier metal layer 48 prevents copper from diffusing into the insulating layers by copper lines formed in a subsequent step. Copper is deposited on the second barrier metal layer 48 15 by, for example, an electroplating process, thereby forming a first seed layer (not shown). The first seed layer is copper and has a thickness of, for example, 1 〇 nm. A first copper coating is deposited on the first seed layer by, for example, an electroplating process, thereby forming a first copper layer 50. The first copper layer 50 includes the first seed layer and the first copper coating and has a thickness of, for example, 600 nm. 20 a portion of the second barrier metal layer 48 on the second insulating layer 40 and a portion of the first copper layer 50 above the second insulating layer 40 are removed by a CMP process. The first wirings 51 are formed in the first wiring trenches 46. The first wiring 51 includes a majority of the second barrier metal layer 48 remaining in the first wiring trenches 46 and the first copper layer 50 remains in most of the portions of 20 200921788, and is used The process of forming the first wirings 51 as described above is referred to as a single damascene process. As shown in Fig. 8A, SiC: Ο : Η is deposited on the second insulating layer 40 by, for example, a CVD process, thereby forming a third insulating layer 52. The fifth insulating layer 52 is SiC : Ο : Η and has a thickness of, for example, 30 nm. The third insulating layer 52 serves as a barrier layer for preventing moisture from diffusing and copper from being diffused from the first wirings 51. A third interlayer insulating layer 54 is formed on the third insulating layer 52 by a porous ceria material. The third interlayer insulating layer 54 may be formed in the same manner as that for forming the second interlayer insulating layer 38, and the third interlayer insulating layer 54 has a thickness of, for example, 180 nm. As shown in Fig. 8B, ruthenium dioxide (S i Ο 2 ) is deposited on the third interlayer insulating layer 54 by a plasma enhanced CVD process, thereby forming a fourth insulating layer 56. The fourth insulating layer 56 is made of hafnium oxide and has a thickness of, for example, 30 nm. A fifth interlayer insulating layer 58 is formed on the fourth insulating layer 56 by a porous ceria material. A process for forming the fifth interlayer insulating layer 58 may be the same as that for forming the second interlayer insulating layer 38, and the first copper layer 50 has a thickness of, for example, 16 nm. 20 As shown in Fig. 9, ruthenium dioxide (SiO 2 ) is deposited on the fifth interlayer insulating layer 58 by, for example, a plasma enhanced CVD process, thereby forming a fifth insulating layer 60. The fifth insulating layer 60 is made of ruthenium dioxide and has an thickness of, for example, 30 nm. A second photoresist layer 62 is formed on the fifth insulating layer 60, and the second 21 200921788 photoresist layer 62 has a plurality of second openings 64 formed by photolithography. Through the second openings 64, a plurality of regions are exposed, and the regions are used to form a plurality of vias extending to the first wiring 51.

如第10圖所示，以該第二光阻層62被用來作為一遮罩 5之方式，以例如一含有CF4與CHF3之蝕刻氣體依序乾蝕刻 該第五絕緣層60、該第五層間絕緣層58、該第四絕緣層％、 該第三層間絕緣層54、及該第三絕緣層52，使得該第二光 阻層62被用來作為一遮罩，藉此形成多數延伸通過該第五 絕緣層60、該第五層間絕緣層％、該第四絕緣層56、該第 10三層間絕緣層54、及該第三絕緣層52而到達該等第一配線 51的通孔66。這些絕緣層可以該蝕刻氣體之組成及/或壓力 變化之方式被蝕刻，且在這乾蝕刻步驟中，含有該等Si 〇H 基之被破壞層112形成在該等通孔66之壁中，如第1〇圖中之 叉號所示。 15 邊第二光阻層62係藉例如灰化來移除，即使壁沈積物 在形成該等通孔66時因乾蝕刻而形成在該等通孔的之壁 上，亦可在這灰化步驟中移除該等壁沈積物。 一第三光阻層68形成在該第五絕緣層60上，且該第五 絕緣層60中具有該等通孔66。該第三光阻層68具有多數藉 20光刻形成之第三開口 70 ,且透過該等第三開口 70，多數用 以形成多數第二配線77b之區域暴露出來。 如第11圖所示，以該第三光阻層68被用來作為一遮罩 之方式，以例如一CF4氣體與一CHF3氣體依序乾蝕刻該第 五絕緣層60、該第五層間絕緣層58、及該第四絕緣層％， 22 200921788 藉此形成該等第二配線77b。該等第二配線77b延伸通過該 第五絕緣層60、該第五層間絕緣層58、及該第四絕緣層％， 且該等第二配線溝槽72與該等通孔66連接。在這乾蝕刻步 驟中，含有Si-OH基之被破壞層112形成在該等第二配線溝 5 槽72之壁中’如第11圖中之又號所示。 該第三光阻層68係藉例如灰化來移除，即使壁沈積物 在形成該等第二配線溝槽72時因乾蝕刻而形成在該等第二 配線溝槽72之壁中，亦可在這灰化步驟中移除該等壁沈積 物。 10 如第12圖所示，在將3cc之例如六曱基二矽氮烷之矽燒 化合物滴在該第五絕緣層60上且接著以1，〇〇〇rpm對該第五 絕緣層60進行旋塗60秒後’在例如120°C下將該半導體基板 10烘烤60秒且再以一熱板在250°c下烘烤6〇秒。這使由在形 成該等通孔66與該等第二配線溝槽72時因乾蝕刻產生之 15 Si-OH基可以轉變成Si-CH3基’藉此可修復存在該等通孔66 與該等第二配線溝槽72之壁中的被破壞層112。這亦會形成 該等已修復層116。 在這步驟中，可以使用在第一實施例中所述之用以修 復該被破壞層112的相同石夕烧化合物與製程。 20 如第13圖所示，以該半導體基板1〇在一氮壞境氣體中 被加熱至例如400。(：之方式，利用一由Ushio Inc.取得之 UVL-7000 H4-N高壓水銀燈，以具有例如200至600nm之波 長之紫外線照射該第五絕緣層60十分鐘。這使得剩餘之 Si-OH基可藉縮合轉變成Si-0-Si基，因此可防止因該專剩餘 23 200921788 之Si-OH基吸收水份。 在這步驟中，可使用與用以縮合在第一實施例中所示 之Si-ΟΗ基者相同之製程與條件。在這步驟中可進行電子束 照射，而不是以與在第一實施例中所示者相同之方式進行 5 光照射。 藉例如一濺鍵製程，將氮化组沈積在該第五絕緣層60 上’藉此形成一第三障壁金屬層74。該第三障壁金屬層74 是氮化钽，且具有例如10nm之厚度。該第三障壁金屬層74 防止銅由在一後續步驟中形成之銅線擴散至該等絕緣層 10 中。 藉例如一濺鍍製程，將銅沈積在該第三障壁金屬層74 上’藉此形成一第二晶種層（圖未示）。該第二晶種層是由銅 形成，且具有例如1 Onm之厚度。 藉例如一電鍍製程，將一第二銅塗層沈積在該第二晶 15種層上，藉此形成一第二銅層76。該第二銅層76包括該第 二晶種層與該第二銅塗層，且具有例如1，4〇〇ηΠι之厚度。 該第二銅層76位在該第五絕緣層60上之一部份及該第 二障壁金屬層74位在該第五絕緣層60上方之一部份係藉一 CMP製程移除，藉此形成可互相連接之第二接觸栓塞77& 20與該等第二配線77b。該等第二接觸栓塞77a包括該等第三 障壁金屬層74留在該等通孔66中之多數部份及該第二銅層 %留在其中之多數部份，且該等第二配線77b包括該第三障 壁金屬層74留在該等第二配線溝槽72中之多數部份及今第 二銅層76留在其中之多數部份。一用以如前述般形成該等 24 200921788 第二接觸栓塞77a與該等第二配線77b之製程被稱為一雙金 屬鑲嵌製程。 如第14圖所示，藉例如一CVD製程，將SiC : Ο : Η沈 積在該第五絕緣層60上，藉此形成一第六絕緣層78。該第 5 六絕緣層78是SiC : Ο : Η，且具有例如30nm之厚度。該第 六絕緣層78作為一用以防止水份擴散及銅由該等第二配線 77b擴散出來之障壁層。 藉依需要重覆與前述相同之步驟，形成未顯示第三配 線等，藉此完成依據本方法之半導體裝置。 10 依據這實施例，可防止絕緣層之介電常數由於乾蝕刻 所造成之破壞而增加，且亦可防止絕緣層之介電常數因該 絕緣層暴露於空氣而增加。這使該絕緣層可具有一低介電 常數與高可靠性，因此，如果使用該絕緣層作為多層配線 結構之一層間絕緣層，則可獲得一具有一高回應速度之半 15 導體裝置。 [第三實施例] 以下將參照第15與16圖說明第三實施例之半導體裝置 之製造方法。 第15圖是一顯示這實施例之半導體裝置製造方法的流 20 程圖，且第16圖是顯示這實施例之半導體裝置製造方法的 步驟。 如第15圖所示，這實施例之半導體裝置製造方法包括 一沈積一二氧化矽基絕緣層之步驟（步驟S31)、一將該二氧 化矽基絕緣層拋光之步驟（步驟S32)、一利用一矽烷化合物 25 200921788 修復因乾蝕刻造成之破壞之步驟(步驟S33)、及一藉光或一 電子束照射縮合Si-OH基之步驟（步驟S34)。 以下將參照第16圖詳細說明前述步驟。 該二氧化矽基絕緣層202沈積在一底基板2〇〇(在第16A 5圖中之步驟S31)上，且該底基板200之例包括如矽基板之半 導體基板及包括MIS電晶體、一或多數配線層、及其他組件 的半導體基板。 該二氧化矽基絕緣層202可由與用以形成在第一實施 例中所述之二氧化矽基絕緣層102者實質相同之材料製 10成，且該二氧化矽基絕緣層202可以藉與用以形成在第一實 施例中所述之二氧化矽基絕緣層1〇2者實質相同之製程形 成。 e玄絕緣層202藉例如一化學機械拋光(CMP)製程來拋 光，使得該絕緣層202具有一預定厚度。在這操作中，一具 15有由於拋光造成之破壞的被破壞層形成在該絕緣層202之 被拋光表面上（第16B圖）。 該用語“由於拋光造成之破壞，，表示由CMP所使用之酸 性或鹼性化學溶液所造成之破壞。在該絕緣層中由酸性或 鹼性化學溶液所造成之破壞以及在第一與第二實施例中所 20述之由乾蝕刻造成的破壞會產生Si-OH鍵結。 因拋光該絕緣層202所造成之破壞係以該矽烷化合物 修復（步驟S33) ’且在這操作中，修復在該絕緣層2〇2上之被 破壞層204(第16C圖所示之已修復層206)。 特別地，由拋光造成之破壞所產生的Si_〇H可與該矽烷 26 200921788 化合物反應。一用以使該Si-OH與該矽烷化合物之製程並未 特別受到限制，且這製程之較佳例子包括在大氣壓或在真 空下利用該矽烷化合物實施之一旋塗製程或一蒸鍍製程。 特別地，該蒸鍍製程特別適合，因為該蒸鍍法不受表面張 5 力影響。 在該蒸鍍製程中，該底基板最好被加熱至50°C至350°C 之溫度，使得該矽烷化合物在該絕緣層202中擴散且補強一 已修復部份。在該旋塗製程中，在大氣壓下以一旋塗機處 理，且接著對該旋塗層進行烘烤，使得該等已修復部份被 10 補強。此時，最好以由50°C至350°C之範圍内之單一溫度或 不同溫度進行烘烤。 處理之溫度最好依據該矽烷化合物之種類，在一由 50°C至350°C之範圍内決定。該處理溫度之上限依據該矽烷 化合物之沸點來決定，且因此設定為低於或等於該矽烷化 15 合物之沸點。該處理溫度之下限是50°C，因為前述破壞無 法以該石夕烧化合物充份地修復。 可用以修復之矽烷化合物並未特別受限且可包含一可 與由乾蝕刻造成之破壞所產生之Si-OH反應的官能基，且該 矽烷化合物之例包括如二甲基二矽氮烷、四曱基二矽氮 20 烷、及六甲基二矽氮烷之矽氮烷化合物；如雙（三甲基矽基) 乙醯胺及雙（三乙基矽基）乙醯胺之矽醯胺化合物；如三曱氧 矽烷、三乙氧矽烷、甲基三甲氧矽烷、甲基三乙氧矽烷、 二甲基三甲氧矽烷、二甲基三乙氧矽烷、三甲基三甲氧矽 烷、三甲基三乙氧矽烷、乙基三甲氧矽烷、乙基三乙氧矽 27 200921788 烷、二乙基三曱氧矽烷、二乙基三乙氧矽烷、三乙基三甲 氧石夕烧、三乙基三乙氧石夕烧、丙基三甲氧石夕燒、丙基二乙 氧矽烧、二丙基三甲氧矽烧、二丙基三乙氧矽燒、三丙基 三甲氧矽烷、三丙基三乙氧矽烷、苯基三曱氧矽烷、苯基 5三乙氧矽烷、二苯基三甲氧矽烷、二苯基三乙氧；g夕院、三 苯基三甲氧矽烷、三苯基三乙氧矽烷、笨曱基甲氧石夕烧、 苯曱基乙氧矽烷、二甲苯基曱氧矽烷、二甲苯基乙氧石夕烧、 二苯甲基甲氧石夕院、及二苯甲基乙氧石夕烧之院氧石夕院化合 物；及如二乙醯氧石夕院、三乙氧石夕烧、曱基三乙氧石夕烧、 10二甲基乙醯氧矽烷、三甲基乙醯氧矽烷、乙基乙醯氧石夕烷、 二乙基乙醯氧石夕烧、三乙基乙醢氧;5夕烧、二丙基乙醢氧石夕 烷、三丙基乙醯氧矽烷、苯基三乙醯氧矽烷、二苯基乙醯 氧矽烷、三苯基乙醯氧矽烷、苯甲基乙醯氧矽烷、二曱苯 基乙醯乳石夕烧、及一苯曱基三乙醯氧石夕烧之乙酿氧石夕烧化 15 合物。 該破壞之修復使存在於該被破壞層204中之Si-OH可以 被轉變成Si-CHs，使疏水性增強。但是，因為該矽烷化合 物具有大分子量，且這會導致空間位阻；因此難以將si_〇H 全部轉變成S1-CH3。因此，如果該被破壞層2〇4被放置在空 20氣中’則&_011吸收水份’造成介電常數增加。 依據這實施例之半導體裝置製造方法，在以該矽烷化 合物修復該破壞後，剩餘之Si-〇H被縮合(脫氫縮合），使得 Si-0-Si鍵結形成’藉此防止吸收水份（步驟S34)。Si_〇H可 以光或一電子束照射該二氧化矽基絕緣層1〇2且以3〇〇c至 28 200921788 400°C加熱該底基板100之方式加以縮合，如第l6D圖所示。 一用以縮合之光源並沒有特別之限制且最好以丨7 〇至 700nm之波長發射光，該光源之例包括準分子燈、水銀p、 及金屬_素燈。在被光照射之該基板之溫度最好是3〇()(^至 5 400oC。 一環境氣體最好具有等於或小於150ppm之氧含量且 可包含氮、氦(He)及氬之一或多種並且可為真空。洛在真 空中（在低壓下）進行照射時，氮、氦(He)及氩之—或多種可 以一或多個質量流量計導入一真空室中，使得該真空室具 1〇 有一預定值壓力。 在藉電子束縮合時，該被破壞層最好以一在真空中具 有1至15kV之加速電壓的電子束加以照射。當該電子束小於 ikv時，無法達成充分的效果。當該加速電壓大於15kv時， 該絕緣層會被破壞。 15 在照射光或電子束時的處理溫度最好在由30°C至 400°C之範圍内，且可依據該二氧化矽基絕緣層之種類選 擇。該處理溫度之上限依據形成一絕緣層之被破壞層之溫 度上限來決定’且係小於該被破壞層之溫度上限。該處理 溫度之下限是30°C，因為縮合反應在溫度低於30°C時不會 20 發生。 由於該等Si-ΟΗ係在如前所述地以矽烧化合物修復破 壞後才被縮合，所以可以大幅減少該絕緣層之吸水性。即 使該絕緣層被放置於空氣中，這亦可大幅減少被該絕緣層 所吸收之水份量，因此，可有效地防止該絕緣層之介電常 29 200921788 數因吸收水份而增加。 依據這實施例，即使該二氧化矽基絕緣層102被放置在 空氣中，亦可修復在該絕緣層中因拋光造成之破壞，且可 防止該絕緣層之介電常數增加。 5 [第四實施例] 以下將參照第17至21圖說明一第四實施例之半導體裝 置的製造方法，且與在第1至16圖所示之第一至第三實施例 之任一者之半導體裝置製造方法中說明的相同組件或構件 係以在此所使用者相同之符號表示，並且將簡短地說明或 10 將不加以說明。 第17至21圖係截面圖，顯示這實施例之半導體裝置製 造方法之步驟。 在這實施例中，將說明以下例子：即，一依據該第三 實施例之製造方法應用於依據該第二實施例之半導體裝置 15 製造方法的例子。 以下組件以與例如在第4 A至5 B圖示之第二實施例之 半導體裝置製造方法中所使用者實質相同之方式，形成在 一半導體基板10上（第17A圖）：一隔離層12、一MOS電晶體 24、一層間絕緣層26 ' —擋止層、一接觸栓塞35、一絕緣 20 層36、一層間絕緣層38、及一絕緣層40。 一用以形成一延伸通過該絕緣層40、該層間絕緣層及 該絕緣層36之配線51的配線溝槽46係以與例如在第6A與 6B圖所示之第二實施例之半導體裝置製造方法中所使用者 實質相同之方式形成。 30 200921788 在开y成孩配線溝槽46時因乾姓刻造成之被破壞層係 以與例如在第7A與7B圖所示之第二實施例之半導體裝置 製造方法中所使用者實質相同之方式，以一石夕燒化合物加 以處理且以-紫外線加以照射，藉此修復該被破壞層（—在 5第17B圖中所示之已修復層116)。 藉例如-錢鍍製程，將一層氮化组(蘭)沈積在該絕緣 層40上，且具有例如50nm之厚度，藉此形成一由簡製成 之障壁金屬層48。 藉例如一濺鍍製程’將—層銅沈積在該障壁金屬層48 10上以具有一例如10nm之厚度，藉此形成一由Cu製成之晶種 副層（圖未示）。 藉例如一電鍍製程，將—銅副層沈積在形成為一晶種 之晶種副層上，藉此形成一包括該晶種副層且具有例如 600nm之厚度之Cu層50。 15 藉一 CMP製程部份地移除設置在該絕緣層40上之該Cu 層50與障壁金屬層48，藉此在該配線溝槽46中形成該配線 51。該配線51包括該障壁金屬層48之一部份及該Cu層5〇之 一部份，且該CVD製程用之漿液最好依據用以形成該g己線 51或該絕緣層40之材料來選擇。在這拋光步驟中，一含濟 20 Si-OH之被破壞層形成在該絕緣層40中。 在形成該配線51之步驟中，一用以抛光之酸性或驗择 化學溶液作用在該絕緣層40上，以在該絕緣層中產生 鍵結。s玄用语‘ 一在该絕緣層上產生物理或化學作用之〆 驟”在此係表示一加工該絕緣層之步驟。加工該絕緣層之少 31 200921788 驟之例包括-藉乾姓刻等將該絕緣層圖案化之步驟、— 扎光將出現在該絕緣層上之導電層移除之步驟、及' 光部份地移除該絕緣層之步驟。 · 在"亥絕緣層上，滴上3CC之如六甲基二石夕氮烧之石夕燒^ 5合物，且以丨，0001^111對該絕緣層進行旋塗60秒，在 l2〇C下於一熱板上烘烤60秒；接著在25〇°c下再烘烤6〇 秒。這使由在形成該配線51時因拋光在該絕緣層中產生之 Si-OH可以轉變成Si-CHs ’藉此可修復該絕緣層4〇之破壞。 用以修復該破壞之石夕烧化合物及使用該矽烧化合物之 10處理方法可以與第三實施例之半導體裝置製造方法中所述 之用以修復在該絕緣層202上之被破壞層204的處理方法相 同。 以該半導體基板在一氮環境氣體中被加熱至例如 400°C之方式，利用—高壓水銀燈(例如由Ushio Inc.取得之 15 UVL-7000 H4-N)，以具有例如200至600nm之波長之紫外線 照射該絕緣層大約十分鐘（第18A圖）。這使得在以該*夕烷化 合物修復該破壞後剩餘之Si-ΟΗ可被縮合，以形成&七-呂土 鍵結，因此，可防止Si-OH吸收水份。 在該第三實施例中所述之方法與條件$以用於用以縮 20合Si-OH之光照射’且可進行電子束照射而祚在邊第三實施 例中所述之光照射。在該第三實施例中所述之方法與條件 可以用於電子束照射。 以與在例如第8 A至9圖所示之第二實施例之半導體襄 置製造方法中所使用者實質相同之方式，在具有配線51埋 32 200921788 没於其中之絕緣層4〇上，形成一絕緣層52、一層間絕緣層 54及絕緣層60(第18B圖）。在這實施例中，所使用的是 一由該絕緣層60、該層間絕緣層54及該絕緣層52構成之三 層結構。或者，可如在該第二實施例中所述地使用一包括 5 一作為一蝕刻擋止部之絕緣層56的結構。在這實施例中， / g門 '、、邑緣層54可以是一具有例如18〇nmi厚度的多孔質 -氧化層。 以與在例如第⑴與丨丨圖所示之第二實施例之半導體裝 置製造方法中所使用者實質相同的方式，形成以下孔與溝 10槽.即，一延伸通過該絕緣層52與該層間絕緣層54而到達 β玄配線51之通孔66，及一用以形成一延伸通過該層間絕緣 層54與該絕緣層60之配線77b的配線溝槽72。 以與在例如第7A與7B圖所示之第二實施例之半導體 裝置製造方法中所使用者實質相同的方式，以一矽烷化合 15物處理且以—紫外線照射一在形成該通孔66與該配線溝槽 46時因乾蝕刻所產生之被破壞層，藉此修復該被破壞層（一 在第19圖中所示之已修復層116)。 藉例如一濺鍍製程，將一層TaN沈積在該絕緣層60上， 以具有例如1 〇nm之厚度，且藉此形成一由TaN製成之障壁 2〇 金屬層74。 藉例如一濺鍍製程，將一層銅沈積在該障壁金屬層74 上以具有一例如l〇nm之厚度，藉此形成一由Cu製成之晶種 副層（圖未示）。 藉例如一電鍍製程，將銅沈積在形成為一晶種之晶種 33 I. 200921788 副層上，藉此形成一包括該晶種副層且具有例如14〇〇nmi 厚度之Cu層76。 藉一CMP製程部份地移除設置在該絕緣層60上之該銅 層76與障壁金屬層74，藉此一接觸拴塞77a與該配線77b在 5 —步驟中為單件式結構。該接觸栓塞77a係設置在該通孔66 中且包括該障壁金屬層74之一部份及該銅層76之_部份， 並且該配線7 7 b係設置在該配線溝槽7 2中且包括該障壁金 屬層74之一部份及該銅層76之一部份。該CVD製程用之漿 液最好依據用以形成該接觸栓塞77a與該配線77b之材料或 10用以形成該絕緣層60之材料來選擇，且在這拋光步驟中， 一含有Si-OH之被破壞層形成在該絕緣層6〇中。 在該絕緣層上，滴上3cc之如六曱基二矽氮烷之矽烷化 合物，且以l，00〇rpm對該絕緣層進行旋塗6〇秒，在例如 120〇C下於一熱板上烘烤6〇秒；接著在25〇QCt再烘烤6〇 15秒。這使由在形成該接觸栓塞77a與該配線77b時因拋光在 該絕緣層中產生之Si~〇H可以轉變成Si-CH3,藉此修復該絕 緣層40之破壞。 用以修復該破壞之石夕烧化合物及使用該石夕烧化合物之 處理方法可以與第三實施例之半導體裝置製造方法中所述 2〇之用以修復在該絕緣層2〇2上之被破壞層2〇4的處理方法相 同。 以該半導體基板在一氮環境氣體中被加熱至例如 400 C之方式和用一尚壓水銀燈(例如由Ushio Inc.取得之 UVL-7000 H4-N) ’以具有例如2〇〇至働⑽之波長之紫外線 34 200921788 照射該絕緣層大約十分鐘（第20圖）。這使得在以該矽烷化入 物修復該破壞後剩餘之Si-OH可被縮合，以形成鍵 結’因此’可防止Si_〇H吸收水份。 在該第四實施例中所述之方法與條件可以用於用以縮 5合Si-ΟΗ之光照射，且可進行電子束照射而非在該第四實施 例中所述之光照射。在該第四實施例中所述之方法與條件 可以用於電子束照射。 藉例如一CVD製程，在該層間絕緣層上沈積一層以匚. Ο : Η ’以具有大約3〇nm之厚度，藉此形成一由&匚：n w · Η 10 製成之絕緣層78(第21圖）。 依需要重覆與前述者相同之步驟，以形成—未顯示之 第三配線等’藉此完成這實施例之半導體裝置。 如前所述，依據這實施例，以修復該等絕緣層之工作 破壞之方式，可防止該等絕緣層之介電常數增加。此外， 15即使該等絕緣層被放置在空氣中’亦可防止其介電常數増 加。這使該等絕緣層可具有一低介電常數及高可靠性，因 此，如果該等絕緣層應用於例如多層配線結構用之層間絕 緣層，則可增加一半導體裝置之回應速度。 [第五實施例] 20 以下將參照第22至26圖說明一第五實施例之半導體裝 置的製造方法，且與在第1至21圖所示之第一至第四實施例 之任-者之半導體裝置製造方法中說明的相同組件或構件 係以在此所使用者相同之符號表示，並且將簡單地說明或 將不加以說明。 35 200921788 第22至26圖是截面圖，顯示這實施例之半導體裝置製 造方法之步驟。 在這實施例中，將說明以下例子：即，一依據該第三 實施例之製造方法應用於依據該第二實施例之半導體裝置 5 製造方法的例子。 以下組件以與例如在第4 A至5 B圖示之第二實施例之 半導體裝置製造方法中所使用者實質相同之方式，形成在 一半導體基板10上（第22A圖）：一隔離層12、一MOS電晶體 24、一層間絕緣層26、一檔止層、一接觸栓塞35、一絕緣 10 層36、一層間絕緣層38、及一絕緣層40。 一用以形成一延伸通過該絕緣層40、該層間絕緣層及 該絕緣層36之配線51的配線溝槽46係以與例如在第6A與 6B圖所示之第二實施例之半導體裝置製造方法中所使用者 實質相同之方式形成。 15 —在形成該配線溝槽4 6時因乾蝕刻造成之被破壞層係 以與例如在第7A與7B圖所示之第二實施例之半導體裝置 製造方法中所使用者實質相同之方式，以一矽烷化合物加 以處理且以一紫外線加以照射，藉此修復該被破壞層（一在 第22B圖中所示之已修復層116)。 20 藉例如一濺鍍製程，將一層氮化钽(TaN)沈積在該絕緣 層40上，且具有例如50nm之厚度，藉此形成一由TaN製成 之障壁金屬層48。 藉例如一濺鍍製程，將一層銅沈積在該障壁金屬層48 上以具有一例如1 〇nm之厚度，藉此形成一由Cu製成之晶種 36 200921788 副層（圖未示）。 藉例如一電鍍製稃，將一銅副層沈積在形成為一晶種 之晶種副層上，藉此形成包括θ曰種副層且具有例如 600nm之厚度之Cu層5〇。 5 藉一 CMP製程部份地移除設置在該層間絕緣層38上之 該Cu層50、障壁金屬層48及絕緣層40，藉此在該配線溝槽 46中形成該配線51。該配線51包括該障壁金屬層48之一部 份及該Cu層50之一部份。 在這實施例中，該絕緣層40係在形成該配線51之拋光 10步驟中移除。該絕緣層40係被用來作為一用以形成該配線 溝槽46之硬遮罩，且通常是由一介電常數大於用以形成該 層間絕緣層38之材料之介電常數的材料製成。在這實施例 中，為了使該層間絕緣層可以具有—低介電常數，在形成 該配線51之拋光步驟中移除該絕緣層40。由於是藉拋光移 15 除該絕緣層40，所以在設置於該絕緣層40下方之層間絕緣 層38中會形成一含有Si-ΟΗ之被破壞層。 以與在例如第18B圖所示之第四實施例之半導體裝置 製造方法中所使用者實質相同的方式’以一矽烷化合物處 理且以一紫外線照射一在形成該配線51時因拋光而在該層 20 間絕緣層38中產生之被破壞層，藉此修復該被破壞層（第 23A圖）。 由於該絕緣層40係藉拋光來移除，所以設置在其下方 之層間絕緣層38會被破壞且因此該層間絕緣層38之介電常 數會增加。但是，由於該層間絕緣層38之破壞被前述處理 37 200921788 修復，所以可防止該層間絕緣層38之介電常數增加，且移 除該絕緣層40使該層間絕緣層可具有一較低之介電常數。 以與在例如第18A圖所示之第三實施例之半導體裝置 製造方法中所使用者實質相同之方式，在具有配線51埋設 5 於其中之層間絕緣層38上，形成一絕緣層52、一層間絕緣 層54、及一絕緣層60(第23B圖）。在這實施例中，所使用的 是一由該絕緣層60、該層間絕緣層54及該絕緣層52構成之 三層結構。或者，可如在該第二實施例中所述地使用一包 括一作為一蝕刻擋止部之絕緣層56的結構。 10 以與在例如第10與11圖所示之第二實施例之半導體裝 置製造方法中所使用者實質相同的方式，形成以下孔與溝 槽：即，一延伸通過該絕緣層52與該層間絕緣層54而到達 該配線51之通孔66，及一用以形成一延伸通過該層間絕緣 層54與該絕緣層60之配線77b的配線溝槽72。 15 以與在例如第12與13圖所示之第二實施例之半導體裝 置製造方法中所使用者實質相同的方式，以一矽烷化合物 處理且以一紫外線照射一在形成該通孔6 6與該配線溝槽4 6 時因乾蝕刻所產生之被破壞層，藉此修復該被破壞層（一在 第24圖中所示之已修復層116)。 20 藉例如一滅;鑛製程，將一層TaN沈積在該絕緣層60上， 以具有例如1 〇nm之厚度，且藉此形成一由TaN製成之障壁 金屬層74。 藉例如一減鑛製程，將一層銅沈積在該障壁金屬層74 上以具有一例如l〇nm之厚度，藉此形成一由Cu製成之晶種 38 200921788 副層（圖未示）。 藉例如一電鍍製程，將銅沈積在形成為一晶種之晶種 副層上，藉此形成一包括該晶種副層且具有例如之 厚度之Cii層76。 5 藉一 CMP製程部份地移除設置在該絕緣層60上之該銅 層76與障壁金屬層74，藉此一接觸栓塞77a與該配線77b在 一步驟中為單件式結構。該接觸栓塞77a係設置在該通孔66 中且包括該障壁金屬層74之一部份及該銅層76之一部份， 並且該配線77b係設置在該配線溝槽72中且包括該障壁金 10 屬層74之一部份及該銅層76之一部份。 在這實施例中’該絕緣層6〇係在形成該接觸栓塞77a與 該配線77b之拋光步驟中移除。該絕緣層60係被用來作為一 用以形成該通孔66與該配線溝槽46之硬遮罩，且通常是由 一介電常數大於用以形成該層間絕緣層54之材料之介電常 15數的材料製成。在這實施例中，為了使該層間絕緣層可以 具有一低介電常數，在形成該接觸拴塞77a與該配線77b之 拋光步驟中移除該絕緣層60。由於是藉拋光移除該絕緣層 60，所以在設置於該絕緣層60下方之層間絕緣層54中會形 成一含有Si-OH之被破壞層。 20 以與在例如第19圖所示之第四實施例之半導體裝置製 造方法中所使用者實質相同的方式，以一矽烷化合物處理 且以一紫外線照射一在形成該接觸栓塞7 7 a與該配線7 7 b時 因乾钮刻而在該層間絕緣層54中產生之被破壞層，藉此修 復該被破壞層（第25圖）。 39 200921788 由於該絕緣層60係藉拋光來移除，所以設置在其下方 之層間絕緣層54會被破壞且因此該層間絕緣層54之介電常 數會增加。但是，由於該層間絕緣層54之破壞被前述處理 修復，所以可防止該層間絕緣層54之介電常數增加，且移 5除該絕緣層60使該層間絕緣層可具有一較低之介電常數。 藉例如一CVD製程，在該層間絕緣層上沈積_層sic : 以具有大約30nm之厚度，藉此形成一由：〇 : η 製成之絕緣層78(第26圖）。 如岫所述，依據這實施例，以修復該等絕緣層之工作 1〇破壞之方式，可防止該等絕緣層之介電常數增加。此外， 即使。亥等絕緣層被放置在空氣中，亦可防止其介電常數增 加。每使該等絕緣層可具有一低介電常數及高可靠性因 如果4等絕緣層應用於例如多層配線結構用之層間絕 緣層’則可增加—半導«置之回應速度。 15 [其他實施例] 法本發明不限於第一與第二實施例之半導體裝置及方 ^可以廣泛地應用於包括二氧化矽基絕緣層之各種半 晋 該等層之包括在該等半導體裝置之層的厚度及用以形成 材料可以在本發明之範圍内改變。 20 [例子] [例1]As shown in FIG. 10, in the manner in which the second photoresist layer 62 is used as a mask 5, the fifth insulating layer 60, the fifth is sequentially dry-etched, for example, by an etching gas containing CF4 and CHF3. The interlayer insulating layer 58, the fourth insulating layer %, the third interlayer insulating layer 54, and the third insulating layer 52 are such that the second photoresist layer 62 is used as a mask, thereby forming a majority extension The fifth insulating layer 60, the fifth interlayer insulating layer %, the fourth insulating layer 56, the third three-layer insulating layer 54, and the third insulating layer 52 reach the through holes 66 of the first wirings 51. . The insulating layer may be etched in a manner that changes the composition and/or pressure of the etching gas, and in the dry etching step, the damaged layer 112 containing the Si 〇 H groups is formed in the wall of the through holes 66, As shown by the cross in Figure 1 . The second photoresist layer 62 is removed by, for example, ashing, and even if the wall deposit is formed on the wall of the through holes by dry etching when the through holes 66 are formed, the ash may be ashed. The wall deposits are removed in the step. A third photoresist layer 68 is formed on the fifth insulating layer 60, and the through holes 66 are formed in the fifth insulating layer 60. The third photoresist layer 68 has a plurality of third openings 70 formed by photolithography, and through the third openings 70, a plurality of regions for forming a plurality of second wirings 77b are exposed. As shown in FIG. 11, the third photoresist layer 68 is used as a mask to sequentially dry the fifth insulating layer 60 and the fifth interlayer insulating layer by, for example, a CF4 gas and a CHF3 gas. The layer 58 and the fourth insulating layer %, 22 200921788 thereby form the second wiring 77b. The second wiring 77b extends through the fifth insulating layer 60, the fifth interlayer insulating layer 58, and the fourth insulating layer %, and the second wiring trenches 72 are connected to the via holes 66. In this dry etching step, a damaged layer 112 containing Si-OH groups is formed in the walls of the grooves 24 of the second wiring trenches 5 as shown in the figure in Fig. 11. The third photoresist layer 68 is removed by, for example, ashing, even if the wall deposits are formed in the walls of the second wiring trenches 72 by dry etching when the second wiring trenches 72 are formed. The wall deposits can be removed during this ashing step. 10, as shown in FIG. 12, 3 cc of a calcining compound such as hexakisodiazane is dropped on the fifth insulating layer 60 and then the fifth insulating layer 60 is performed at 1, rpm. After spin coating for 60 seconds, the semiconductor substrate 10 was baked at, for example, 120 ° C for 60 seconds and then baked at 250 ° C for 6 seconds with a hot plate. This allows 15 Si-OH groups generated by dry etching in forming the via holes 66 and the second wiring trenches 72 to be converted into Si-CH3 groups' thereby repairing the presence of the via holes 66 and The damaged layer 112 in the wall of the second wiring trench 72. This also forms the repaired layer 116. In this step, the same sinter compound and process for repairing the damaged layer 112 described in the first embodiment can be used. As shown in Fig. 13, the semiconductor substrate 1 is heated to, for example, 400 in a nitrogen atmosphere. (In the manner of using a UVL-7000 H4-N high-pressure mercury lamp obtained by Ushio Inc., the fifth insulating layer 60 is irradiated with ultraviolet rays having a wavelength of, for example, 200 to 600 nm for ten minutes. This makes the remaining Si-OH group It can be converted into a Si-0-Si group by condensation, thereby preventing absorption of moisture by the Si-OH group of the exclusive remainder 23 200921788. In this step, it can be used and used for condensation as shown in the first embodiment. The Si-ruthenium is the same process and condition. In this step, electron beam irradiation can be performed instead of 5 light irradiation in the same manner as shown in the first embodiment. A nitride layer is deposited on the fifth insulating layer 60 to thereby form a third barrier metal layer 74. The third barrier metal layer 74 is tantalum nitride and has a thickness of, for example, 10 nm. The third barrier metal layer 74 Preventing copper from being diffused into the insulating layer 10 by a copper line formed in a subsequent step. Copper is deposited on the third barrier metal layer 74 by, for example, a sputtering process, thereby forming a second seed layer (not shown). The second seed layer is formed of copper and has There is, for example, a thickness of 1 Onm. A second copper coating is deposited on the second crystal 15 layer by, for example, an electroplating process, thereby forming a second copper layer 76. The second copper layer 76 includes the first a second seed layer and the second copper coating, and having a thickness of, for example, 1,4〇〇ηΠ. The second copper layer 76 is located on a portion of the fifth insulating layer 60 and the second barrier metal layer A portion of the 74th portion above the fifth insulating layer 60 is removed by a CMP process, thereby forming interconnectable second contact plugs 77 & 20 and the second wiring 77b. The second contact plugs 77a includes a majority of the third barrier metal layer 74 remaining in the vias 66 and a majority of the second copper layer % remaining therein, and the second wiring 77b includes the third barrier metal The layer 74 remains in the majority of the second wiring trenches 72 and the majority of the second copper layer 76 remains therein. One is used to form the 24 200921788 second contact plugs 77a and The process of the second wiring 77b is referred to as a dual damascene process. As shown in Fig. 14, by, for example, a CVD process, SiC is: Ο : Η is deposited on the fifth insulating layer 60, thereby forming a sixth insulating layer 78. The sixth insulating layer 78 is SiC : Ο : Η and has a thickness of, for example, 30 nm. The sixth insulating layer 78 As a barrier layer for preventing moisture diffusion and diffusion of copper from the second wiring 77b, the same steps as described above are repeated as needed to form a semiconductor wire not shown, thereby completing the semiconductor according to the method. According to this embodiment, it is possible to prevent the dielectric constant of the insulating layer from being increased due to damage caused by dry etching, and also to prevent the dielectric constant of the insulating layer from being increased by exposure of the insulating layer to air. This allows the insulating layer to have a low dielectric constant and high reliability. Therefore, if the insulating layer is used as an interlayer insulating layer of a multilayer wiring structure, a half-conductor device having a high response speed can be obtained. [Third Embodiment] A method of manufacturing a semiconductor device of a third embodiment will be described below with reference to Figs. Fig. 15 is a flow chart showing the manufacturing method of the semiconductor device of this embodiment, and Fig. 16 is a view showing the steps of the manufacturing method of the semiconductor device of this embodiment. As shown in FIG. 15, the semiconductor device manufacturing method of this embodiment includes a step of depositing a germanium dioxide-based insulating layer (step S31), a step of polishing the germanium dioxide-based insulating layer (step S32), and a step The step of repairing the damage due to dry etching (step S33), and the step of condensing the Si-OH group by light irradiation or an electron beam irradiation using a monooxane compound 25 200921788 (step S34). The foregoing steps will be described in detail below with reference to Fig. 16. The ceria-based insulating layer 202 is deposited on a substrate 2 (in step S31 in FIG. 16A), and the substrate 200 includes a semiconductor substrate such as a germanium substrate and a MIS transistor. Or a semiconductor substrate of many wiring layers and other components. The ceria-based insulating layer 202 may be made of a material substantially the same as that used to form the ceria-based insulating layer 102 described in the first embodiment, and the ceria-based insulating layer 202 may be used. The process for forming the ceria-based insulating layer 1 2 described in the first embodiment is substantially the same. The e-insulating layer 202 is polished by, for example, a chemical mechanical polishing (CMP) process such that the insulating layer 202 has a predetermined thickness. In this operation, a damaged layer having 15 damage due to polishing is formed on the polished surface of the insulating layer 202 (Fig. 16B). The term "destruction due to polishing indicates damage caused by an acidic or alkaline chemical solution used by CMP. Destruction caused by an acidic or alkaline chemical solution in the insulating layer and in the first and second The damage caused by the dry etching described in the embodiment 20 causes Si-OH bonding. The damage caused by polishing the insulating layer 202 is repaired with the decane compound (step S33)' and in this operation, the repair is performed. The damaged layer 204 on the insulating layer 2〇2 (the repaired layer 206 shown in Fig. 16C). In particular, Si_〇H generated by the destruction caused by polishing can react with the compound of the decane 26 200921788. The process for making the Si-OH and the decane compound is not particularly limited, and preferred examples of the process include performing a spin coating process or an evaporation process using the decane compound at atmospheric pressure or under vacuum. The evaporation process is particularly suitable because the evaporation process is not affected by the surface tension. In the evaporation process, the base substrate is preferably heated to a temperature of 50 ° C to 350 ° C to make the decane. Compound in the absolute The layer 202 diffuses and reinforces a repaired portion. In the spin coating process, it is treated by a spin coater at atmospheric pressure, and then the spin coating is baked, so that the repaired portions are reinforced by 10 In this case, it is preferred to bake at a single temperature or a different temperature ranging from 50 ° C to 350 ° C. The temperature of the treatment is preferably from 50 ° C to 350 ° C depending on the type of the decane compound. The upper limit of the treatment temperature is determined according to the boiling point of the decane compound, and is therefore set to be lower than or equal to the boiling point of the decaneated compound. The lower limit of the treatment temperature is 50 ° C because the aforementioned damage cannot be The cerium compound which can be repaired is not particularly limited and may include a functional group which can react with Si-OH generated by destruction by dry etching, and the decane compound Examples include decazane compounds such as dimethyl diazane, tetradecyl diazane 20 alkane, and hexamethyldioxane; such as bis(trimethyldecyl)acetamide and bis (three) a decylamine compound of ethyl decyl acetamide; Trioxoxane, triethoxydecane, methyltrimethoxydecane, methyltriethoxydecane, dimethyltrimethoxydecane, dimethyltriethoxydecane, trimethyltrimethoxydecane, trimethyltriethyl Oxane, ethyltrimethoxydecane, ethyltriethoxyphosphonium 27 200921788 alkane, diethyltrioxoxadecane, diethyltriethoxyoxane, triethyltrimethoxysulfate, triethyltriethoxy Shi Xi Shao, propyl trimethoxide, propyl diethoxy oxime, dipropyl trimethoate, dipropyl triethoxy oxime, tripropyltrimethoxy decane, tripropyl triethoxy Decane, phenyl trioxoxane, phenyl 5 triethoxy decane, diphenyl trimethoxy decane, diphenyl triethoxy; g Xiyuan, triphenyltrimethoxy decane, triphenyl triethoxy decane, Alum-based methoxymethoxine, benzoyl ethoxy decane, xylyl sulfoxane, xylyl ethoxylate, diphenylmethyl methoxide, and diphenylmethyl ethoxylate Oxygen stone compound compound; and such as bismuth oxysphate sage, triethoxy sulphate, sulphur-based triethoxy sulphate, 10 dimethyl oxime Alkane, trimethyl ethoxy oxane, ethyl ethoxy oxetane, diethyl ethoxide, triethyl ethane oxyhydroxide; 5 kiln, dipropyl ethoxy oxetane, Tripropyl ethoxy decane, phenyl triethoxy decane, diphenyl ethoxy oxane, triphenyl ethoxy decane, benzyl oxoxane, diphenyl phenyl hydrazine And the benzophenone triethoxyphthalate sintered in the brewing of the oxygen stone smelting 15 compound. The repair of the damage allows the Si-OH present in the damaged layer 204 to be converted into Si-CHs to enhance hydrophobicity. However, since the decane compound has a large molecular weight, and this causes steric hindrance; therefore, it is difficult to convert all of si_〇H into S1-CH3. Therefore, if the damaged layer 2〇4 is placed in the air, then &_011 absorbs water' to cause an increase in the dielectric constant. According to the semiconductor device manufacturing method of this embodiment, after the destruction is repaired with the decane compound, the remaining Si-〇H is condensed (dehydrogenation condensation) so that Si-0-Si bonds are formed to thereby prevent absorption of moisture. (Step S34). Si_〇H may be condensed by irradiating the ceria-based insulating layer 1〇2 with light or an electron beam and heating the base substrate 100 at 3〇〇c to 28 200921788 400°C, as shown in Fig. 6D. A light source for condensation is not particularly limited and preferably emits light at a wavelength of from 丨7 〇 to 700 nm, and examples of the light source include an excimer lamp, a mercury p, and a metal-based lamp. The temperature of the substrate irradiated with light is preferably 3 〇 () to 5 400 ° C. An ambient gas preferably has an oxygen content equal to or less than 150 ppm and may contain one or more of nitrogen, helium (He) and argon. And can be vacuum. When irradiated in a vacuum (at low pressure), nitrogen, helium (He) and argon - or a plurality of mass flow meters can be introduced into a vacuum chamber, so that the vacuum chamber has 1 〇 has a predetermined value of pressure. When condensing by electron beam, the damaged layer is preferably irradiated with an electron beam having an acceleration voltage of 1 to 15 kV in a vacuum. When the electron beam is smaller than ikv, sufficient effect cannot be achieved. When the accelerating voltage is greater than 15 kV, the insulating layer may be destroyed. 15 The processing temperature in the case of irradiating light or electron beam is preferably in the range of 30 ° C to 400 ° C, and may be based on the ceria group. The type of the insulating layer is selected. The upper limit of the processing temperature is determined according to the upper temperature limit of the damaged layer forming an insulating layer and is less than the upper limit of the temperature of the damaged layer. The lower limit of the processing temperature is 30 ° C because of the condensation reaction. Not when the temperature is below 30 ° C Will occur at 20. Since the Si-lanthanum is condensed after being repaired and destroyed by the smoldering compound as described above, the water absorbing property of the insulating layer can be greatly reduced. Even if the insulating layer is placed in the air, this The amount of moisture absorbed by the insulating layer can also be greatly reduced, and therefore, the dielectric of the insulating layer can be effectively prevented from increasing due to absorption of moisture. According to this embodiment, even the ceria-based insulating layer is provided. The 102 is placed in the air, and the damage caused by the polishing in the insulating layer can be repaired, and the dielectric constant of the insulating layer can be prevented from increasing. [Fourth Embodiment] Hereinafter, a description will be given with reference to Figs. The manufacturing method of the semiconductor device of the fourth embodiment, and the same components or components as those described in the semiconductor device manufacturing method of any of the first to third embodiments shown in FIGS. 1 to 16 are here. The same symbol is used for the user, and will be briefly explained or 10 will not be described. Sections 17 to 21 are sectional views showing the steps of the method of manufacturing the semiconductor device of this embodiment. In this embodiment, The following example will be explained: an example in which the manufacturing method according to the third embodiment is applied to the manufacturing method of the semiconductor device 15 according to the second embodiment. The following components are in the second and illustrated, for example, in FIGS. 4A to 5B. The semiconductor device manufacturing method of the embodiment is formed in a substantially identical manner on a semiconductor substrate 10 (FIG. 17A): an isolation layer 12, a MOS transistor 24, and an interlayer insulating layer 26'-stop layer. a contact plug 35, an insulating 20 layer 36, an interlayer insulating layer 38, and an insulating layer 40. A wiring for forming a wiring 51 extending through the insulating layer 40, the interlayer insulating layer, and the insulating layer 36. The trench 46 is formed in substantially the same manner as the user of the semiconductor device manufacturing method of the second embodiment shown in Figs. 6A and 6B. 30 200921788 The damaged layer caused by the dry name is substantially the same as the user of the semiconductor device manufacturing method of the second embodiment shown in FIGS. 7A and 7B at the time of opening the wiring trench 46. The method is treated with a radiant compound and irradiated with - ultraviolet rays, thereby repairing the damaged layer (the repaired layer 116 shown in Figure 5B). A layer of nitride (lane) is deposited on the insulating layer 40 by, for example, a vacuum plating process, and has a thickness of, for example, 50 nm, thereby forming a barrier metal layer 48 which is simply formed. A layer of copper is deposited on the barrier metal layer 48 10 by, for example, a sputtering process to have a thickness of, for example, 10 nm, thereby forming a seed sublayer (not shown) made of Cu. The copper sublayer is deposited on the seed sublayer formed as a seed by, for example, an electroplating process, thereby forming a Cu layer 50 including the seed sublayer and having a thickness of, for example, 600 nm. The Cu layer 50 and the barrier metal layer 48 disposed on the insulating layer 40 are partially removed by a CMP process, whereby the wiring 51 is formed in the wiring trench 46. The wiring 51 includes a portion of the barrier metal layer 48 and a portion of the Cu layer 5, and the CVD process slurry is preferably formed according to a material for forming the g-line 51 or the insulating layer 40. select. In this polishing step, a damaged layer containing the 20 Si-OH is formed in the insulating layer 40. In the step of forming the wiring 51, an acidic or electrochemical solution for polishing is applied to the insulating layer 40 to bond in the insulating layer. The term "a physical or chemical action on the insulating layer" means a step of processing the insulating layer. The processing of the insulating layer is less than 31. The step of patterning the insulating layer, the step of removing the conductive layer on the insulating layer, and the step of partially removing the insulating layer by light. · On the "Heil insulating layer, dripping On the upper 3CC, such as hexamethyl bismuth sulphide, the sulphur is burned, and the insulating layer is spin-coated with 丨, 0001^111 for 60 seconds, and baked on a hot plate at l2〇C. 60 seconds; then baking at 25 ° C for 6 seconds. This allows the Si-OH generated in the insulating layer to be converted into Si-CHs by polishing in the formation of the wiring 51, thereby repairing the The destruction of the insulating layer 4 。. The method for repairing the damaged ceramsite compound and the method of using the sinter compound can be repaired in the insulating layer 202 as described in the semiconductor device manufacturing method of the third embodiment. The treatment method of the damaged layer 204 is the same. The semiconductor substrate is added in a nitrogen atmosphere. The insulating layer is irradiated with ultraviolet rays having a wavelength of, for example, 200 to 600 nm for about ten minutes by means of a high pressure mercury lamp (for example, 15 UVL-7000 H4-N obtained by Ushio Inc.) to, for example, 400 ° C (Fig. 18A). This allows Si-germanium remaining after repairing the damage with the * olefin compound to be condensed to form a <seven-altite bond, thereby preventing Si-OH from absorbing moisture. In this third embodiment The method and condition described above are used for light irradiation for shrinking 20-Si-OH and electron beam irradiation can be performed while illuminating the light described in the third embodiment. In the third embodiment The method and conditions described herein can be applied to electron beam irradiation. In a manner substantially the same as that of the user in the semiconductor device manufacturing method of the second embodiment shown in Figs. 8A to 9 An insulating layer 52, an interlayer insulating layer 54, and an insulating layer 60 (Fig. 18B) are formed on the insulating layer 4, which is not buried therein. In this embodiment, an insulating layer 60 is used. The interlayer insulating layer 54 and the insulating layer 52 constitute a three-layer structure. A structure including an insulating layer 56 as an etch stop may be used as described in the second embodiment. In this embodiment, the /g gate', the rim layer 54 may be a porous-oxidized layer having a thickness of, for example, 18 μm. The following pores and grooves are formed in substantially the same manner as in the semiconductor device manufacturing method of the second embodiment shown in the first (1) and the first embodiment. 10 slots, that is, a through hole 66 extending through the insulating layer 52 and the interlayer insulating layer 54 to the β-mining line 51, and a wiring 77b extending through the interlayer insulating layer 54 and the insulating layer 60 Wiring trench 72. In a manner substantially the same as that of the user in the semiconductor device manufacturing method of the second embodiment shown in FIGS. 7A and 7B, the treatment is performed with a decane compound 15 and the ultraviolet ray is used to form the via hole 66. The wiring trench 46 is damped by dry etching, thereby repairing the damaged layer (a repaired layer 116 shown in Fig. 19). A layer of TaN is deposited on the insulating layer 60 by, for example, a sputtering process to have a thickness of, for example, 1 〇 nm, and thereby form a barrier 2 〇 metal layer 74 made of TaN. A layer of copper is deposited on the barrier metal layer 74 by, for example, a sputtering process to have a thickness of, for example, 10 nm, thereby forming a seed sublayer (not shown) made of Cu. Copper is deposited on the sublayer formed as a seed crystal 33 I. 200921788 by, for example, an electroplating process, thereby forming a Cu layer 76 including the seed sublayer and having a thickness of, for example, 14 〇〇 nmi. The copper layer 76 and the barrier metal layer 74 disposed on the insulating layer 60 are partially removed by a CMP process, whereby a contact plug 77a and the wiring 77b are in a single-piece structure in the step of 5. The contact plug 77a is disposed in the through hole 66 and includes a portion of the barrier metal layer 74 and a portion of the copper layer 76, and the wiring 7 7 b is disposed in the wiring trench 7 2 and A portion of the barrier metal layer 74 and a portion of the copper layer 76 are included. The slurry for the CVD process is preferably selected depending on the material used to form the contact plug 77a and the wiring 77b or the material used to form the insulating layer 60, and in this polishing step, a Si-OH containing layer is selected. A fracture layer is formed in the insulating layer 6〇. On the insulating layer, 3 cc of a decane compound such as hexakisodiazane was dropped, and the insulating layer was spin-coated at 1,100 rpm for 6 seconds, for example, at 120 ° C on a hot plate. Bake on for 6 sec seconds; then bake at 6 〇 QCt for 6 〇 15 seconds. This allows Si to 〇H which is generated in the insulating layer by polishing in forming the contact plug 77a and the wiring 77b to be converted into Si-CH3, thereby repairing the destruction of the insulating layer 40. The treatment method for repairing the damage and the treatment method using the same can be used to repair the insulation layer 2〇2 in the semiconductor device manufacturing method of the third embodiment. The treatment method of the destruction layer 2〇4 is the same. The semiconductor substrate is heated to, for example, 400 C in a nitrogen atmosphere gas and a still-pressure mercury lamp (for example, UVL-7000 H4-N obtained by Ushio Inc.) to have, for example, 2 Å to 働 (10). The wavelength of ultraviolet light 34 200921788 illuminates the insulating layer for about ten minutes (Fig. 20). This allows the remaining Si-OH to be condensed after repairing the damage with the decanoate to form a bond 'and thus' prevents Si_〇H from absorbing moisture. The method and conditions described in the fourth embodiment can be applied to light irradiation for reducing Si-ΟΗ, and electron beam irradiation can be performed instead of the light irradiation described in the fourth embodiment. The method and conditions described in this fourth embodiment can be used for electron beam irradiation. By way of, for example, a CVD process, a layer of 匚. Ο : Η ' is deposited on the interlayer insulating layer to have a thickness of about 3 〇 nm, thereby forming an insulating layer 78 made of &匚:nw · Η 10 ( Figure 21). The same steps as those described above are repeated as needed to form a third wiring or the like which is not shown, thereby completing the semiconductor device of this embodiment. As described above, according to this embodiment, the dielectric constant of the insulating layers can be prevented from increasing in a manner of repairing the operational breakdown of the insulating layers. Further, 15 even if the insulating layers are placed in the air', the dielectric constant is prevented from increasing. This allows the insulating layers to have a low dielectric constant and high reliability, and therefore, if the insulating layers are applied to, for example, an interlayer insulating layer for a multilayer wiring structure, the response speed of a semiconductor device can be increased. [Fifth Embodiment] 20 Hereinafter, a method of manufacturing a semiconductor device according to a fifth embodiment will be described with reference to FIGS. 22 to 26, and any of the first to fourth embodiments shown in FIGS. 1 to 21 The same components or components described in the semiconductor device manufacturing method are denoted by the same symbols as those of the user herein, and will be simply described or will not be described. 35 200921788 Figures 22 to 26 are cross-sectional views showing the steps of the method of fabricating the semiconductor device of this embodiment. In this embodiment, an example will be explained in which a manufacturing method according to the third embodiment is applied to an example of a manufacturing method of the semiconductor device 5 according to the second embodiment. The following components are formed on a semiconductor substrate 10 (Fig. 22A) in the same manner as the user of the semiconductor device manufacturing method of the second embodiment illustrated in Figs. 4A to 5B: an isolation layer 12 An MOS transistor 24, an interlayer insulating layer 26, a stop layer, a contact plug 35, an insulating 10 layer 36, an interlayer insulating layer 38, and an insulating layer 40. A wiring trench 46 for forming a wiring 51 extending through the insulating layer 40, the interlayer insulating layer, and the insulating layer 36 is fabricated by a semiconductor device such as the second embodiment shown in FIGS. 6A and 6B. The methods are formed in substantially the same way as the users. 15 - the damaged layer due to dry etching in forming the wiring trench 46 is substantially the same as the user in the semiconductor device manufacturing method of the second embodiment shown in Figs. 7A and 7B, The damaged layer (a repaired layer 116 shown in Figure 22B) is repaired by treatment with a decane compound and irradiation with an ultraviolet ray. A layer of tantalum nitride (TaN) is deposited on the insulating layer 40 by, for example, a sputtering process, and has a thickness of, for example, 50 nm, thereby forming a barrier metal layer 48 made of TaN. A layer of copper is deposited on the barrier metal layer 48 by, for example, a sputtering process to have a thickness of, for example, 1 〇 nm, thereby forming a seed layer 36 200921788 (not shown) made of Cu. A copper sublayer is deposited on the seed sublayer formed as a seed by, for example, electroplating, whereby a Cu layer 5 having a thickness of, for example, 600 nm is formed. The Cu layer 50, the barrier metal layer 48, and the insulating layer 40 disposed on the interlayer insulating layer 38 are partially removed by a CMP process, whereby the wiring 51 is formed in the wiring trench 46. The wiring 51 includes a portion of the barrier metal layer 48 and a portion of the Cu layer 50. In this embodiment, the insulating layer 40 is removed in the polishing 10 step of forming the wiring 51. The insulating layer 40 is used as a hard mask for forming the wiring trench 46, and is typically made of a material having a dielectric constant greater than the dielectric constant of the material used to form the interlayer insulating layer 38. . In this embodiment, in order to make the interlayer insulating layer have a low dielectric constant, the insulating layer 40 is removed in the polishing step of forming the wiring 51. Since the insulating layer 40 is removed by polishing, a damaged layer containing Si-germanium is formed in the interlayer insulating layer 38 disposed under the insulating layer 40. In the same manner as the user in the semiconductor device manufacturing method of the fourth embodiment shown in FIG. 18B, 'the treatment with a decane compound and irradiation with an ultraviolet ray at the time of forming the wiring 51 is performed by polishing. The damaged layer is formed in the insulating layer 38 between the layers 20, thereby repairing the damaged layer (Fig. 23A). Since the insulating layer 40 is removed by polishing, the interlayer insulating layer 38 disposed under it is destroyed and thus the dielectric constant of the interlayer insulating layer 38 is increased. However, since the damage of the interlayer insulating layer 38 is repaired by the foregoing process 37 200921788, the dielectric constant of the interlayer insulating layer 38 can be prevented from increasing, and the insulating layer 40 can be removed so that the interlayer insulating layer can have a lower dielectric layer. Electric constant. An insulating layer 52 and a layer are formed on the interlayer insulating layer 38 having the wiring 51 embedded therein in substantially the same manner as the user of the semiconductor device manufacturing method of the third embodiment shown in FIG. 18A. An insulating layer 54 and an insulating layer 60 (Fig. 23B). In this embodiment, a three-layer structure composed of the insulating layer 60, the interlayer insulating layer 54, and the insulating layer 52 is used. Alternatively, a structure including an insulating layer 56 as an etching stopper may be used as described in the second embodiment. 10 forming the following holes and trenches in substantially the same manner as the user in the semiconductor device manufacturing method of the second embodiment shown in FIGS. 10 and 11 : that is, an extension through the insulating layer 52 and the interlayer The insulating layer 54 reaches the through hole 66 of the wiring 51, and a wiring trench 72 for forming a wiring 77b extending through the interlayer insulating layer 54 and the insulating layer 60. 15 is formed in a manner similar to that of the user in the semiconductor device manufacturing method of the second embodiment shown in FIGS. 12 and 13 by a monooxane compound and irradiated with an ultraviolet ray to form the via hole 6 6 The wiring trench 46 is a damaged layer resulting from dry etching, thereby repairing the damaged layer (a repaired layer 116 shown in Fig. 24). By depositing a layer of TaN on the insulating layer 60 to have a thickness of, for example, 1 〇 nm, and thereby forming a barrier metal layer 74 made of TaN. A layer of copper is deposited on the barrier metal layer 74 to have a thickness of, for example, 10 nm, for example, by a subtractive process, thereby forming a seed layer 38 200921788 sub-layer (not shown) made of Cu. Copper is deposited on the seed sublayer formed as a seed by, for example, an electroplating process, thereby forming a Cii layer 76 including the seed sublayer and having a thickness of, for example. 5 The copper layer 76 and the barrier metal layer 74 disposed on the insulating layer 60 are partially removed by a CMP process, whereby the contact plug 77a and the wiring 77b are in a single piece structure in one step. The contact plug 77a is disposed in the through hole 66 and includes a portion of the barrier metal layer 74 and a portion of the copper layer 76, and the wiring 77b is disposed in the wiring trench 72 and includes the barrier A portion of the gold 10 layer 74 and a portion of the copper layer 76. In this embodiment, the insulating layer 6 is removed in the polishing step of forming the contact plug 77a and the wiring 77b. The insulating layer 60 is used as a hard mask for forming the via 66 and the wiring trench 46, and is typically a dielectric having a dielectric constant greater than the material used to form the interlayer insulating layer 54. Often made of 15 materials. In this embodiment, in order to allow the interlayer insulating layer to have a low dielectric constant, the insulating layer 60 is removed in the polishing step of forming the contact plug 77a and the wiring 77b. Since the insulating layer 60 is removed by polishing, a damaged layer containing Si-OH is formed in the interlayer insulating layer 54 disposed under the insulating layer 60. 20 is treated with a decane compound and irradiated with an ultraviolet ray to form the contact plug 7 7 a in substantially the same manner as the user in the semiconductor device manufacturing method of the fourth embodiment shown in FIG. When the wiring 7 7 b is broken, a damaged layer is formed in the interlayer insulating layer 54 to repair the damaged layer (Fig. 25). 39 200921788 Since the insulating layer 60 is removed by polishing, the interlayer insulating layer 54 disposed thereunder is destroyed and thus the dielectric constant of the interlayer insulating layer 54 is increased. However, since the damage of the interlayer insulating layer 54 is repaired by the foregoing process, the dielectric constant of the interlayer insulating layer 54 can be prevented from increasing, and the insulating layer 60 can be removed so that the interlayer insulating layer can have a lower dielectric. constant. A layer sic is deposited on the interlayer insulating layer by, for example, a CVD process to have a thickness of about 30 nm, thereby forming an insulating layer 78 made of: 〇: η (Fig. 26). As described in the above, according to this embodiment, the dielectric constant of the insulating layers can be prevented from increasing by repairing the destruction of the insulating layers. Also, even. The insulating layer such as the hai is placed in the air to prevent its dielectric constant from increasing. Each of the insulating layers can have a low dielectric constant and high reliability. If the insulating layer of 4 is applied to, for example, the interlayer insulating layer for a multilayer wiring structure, the response speed can be increased. [Other Embodiments] The present invention is not limited to the semiconductor devices of the first and second embodiments and can be widely applied to various semiconductor layers including the ceria-based insulating layer. The thickness of the layers and the materials used to form them can vary within the scope of the invention. 20 [Example] [Example 1]

下化合物注入—200ml反應容器中：20 8§(01莫耳) 之四乙氧矽护 夫今J 莫耳）之縮疋'17.8g((U莫耳）之曱基三乙氧矽烷；23_6g(〇.l 尺甘油氧丙基三甲氧矽烷、及39 6g之曱基異丁 200921788 051。在該反應容器中，以10分鐘滴入；!6.2g(0.9莫耳）四甲基 氫氧化銨之1%水溶液。接著，對在該反應容器中之混合物 進行熟化反應兩小時。 在使用5g之硫酸鎂由該反應混合物中移除過量之水 5後，由該反應混合物中移除由該熟化反應所產生之乙醇， 使得該反應混合物之體積減少至5〇ml。對所得到之反應混 合物，添加20ml之曱基異丁酮，藉此製備一含有一多孔質 二氧化石夕前驅物之塗布溶液。 藉一旋塗製程將該含有多孔質二氧化矽前驅物之塗布 10溶液塗布在-低電阻基板上，且該低電阻基板在25〇〇c下被 預烘烤三分鐘並接著以FT-IR光譜儀加以分析。在大約 95(W ’由Si_0H基之吸收強度所計算出之該低電阻基板 之塗層的交聯程度為75%。 藉-旋塗製程將該含有多孔質二氧化石夕前驅物之塗布 15溶液塗布在-石夕基板300上，使得該含有多孔f二氧化石夕前 驅物之塗布溶液具有大約4〇〇nm之厚度。 在2實，將塗布有該含有多孔質二氡切前驅物之塗 布溶液之矽基板300預烘烤三分鐘。 接著’於-具有氮環境氣體之電爐中，以4〇〇〇c將在該 如預輯⑦基板上之含有多孔質二氧切祕物之塗布 溶液硬化30分鐘，藉此形成一二氧化石夕基多孔質絕緣層 302 ’如第27A圖所示。 該二氧化石夕基多孔質絕緣層302係利用一 CHF3與CF4 之氣體混合物以一 RIE蝕刻機在以下條件卞進行乾钮刻： 200921788 50sccm之CHF3流量、lOOsccm之CF4流量、50mTorr之室壓、 及200W之功率。這使該二氧化矽基多孔質絕緣層302之厚 度可減少至大約2〇〇nm，且亦使一被破壞層304可形成於其 上，如第27B圖所示。 5 將3cc之六甲基二矽氮烷滴在該被破壞層304上，再以 1，000rpm對該被破壞層304進行旋塗60秒。 利用一熱板在120°C將該矽基板300烘烤60秒鐘且在 250°C再烘烤60秒鐘’藉此製備該被破壞層3〇4且因此在該 二氧化矽基多孔質絕緣層302上形成一已修復層306，如第 10 27C圖所示。 如第27D圖所示，以該矽基板300在一氮環境氣體中被 加熱至400°C之方式’利用一由Ushio Inc.取得之UVL-7000 H4-N咼壓水銀燈，以一具有2〇〇至6〇〇nm之波長的紫外線照 射該二氧化矽基多孔質絕緣層3〇2十分鐘。 15 在各步驟及暴露於空氣一星期後，以一水銀探針測量 s玄一氧化石夕基多孔質絕緣層302之電容，且由其電容計算該 二氧化矽基多孔質絕緣層302之介電常數。計算之結果係摘 錄於表1中。 如表1中所示，剛形成之二氧化矽基多孔質絕緣層3〇2 20具有2.24之介電常數。由於存在有該被破壞層304，其介電 常數會因乾钮刻該二氧化石夕基多孔質絕緣層3〇2而增加，使 得乾蝕刻後之二氧化矽基絕緣層3〇具有2 86之介電常數。 藉以該矽烷化合物處理該乾蝕刻後之二氧化矽基多孔質絕 緣層302，減少该一氧化矽基多孔質絕緣層3〇2之介電常 42 200921788 數，但並未回到其初始值。處理後之二氧化矽基多孔質絕 緣層302具有2.36之介電常數，且該處理後之二氧化矽基多 孔貝％緣層302之介電常數再藉以紫外線照射乾蝕刻後之 一氡化矽基多孔質絕緣層3〇2來減少，使得被照射後之二氧 化石夕基多孔質絕緣層3〇2具有2 26之介電常數。暴露於空氣 一星期後之二氧化矽基多孔質絕緣層3〇2具有2 25之介電 常數。 [例2] 10 15 以，、例1中所述者實質相同之方式製備一評價樣本，但 所進行的是電子束照射而非如第27D圖所示般地以紫外線 照射。在製備該評價樣本時，以在真$中將一絲板加熱 至400°C之方式，以-具有碰v之加速電壓的電子束照射一 乾蝕刻後之一氧化矽基多孔質絕緣層丨分鐘。 在各步驟及暴露於空氣—星期後，以一水銀探針測量 該二氧化矽基多孔質絕緣層之電容，且 氧化石夕基多孔質絕緣層之介電常數。計算:結果係摘= 表1中。 如表1中所示，剛形成之二氧化石夕基多孔質絕緣層具有 2.24之介電常數。由於存在有_被錢層，其介電常數會 因乾蚀刻該二氧化石夕基多孔質絕緣層而增加，使得乾蚀刻 後之二氧化石夕基絕緣層具有2.86之介電常數。藉以該石夕院 化合物處理該乾蚀刻後之二氧化石夕基多孔質絕緣層，減少 該二氧化石夕基多孔質絕緣層之介電常鼓，但並未回到其初 始值。處理後之二氧化石夕基多孔質絕緣層具有η之介電 43 200921788 常數，且該處理後之二氧化矽基多孔質絕緣層之介電常數 再藉以電子束照射該乾蝕刻後之二氧化矽基多孔質絕緣層 302來減少，使得被照射後之二氧化矽基多孔質絕緣層具有 2.28之介電常數。暴露於空氣一星期後之二氧化矽基多孔 5 質絕緣層具有2.26之介電常數。 [比較例1 ] 以與例1或2中所述者實質相同之方式製備一評價樣 本，但未進行如第27D圖所示之紫外線或電子束照射。 在各步驟及暴露於空氣一星期後，以一水銀探針測量 10 該評價樣本之二氧化矽基多孔質絕緣層之電容，且由其電 容計算該二氧化矽基多孔質絕緣層之介電常數。計算之結 果係摘錄於表1中。 如表1中所示，剛形成之二氧化矽基多孔質絕緣層具有 2.24之介電常數。由於存在有一被破壞層，其介電常數會 15 因乾蝕刻該二氧化矽基多孔質絕緣層而增加，使得乾蝕刻 後之二氧化矽基絕緣層具有2.86之介電常數。藉以該矽烷 化合物處理該乾蝕刻後之二氧化矽基多孔質絕緣層，減少 該二氧化矽基多孔質絕緣層之介電常數，但並未回到其初 始值，且處理後之二氧化矽基多孔質絕緣層具有2.36之介 20 電常數。 該處理後之二氧化矽基多孔質絕緣層暴露於空氣一星 期，但未對該處理後之二氧化矽基多孔質絕緣層照射紫外 線或電子束。所得之二氧化矽基多孔質絕緣層具有2.52之 介電常數。 44 200921788 [表i] 製程 介電常數 例1 例2 比較例1 剛形成之二氧 化矽基多孔質 絕緣層 2.24 2.24 2.24 剛乾蝕刻後 2.86 2.86 2.86 以矽烷化合物 剛處理後 2.36 2.36 2.36 以紫外線剛照 射後 2.26 以電子束剛照 射後 2.28 - 在暴露於空氣 一星期後 2.25 2.26 2.52 [例3] 依據該第二實施例之方法製造一半導體裝置。特別 地，該半導體裝置之第二與第三配線係在相同之製程條件 5 下形成。 利用該半導體裝置之多層配線測量一百萬通孔之產 率，使得所測得之產率為91%，且由該層間電容所測得之 一層間絕緣層之有效介電常數是2·60。在該半導體裝置以 200°C在高溫下儲存1,000小時後，測量該半導體裝置之配線 10 電阻，且測量結果顯示其配線電阻沒有增加。 [例4] 藉與在例3中所述者實質相同之方法製造一半導體裝 置，但在以該矽烷化合物修復破壞後於一氦環境氣體中進 行紫外線照射。特別地，以一基板在一氦環境氣體中被加 15 熱至400°C之方式，利用一由Ushio Inc.取得之UVL-7000 45 200921788 H4_N高壓水銀燈，以一具有200至600nm之波長的紫外線照 射其破壞被修復之絕緣層十分鐘。 利用該半導體裝置之多層配線測量一百萬通孔之產 率，使得所測得之產率為94%，且由該層間電容所測得之 5 一層間絕緣層之有效介電常數是2.58。在該半導體裝置以 - 200°C在高溫下儲存1，〇〇〇小時後，測量該半導體裝置之配線 電阻’且測量結果顯示其配線電阻沒有增加。 [例5] 藉與在例3中所述者實質相同之方法製造一半導體裝 10置’但在以該矽烷化合物修復破壞後於一氬環境氣體中進 .行紫外線照射。特別地，以一基板在一氬環境氣體中被加 熱至400°C之方式，利用一由Ushio Inc.取得之UVL-7000 H4-N高壓水銀燈，以一具有2〇〇至6〇〇11111之波長的紫外線照 射其破壞被修復之絕緣層十分鐘。 15 利用該半導體裝置之多層配線測量一百萬通孔之產 率，使得所測得之產率為93%，且由該層間電容所測得之 一層間絕緣層之有效介電常數是2.61。在該半導體裝置以 200°C在高溫下儲存1 ,〇〇〇小時後，測量該半導體裝置之配線 電阻，且測量結果顯示其配線電阻沒有增加。 20 [例 6] 藉與在例3中所述者實質相同之方法製造一半導體裝 置，但在以該矽烷化合物修復破壞後於一真空中進行紫外 線照射。特別地，以一基板在一真空中被加熱至400°C之方 式，利用一由Ushio Inc.取得之UVL-7000 H4-N高壓水銀 46 200921788 燈，以一具有200至600nm之波長的紫外線照射其破壞被修 復之絕緣層十分鐘。 利用該半導體裝置之多層配線測量一百萬通孔之產 率，使得所測得之產率為96%，且由該層間電容所測得之 5 一層間絕緣層之有效介電常數是2.52。在該半導體裝置以 200°C在高溫下儲存1,000小時後，測量該半導體裝置之配線 電阻，且測量結果顯示其配線電阻沒有增加。 [例7] 藉與在例3中所述者實質相同之方法製造一半導體裝 10 置，但在以該矽烷化合物修復破壞後進行電子束照射而非 紫外線照射。特別地，以一基板在一真空中被加熱至400°C 之方式，以一具有10kV之加速電壓的電子束照射一絕緣層1 分鐘。 利用該半導體裝置之多層配線測量一百萬通孔之產 15 率，使得所測得之產率為90%，且由該層間電容所測得之 一層間絕緣層之有效介電常數是2.63。在該半導體裝置以 200°C在高溫下儲存1，000小時後，測量該半導體裝置之配線 電阻，且測量結果顯示其配線電阻沒有增加。 [比較例2] 20 藉與在例3中所述者實質相同之方法製造一半導體裝 置，但未進行以矽烷化合物修復破壞、光照射、及電子束 照射。 利用該半導體裝置之多層配線測量一百萬通孔之產 率，使得所測得之產率為72%，且由該層間電容所測得之 47 200921788 -層間絕緣層之有效介電常數是2.96。在該半導體裝置以 200 C在^下儲存小時後’測量解導體裝置之配線 電阻’且測量結果顯示有概之通孔之配線電阻增加。 [比較例3] 曰 以藉在例3中所述之製程相同之方法以石夕烧化合物但 未進以照射或電子束照射來修復破壞之方式，製造一丰 導體裝置。 + 利用該半導體裝置之多層配線測量—百萬連續通孔之 產率，使得所測得之產率為81%，且由該層間電容所測得 H)之-層間絕緣層之有效介電常數是2 82。在該半導體裝置 以200。^冑溫預存丨，_、賴，㈣ 線電阻，且測量結果顯示有㈣之通孔之電 =配 [例8] 將以下化合物注入一200ml反應容器中：2〇柳」莫耳) 之四乙氧石夕烧、莫耳)之甲基三乙氧石夕烧；23摊】 莫耳）之縮水甘油氧丙基三甲氧魏、及39却之甲基異丁 酮。在該反應容器中，以10分鐘滴入162g(〇9莫耳)四甲基 氯氧化銨之1%水溶液。在滴入完成後，進行熟化兩小時: 在使用5g之硫酸鎂由該反應液體中移除過量之水後， 2〇在一旋轉蒸發器中由該反應液體移除因熟化所產生之乙 醇’使得該反應液體之體積減少至5〇ml。對該濃縮反應液 體’添加2_之甲基異丁酮，藉此製備一用以形成一配線 隔離層之多孔質二氧化矽前驅物塗布溶液。 藉-旋塗製程將該多孔質二氧化石夕前驅物塗布溶液塗 48 200921788 布在一低電阻基板上，且接著在250。(：下預烘烤三分鐘。以 FT-IR由一集中在950cm-1、對應於基之吸收峰所測定 之該多孔質二氧化矽前驅物塗布溶液的交聯程度為75%。 藉一旋塗製程將該多孔質二氧化矽前驅物塗布溶液塗 5布在一由矽製成之底基板200上，以具有40〇nm之厚度。 在250°C，將設置在該底基板2〇〇上之多孔質二氧化矽 前驅物塗布溶液層預烘烤三分鐘。 接著，於一具有氮環境氣體之電爐中，以4〇〇〇c將在該 預洪烤後之多孔質二氧化矽前驅物塗布溶液硬化30分鐘， 10藉此形成一二氧化矽基多孔質絕緣層202(見第16A圖）。 該二氧化矽基多孔質絕緣層202係利用化學機械拋光 (CMP)裝置拋光。這使該二氧化矽基多孔質絕緣層2〇2之厚 度可減少，且使一被破壞層2〇4可形成於其上（見第16B圖）。 以虱氟酸之0.5%水溶液清潔該被搬光之二氧化石夕基多 15 孔質絕緣層202。 將3cc之六甲基二矽氮烷滴在該被拋光之二氧化矽基 多孔質絕緣層202上’且以丨000rpm對該二氧化矽基多孔質 絕緣層202進行旋塗60秒。 在一熱板上以120°C將該二氧化矽基多孔質絕緣層2〇2 20烘烤60秒鐘且以250°c再烘烤60秒鐘，這使該被破壞層204 可被修復，藉此在該二氧化矽基多孔質絕緣層202上形成一 已修復層206(見第16C圖）。 以該基板在一氮環境氣體中被加熱至4〇〇。(：之方式，利 用一高壓水銀燈（由Ushio lnc.取得之uVL-7000 H4-N)，以 49 200921788 一具有200至600nm之波長的紫外線照射該二氧化矽基多孔 質絕緣層202十分鐘（第16圖）。 [例9] 以與例8中所述者實質相同之方式製備一評價樣本，但 5 在第16D圖所示之步驟中所進行的是電子束照射而非光照 射。特別地，以在真空中將一基板加熱至400°C之方式，以 一具有10kV之加速電壓的電子束照射二氧化矽基多孔質絕 緣層1分鐘。 表2節錄在各步驟及置於空氣一星期後，該二氧化矽基 10 多孔質絕緣層之介電常數，且該介電常數係由以一水銀探 針測定之電容計算而得。 如表2中所示，剛形成之二氧化矽基多孔質絕緣層202 具有2.24之介電常數。拋光這層會形成一被破壞層204，使 其介電常數增加至3.12。以該矽烷化合物修復該被破壞層 15 使其介電常數減少至2.39 ;但是，其介電常數並未回到其 初始值。以該矽烷化合物處理且接著以紫外線照射後之二 氧化矽基多孔質絕緣層202具有接近其初始值之介電常數 2.25，且置於空氣一星期後之二氧化矽基多孔質絕緣層202 具有2.26之介電常數。 20 [比較例4] 以與例8或9中所述者實質相同之方式製備一評價樣 本，但未進行如第16D圖所示步驟中之紫外線或電子束照 射。 表2節錄在各步驟中處理及置於空氣一星期後之二氧 50 200921788 化矽基多孔質絕緣層之介電常數，且該介電常數係由以一 水銀探針測定之電容計算而得。 如表2中所示，剛形成之二氧化矽基多孔質絕緣層具有 2.24之介電常數。拋光這層會形成一被破壞層204，使其介 5 電常數增加至3.12。以該矽烷化合物修復該被破壞層使其 介電常數減少至2.39 ;但是，其介電常數並未回到其初始 值。未以光或紫外線照射且置於空氣一星期後之二氧化矽 基多孔質絕緣層具有2.55之介電常數。 [表2] 製程 介電常數 例1 例2 比較例1 剛形成之二氧 化矽基多孔質 絕緣層 2.24 2.24 2.24 剛拋光後 3.12 3.12 3.12 以矽烷化合物 剛處理後 2.39 2.39 2.39 以紫外線剛照 射後 2.25 - - 以電子束剛照 射後 - 2.25 - 在暴露於空氣 一星期後 2.25 2.26 2.55 10 [例 10] 以與例8中所述者實質相同之方式製備多數評價樣 本，但在第16D圖所示之步驟中照射光時熱處理之溫度改 變。特別地，以該等評價樣本各在30°C、60°C、100°C、 150°C、200°C、250°C、300°C、350°C、或400°C加熱之方 15 式，以光照射該等評價樣本。 51 200921788 表3節錄剛形成及置於空氣一星期後之評價樣本 _ 氧化矽基多孔質絕緣層之介電常數，且該介電常數係由以 一水銀探針測定之電容計算而得。 如表3中所示，剛形成之評價樣本之二氧化矽基多孔質 5絕緣層2〇2具有2.24至2.26之介電常數。置於空氣—星期後 之二氧化矽基多孔質絕緣層202 ’以及剛形成者具有2 至 2.26之低介電常數。 [例 11] 10 15 20 以與例9中所述者實質相同之方式製備多數評價樣 本，但在第16D圖所示之步驟中照射電子束時熱處理之;田声 改變。特別地’以該等評價樣本各在30°C、60DC、 150〇C、200°C、250°C、300X、350〇C、或400T加熱之方 式，以光照射該等評價樣本。 表3節錄剛形成及置於空氣—星期後之評價樣本之 氧化矽基多孔質絕緣層之介電常數，且該介電常數係由f 一水銀探針測定之電容計算而得。 Μ 如表3中所示，剛形成之評價樣本之二氧化石夕基多 絕緣層202具有2·24至2.26之介電常數。置於空氣—星期^ 之二氧财基多孔質絕緣層202，以及剛形成者具有=後 2.26之小介電常數。 1 [比較例5] 以與例1G或11巾所述者實質相同之方式製備評價樣 本’但未進妙第16D圖所示步驟中之紫外線或電子束照 射。 '、、、 52 200921788 表3節錄在各步驟中處理及置於空氣一星期後之二氧 化矽基多孔質絕緣層之介電常數，且該介電常數係由以一 水銀探針測定之電容計算而得。 如表3中所示，剛形成之評價樣本之二氧化矽基多孔質 5 絕緣層202具有2.34至2.39之介電常數。即，剛形成之評價 樣本之二氧化矽基多孔質絕緣層202之介電常數大於在進 行光或電子束照射之例10或11中所述之介電常數。置於.空 氣一星期後之二氧化矽基多孔質絕緣層202具有2.52至2.56 之大介電常數。 10 [例 12] 依據第四實施例之半導體裝置製造方法形成一第三配 線層及其他構件。在乾蝕刻與拋光後以一矽烷化合物修復 破壞後，在一氮環境氣體中進行紫外線照射。該第三配線 層係在與用以形成一第二配線層者實質相同之製程條件下 15 形成。 利用在如前述般製成之半導體裝置中之多層配線測量 一百萬連續通孔之產率，這顯示該等通孔之產率是91%， 且由該層間電容所測得之一層間絕緣層之有效介電常數是 2.60。該半導體裝置在200°C下放置1000小時且接著測量配 20 線電阻，這顯示其電阻未增加。 53 200921788 [表3] 介電常數 熱處理 例10 例11 比較例5 溫度 放置在 放置在 放置在 [°C] 剛形成 空氣中 剛形成 空氣中 剛形成 空氣中 一星期 一星期 一星期 30 2.26 2.26 2.25 2.25 2.39 2.55 60 2.26 2.26 2.25 2.25 2.38 2.54 100 2.25 2.25 2.24 2.26 2.28 2.56 150 2.26 2.25 2.26 2.25 2.36 2.55 200 2.25 2.26 2.25 2.26 2.37 2.55 250 2.26 2.24 2.25 2.25 2.35 2.53 300 2.24 2.26 2.25 2.24 2.35 2.52 350 2.25 2.25 2.24 2.25 2.36 2.53 400 2.25 2.24 2.25 2.25 2.34 2.52 [例 13] 以與例12中所述者實質相同之製程製造一半導體裝 置，但在乾蝕刻與拋光後以矽烷化合物修復破壞後，於一 5 氦環境氣體中進行紫外線照射。特別地，在修復破壞後， 以利用一高壓水銀燈（由Ushio Inc·取得之UVL-7000 H4-N)，以一具有200至600nm之波長的紫外線照射一層十 分鐘且該基板在氦環境氣體中被加熱至400°C之方式，進行 紫外線照射。 10 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是94%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.58。 該半導體裝置在20 0° C下放置10 0 0小時且接著測量配線電 阻，這顯示其電阻未增加。 15 [例 14] 以與例12中所述者實質相同之製程製造一半導體裝 54 200921788 置，但在乾蝕刻與拋光後以矽烷化合物修復破壞後，於一 氬*環境氣體中進行紫外線照射。特別地，在修復破壞後， 以利用一南壓水銀燈（由Ushio inc.取得之UVL-7000 H4_N)，以一具有200至600nm之波長的紫外線照射一層十 5分鐘且該基板在氬環境氣體中被加熱至400。(：之方式，進行 紫外線照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是93%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2 61。 10該半導體裝置在200°C下放置1 〇〇〇小時且接著測量配線電 阻，這顯示其電阻未增加。 [例 15] 以與例12中所述者實質相同之方式製造一半導體裝 置’但在乾蝕刻與拋光後以矽烷化合物修復破壞後，於真 15 空中進行紫外線照射。特別地，在修復破壞後，以利用一 高壓水銀燈（由Ushio Inc.取得之UVL-7000 H4-N)，以一具 有200至600nm之波長的紫外線照射一層十分鐘且該基板在 真空中被加熱至400°C之方式，進行紫外線照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 2〇 連續通孔之產率，這顯示該等通孔之產率是96%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.52。 該半導體裝置在200°C下放置1000小時且接著測量配線電 阻，這顯示其電阻未增加。 [例 16] 55 200921788 藉與在例12中所述者實質相同之製程製造一半導體裝 置，但在以該矽烷化合物修復破壞後進行電子束照射而非 紫外線照射。特別地，以一基板在一真空中被加熱至400°C 之方式，以一具有10kV之加速電壓的電子束照射一層1分 5 鐘。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是90%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.63。 該半導體裝置在200°C下放置1000小時且接著測量配線電 10 阻，這顯示其電阻未增加。 [比較例6] 藉與在例12中所述者實質相同之製程製造一半導體裝 置，但未以矽烷化合物修復破壞，或未進行光或電子束照 射。 15 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是72%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.82。 該半導體裝置在200°C下放置1000小時且接著測量配線電 阻，這顯示有45%之通孔之配線電阻增加。 20 [比較例7] 藉與在例12中所述者實質相同之製程製造一半導體裝 置，但以矽烷化合物修復破壞，且未進行光或電子束照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是81%，且由該 56 200921788 層間電容所測得之一層間絕緣層之有效介電常數是2.82。 5亥半導體裝置在2〇〇。(：下放置10〇〇小時且接著測量配線電 阻’這顯示有18%之通孔之配線電阻增加。 [例 17] 5 依據第五實施例之半導體裝置製造方法形成一第三配 線層及其他構件。在乾蝕刻與拋光後以一矽烷化合物修復 破壞後’在一氮環境氣體中進行紫外線照射。該第三配線 θ係在與用以形成一第二配線層者實質相同之製程條件下 形成。 1〇 利用在如前述般製成之半導體裝置中之多層配線測量 ~~百萬連續通孔之產率，這顯示該等通孔之產率是94%， 且由該層間電容所測得之一層間絕緣層之有效介電常數是 2.49。該半導體裝置在200°C下放置1000小時且接著測量配 線電阻’這顯示其電阻未增加。 15 [例 18] 以與例17中所述者實質相同之製程製造一半導體裝 置’但在乾蝕刻與拋光後以矽烷化合物修復破壞後，於一 氮環境氣體中進行紫外線照射。特別地，在修復破壞後， 以利用一高壓水銀燈（由Ushio Inc.取得之UVL-7000 20 H4-N)，以一具有2〇〇至600nm之波長的紫外線照射一層十 分鐘且該基板在氦環境氣體中被加熱至4〇(TC之方式，進行 紫外線照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是96%，且由該 57 200921788 層間電容所測得之一層間絕緣層之有效介電常數是2.47。 該半導體裝置在200°C下放置1 〇〇〇小時且接著測量配線電 阻’這顯示其電阻未增加。 [例 19] 5 以與例17中所述者實質相同之製程製造一半導體裝 置’但在乾敍刻與拋光後以石夕烧化合物修復破壞後，於一 氬環境氣體中進行紫外線照射。特別地，在修復破壞後， 以利用一高壓水銀燈（由Ushio lnc·取得之UVL-7000 H4-N)，以一具有200至600nm之波長的紫外線照射一層十 10分鐘且該基板在氬環境氣體中被加熱至4〇〇°C之方式，進行 紫外線照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是97%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2 47。 15該半導體裝置在2〇〇°C下放置1 〇〇〇小時且接著測量配線電 阻’這顯示其電阻未增加。 [例 20] 以與例17中所述者實質相同之方式製造一半導體裝 置，但在乾蝕刻與拋光後以矽烷化合物修復破壞後，於真 20空中進行紫外線照射。特別地，在修復破壞後，以利用一 咼壓水銀燈（由Ushio Inc.取得之UVL_7〇〇〇 h4_n)，以一具 有200至600nm之波長的紫外線照射一層十分鐘且該基板在 真空中被加熱至400°C之方式’進行紫外線照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 58 200921788 連續通孔之產率，這顯示該等通孔之產率是95%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.46。 該半導體裝置在200°C下放置1000小時且接著測量配線電 阻，這顯示其電阻未增加。 5 [例 21] 藉與在例17中所述者實質相同之製程製造一半導體裝 置，但在以該矽烷化合物修復破壞後進行電子束照射而非 紫外線照射。特別地，以一基板在一真空中被加熱至400°C 之方式，以一具有10kV之加速電壓的電子束照射一層1分 10 鐘。 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是93%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.47。 該半導體裝置在200°C下放置1000小時且接著測量配線電 15 阻，這顯示其電阻未增加。 [比較例8] 藉與在例17中所述者實質相同之製程製造一半導體裝 置，但未以矽烷化合物修復破壞，或未進行光或電子束照 射。 20 利用在所製成之半導體裝置中之多層配線測量一百萬 連續通孔之產率，這顯示該等通孔之產率是65%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.76。 該半導體裝置在200°C下放置1000小時且接著測量配線電 阻，這顯示有58%之通孔之配線電阻增加。 59 200921788 [比較例9] 藉與在例17中所述者實質相同之製程製造一半導體裝 置，但以矽烷化合物修復破壞，且未進行光或電子束照射。 利用在所製成之半導體裝置中之多層配線測量一百萬 5 連續通孔之產率，這顯示該等通孔之產率是67%，且由該 層間電容所測得之一層間絕緣層之有效介電常數是2.75。 該半導體裝置在200°C下放置1000小時且接著測量配線電 阻，這顯示有26%之通孔之配線電阻增加。 【圖式簡單說明3 10 第1圖是一流程圖，顯示第一實施例之半導體裝置之製 造方法； 第2A至2C圖是截面圖，顯示第一實施例之方法的步 驟； 第3A至3C圖是截面圖，顯示第一實施例之方法的步 15 驟； 第4A至4C圖是截面圖，顯示第二實施例之方法的步 驟； 第5A與5B圖是截面圖，顯示第二實施例之方法的步 驟； 20 第6A與6B圖是截面圖，顯示第二實施例之方法的步 驟； 第7A與7B圖是截面圖，顯示第二實施例之方法的步 驟； 第8A與8B圖是截面圖，顯示第二實施例之方法的步 60 200921788The following compound is injected into a 200 ml reaction vessel: 20 8 § (01 mol) of tetraethoxy oxime, the current J 莫 之 疋 '17.8 g ((U Moer) decyl triethoxy decane; 23_6 g (〇.l glycerol oxypropyltrimethoxy decane, and 39 6g of decyl isobutyl 200921788 051. In this reaction vessel, drip in 10 minutes; !6.2g (0.9 mol) tetramethylammonium hydroxide a 1% aqueous solution. Next, the mixture in the reaction vessel is subjected to a ripening reaction for two hours. After the excess water 5 is removed from the reaction mixture using 5 g of magnesium sulfate, the ripening is removed from the reaction mixture. The ethanol produced by the reaction is reduced to a volume of 5 〇ml. To the obtained reaction mixture, 20 ml of decyl isobutyl ketone is added, thereby preparing a porous silica dioxide precursor. Coating solution: The coating 10 solution containing the porous ceria precursor is coated on a low-resistance substrate by a spin coating process, and the low-resistance substrate is prebaked at 25 ° C for three minutes and then Analysis by FT-IR spectrometer at about 95 (W' absorption by Si_0H group The degree of crosslinking of the coating of the low-resistance substrate calculated by the degree is 75%. The coating 15 solution containing the porous silica dioxide precursor is coated on the Shishi substrate 300 by a spin coating process. The coating solution containing the porous f-earth dioxide precursor has a thickness of about 4 Å. In 2, the ruthenium substrate 300 coated with the coating solution containing the porous bismuth-cut precursor is prebaked for three minutes. Then, in a furnace with a nitrogen atmosphere gas, the coating solution containing the porous dioxic material on the substrate as described in the pre-set 7 is hardened for 30 minutes at 4 〇〇〇c, thereby forming a dioxide. The Shishiji porous insulating layer 302' is as shown in Fig. 27A. The silica-based porous insulating layer 302 is dry-engraved by a RIE etching machine using a gas mixture of CHF3 and CF4 under the following conditions: 200921788 50sccm CHF3 flow rate, lOOsccm CF4 flow rate, 50mTorr chamber pressure, and 200W power. This makes the thickness of the cerium oxide-based porous insulating layer 302 can be reduced to about 2 〇〇 nm, and also destroyed. a layer 304 can be formed thereon, Figure 27B shows: 5 cc of hexamethyldioxane is dropped onto the damaged layer 304, and the damaged layer 304 is spin-coated at 1,000 rpm for 60 seconds. Using a hot plate at 120 ° C baking the tantalum substrate 300 for 60 seconds and baking at 250 ° C for 60 seconds ' thereby preparing the damaged layer 3〇4 and thus forming a layer on the ceria-based porous insulating layer 302 The repair layer 306 is as shown in Fig. 10 27C. As shown in Fig. 27D, the UV substrate 750 obtained by Ushio Inc. is used in such a manner that the ruthenium substrate 300 is heated to 400 ° C in a nitrogen atmosphere. The H4-N pressure mercury lamp irradiated the ceria-based porous insulating layer with ultraviolet rays having a wavelength of from 2 Å to 6 Å for 3 Torr for 10 minutes. 15 After each step and one week after exposure to air, the capacitance of the smectite-based porous insulating layer 302 is measured by a mercury probe, and the capacitance of the ceria-based porous insulating layer 302 is calculated from the capacitance thereof. Electric constant. The results of the calculations are summarized in Table 1. As shown in Table 1, the newly formed cerium oxide-based porous insulating layer 3 〇 2 20 has a dielectric constant of 2.24. Due to the presence of the damaged layer 304, the dielectric constant thereof is increased by the dry button engraving the dioxide-based porous insulating layer 3〇2, so that the dry-etched ceria-based insulating layer 3 has 2 86 Dielectric constant. By treating the dry-etched ceria-based porous insulating layer 302 with the decane compound, the dielectric constant of the ceria-based porous insulating layer 3〇2 is reduced, but the initial value is not returned. The treated ceria-based porous insulating layer 302 has a dielectric constant of 2.36, and the dielectric constant of the treated ceria-based porous shell-% edge layer 302 is further dried by ultraviolet irradiation. The base porous insulating layer 3 〇 2 is reduced so that the irradiated SiO 2 夕-based porous insulating layer 3 〇 2 has a dielectric constant of 2 26 . The cerium oxide-based porous insulating layer 3 〇 2 after exposure to air for one week has a dielectric constant of 2 25 . [Example 2] 10 15 An evaluation sample was prepared in substantially the same manner as described in Example 1, except that electron beam irradiation was performed instead of ultraviolet irradiation as shown in Fig. 27D. In the preparation of the evaluation sample, one of the yttrium oxide-based porous insulating layers after the dry etching was irradiated with an electron beam having an acceleration voltage of v in a manner of heating a filament plate to 400 ° C in true $ for Min. After each step and exposure to air - week, the capacitance of the ceria-based porous insulating layer and the dielectric constant of the oxidized oxide-based porous insulating layer were measured with a mercury probe. Calculation: Results are extracted = Table 1. As shown in Table 1, the newly formed SiO 2 octagonal porous insulating layer had a dielectric constant of 2.24. Since there is a layer of _ 被, the dielectric constant thereof is increased by dry etching the SiO 2 octagonal porous insulating layer, so that the dry etched SiO 2 基 insulating layer has a dielectric constant of 2.86. The dry-etched ruthenium oxide-based porous insulating layer was treated with the Shi Xiyuan compound to reduce the dielectric normal drum of the SiO-based porous insulating layer, but did not return to its initial value. The treated dioxide-based porous insulating layer has a dielectric constant of η 43 200921788, and the dielectric constant of the treated cerium oxide-based porous insulating layer is further irradiated by electron beam irradiation after the dry etching. The ruthenium-based porous insulating layer 302 is reduced so that the erbium oxide-based porous insulating layer after irradiation has a dielectric constant of 2.28. The ceria-based porous insulating layer after exposure to air for one week had a dielectric constant of 2.26. [Comparative Example 1] An evaluation sample was prepared in substantially the same manner as described in Example 1 or 2, but ultraviolet or electron beam irradiation as shown in Fig. 27D was not performed. After each step and one week after exposure to air, the capacitance of the ceria-based porous insulating layer of the evaluation sample was measured by a mercury probe, and the dielectric of the ceria-based porous insulating layer was calculated from the capacitance thereof. constant. The results of the calculation are summarized in Table 1. As shown in Table 1, the newly formed ceria-based porous insulating layer had a dielectric constant of 2.24. Since there is a damaged layer, the dielectric constant thereof is increased by dry etching the ceria-based porous insulating layer, so that the dry-etched ceria-based insulating layer has a dielectric constant of 2.86. The dry-etched ceria-based porous insulating layer is treated with the decane compound to reduce the dielectric constant of the ceria-based porous insulating layer, but does not return to its initial value, and the treated cerium oxide The base porous insulating layer has a dielectric constant of 2.36. The treated cerium oxide-based porous insulating layer was exposed to air for one week, but the treated cerium oxide-based porous insulating layer was not irradiated with ultraviolet rays or electron beams. The obtained ceria-based porous insulating layer had a dielectric constant of 2.52. 44 200921788 [Table i] Process permittivity example 1 Example 2 Comparative example 1 Just formed ruthenium oxide based porous insulation layer 2.24 2.24 2.24 Immediately after dry etching 2.86 2.86 2.86 Immediately after treatment with decane compound 2.36 2.36 2.36 2.26 after irradiation 2.28 after electron beam irradiation - 2.25 2.26 2.52 after one week of exposure to air [Example 3] A semiconductor device was fabricated according to the method of the second embodiment. In particular, the second and third wiring lines of the semiconductor device are formed under the same process conditions 5. The yield of one million via holes was measured using the multilayer wiring of the semiconductor device such that the measured yield was 91%, and the effective dielectric constant of an interlayer insulating layer measured by the interlayer capacitance was 2.60. . After the semiconductor device was stored at 200 ° C for 1,000 hours at a high temperature, the wiring resistance of the semiconductor device was measured, and the measurement results showed that the wiring resistance was not increased. [Example 4] A semiconductor device was fabricated by substantially the same method as described in Example 3, but ultraviolet rays were irradiated in an atmosphere of the atmosphere after the damage was repaired by the decane compound. Specifically, a UVL-7000 45 200921788 H4_N high-pressure mercury lamp obtained by Ushio Inc. is used as a substrate with a heat of 200 to 600 nm by adding 15 heat to 400 ° C in an atmosphere. Irradiate it to destroy the repaired insulation for ten minutes. The yield of one million via holes was measured using the multilayer wiring of the semiconductor device so that the measured yield was 94%, and the effective dielectric constant of the insulating layer of 5 layers measured by the interlayer capacitance was 2.58. After the semiconductor device was stored at -200 ° C for 1 hour, the wiring resistance of the semiconductor device was measured and the measurement showed that the wiring resistance did not increase. [Example 5] A semiconductor package was fabricated by substantially the same method as described in Example 3, but ultraviolet rays were irradiated in an argon atmosphere after repair and destruction by the decane compound. Specifically, a UVL-7000 H4-N high-pressure mercury lamp obtained by Ushio Inc. is used in a manner that a substrate is heated to 400 ° C in an argon atmosphere to have a range of 2 〇〇 to 6 〇〇 11111. The wavelength of ultraviolet radiation irritates the repaired insulation layer for ten minutes. 15 The yield of one million vias was measured using the multilayer wiring of the semiconductor device such that the measured yield was 93%, and the effective dielectric constant of the interlayer insulating layer measured by the interlayer capacitance was 2.61. After the semiconductor device was stored at 200 ° C for 1 hour, the wiring resistance of the semiconductor device was measured, and the measurement results showed that the wiring resistance did not increase. 20 [Example 6] A semiconductor device was fabricated by substantially the same method as described in Example 3, but ultraviolet rays were irradiated in a vacuum after repairing the damage with the decane compound. Specifically, a UVL-7000 H4-N high-pressure mercury 46 200921788 lamp obtained by Ushio Inc. is irradiated with ultraviolet light having a wavelength of 200 to 600 nm in a manner in which a substrate is heated to 400 ° C in a vacuum. It destroys the repaired insulation for ten minutes. The yield of one million via holes was measured using the multilayer wiring of the semiconductor device so that the measured yield was 96%, and the effective dielectric constant of the insulating layer of 5 layers measured by the interlayer capacitance was 2.52. After the semiconductor device was stored at 200 ° C for 1,000 hours at a high temperature, the wiring resistance of the semiconductor device was measured, and the measurement result showed that the wiring resistance was not increased. [Example 7] A semiconductor device was fabricated by substantially the same method as described in Example 3, but subjected to electron beam irradiation instead of ultraviolet irradiation after repair and destruction by the decane compound. Specifically, an insulating layer was irradiated with an electron beam having an acceleration voltage of 10 kV for 1 minute in such a manner that a substrate was heated to 400 ° C in a vacuum. The multilayer wiring of the semiconductor device was used to measure the yield of one million via holes so that the measured yield was 90%, and the effective dielectric constant of the interlayer insulating layer measured by the interlayer capacitance was 2.63. After the semiconductor device was stored at 200 ° C for 1,000 hours at a high temperature, the wiring resistance of the semiconductor device was measured, and the measurement result showed that the wiring resistance was not increased. [Comparative Example 2] 20 A semiconductor device was manufactured by substantially the same method as described in Example 3, except that the decane compound was repaired and destroyed, light irradiated, and electron beam irradiated. The yield of one million vias was measured using the multilayer wiring of the semiconductor device such that the measured yield was 72%, and the effective dielectric constant of the interlayer insulation layer was determined by the interlayer capacitance of 47 200921788 - the dielectric constant of the interlayer insulating layer was 2.96. . After the semiconductor device was stored at 200 C for a few hours, the wiring resistance of the de-conducting device was measured and the measurement results showed that the wiring resistance of the via hole was increased. [Comparative Example 3] 一 A conductor device was manufactured by the same method as described in Example 3, except that the stone was burned or irradiated with electron beam to repair the damage. + Using the multilayer wiring of the semiconductor device to measure - the yield of millions of continuous vias, so that the measured yield is 81%, and the effective dielectric constant of the interlayer insulating layer is measured by the interlayer capacitance H) It is 2 82. In the semiconductor device is 200. ^胄温预存丨, _, 赖, (4) Line resistance, and the measurement results show that there is (4) the electrical conductivity of the through hole = [Example 8] The following compound is injected into a 200ml reaction vessel: 2 〇柳”莫耳) Ethoxylated sulphur, sulphur, methyl triethoxy sulphate; 23; Mohr) glycidyl propyl trimethoxide, and 39 methyl isobutyl ketone. Into the reaction vessel, 162 g (〇9 mol) of a 1% aqueous solution of tetramethylammonium chloride was added dropwise over 10 minutes. After the completion of the dropwise addition, the ripening was carried out for two hours: after removing excess water from the reaction liquid using 5 g of magnesium sulfate, the ethanol produced by the ripening was removed from the reaction liquid in a rotary evaporator. The volume of the reaction liquid was reduced to 5 〇 ml. To the concentrated reaction liquid, '2' of methyl isobutyl ketone was added, thereby preparing a porous ceria precursor coating solution for forming a wiring separator. The porous silica dioxide precursor coating solution was applied to a low resistance substrate by a spin-coating process, and then at 250. (: pre-baking for three minutes. The cross-linking degree of the porous ceria precursor coating solution measured by FT-IR from a concentration of 950 cm-1 corresponding to the base is 75%. The spin coating process coats the porous ceria precursor coating solution 5 on a base substrate 200 made of tantalum to have a thickness of 40 Å. At 250 ° C, it will be disposed on the base substrate 2 The porous ceria precursor coating solution layer is prebaked for three minutes on the crucible. Next, the pre-flooded porous ceria is placed in an electric furnace having a nitrogen atmosphere gas at 4 〇〇〇c. The precursor coating solution is cured for 30 minutes, thereby forming a cerium oxide-based porous insulating layer 202 (see Fig. 16A). The cerium oxide-based porous insulating layer 202 is polished by a chemical mechanical polishing (CMP) apparatus. This allows the thickness of the ceria-based porous insulating layer 2〇2 to be reduced, and a damaged layer 2〇4 can be formed thereon (see Fig. 16B). The solution is cleaned with a 0.5% aqueous solution of hydrofluoric acid. The light-transmissive silica dioxide Xijiduo 15 pore insulating layer 202. 3cc of hexamethyldioxane On the polished ceria-based porous insulating layer 202, the ceria-based porous insulating layer 202 was spin-coated at 10,000 rpm for 60 seconds. The oxidizing was performed at 120 ° C on a hot plate. The bismuth-based porous insulating layer 2 〇 2 20 is baked for 60 seconds and baked at 250 ° C for 60 seconds, which allows the damaged layer 204 to be repaired, whereby the cerium oxide-based porous insulating layer is A repaired layer 206 is formed on 202 (see Fig. 16C). The substrate is heated to 4 Torr in a nitrogen atmosphere. (: By means of a high pressure mercury lamp (uVL-7000 by Ushio Lnc.) H4-N), the ceria-based porous insulating layer 202 was irradiated with ultraviolet rays having a wavelength of 200 to 600 nm for ten minutes (Fig. 16). [Example 9] It was substantially the same as described in Example 8. In this way, an evaluation sample is prepared, but 5 is carried out in the step shown in Fig. 16D by electron beam irradiation instead of light irradiation. Specifically, in a manner of heating a substrate to 400 ° C in a vacuum, An electron beam having an accelerating voltage of 10 kV was used to illuminate the ceria-based porous insulating layer for 1 minute. The dielectric constant of the porous insulating layer of the cerium oxide base 10 after each step and one week after the air is placed, and the dielectric constant is calculated from the capacitance measured by a mercury probe. The newly formed cerium oxide-based porous insulating layer 202 has a dielectric constant of 2.24. Polishing this layer forms a damaged layer 204, which increases its dielectric constant to 3.12. Repairing the damaged layer with the decane compound 15 The dielectric constant is reduced to 2.39; however, the dielectric constant does not return to its initial value. The ceria-based porous insulating layer 202 treated with the decane compound and then irradiated with ultraviolet rays has a value close to its initial value. The cerium oxide-based porous insulating layer 202 having a dielectric constant of 2.25 and placed in air for one week had a dielectric constant of 2.26. 20 [Comparative Example 4] An evaluation sample was prepared in substantially the same manner as described in Example 8 or 9, but ultraviolet or electron beam irradiation in the step shown in Fig. 16D was not carried out. Table 2 shows the dielectric constant of the yttrium-based porous insulating layer treated in each step and placed in air for one week, and the dielectric constant is calculated from the capacitance measured by a mercury probe. . As shown in Table 2, the newly formed cerium oxide-based porous insulating layer had a dielectric constant of 2.24. Polishing this layer creates a damaged layer 204 which increases its dielectric constant to 3.12. The damaged layer was repaired with the decane compound to reduce the dielectric constant to 2.39; however, its dielectric constant did not return to its original value. The ceria-based porous insulating layer which was not irradiated with light or ultraviolet rays and was left to air for one week had a dielectric constant of 2.55. [Table 2] Process dielectric constant Example 1 Example 2 Comparative Example 1 Freshly formed ceria-based porous insulating layer 2.24 2.24 2.24 Immediately after polishing 3.12 3.12 3.12 Immediately after treatment with decane compound 2.39 2.39 2.39 Immediately after irradiation with ultraviolet light 2.25 - - after electron beam irradiation - 2.25 - After one week of exposure to air 2.25 2.26 2.55 10 [Example 10] Most evaluation samples were prepared in substantially the same manner as described in Example 8, but shown in Figure 16D The temperature of the heat treatment changes when the light is irradiated in the step. In particular, each of the evaluation samples is heated at 30 ° C, 60 ° C, 100 ° C, 150 ° C, 200 ° C, 250 ° C, 300 ° C, 350 ° C, or 400 ° C. The evaluation samples are irradiated with light. 51 200921788 Table 3 for an evaluation of the sample immediately after formation and air placement for one week _ The dielectric constant of the yttrium oxide-based porous insulating layer, and the dielectric constant is calculated from the capacitance measured by a mercury probe. As shown in Table 3, the ceria-based porous 5 insulating layer 2〇2 of the just-formed evaluation sample had a dielectric constant of 2.24 to 2.26. The ruthenium oxide-based porous insulating layer 202' placed in the air-week and the etched body have a low dielectric constant of 2 to 2.26. [Example 11] 10 15 20 A majority of the evaluation samples were prepared in substantially the same manner as those described in Example 9, but heat-treated while irradiating the electron beam in the step shown in Fig. 16D; the field sound was changed. Specifically, the evaluation samples were irradiated with light in such a manner that the evaluation samples were each heated at 30 ° C, 60 DC, 150 ° C, 200 ° C, 250 ° C, 300 X, 350 ° C, or 400 T. Table 3 summarizes the dielectric constant of the yttrium oxide-based porous insulating layer which has just been formed and placed in the air-week evaluation sample, and the dielectric constant is calculated from the capacitance measured by the f-mercury probe. As shown in Table 3, the newly formed evaluation sample of the SiO 2 octagonal insulating layer 202 has a dielectric constant of 2.24 to 2.26. The oxygen-based porous insulating layer 202 is placed in the air-week, and the small dielectric constant of the immediately-formed 2.26. 1 [Comparative Example 5] An evaluation sample was prepared in substantially the same manner as described in Example 1G or 11 towel, but the ultraviolet or electron beam irradiation in the step shown in Fig. 16D was not carried out. ',,, 52 200921788 Table 3 shows the dielectric constant of the cerium oxide-based porous insulating layer treated in each step and placed in air for one week, and the dielectric constant is determined by a mercury probe. Calculated. As shown in Table 3, the ceria-based porous 5 insulating layer 202 of the just-formed evaluation sample had a dielectric constant of 2.34 to 2.39. Namely, the dielectric constant of the ceria-based porous insulating layer 202 of the newly formed evaluation sample is larger than the dielectric constant described in Example 10 or 11 in which light or electron beam irradiation is performed. The ceria-based porous insulating layer 202 placed after one week of air has a large dielectric constant of 2.52 to 2.56. 10 [Example 12] A third wiring layer and other members were formed in accordance with the semiconductor device manufacturing method of the fourth embodiment. After dry etching and polishing, after destruction by a decane compound, ultraviolet irradiation was performed in a nitrogen atmosphere. The third wiring layer is formed under substantially the same process conditions as those used to form a second wiring layer. The yield of one million continuous vias was measured using a multilayer wiring in a semiconductor device fabricated as described above, which showed that the yield of the vias was 91%, and one of the interlayer insulations was measured by the interlayer capacitance. The effective dielectric constant of the layer is 2.60. The semiconductor device was placed at 200 ° C for 1000 hours and then measured with a 20-wire resistance, which showed that its resistance did not increase. 53 200921788 [Table 3] Dielectric constant heat treatment example 10 Example 11 Comparative Example 5 The temperature was placed in the air immediately formed in the air immediately formed in [°C]. Just formed in the air Monday Monday 30. 2.26 2.26 2.25 2.25 2.39 2.25 60 2.26 2.26 2.25 2.25 2.38 2.54 100 2.25 2.25 2.24 2.26 2.28 2.56 150 2.26 2.25 2.26 2.25 2.36 2.25 200 2.25 2.26 2.25 2.26 2.37 2.55 250 2.26 2.24 2.25 2.25 2.35 2.53 300 2.24 2.26 2.25 2.24 2.35 2.52 350 2.25 2.25 2.24 2.25 2.36 2.53 400 2.25 2.24 2.25 2.25 2.34 2.52 [Example 13] A semiconductor device was fabricated in substantially the same manner as described in Example 12, but after dry etching and polishing, after destruction by decane compound, at 5 氦 ambient gas UV irradiation is carried out. Specifically, after repairing the damage, a high-pressure mercury lamp (UVL-7000 H4-N obtained by Ushio Inc.) is irradiated with ultraviolet rays having a wavelength of 200 to 600 nm for ten minutes and the substrate is in a krypton atmosphere. Ultraviolet irradiation was carried out by heating to 400 °C. 10 measuring the yield of one million continuous vias using the multilayer wiring in the fabricated semiconductor device, which shows that the yield of the vias is 94%, and an interlayer insulating layer is measured by the interlayer capacitance The effective dielectric constant is 2.58. The semiconductor device was placed at 20,000 ° C for 100 hours and then the wiring resistance was measured, which showed that its resistance did not increase. 15 [Example 14] A semiconductor package 54 200921788 was fabricated in substantially the same manner as described in Example 12, but after dry etching and polishing, after destruction by decane compound, ultraviolet irradiation was performed in an argon* atmosphere. Specifically, after the damage is repaired, a layer of ultraviolet light having a wavelength of 200 to 600 nm is irradiated with ultraviolet rays for a period of ten to five minutes using a south pressure mercury lamp (UVL-7000 H4_N obtained by Ushio Inc.) and the substrate is in an argon atmosphere. It is heated to 400. (In the manner of ultraviolet radiation. The yield of one million continuous vias was measured by the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the vias was 93%, and the interlayer capacitance was The effective dielectric constant of one of the interlayer insulating layers measured was 2 61. 10 The semiconductor device was placed at 200 ° C for 1 且 and then the wiring resistance was measured, which showed that the resistance did not increase. [Example 15] A semiconductor device was fabricated in substantially the same manner as described in Example 12, but after dry etching and polishing, after repairing and destroying with a decane compound, ultraviolet irradiation was performed in the air. In particular, after repairing the damage, a high voltage was utilized. A mercury lamp (UVL-7000 H4-N obtained by Ushio Inc.) was irradiated with ultraviolet rays by irradiation with a layer of ultraviolet rays having a wavelength of 200 to 600 nm for ten minutes and the substrate was heated to 400 ° C in a vacuum. The multilayer wiring in the fabricated semiconductor device measures the yield of one million 2 Å continuous vias, which shows that the yield of the vias is 96%, and an interlayer insulating layer is measured by the interlayer capacitance. The effective dielectric constant was 2.52. The semiconductor device was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed that the resistance did not increase. [Example 16] 55 200921788 By the process substantially the same as described in Example 12 Manufacturing a semiconductor device, but performing electron beam irradiation instead of ultraviolet irradiation after repairing and destroying the decane compound. Specifically, a substrate is heated to 400 ° C in a vacuum to have an accelerating voltage of 10 kV. The electron beam was irradiated for one minute and five minutes. The yield of one million continuous vias was measured by the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the via holes was 90%, and the interlayer capacitance was The effective dielectric constant of one of the interlayer insulating layers measured was 2.63. The semiconductor device was placed at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed that the resistance did not increase. [Comparative Example 6] The semiconductor device was fabricated in substantially the same process as described in Example 12, but was not repaired by decane compound or was not irradiated with light or electron beams. 15 Used in the fabricated semiconductor device The multilayer wiring measures the yield of one million continuous vias, which shows that the yield of the vias is 72%, and the effective dielectric constant of an interlayer insulating layer measured by the interlayer capacitance is 2.82. It was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed an increase in the wiring resistance of 45% of the via holes. 20 [Comparative Example 7] A semiconductor device was fabricated by a process substantially the same as described in Example 12. However, the decane compound is repaired and destroyed, and no light or electron beam irradiation is performed. The yield of one million continuous via holes is measured by the multilayer wiring in the fabricated semiconductor device, which shows that the yield of the via holes is 81%, and the effective dielectric constant of an interlayer insulating layer measured by the 56 200921788 interlayer capacitance is 2.82. 5 Hai semiconductor device is at 2〇〇. (: Placement under 10 hrs and then measurement of wiring resistance' This shows an increase in wiring resistance of 18% of via holes. [Example 17] 5 A third wiring layer and other are formed according to the semiconductor device manufacturing method of the fifth embodiment. a member. After dry etching and polishing, after repairing and destroying with a decane compound, ultraviolet irradiation is performed in a nitrogen atmosphere. The third wiring θ is formed under substantially the same process conditions as those for forming a second wiring layer. Using a multilayer wiring in a semiconductor device fabricated as described above to measure the yield of ~~ million continuous vias, which shows that the yield of the vias is 94%, and is measured by the interlayer capacitance The effective dielectric constant of one of the interlayer insulating layers was 2.49. The semiconductor device was placed at 200 ° C for 1000 hours and then the wiring resistance was measured 'this shows that the resistance did not increase. 15 [Example 18] As described in Example 17 A semiconductor device is manufactured in substantially the same process. However, after dry etching and polishing, the cerium compound is repaired and destroyed, and ultraviolet rays are irradiated in a nitrogen atmosphere. Specifically, after repairing and destroying, A high pressure mercury lamp (UVL-7000 20 H4-N obtained by Ushio Inc.) is irradiated with a layer of ultraviolet light having a wavelength of 2 to 600 nm for ten minutes and the substrate is heated to 4 Torr in a helium atmosphere. In the manner of ultraviolet irradiation, the yield of one million continuous via holes is measured by the multilayer wiring in the fabricated semiconductor device, which shows that the yield of the via holes is 96%, and the interlayer capacitance of the 57 200921788 is The effective dielectric constant of one of the interlayer insulating layers measured was 2.47. The semiconductor device was placed at 200 ° C for 1 且 and then the wiring resistance was measured 'this shows that the resistance did not increase. [Example 19] 5 The semiconductor device of the same process as described in Example 17 was fabricated, but after the dry etching and polishing, the ultraviolet ray was irradiated in an argon atmosphere after the damage was repaired by the shovel compound. In particular, after repairing the damage, Using a high-pressure mercury lamp (UVL-7000 H4-N obtained by Ushio Lnc), a layer of ultraviolet light having a wavelength of 200 to 600 nm is irradiated for ten to ten minutes and the substrate is heated to 4 〇〇 in an argon atmosphere. C Ultraviolet irradiation. The yield of one million continuous vias was measured by the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the vias was 97%, and was measured by the interlayer capacitance. The effective dielectric constant of one of the interlayer insulating layers is 2 47. 15 The semiconductor device is placed at 2 ° C for 1 且 and then the wiring resistance is measured 'this shows that the resistance does not increase. [Example 20] A semiconductor device was fabricated in substantially the same manner as described in Example 17, but after dry etching and polishing, after repairing and destroying with a decane compound, ultraviolet irradiation was performed in the true 20 air. In particular, after repairing the damage, a pressure was utilized. A mercury lamp (UVL_7〇〇〇h4_n obtained by Ushio Inc.) was irradiated with ultraviolet rays by irradiating a layer of ultraviolet rays having a wavelength of 200 to 600 nm for ten minutes and heating the substrate to 400 ° C in a vacuum. The yield of one million 58 200921788 continuous vias was measured using the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the vias was 95%, and one of the interlayer insulations was measured by the interlayer capacitance. The effective dielectric constant of the layer is 2.46. The semiconductor device was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed that its resistance did not increase. 5 [Example 21] A semiconductor device was fabricated by a process substantially the same as that described in Example 17, but subjected to electron beam irradiation instead of ultraviolet irradiation after repair and destruction by the decane compound. Specifically, a substrate was irradiated with an electron beam having an acceleration voltage of 10 kV for one minute and ten minutes in such a manner that a substrate was heated to 400 ° C in a vacuum. The yield of one million continuous vias was measured using the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the vias was 93%, and one of the interlayer insulating layers was measured by the interlayer capacitance. The effective dielectric constant is 2.47. The semiconductor device was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed that the resistance did not increase. [Comparative Example 8] A semiconductor device was fabricated by a process substantially the same as that described in Example 17, except that the destruction was not repaired with a decane compound, or light or electron beam irradiation was not performed. 20 measuring the yield of one million continuous vias using the multilayer wiring in the fabricated semiconductor device, which shows that the yield of the vias is 65%, and an interlayer insulating layer is measured by the interlayer capacitance The effective dielectric constant is 2.76. The semiconductor device was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed an increase in the wiring resistance of 58% of the via holes. 59 200921788 [Comparative Example 9] A semiconductor device was fabricated by a process substantially the same as that described in Example 17, except that the destruction was repaired with a decane compound, and no light or electron beam irradiation was performed. The yield of one million 5 continuous vias was measured using the multilayer wiring in the fabricated semiconductor device, which showed that the yield of the vias was 67%, and an interlayer insulating layer was measured from the interlayer capacitance. The effective dielectric constant is 2.75. The semiconductor device was allowed to stand at 200 ° C for 1000 hours and then the wiring resistance was measured, which showed an increase in the wiring resistance of 26% of the via holes. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device of a first embodiment; FIGS. 2A to 2C are cross-sectional views showing steps of a method of the first embodiment; FIGS. 3A to 3C Figure 5 is a cross-sectional view showing step 15 of the method of the first embodiment; Figures 4A to 4C are cross-sectional views showing the steps of the method of the second embodiment; and Figs. 5A and 5B are cross-sectional views showing the second embodiment Steps of the method; 20 Figures 6A and 6B are cross-sectional views showing the steps of the method of the second embodiment; Figures 7A and 7B are cross-sectional views showing the steps of the method of the second embodiment; Figs. 8A and 8B are Cross-sectional view showing step 60 of the method of the second embodiment 200921788

第9圖是一截面圖，顯示第二實施例之方法的—步驟. 第10圖是一截面圖，顯示第二實施例之方法的一步驟. 第11圖是一截面圖，顯示第二實施例之方法的—弗驟 5 第12®是—截面圖，顯示第二實施例之方法的—步驟· 第13圖是一截面圖，顯示第二實施例之方法的—步驟· 第14圖是一截面圖，顯示第二實施例之方法的—步驟. 第15圖是-流程圖，顯示第三實施例之方法的步驟. 第16A至16D圖是載面圖，顯示第三實施例之方法的牛 10 驟； v 第17A與17B圖是截面圖，顯示第四實施例之方法的牛 驟； 、乂Figure 9 is a cross-sectional view showing the steps of the method of the second embodiment. Figure 10 is a cross-sectional view showing a step of the method of the second embodiment. Figure 11 is a cross-sectional view showing the second embodiment Example of the method - the fifth step 12 is a cross-sectional view showing the method of the second embodiment - step · Figure 13 is a cross-sectional view showing the method of the second embodiment - step · Figure 14 A cross-sectional view showing the steps of the method of the second embodiment. Fig. 15 is a flow chart showing the steps of the method of the third embodiment. Figs. 16A to 16D are plan views showing the method of the third embodiment. Figure 10A and 17B are cross-sectional views showing the method of the fourth embodiment;

第18A與18B圖是戴面圖，顯示第四實施例之方法的牛 驟； /、V 第19圖是-截面圖，顯示第四實施例之方法的—步驟； 第20圖是-截面圖，顯示第四實施例之方法的—步驟； 第21圖是-載面圖，顯示第四實施例之方法的—步驟. 第22A與22B®是截面圖，顯示第五實施例之方法的一 步驟； 顯示第五實施例之方法的— 20 第23A與23B圖是截面圖 步驟； —步驟 ~步驟 —步驟 第24圖是-截面圖，顯示第五實施例之方法的 第25圖是—截面圖’顯示第五實施例之方法的 第26圖是-截面圖，顯示第五實施例之方法的 61 200921788 第27A至27D圖是截面圖，顯示用以製備一用以說明此 方法優點之評價樣本之方法的步驟。 【主要元件符號說明】 10...半導體基板 51 ·..第一配線 12···隔離層 52·.·第三絕緣層 14...元件區域 54...第三層間絕緣層 16···閘絕緣層 56.··第四絕緣層 18...閘電極 58...第五層間絕緣層 22...源極/汲極區域 60...第五絕緣層 24...MOS電晶體 62...第二光阻層 26...第一層間絕緣層 64...第二開口 28...擔止層 66...通孔 30...接觸孔 68.··第三光阻層 32...第一障壁金屬層 70...第三開口 34...鶴層 72···第二配線溝槽 35…第一接觸栓塞 74...第三障壁金屬層 36.··第一絕緣層 76...第二銅層 38…第二層間絕緣層 77a…第二ί妾觸滅 40...第二絕緣層 77b…第二配線 42...第一光阻層 78…第六絕緣層 44…第一開口 100. ·_底基板 46...第一配線溝槽 102…二氧化矽基絕海 48...第二障壁金屬層 104...硬遮罩 50...第一銅層 106...光阻層 62 200921788 108…第一開口 206…已修復層 110...第二開口 300.··矽基板 112…被破壞層 302...二氧化石夕基多孔質絕緣層 114...壁沈積物 304…被破壞層 116…已修復層 306...已修復層 200…底基板 S11〜S15...步驟 202…二氧化矽基絕緣層 204…被破壞層 S31〜S34...步驟 63Figs. 18A and 18B are front views showing the method of the fourth embodiment; /, V Fig. 19 is a cross-sectional view showing the steps of the method of the fourth embodiment; Fig. 20 is a sectional view The steps of the method of the fourth embodiment are shown; the 21st is a plan view showing the steps of the method of the fourth embodiment. The 22A and 22B® are sectional views showing one of the methods of the fifth embodiment. Steps; showing the method of the fifth embodiment - 20 FIGS. 23A and 23B are cross-sectional steps; - step to step - step 24 is a cross-sectional view showing the 25th figure of the method of the fifth embodiment is - section Figure 26 is a cross-sectional view showing a method of the fifth embodiment, showing a method of the fifth embodiment. 61 200921788 Figs. 27A to 27D are cross-sectional views showing an evaluation for explaining the merits of the method. The steps of the method of the sample. [Description of main component symbols] 10...Semiconductor substrate 51 ·.. First wiring 12···Isolation layer 52·.·3rd insulating layer 14...Element region 54...3rd interlayer insulating layer 16· · Gate insulating layer 56. · Fourth insulating layer 18... Gate electrode 58... Fifth interlayer insulating layer 22... Source/drain region 60... Fifth insulating layer 24... MOS transistor 62...second photoresist layer 26...first interlayer insulating layer 64...second opening 28...loading layer 66...through hole 30...contact hole 68. · Third photoresist layer 32... First barrier metal layer 70... Third opening 34... Crane layer 72... Second wiring trench 35... First contact plug 74... Third Barrier metal layer 36.....first insulating layer 76...second copper layer 38...second interlayer insulating layer 77a...second photoresist 40...second insulating layer 77b...second wiring 42.. The first photoresist layer 78...the sixth insulating layer 44...the first opening 100. The bottom substrate 46...the first wiring trench 102...the cerium oxide base 48...the second barrier metal layer 104 ...hard mask 50...first copper layer 106...photoresist layer 62 200921788 108...first opening 206...repaired layer 110...second open Mouth 300.·矽 substrate 112...destroyed layer 302...cerium oxide base insulating layer 114...wall deposit 304...destroyed layer 116...repaired layer 306...healed layer 200 ...substrate S11 to S15...Step 202: Ceria-based insulating layer 204... Destroyed layer S31 to S34...Step 63

Claims (1)

200921788 十、申請專利範圍： 1. 一種半導體裝置之製造方法，包含： 形成一具有二氧化矽基絕緣材料之絕緣層； 加工該絕緣層； 5 藉塗布一矽烷化合物以在該絕緣層上作用，使該絕 緣層疏水化；及 以光或一電子束照射該絕緣層。 2. 如申請專利範圍第1項之方法，其中加工該絕緣層係藉 乾餘刻該絕緣層來進行。 10 3.如申請專利範圍第1項之方法，其中加工該絕緣層係藉 拋光該絕緣層來進行。 4. 如申請專利範圍第1項之方法，更包含在形成包含該二 氧化矽基絕緣材料之絕緣層之前，且在藉塗布該矽烷化 合物以在該絕緣層上作用，使該絕緣層疏水化之後，以 15 由氧、氬、氫、氮或一選自於氧、氬、氫與氮之某些氣 體之氣體混合物所產生的電漿處理該絕緣層。 5. 如申請專利範圍第4項之方法，其中以由氧、氬、氫、 氮或一選自於氧、氬、氫與氮之某些氣體之氣體混合物 所產生的電漿處理該絕緣層將一因加工該絕緣層所產 20 生之副產物由該絕緣層中移除。 6. 如申請專利範圍第1項之方法，更包含在形成包含該二 氧化矽基絕緣材料之絕緣層之前，且在藉塗布該矽烷化 合物以在該絕緣層上作用，使該絕緣層疏水化之後，利 用一化學溶液將因加工該絕緣層所產生之副產物由該 64 200921788 絕緣層中移除。 7. 如申請專利範圍第1項之方法，其中以光或該電子束照 射該絕緣層係在30°C至400°C之溫度下進行。 8. 如申請專利範圍第1項之方法，其中以光或該電子束照 射該絕緣層係在一具有等於或小於150ppm之氧含量之 環境氣體中進行。 9. 如申請專利範圍第8項之方法，其中該環境氣體包含 氮、氦、及氬之一或多種氣體。 10. 如申請專利範圍第8項之方法，其中該環境氣體被抽真 10 空。 11. 如申請專利範圍第1項之方法，其中藉塗布該矽烷化合 物以在該絕緣層上作用，使該絕緣層疏水化係在20°C至 350°C之溫度下進行。 12. 如申請專利範圍第1項之方法，其中藉塗布該矽烷化合 15 物以在該絕緣層上作用，使該絕緣層疏水化係將一含有 該矽烷化合物之蒸氣塗布在該絕緣層上。 13. 如申請專利範圍第1項之方法，其中藉塗布該矽烷化合 物以在該絕緣層上作用，使該絕緣層疏水化係藉旋塗將 該矽烷化合物塗布在該絕緣層上。 20 14.如申請專利範圍第13項之方法，更包含在藉旋塗將該矽 烷化合物塗布在該絕緣層上後，以50°C至350°C之溫度 加熱該絕緣層。 15.如申請專利範圍第1項之方法，其中該矽烷化合物是一 石夕氮烧化合物、一醯胺梦烧化合物、一烧氧碎烧化合 65 200921788 物、或一乙酸氧石夕烧化合物。 16. 如申請專利範圍第1項之方法，其中該絕緣層是一積 層，且該積層包含一二氧化石夕基多孔質絕緣層。 17. 如申請專利範圍第1項之方法，其中該絕緣層是一積 5 層，且該積層包含一由一電漿加強CVD製程形成之 SiOC 層。 18. —種半導體裝置之製造方法，包含： 在一半導體基板上形成一包含二氧化矽基絕緣材 料之絕緣層； 10 藉乾蝕刻在該絕緣層中形成一開口； 在該絕緣層與該開口上方形成一導電層； 藉利用拋光在該絕緣層上方之導電層而部份地移 除該導電層，形成一包括設置在該開口中之導電層之一 部份的配線； 15 藉塗布一矽烷化合物以在該絕緣層上作用，使該絕 緣層疏水化；及 以光或一電子束照射該絕緣層； 其中藉塗布該矽烷化合物以在該絕緣層上作用，使 該絕緣層疏水化；及以光或該電子束照射該絕緣層係在 20 藉乾蝕刻在該絕緣層中形成一開口及在該絕緣層與該 開口上方形成該導電層之間進行，或者，在藉利用拋光 在該絕緣層上方之導電層而部份地移除該導電層，形成 包括設置在該開口中之導電層之一部份的配線之後進 行。 66 200921788 19. 如申請專利範圍第18項之方法，其中在該半導體基板上 形成包含二氧化石夕基絕緣材料之絕緣層形成一第一絕 緣層及一第二絕緣層，且該第二絕緣層形成在該第一絕 緣層上，並且藉利用拋光在該絕緣層上方之導電層而部 5 份地移除該導電層，形成包括設置在該開口中之導電層 之一部份的配線移除該第二絕緣層及該導電層。 20. 如申請專利範圍第19項之方法，其中當藉利用拋光在該 絕緣層上方之導電層而部份地移除該導電層，形成包括 設置在該開口中之導電層之一部份的配線時，該第二絕 10 緣層是一硬遮罩。 67200921788 X. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: forming an insulating layer having a cerium oxide-based insulating material; processing the insulating layer; 5 by applying a decane compound to act on the insulating layer, Hydrophobizing the insulating layer; and illuminating the insulating layer with light or an electron beam. 2. The method of claim 1, wherein processing the insulating layer is performed by etching the insulating layer. 10. The method of claim 1, wherein the processing the insulating layer is performed by polishing the insulating layer. 4. The method of claim 1, further comprising: hydrophobizing the insulating layer before forming the insulating layer comprising the ceria-based insulating material and applying the decane compound to act on the insulating layer Thereafter, the insulating layer is treated with a plasma generated by oxygen, argon, hydrogen, nitrogen or a gas mixture selected from the group consisting of oxygen, argon, hydrogen and nitrogen. 5. The method of claim 4, wherein the insulating layer is treated with a plasma produced by oxygen, argon, hydrogen, nitrogen or a gas mixture selected from the group consisting of oxygen, argon, hydrogen and nitrogen. A by-product produced by processing the insulating layer was removed from the insulating layer. 6. The method of claim 1, further comprising: hydrophobizing the insulating layer before forming the insulating layer comprising the ceria-based insulating material and applying the decane compound to act on the insulating layer Thereafter, by-products resulting from processing the insulating layer are removed from the 64 200921788 insulating layer by a chemical solution. 7. The method of claim 1, wherein the insulating layer is irradiated with light or the electron beam at a temperature of from 30 ° C to 400 ° C. 8. The method of claim 1, wherein the insulating layer is irradiated with light or the electron beam in an ambient gas having an oxygen content equal to or less than 150 ppm. 9. The method of claim 8, wherein the ambient gas comprises one or more of nitrogen, helium, and argon. 10. The method of claim 8, wherein the ambient gas is evacuated. 11. The method of claim 1, wherein the insulating layer is hydrophobized at a temperature of from 20 ° C to 350 ° C by applying the decane compound to act on the insulating layer. 12. The method of claim 1, wherein the insulating layer hydrophobically coats a vapor containing the decane compound on the insulating layer by applying the decane compound to act on the insulating layer. 13. The method of claim 1, wherein the decane compound is applied to the insulating layer by spin coating by applying the decane compound to act on the insulating layer. The method of claim 13, further comprising heating the insulating layer at a temperature of from 50 ° C to 350 ° C after coating the decane compound on the insulating layer by spin coating. 15. The method of claim 1, wherein the decane compound is a sulphate compound, a decylamine compound, an anaerobic sulphur compound 65 200921788, or an oxysulfate compound. 16. The method of claim 1, wherein the insulating layer is a laminate and the laminate comprises a silica dioxide base insulating layer. 17. The method of claim 1, wherein the insulating layer is a layer of 5 layers, and the layer comprises a SiOC layer formed by a plasma enhanced CVD process. 18. A method of fabricating a semiconductor device, comprising: forming an insulating layer comprising a cerium oxide-based insulating material on a semiconductor substrate; 10 forming an opening in the insulating layer by dry etching; and forming the opening in the insulating layer Forming a conductive layer thereon; partially removing the conductive layer by polishing a conductive layer over the insulating layer to form a wiring including a portion of the conductive layer disposed in the opening; 15 by coating a decane The compound acts on the insulating layer to hydrophobize the insulating layer; and irradiates the insulating layer with light or an electron beam; wherein the insulating layer is hydrophobized by applying the decane compound to act on the insulating layer; Irradiating the insulating layer with light or the electron beam is performed by forming an opening in the insulating layer by dry etching and forming the conductive layer between the insulating layer and the opening, or by using polishing in the insulating layer The conductive layer above the layer is partially removed to form a wiring including a portion of the conductive layer disposed in the opening. The method of claim 18, wherein the insulating layer comprising the SiO2 insulating material is formed on the semiconductor substrate to form a first insulating layer and a second insulating layer, and the second insulating layer a layer is formed on the first insulating layer, and the conductive layer is partially removed by polishing a conductive layer over the insulating layer to form a wiring shift including a portion of the conductive layer disposed in the opening Except the second insulating layer and the conductive layer. 20. The method of claim 19, wherein the conductive layer is partially removed by using a conductive layer polished over the insulating layer to form a portion including a conductive layer disposed in the opening When wiring, the second insulating layer 10 is a hard mask. 67
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