200916799 - 九、發明說明： *【發明所屬之技術領域】 - 本發明係關於一種顯示模組。 【先前技術】 隨著近年來電子顯示產品之輕薄化發展趨勢，電子顯 示產品之集成化程度愈來愈高，而設於該電子產品之電子 元器件之體積與重量亦愈來愈小，故，對於封裝於該電子 顯示產品之電子元器件之封裝品質要求更高。 目前顯不模組之驅動積體電路晶片及軟性電路板 (Flexible Printed Circuit Board，FPCB)係分別採用玻璃覆 晶（Chip on Glass，COG)方式及軟膜與玻璃接合（Film on Glass，FOG)方式封裝於顯示面板。但是驅動積體電路晶片 及軟性電路板與顯示面板相接觸區域之邊緣位置往往會因 為設備設定等外界因素而導致封裝品質不佳，為保證驅動 積體電路晶片及軟性電路板之封裝品質，通常需要對封裝 後之顯示模組進行檢測，以確定封裝品質。 請參閱圖1，係一種先前技術顯示模組之立體組裝示意 圖。該顯示模組10包括一顯示面板11、一驅動積體電路晶 片13及一軟性電路板15。其中該驅動積電路晶片13係採用 玻璃覆晶方式與該顯示面板11電連接，該軟性電路板15之 一端係採用軟膜與玻璃接合方式與該顯示面板11電連接。 再請參閱圖2，係圖1所示顯示模組10之顯示面板11之 平面示意圖。該顯示面板11包括一位於該顯示面板11外圍 區域之一晶片封裝區域112及一軟性電路板封裝區域122。 7 200916799 於該晶片封裝區域112内設置有複數平行間隔排佈之 驅動線路連接端113及六第一檢測端114、115、116、117、 118及119。該第一檢測端114、115及116相鄰設置，且該第 一檢測端115、116相互短路。該第一檢測端117、118及119 亦相鄰設置、且該第一檢測端117、118相互短路。同時該 驅動線路連接端113夾於該第一檢測端116、117之間。 於該軟性電路板封裝區域122内，同樣包括平行間隔排 佈之複數驅動線路連接端123及六第二檢測端124、125、 126、127、128及129。該第二檢測端124、125及126相鄰設 置，並分別與該晶片封裝區域112内之第一檢測端114、115 及116--對應電連接；該第二檢測端127、128及129亦相 鄰設置，並分別與該晶片封裝區域112内之第一檢測端 117、118及119--對應電連接。該驅動線路連接端123夾 於該第二檢測端126、127之間。 再請參閱圖3，係該驅動積體電路晶片13之平面示意 圖。於該驅動積體電路晶片13表面設置有複數焊接引腳133 及六檢測引腳134、135、136、137、138及139。其中該檢 測引腳134、135及136相鄰設置。該檢測引腳137、138及139 亦相鄰設置。該複數焊接引腳133夾於該檢測引腳136、137 之間。當該驅動積體電路13藉由玻璃覆晶方式封裝於該晶 片封裝區域112内時，該驅動積體電路13之六檢測引腳 134、135、136、137、138及139分別對應與該晶片封裝區 域112内之六第一檢測端114、115、116、117、118及119 藉由異方性導電膠（Anisotropic Conductive Film，ACF)電 200916799 . 連接。 再請參閱圖4 ’係該軟性電路板15之平面示意圖。該軟 - 性電路板15端部設置有六檢測焊點154、155、156、157、 158及159，以及與該檢測焊點154、155、156、157、158、 159分別對應電連接之六檢測觸點164、165、166、167、168 及 169。其中該檢測焊點 154、155、156、157、158、159 與該檢測觸點164、165、166、167、168、169分居該軟性 電路板15之二端部。當該軟性電路板15藉由軟膜與玻璃接 合方式封裝於該軟性電路板封裝區域12 2時，該軟性電路板 15之六檢測焊點154、155、156、157、158及159對應與該 軟性電路板封裝區域122内之六第二檢測端124、125、126、 127、128及129藉由異方性導電膠電連接。 當組裝該顯示模組10時，藉由異方性導電膠分別將該 驅動積體電路晶片13及該軟性電路板15封裝於該顯示面板 11，如此完成該顯示模組10之組裝。其中該驅動積體電路 晶片13之檢測引腳134、135、136、137、138、139與該晶 ^ 片封裝區域112内之第一檢測端114、115、116、117、118 及119間對應形成複數第一電阻R1，該軟性電路板15之檢 測焊點154、155、156、157、158及159與該軟性電路板封 裝區域122内之第二檢測端124、125、126、127、128及129 間形成複數第二電阻R2。同時在該顯示模組10内藉由該檢 測引腳、該第一檢測端、該第二檢測端、該檢測焊點、該 檢測觸點形成複數分壓檢測電路。 當對該顯示模組10進行檢測時，取其中三檢測觸點 200916799 .153、154及155為例，其檢測步驟如下： • 步驟一，選擇該軟性電路板15之檢測觸點164為輸入 - 端，選擇該檢測觸點165為輸出端形成一第一分壓檢測電 路。其中該第一分壓檢測電路係由該檢測觸點164、該檢測 焊點154與該第二檢測端124所形成之第二電阻R2、該第一 檢測端114、115與該驅動積體電路晶片13之檢測引腳13 4、 135所形成之二第一電阻R1、該第二檢測端125與該檢測焊 點165所形成之另一第二電阻R2依次串接組成之分壓電 路。 步驟二，提供一電壓表，藉由該電壓表之檢測觸頭分 別對應觸接該第一分壓檢測電路之輸入端與輸出端，並對 應讀出該第一分壓檢測電路之分壓值VI，則該檢測結果係 等於二第一電阻R1及二第二電阻R2所分擔電壓之和。 步驟三，選擇該軟性電路板15之檢測觸點165為另一輸 入端，選擇該檢測觸點166為另一輸出端，則形成一第二分 壓檢測電路，其係由該第一檢測觸點165、該檢測焊點155 與該第二檢測端125所形成之第二電阻R2、該第一檢測端 115、該驅動積體電路晶片13之檢測引腳13 5、該第二檢測 端126與該檢測焊點166所形成之另一第二電阻R2串接組 成之分壓電路。 步驟四，提供一電壓表，藉由該電壓表檢測該第二分 壓檢測電路之分壓值V2，則該檢測結果係等於該二第二電 阻R2所分擔之電壓之和。同時該二第一電阻R1所分擔之電 壓等於該二檢測結果之差值，即V1-V2。 10 200916799 步驟五’根據上述第一電阻R1、苐二電阻R2之分壓 值刀別對應判斷该驅動積體電路晶片；[3及該軟性電路板 15與該顯示面板u之接合品質。當該分壓值不在設定範圍 内時’則表明其封裝不良。 练上所述，在該顯示模組10中，於該軟性電路板15上 =置複數檢測觸點，藉由該檢測觸點能夠有效確定該軟性 ，:板15及該驅動積體電路晶片13與該顯示面板n之封裝 :¾，使得作業人員根據該檢測結果對應快速、有效找出 導致封裝不良之原因’並對應改進，進—步提高產品良率。 但’其亦存在如下缺陷： 電路it為：定第—電阻M之接合品質’需要於該軟性 、面<置複數檢測觸點，且該軟性電路板15係可 挠性件，如此使得檢測定位不方便。 其次，為確定第一電阻耵之接合品 ，觸點進行至少兩次之檢測過程推算而；要 :驟!雜抽量生產過程中，作業人員只能對大：量 產扣進订抽樣檢測以確定產品壓合品f 測精準度降低。 便侍產m良率檢 【發明内容】 一種方便檢測且能夠精準檢測 有鐘於此，有必要提供 產品良率之顯示模組。 一種顯示模組， 片及一軟性電路板 一檢測端及複數第 晶 第 括—顯示面板、—驅動積體電路 ’该顯示面板包括對應電連接之複數 -檢測端。其中該驅動積體電路晶片 11 200916799 •與該複數第-檢測端對應電連接，該軟性電路板與 一 铋測端對應電連接。該驅動積體電路晶片、該敕性 H = 該複數第二檢測端組成複數：測迴 κ °積體電路晶片自動檢測該檢測迴路之分壓值。 曰曰曰片板其:Γ顯示面板、一驅動積體電路 封袭區域=板板包括對應電連接之晶片 料aμ 路板封襞區域’該驅動積體電路晶片設 區i曰曰ίϊ裝區域’該軟性電路板設於該軟性電路板封裝 s片斑驅動積體電路晶片自動檢測該驅動積體電路 路板與該軟性電路電:及自動檢測該軟性電 =於先前技術，在本發明之顯示模組中，在該 面設置複數檢測端，使得該驅動積體電 ==及該複數檢測端組成複數檢測迴路。藉由該： 晶片之自動檢測功能，自動對該驅動積體電路 該顯示面板間之封裝品質以及該軟性電路板盘該顯 質進，檢測，避免使用額外的檢測設 對每g w /貝工 同扦，該種檢測模式能夠快速、方便 顯示模线行檢測，使得在大批量生產過程中，作 精確度，降低產品不4 k測效率的同時，還提高檢測 【實施方式】 立體二f閱圖5 ’其係本發明顯示模組—較佳實施方式之 體'解示意圖。該顯示模組2包括-顯示面板20、一驅 12 200916799 動積體電路晶片40及一軟性電路板60。其中該驅動積電 路晶片40係採用玻璃覆晶方式與該顯示面板20電連接， 該軟性電路板60之一端係採用軟膜與玻璃接合方式與該 顯示面板20電連接。 再請參閱圖6，係圖5所示顯示模組2之顯示面板20 之平面示意圖。該顯示面板20係一顯示終端，其包括一位 於中央區域之顯示區域21、一位於邊緣位置之晶片封裝區 域22及一軟性電路板封裝區域24。 於該晶片封裝區域22設置有複數平行間隔排佈之驅 動線路連接端220及六第一檢測端221、222、223、224、 225及226。該第一檢測端221、222及223相鄰設置，且 該第一檢測端222、223彼此相互短路。該第一檢測端224、 225及226亦相鄰設置，且該第一檢測端224、225彼此相 互短路。同時該第一檢測端221、222及223與另三第一檢 測端224、225及226對稱分佈於該驅動線路連接端220 兩侧，使得該驅動線路連接端220夾於該第一檢測端223、 224之間。 於該軟性電路板封裝區域24内，同樣包括平行間隔排 佈之複數驅動線路連接端240及四第二檢測端241、242、 245及246。該第二檢測端241及242相鄰設置，並分別與 該晶片封裝區域22内之第一檢測端221、222分別對應電 連接；該第二檢測端245及246亦相鄰設置，並分別與該 晶片封裝區域22内之第一檢測端225、226分別對應電連 接。該驅動線路連接端240夾於該第二檢測端242、245 13 200916799 -.之間。 ' 再請參閱圖7 ’係圖5所不驅動積體電路晶片40之平 - 面示意圖。於該驅動積體電路晶片40表面設置有複數焊接 弓j腳400及六檢測弓丨腳401 ' 402 ' 403、404、405及406 ° 其中該檢測引腳401、402及403相鄰設置，該檢測引腳 404、405及406亦相鄰設置，該複數焊接引腳400夾於該 檢測引腳403、404之間。當該驅動積體電路40藉由玻璃 覆晶方式封裝於該晶片封裝區域22時’該驅動積體電路 40之六檢測弓I腳401、402、403 ' 404 ' 405及406分別對 應與該晶片封裝區域22内之六第一檢測端221、222、223、 224、225及226電連接。其中該驅動積體電路晶片40用 以產生固定電壓驅動訊號VDD，並分析與其電連接之分壓 電路之電壓大小，在其内部對應儲存有複數設定之標準電 壓值Vs查找表，以供在驅動積體電路晶片40在對所檢測 之分壓電路分析時作為參考。 請參閱圖8，係圖5所示軟性電路板60之平面示意 圖。該軟性電路板60與該顯示面板20相接觸之端部設置 有四檢測焊點601、602、605及606。其中該檢測焊點601 及602相鄰設置，且在該軟性電路板60内部藉由導線電連 接。該檢測焊點605及606亦相鄰設置，同樣在該軟性電 路板60内部藉由導線電連接。當該軟性電路板60藉由軟 膜與玻璃接合方式封裝於該軟性電路板封裝區域24内 時，該軟性電路板60之四檢測焊點601、602、605及606 對應與該軟性電路板封裝區域24内之四第二檢測241、 14 200916799 242、245及246電連接。 再請參閱圖9，係圖5所示顯示模組2之立體組裝示 意圖。當組裝該顯示模組2時，首先於該晶片封裝區域22 内藉由異方性導電膠將該驅動積體電路晶片40封裝於該 顯示面板20，其封裝後之侧面結構如圖10所示。因為異 方性導電膠本身具電阻特性，所以當該異方性導電膠夾於 該驅動積體電路晶片40與該顯不面板20間時’則在該驅 動積體電路晶片40之每一檢測引腳401、402、403、404、 405及406與該晶片封裝區域22内之每一第一檢測端 221、222、223、224、225 及 226 之間形成一第一電阻， 設定其阻值為R1。 接著，於該軟性電路板封裝區域24内，同樣藉由異方 性導電膠將該軟性電路板60封裝於該顯示面板20，其封 裝後之侧面結構如圖10所不。同樣因為該異方性導電膠本 身具電阻特性，則在該軟性電路板60之每一檢測焊點 601、602、605及606與該軟性電路板封裝區域24内之每 一第二檢測端241、242、245及246之間形成一第二電阻， 設定其阻值為R2。如此，完成該顯示模組2之組裝。 當該顯示模組2組裝完成後，則在該顯示模組2内藉 由該驅動積體電路晶片40、該第一電阻R1、該第一檢測 端 221、222、223、224 ' 225 及 226、該第二檢測端 241、 242、245及246、該第二電阻R2及該檢測焊點601、602、 605及606組合形成若干檢測迴路。其中於玻璃覆晶方式 及軟膜與玻璃接合方式中，往往會因為熱壓溫度、熱壓觸 15 200916799 . 頭壓力設定及異方性導電膠本身特性等因素而導致該第一 .電阻R1及該第二電阻R2不在設定範圍内，進而影響該顯 • 示模組2像素區域之發光品質。所以需要藉由對該檢測迴 路進行檢測，進而確定該顯示模組2中該驅動積體電路晶 片40及該軟性電路板60之封裝品質。 當對該顯示模組2進行檢測時，取該晶片封裝區域22 内之三第一檢測觸端221、222及223為例，其包括如下檢 測步驟： 步驟一，選擇該第一檢測端222作為輸入端，選擇該 第一檢測端221作為輸出端，則形成一第一檢測迴路。 該第一檢測迴路係由該驅動積體電路晶片40之檢測 引腳402、該第一檢測端222、該第二檢測端242、該軟性 電路板60之檢測焊點602、601、該第二檢測端241、該第 一檢測端2 21及該驅動積體電路晶片40之檢測引腳4 01 依次串接設置組成之分壓電路，其中在該第一檢測迴路中 包括二第一電阻R1和二第二電阻R2。該二第一電阻R1 分別存在於該檢測引腳401、402與該第一檢測端221、222 間。該二第二電阻R2分別存在於該檢測焊點601、602與 該第二焊接端241、242間。 步驟二》該驅動積體電路晶片40產生·一固定電壓驅動 訊號VDD，檢測該第一檢測迴路之第一分壓值VI。 其中該固定電壓訊號VDD自該驅動積體電路晶片40 之檢測引腳402施加至該第一檢測迴路，並自該驅動積體 電路晶片40之檢測引腳401傳回至該驅動積體電路晶片 16 200916799 40，從而獲得一第一分壓值分壓值VI。該第一分壓值VI 等於該第一檢測迴路之二第一電阻R1及二第二電阻R2所 分擔之電壓和。 步驟三，選擇該第一檢測端222作為輸入端，選擇該 第一檢測端223作為輸出端，則形成一第二檢測迴路。 該第二檢測迴路係由該驅動積體電路晶片40之檢測 引腳402、該第一檢測端222、該第一檢測端223及該驅動 積體電路晶片40之檢測引腳403依次串接設置組成之分壓 電路，其中在該第二檢測迴路中包括二第一電阻R1。該二 第一電阻R1分別存在於該檢測引腳402、403與該第一檢 測端222、223間。 步驟四’該驅動積體電路晶片40再次產生·一固定電壓 驅動訊號VDD，檢測該第二檢測迴路之第二分壓值V2。 其中該固定電壓驅動訊號VDD自該驅動積體電路晶 片40之檢測引腳402施加至該第二檢測迴路，並自該驅動 積體電路晶片4 0之檢測引腳4 0 3傳回至該驅動積體電路晶 片40，從而獲得一第二分壓值V2。該第二分壓值V2等於 該第二檢測迴路之二第一電阻R1所分擔之電壓和，根據 該第一、第二分壓值VI、V2作差值運算分析，分別計算 出該第一電阻R1及該第二電阻R2所分擔之電壓。 步驟五，將上一步驟之分析結果與儲存於該驅動積體 電路晶片40之標準電壓值Vs進行比對，根據該比對結果 確定該驅動積體電路晶片40及該軟性電路板60之封裝品 質，並將該判斷結果轉換為數字訊號顯示於該顯示面板20 17 200916799 .之顯不區域21。 具虹的，因為該固定電壓驅動訊號 戶:以當該第一電阻R1所分擔之電壓過大或者過 ; 表;驅動積體電路晶片40之邊緣與該顯示面板20間之^ 一電阻R1過大或去禍，丨，μ , J ^ ^ /者]即輸出該驅動積體電路晶片4〇200916799 - IX. Description of the invention: * [Technical field to which the invention pertains] - The present invention relates to a display module. [Prior Art] With the development trend of light and thin electronic display products in recent years, the integration degree of electronic display products is becoming higher and higher, and the size and weight of electronic components disposed in the electronic products are becoming smaller and smaller. The packaging quality requirements for electronic components packaged in the electronic display product are higher. At present, the drive integrated circuit board and the flexible printed circuit board (FPCB) of the module are respectively made of chip on glass (COG) and film on glass (FOG). Packaged in the display panel. However, the edge position of the area where the integrated circuit chip and the flexible circuit board are in contact with the display panel tends to be poor in package quality due to external factors such as device setting, and in order to ensure the package quality of the driver integrated circuit chip and the flexible circuit board, usually The packaged display module needs to be tested to determine the package quality. Please refer to FIG. 1, which is a perspective assembled view of a prior art display module. The display module 10 includes a display panel 11, a driving integrated circuit chip 13, and a flexible circuit board 15. The driver circuit chip 13 is electrically connected to the display panel 11 by means of a flip chip, and one end of the flexible circuit board 15 is electrically connected to the display panel 11 by a soft film and glass bonding. Referring to FIG. 2, FIG. 2 is a schematic plan view of the display panel 11 of the display module 10 shown in FIG. The display panel 11 includes a chip package region 112 and a flexible circuit board package region 122 in a peripheral region of the display panel 11. 7 200916799 A plurality of parallel spaced-apart drive line connection ends 113 and six first detection terminals 114, 115, 116, 117, 118 and 119 are disposed in the chip package area 112. The first detecting ends 114, 115 and 116 are disposed adjacent to each other, and the first detecting ends 115, 116 are short-circuited to each other. The first detecting ends 117, 118, and 119 are also disposed adjacent to each other, and the first detecting ends 117, 118 are short-circuited to each other. At the same time, the driving line connection end 113 is sandwiched between the first detecting ends 116, 117. In the flexible circuit board package area 122, the plurality of drive line connection ends 123 and the sixth second detection ends 124, 125, 126, 127, 128 and 129 are also arranged in parallel. The second detecting ends 124, 125, and 126 are adjacently disposed, and are respectively electrically connected to the first detecting ends 114, 115, and 116 in the chip package area 112; the second detecting ends 127, 128, and 129 are also Adjacently disposed, and correspondingly connected to the first detecting ends 117, 118 and 119 in the chip package area 112, respectively. The drive line connection end 123 is sandwiched between the second detection ends 126, 127. Referring again to Fig. 3, a plan view of the drive integrated circuit chip 13 is shown. A plurality of solder pins 133 and six sense pins 134, 135, 136, 137, 138 and 139 are disposed on the surface of the driver integrated circuit chip 13. The detection pins 134, 135 and 136 are arranged adjacent to each other. The detection pins 137, 138, and 139 are also disposed adjacent to each other. The plurality of solder pins 133 are sandwiched between the detection pins 136, 137. When the driver integrated circuit 13 is packaged in the chip package region 112 by glass flip-chip, the six detection pins 134, 135, 136, 137, 138 and 139 of the driver integrated circuit 13 respectively correspond to the chip. The first first detecting ends 114, 115, 116, 117, 118 and 119 in the package region 112 are connected by an anisotropic conductive film (ACF) electric power 200916799. Referring again to FIG. 4, a schematic plan view of the flexible circuit board 15 is shown. The end of the flexible circuit board 15 is provided with six solder joints 154, 155, 156, 157, 158 and 159, and six corresponding electrical connections to the solder joints 154, 155, 156, 157, 158 and 159 respectively. Contacts 164, 165, 166, 167, 168, and 169 are detected. The detecting pads 154, 155, 156, 157, 158, 159 and the detecting contacts 164, 165, 166, 167, 168, 169 are separated from the two ends of the flexible circuit board 15. When the flexible circuit board 15 is packaged in the flexible circuit board package region 12 2 by a flexible film and glass bonding, the six solder joints 154, 155, 156, 157, 158, and 159 of the flexible circuit board 15 correspond to the softness. The six second detecting ends 124, 125, 126, 127, 128, and 129 in the board package area 122 are electrically connected by an anisotropic conductive paste. When the display module 10 is assembled, the driver integrated circuit chip 13 and the flexible circuit board 15 are respectively packaged on the display panel 11 by an anisotropic conductive paste, thus completing the assembly of the display module 10. The detection pins 134, 135, 136, 137, 138, 139 of the driving integrated circuit chip 13 correspond to the first detecting ends 114, 115, 116, 117, 118 and 119 in the chip package area 112. Forming a plurality of first resistors R1, the solder joints 154, 155, 156, 157, 158 and 159 of the flexible circuit board 15 and the second detecting ends 124, 125, 126, 127, 128 in the flexible circuit board package region 122 And 129 form a plurality of second resistors R2. At the same time, the complex voltage detecting circuit is formed in the display module 10 by the detecting pin, the first detecting end, the second detecting end, the detecting soldering point and the detecting contact. When the display module 10 is detected, three detection contacts 200916799 .153, 154, and 155 are taken as an example, and the detection steps are as follows: • Step 1: Select the detection contact 164 of the flexible circuit board 15 as an input - At the end, the detecting contact 165 is selected to form a first voltage dividing detecting circuit for the output end. The first voltage dividing detecting circuit is formed by the detecting contact 164, the second soldering resistor 154 formed by the detecting soldering point 154 and the second detecting end 124, the first detecting end 114, 115 and the driving integrated circuit. The first resistor R1 formed by the detecting pins 13 4 and 135 of the chip 13 and the second resistor R2 formed by the second detecting terminal 125 and the other soldering resistor 165 are sequentially connected in series to form a voltage dividing circuit. Step 2: providing a voltmeter, wherein the detecting contacts of the voltmeter respectively respectively touch the input end and the output end of the first voltage dividing detecting circuit, and correspondingly read the partial pressure value of the first partial voltage detecting circuit VI, the detection result is equal to the sum of the voltages shared by the two first resistors R1 and the second resistors R2. Step 3, selecting the detection contact 165 of the flexible circuit board 15 as another input terminal, and selecting the detection contact 166 as another output terminal, forming a second voltage division detection circuit, which is determined by the first detection touch a second resistor R2 formed by the detecting soldering point 155 and the second detecting end 125, the first detecting end 115, the detecting pin 13 5 of the driving integrated circuit chip 13, and the second detecting end 126 A voltage dividing circuit is formed in series with another second resistor R2 formed by the detecting pad 166. In step 4, a voltmeter is provided, and the voltage dividing value V2 of the second voltage dividing detecting circuit is detected by the voltmeter, and the detection result is equal to the sum of the voltages shared by the two second resistors R2. At the same time, the voltage shared by the two first resistors R1 is equal to the difference between the two detection results, that is, V1-V2. 10 200916799 Step 5 'The drive integrated circuit wafer is judged according to the voltage division value of the first resistor R1 and the second resistor R2; [3] and the bonding quality of the flexible circuit board 15 and the display panel u. When the partial pressure value is not within the set range, it indicates that the package is defective. As described above, in the display module 10, a plurality of detection contacts are disposed on the flexible circuit board 15, and the softness is effectively determined by the detection contacts: the board 15 and the driving integrated circuit chip 13 The package with the display panel n: 3⁄4, so that the operator can quickly and effectively find out the cause of the package failure according to the detection result, and correspondingly improve, and further improve the product yield. However, it also has the following drawbacks: The circuit it is: the first - the bonding quality of the resistor M is required for the softness, the surface < the complex detection contact, and the flexible circuit board 15 is a flexible member, so that the detection Positioning is not convenient. Secondly, in order to determine the joint of the first resistor ,, the contact is subjected to at least two detection processes to calculate; in order to: the production process of the miscellaneous pumping, the operator can only perform the sampling test for the large: mass production buckle Determine the accuracy of the product press f measurement accuracy. It is a convenient display and can accurately detect the display module with the product yield. A display module, a chip and a flexible circuit board, a detecting end and a plurality of first crystal-display panels, a driving integrated circuit, and the display panel includes a plurality of detecting ends corresponding to electrical connections. The driving integrated circuit chip 11 200916799 is electrically connected to the plurality of detecting ends, and the flexible circuit board is electrically connected to a detecting end. The driving integrated circuit chip, the HH = the complex second detecting end constitutes a complex number: the κ ° integrated circuit chip automatically detects the partial pressure value of the detecting circuit. The cymbal plate is: Γ display panel, a driving integrated circuit sealing area = slab includes a correspondingly electrically connected wafer material aμ board sealing area 'the driving integrated circuit chip set area i 曰曰 ϊ ϊ area The flexible circuit board is disposed on the flexible circuit board package s chip spot drive integrated circuit chip to automatically detect the drive integrated circuit circuit board and the flexible circuit: and automatically detect the soft power = in the prior art, in the present invention In the display module, a complex detection end is arranged on the surface, so that the driving integrated body== and the complex detecting end form a complex detecting loop. By the automatic detection function of the chip, the package quality between the display panel of the driving integrated circuit and the display quality of the flexible circuit board are automatically detected, and the use of an additional detection device is avoided for each gw/shell.扦, this kind of detection mode can display the line line detection quickly and conveniently, so that in the mass production process, the accuracy is reduced, the product is not measured at the same time, and the detection is improved. [Embodiment] Stereo two f reading 5 ' is a schematic diagram of a display module of the present invention - a preferred embodiment. The display module 2 includes a display panel 20, a drive 12 200916799, an integrated circuit chip 40 and a flexible circuit board 60. The driving circuit chip 40 is electrically connected to the display panel 20 by means of glass flip-chip, and one end of the flexible circuit board 60 is electrically connected to the display panel 20 by a soft film and glass bonding. Referring to FIG. 6, FIG. 6 is a schematic plan view of the display panel 20 of the display module 2 shown in FIG. The display panel 20 is a display terminal comprising a display area 21 in a central area, a chip package area 22 at the edge position, and a flexible circuit board package area 24. The chip package area 22 is provided with a plurality of parallel spaced drive line connection ends 220 and six first detection ends 221, 222, 223, 224, 225 and 226. The first detecting ends 221, 222 and 223 are arranged adjacent to each other, and the first detecting ends 222, 223 are short-circuited to each other. The first detecting ends 224, 225 and 226 are also disposed adjacent to each other, and the first detecting ends 224, 225 are short-circuited with each other. The first detecting ends 221, 222 and 223 are symmetrically distributed on the two sides of the driving line connecting end 220, so that the driving line connecting end 220 is clamped to the first detecting end 223. Between 224. In the flexible circuit board package area 24, the plurality of drive line connection ends 240 and the fourth second detection ends 241, 242, 245 and 246 are also arranged in parallel. The second detecting ends 241 and 242 are adjacently disposed, and are respectively electrically connected to the first detecting ends 221 and 222 in the chip package area 22 respectively; the second detecting ends 245 and 246 are also adjacently disposed, and respectively The first detecting ends 225, 226 in the chip package region 22 are respectively electrically connected. The drive line connection end 240 is sandwiched between the second detection ends 242, 245 13 200916799 -. Referring again to Fig. 7, a plan view of the integrated circuit wafer 40 is omitted. The surface of the driving integrated circuit chip 40 is provided with a plurality of soldering bows j feet 400 and six detecting bows 401 '402' 403, 404, 405 and 406 °, wherein the detecting pins 401, 402 and 403 are adjacently disposed, Detection pins 404, 405, and 406 are also disposed adjacent to each other, and the plurality of solder pins 400 are sandwiched between the detection pins 403, 404. When the driver integrated circuit 40 is packaged in the chip package region 22 by glass flip-chip, the six detection pins 110, 402, 403' 404' 405 and 406 of the driver integrated circuit 40 respectively correspond to the wafer. The six first detecting ends 221, 222, 223, 224, 225 and 226 in the package area 22 are electrically connected. The driving integrated circuit chip 40 is configured to generate a fixed voltage driving signal VDD, and analyze the voltage level of the voltage dividing circuit electrically connected thereto, and store therein a plurality of standard voltage value Vs lookup tables for setting The driver integrated circuit wafer 40 is used as a reference when analyzing the detected voltage dividing circuit. Referring to Figure 8, a schematic plan view of the flexible circuit board 60 shown in Figure 5 is shown. The end portions of the flexible circuit board 60 that are in contact with the display panel 20 are provided with four detecting pads 601, 602, 605, and 606. The solder joints 601 and 602 are disposed adjacent to each other and are electrically connected by wires inside the flexible circuit board 60. The solder joints 605 and 606 are also disposed adjacent to each other and are also electrically connected by wires within the flexible circuit board 60. When the flexible circuit board 60 is packaged in the flexible circuit board package area 24 by a flexible film and glass bonding, the four solder joints 601, 602, 605, and 606 of the flexible circuit board 60 correspond to the flexible circuit board package area. The fourth detection 24, 14 200916799 242, 245 and 246 of 24 are electrically connected. Referring again to Figure 9, a perspective assembly of the display module 2 shown in Figure 5 is shown. When the display module 2 is assembled, the driving integrated circuit wafer 40 is first packaged in the display panel 20 by the anisotropic conductive paste in the chip package region 22, and the packaged side structure is as shown in FIG. . Since the anisotropic conductive paste itself has a resistive property, when the anisotropic conductive paste is sandwiched between the drive integrated circuit chip 40 and the display panel 20, then each of the drive integrated circuit wafers 40 is detected. A first resistor is formed between the pins 401, 402, 403, 404, 405, and 406 and each of the first detecting ends 221, 222, 223, 224, 225, and 226 in the chip package region 22, and the resistance is set. For R1. Then, in the flexible circuit board package area 24, the flexible circuit board 60 is also packaged in the display panel 20 by an anisotropic conductive paste, and the side structure after the package is as shown in FIG. Also, because the anisotropic conductive paste itself has a resistive characteristic, each of the solder joints 601, 602, 605, and 606 of the flexible circuit board 60 and each of the second detecting ends 241 of the flexible circuit board package region 24 are also provided. A second resistor is formed between 242, 245 and 246, and the resistance is set to R2. In this way, the assembly of the display module 2 is completed. After the display module 2 is assembled, the integrated circuit chip 40, the first resistor R1, the first detecting ends 221, 222, 223, 224' 225 and 226 are driven in the display module 2. The second detecting ends 241, 242, 245 and 246, the second resistor R2 and the detecting pads 601, 602, 605 and 606 combine to form a plurality of detecting circuits. Among the glass flip-chip method and the soft film and glass bonding method, the first resistor R1 and the hot pressing temperature, the hot pressing 15 200916799 , the head pressure setting and the anisotropic conductive rubber itself are often caused. The second resistor R2 is not within the set range, thereby affecting the illumination quality of the pixel area of the display module 2. Therefore, the detection quality of the driving integrated circuit chip 40 and the flexible circuit board 60 in the display module 2 needs to be determined by detecting the detection circuit. For example, when the display module 2 is detected, the first detection terminals 221, 222 and 223 in the chip package area 22 are taken as an example, which includes the following detection steps: Step 1: Select the first detection end 222 as At the input end, the first detecting end 221 is selected as an output end to form a first detecting loop. The first detecting circuit is formed by the detecting pin 402 of the driving integrated circuit chip 40, the first detecting end 222, the second detecting end 242, the detecting solder joints 602, 601 of the flexible circuit board 60, and the second The detecting end 241, the first detecting end 21, and the detecting pin 410 of the driving integrated circuit wafer 40 are sequentially connected in series to form a voltage dividing circuit, wherein the first detecting circuit includes two first resistors R1. And two second resistors R2. The two first resistors R1 are respectively located between the detection pins 401 and 402 and the first detection terminals 221 and 222. The two second resistors R2 are respectively present between the solder joints 601, 602 and the second solder joints 241, 242. Step 2: The driving integrated circuit chip 40 generates a fixed voltage driving signal VDD, and detects a first partial voltage value VI of the first detecting circuit. The fixed voltage signal VDD is applied to the first detection circuit from the detection pin 402 of the driving integrated circuit chip 40, and is transmitted back from the detection pin 401 of the driving integrated circuit chip 40 to the driving integrated circuit chip. 16 200916799 40, thereby obtaining a first partial pressure value divider value VI. The first voltage dividing value VI is equal to the voltage sum of the first resistor R1 and the second resistor R2 of the first detecting circuit. Step 3: Select the first detecting end 222 as an input end, and select the first detecting end 223 as an output end to form a second detecting loop. The second detecting circuit is sequentially connected in series by the detecting pin 402 of the driving integrated circuit wafer 40, the first detecting end 222, the first detecting end 223 and the detecting pin 403 of the driving integrated circuit wafer 40. A voltage dividing circuit is formed, wherein the second detecting circuit includes two first resistors R1. The two first resistors R1 are respectively located between the detection pins 402 and 403 and the first detection terminals 222 and 223. Step 4' The driving integrated circuit chip 40 generates a fixed voltage driving signal VDD again, and detects a second divided voltage value V2 of the second detecting circuit. The fixed voltage driving signal VDD is applied from the detecting pin 402 of the driving integrated circuit chip 40 to the second detecting circuit, and is transmitted back to the driving from the detecting pin 410 of the driving integrated circuit chip 40. The circuit chip 40 is integrated to obtain a second divided voltage value V2. The second voltage dividing value V2 is equal to the voltage sum of the two first resistors R1 of the second detecting circuit, and the difference is calculated according to the first and second voltage dividing values VI and V2, and the first The voltage shared by the resistor R1 and the second resistor R2. Step 5: Comparing the analysis result of the previous step with the standard voltage value Vs stored in the driving integrated circuit chip 40, and determining the package of the driving integrated circuit wafer 40 and the flexible circuit board 60 according to the comparison result. The quality is converted into a digital signal displayed on the display area of the display panel 20 17 200916799 . If the voltage is too large, the voltage shared by the first resistor R1 is too large or too large; the resistance R1 between the edge of the driver integrated circuit chip 40 and the display panel 20 is too large or Going to the disaster, 丨, μ, J ^ ^ / is the output of the driver integrated circuit chip 4〇
Ϊ = 3並傳輸至該顯示區域21以顯示該判斯J 則代表，二二弟一電阻R2所分擔之電壓過大或者過小， 則代表該軟性電路板6G之邊緣與該顯示面板⑼之 良。根據該顯示區域21所顯示之判斷結 ： 致封裝不良之原因，並對應調整以提高產品導 步調整封裝設備之精確度、封裝溫度等。 進— 前技術，在該顯示模組2中， 驅 :4U配…又於該顯不面板20之晶片封裝區域 之禝數弟一檢測端、該軟性電路板封裝區域％内之禎 第二檢測端及該純電路板6G組成㈣ 測’其具有如下優點： 、峪自動檢 "百先’其避免使用額外的檢測設備及定位操作，所以 簡化檢測過程，方便檢測。 減其次2為該騎_叙檢測結果直接麵示面板 ”’、不’使仔作業人員能约有效快速對該顯 裝品質作出判斷，提高工作效率。 、、、且2之封 門内：：因為該自動檢測模式能夠讓作業人員能夠在短時 間内對母-顯示模組2進行檢測，所以在大批量生 不需要抽樣檢測即可直接更加精確對顯示模組2爭。 18 200916799 質做出判斷。 同樣’還可以取晶片封裝區域22内之 r“225及226為檢測對象’進-步確定該 日日片40之另一邊緣與該顯示面板2〇之 所 軟性電路板60與該顯示面板20之封裝品質。 逆 、在該顯示模組2中，設於該顯示面板2〇表面之第— 測端及第二檢測端不限於上述實施方式所揭示之位置，二 2對應設於該晶片封裝區域22内之中間位置，或者該軟性 電路板封裝區域24内之中間位置’以及其他容易出現不 之區域。 综上所述’本發明確已符合發明專利之要件，爱依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施例， 本發明之範圍並不以上述實施例為限，舉凡熟悉本案技藝 〜人士援依本發明之精神所作之等效修飾或變化，皆應涵 盘於以下申請專利範圍内。 19 200916799 【圖式簡單說明】 圖1係-種先前技術顯示模組之立體 圖2係圖1所示顯示模組之顯示面板二：思、圖。 圖3係圖1所示顯示模組之驅動積體電：？；；：。 圖。 包硌日日片之平面示意 圖4係圖i所示顯示模組之軟性電路 图5係本發明顯示模組一 ^千面不思圖。 圖。 …知方式之立體分解示意 示:示Γ組之顯示面板之平面示意圖。 圖所不顯示模組之驅動積體電路晶片之平面示意 圖8係圖5所示顯示模组之軟性 同 ^系圖5所示顯示模組之立體組裝;=面一圖。 =圖圖。9所示顯示模組之顯示模組封裝後之局部側面示 【主要元件符號說明】 2 驅動線路連接端 220、 20 軟性電路板封裝區域 24 21 驅動積體電路晶片 40 22 軟性電路板 60 顯示模組 顯示面板 顯示區域 晶片封裝區域 222、223、224、225 242 、 243 、 244 、 245 402 、 403 、 404 、 405 602 、 605 、 606 221 241 401 601 226 246 406 第一檢測端 弟一檢測端 檢測引腳 檢測烊點 20Ϊ = 3 and transmitted to the display area 21 to display the judgment J. The voltage shared by the second and second resistors R2 is too large or too small, which represents the edge of the flexible circuit board 6G and the display panel (9). According to the judgment result displayed on the display area 21, the cause of the package failure is adjusted, and the adjustment is made to improve the precision of the package adjustment device, the package temperature, and the like. In the prior art, in the display module 2, the drive: 4U is disposed in the chip package area of the display panel 20, and the detection end of the flexible circuit board package area The terminal and the pure circuit board 6G are composed of (4) measuring 'there are the following advantages: 峪 automatic detection " hundred first' which avoids the use of additional testing equipment and positioning operation, so the detection process is simplified and the detection is convenient. Secondly, the second is the riding _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The automatic detection mode enables the operator to detect the mother-display module 2 in a short time, so that the large-volume production does not require sampling detection, and the display module 2 can be directly and more accurately competed. 18 200916799 Quality judgment Similarly, it is also possible to take r "225 and 226 for the detection object" in the chip package area 22 to further determine the other edge of the day wafer 40 and the flexible circuit board 60 of the display panel 2 and the display panel. 20 package quality. In the display module 2, the first detecting end and the second detecting end disposed on the surface of the display panel 2 are not limited to the positions disclosed in the above embodiments, and the second and second corresponding portions are disposed in the chip package area 22. The intermediate position, or the intermediate position within the flexible circuit board package area 24, and other areas that are prone to occur. In summary, the invention has indeed met the requirements of the invention patent, and loves to file a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and all equivalent modifications or changes made by the skilled person to the spirit of the present invention are It should be included in the scope of the following patent application. 19 200916799 [Simple description of the drawing] Fig. 1 is a perspective view of a prior art display module. Fig. 2 is a display panel 2 of the display module shown in Fig. 1: thinking and drawing. Figure 3 is the driving integrated body of the display module shown in Figure 1: ;;:. Figure. Figure 4 is a schematic diagram of the flexible circuit of the display module shown in Figure i. Figure 5 is a display module of the present invention. Figure. ...the three-dimensional decomposition of the knowledge mode shows the schematic diagram of the display panel of the demonstration group. FIG. 8 is a schematic diagram showing the softness of the display module shown in FIG. 5 and the three-dimensional assembly of the display module shown in FIG. 5; = map. Partial side view of the display module of the display module shown in Fig. 9 [Main component symbol description] 2 Drive line connection terminal 220, 20 Flexible circuit board package area 24 21 Drive integrated circuit chip 40 22 Flexible circuit board 60 Display mode Group display panel display area chip package area 222, 223, 224, 225 242, 243, 244, 245 402, 403, 404, 405 602, 605, 606 221 241 401 601 226 246 406 Pin detection defect point 20