200915082 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種快閃記憶體控制器，特別是指一 種可控制多個快閃記憶體的多通道並行快閃記憶體控制器 0 【先前技術】 目前，隨著半導體介質儲存裝置㈣泛0，出現了 讀各樣的儲存設備以及多_存介f。其中，應用範圍 最廣泛的攜帶式儲存設備莫過於隨身碟，它所使用的儲存 介質主要是Flash (快間記憶體）中的Nand Flash，這種 Nand Flash在5賣寫以及抹除等操作過程中，都需要佔用一定 的=間。隨著各種軟體的不斷發展，用戶對需要儲存的資 料量要求越來越大，快閃記憶體儲存裝置的容量也隨之增 加，快閃記憶體在操作過程中需要等待的時間也隨著運算 數量的增大變得越來越久’導致用戶越來越不能夠忍受。 這種以攜帶爲目的的快閃記憶體儲存裝置一般使用 USB介面（通料列匯流排界面），通用的usb2〇協定能夠 支援的讀寫速度爲480Mbps，除去匯流排協定所佔的資料 處理頻寬，實際可用讀寫速度可達到48MBps。而目前普遍 使用的單通道隨身碟在讀操作過程中速率一般1〇MBps，寫 操作速率一般只有8MBps，即使是經過改進的雙通道傳輪 高速隨身碟，讀操作速率不會超過2〇MBps，寫操作速率不 會超過15MBPs。顯而易見，隨身碟的讀寫操作速率跟 USB2.0協定所允許的操作速率有很大的差值，因此理論上 200915082 =還疋了4進1提ι造成這種 快閃記憶體在讀寫以及抹除等操作，都需要佔用要原因疋 間。當用戶在進行資料讀京、^ 2都需要佔用—定的時 :_作資料塊的大小成正比 =作時間越久，快== 率的瓶頸。 Λ J限制整體速 此外，大陸專利“多通道閃存傳輸控制器、芯 =備（公開號CN 1790308A)中提出了多通 構想，但其沒有實現真正的多通道並行工作。 =制信號較共用的，這樣—旦有—個快閃記憶體晶片= 有完成操作任務，所有其他組就不可以開始新的操作 有技術中還缺少-種多通道獨立工作的快閃記憶體控制器 【發明内容】 因此，本發明之目的，即在提供一種有效地提高了快 閃記憶體的讀寫速度且解決現有快閃記憶體晶片在讀寫等 操作過程中出現的瓶頸問題的快閃記憶體控制器。 ， 於是，本發明快閃記憶體控制器是用於控制一快閃呓 憶體陣列，所述快閃記憶體陣列由多組快閃記憶體構成， 所述快閃記憶體控制器包括：一指令解析器、一傳輪护^制 器及多個快閃記憶體控制單元；所述指令解析器進行於人 解析和指令分配’所述指令解析器透過一控制匯流排與所 述傳輸控制器、所述多數個快閃記憶體控制單元分別獨立 傳遞控制資訊；所述各快閃記憶體控制單元分別透過各自 200915082 獨立的控制信號傳輸通道與各組快閃記憶體相連，完成控 制信號的傳遞；所述傳輸控制器透過—資料匯流排與各組 快閃記憶體進行資料傳遞。 較佳的，所述指令解析器與傳輸控制器傳遞控制資訊 的具體過程爲：所述指令解析器將資料控制指令解析成資 料匯流排控制信號發送到所述傳輸控制器，所述傳輸控制 器對所述指令解析器進行信號回傳。 較佳的，所述指令解析器與快閃記憶體控制單元傳遞 控制資訊的具體過程爲：所述指令解析器將控制指令解析 成多組指令佇列，並將各組指令佇列分配給所述各快閃記 憶體控制單元，所述各快閃記憶體控制單元對指令解析器 進行信號回傳。較佳的，所述快閃記憶體控制單元與各組 快閃記憶體的控制信號傳遞的具體過程爲：所述快閃記憶 體控制單元根據接收到的指令仔列產生快閃記憶體操作信 號’控制對應的快閃記憶體。 較佳的，所述的每個快閃記憶體控制單元下連接多個 所述快閃記憶體，且所述控制信號傳輸通道爲指令位址共 用匯流排，透過位址與指令的共用來決定快閃記憶體控制 單元對快閃記憶體進行的操作以及操作的位址。較佳的， 所述傳輪控制器與各組快閃記憶體的資料資訊傳遞具體過 程爲：所述傳輸控制器根據所述指令解析器發來的控制信 號以及一介面控制器内的FIFO模組和所述快閃記憶體的狀 態，並透過串並/並串轉換控制對外資料匯流排和對内資料 匯流排資料的傳遞。較佳的，所述快閃記憶體控制單元的 200915082 個數不超過下列值._儲存裝置的介面速率除以1 後 的整數值。 較佳的，對於USB2.0介面賴存裝置，所述快閃記憶 體控制單元的個數不超過4個。 較佳的，所述快閃記憶體控制器透過ASIC、CPLD或 A貫現。本發明之功效在於：本發明快閃記憶體控制 益由於採用了多通道獨立工作的實現方案，對於利用本發 明快閃§己憶體控制器實現的高速快閃記憶體儲存農置，豆 介面資料傳輸率一般由快閃記憶體晶片的資料傳輸率和； 面協定兩個方面決定，當介面協定的資料傳輸率足夠大的 時候’記憶體介面資料傳輸率一般爲快閃記憶體晶片列數 乘以1GMBPS;隨著快閃記憶體陣列個數的增加，記憶體資 料傳輸率的瓶頸會逐漸集中在記憶體的介面協定上，受到 介面協定資料傳輸率的限制。在目前常用的usB2Q介面記 =體中’其介面協^資料傳輪率爲刪咖，而在讀寫操作 ，考慮到操作的協定會佔去—部分的資料傳輸率，可以 =到的有效資料傳輸率爲麵邮，因此，選擇快閃記憶體 2的大小爲4行4列’經過測試儲存裝置的讀取操作速 率達到35MBPS以上，寫人操作達到25MBps以上提^ 了 現有快間記憶體記憶體的讀寫速率，有效的解決了上述習 知㈣記憶體錯存裝置存在的讀寫操作過程令的瓶頸問題 〇 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 200915082 以下配合參考圖式之—個較佳實施例的詳細說明中，將可 清楚的呈現。 如圖1所不爲快閃記憶體儲存裝i的基本架構圖，快 1 °己隐體儲存裝置與主機之間的介面，可以採用usb2 〇介 面協定。介面控制器連接於快閃記憶體控制器與介面之間 作為主機與快閃記憶體控制器之間的信號傳輸和資料傳 輸。快閃記憶體控制器一般可以設計在一個晶片中，其主 要作用疋根據快閃記憶體陣列的回傳信號，將主機命令進 订解析’產生指令信號仔列，控制需要操作的快閃記憶體 。而快閃記憶體陣列主要用於儲存用戶資料，㈣的設計 包含不同的快閃記憶體個數。 本發明提出的快閃記憶體控制器能控制多個快閃記憶 體組成的快閃記憶體陣列，透過多組獨立的信號線和資料 線」實現每組獨立操作以及資料平行傳輸，達到大容量快 閃z隐體裝置的咼速率讀寫目的。快閃記憶體控制器主要 包括.-指令解析器、一傳輸控制器以及多數個快閃記憶 體控制早兀。指令解析器是進行指令解析以及指令分配的 中樞’是㈣記μ控制器的主控模組；指令解析器根據 對内决閃5己憶體控制單元回傳的快閃記憶體的狀態信號將 指令解析成多組指令仵列，纟中，指令作列包括的主要内 谷有選擇要操作的快閃記憶體資訊、操作内容、要操作的 對内位址以及運算位元，透過控制匯流排把指令仔列分配 給快閃記憶體控制單元；同時，指令解析器還會產生對傳 輸控制器的控制信號，來控制資料匯流排的傳輸，對傳輸 9 200915082 ^的控制&號也是透過對内控制匯流排來進行傳輸的 _ ^日7解析11還會根據傳輸控制器以及快閃記憶體 I 1 °°元回傳的錯块資訊中斷資訊以及操作失敗等信號 一産生中斷明求傳輸給介面控制器。當快閃記憶體控制單 ,解析窃發來的指令佇列時，分別按照指令産生 '」。己u體操作仏冑，控制對應的目標快閃記憶體，把快 ’己隐體D己錄的貪訊讀進來，傳到對内資料匯流排，再由 傳輸控制器傳到對外資料匯流排；或者讀取對内資料匯流 排上的資料透過多組獨立的快閃記憶體資料線把資料寫入 目ί快閃記憶體。傳輸控制器的主要作用就是根據指令解 斤。發來的扎令以及介面控制器内的F_(First化扒⑻ ut)模組和快閃g己憶體晶片的狀態控制資料匯流排的資料 :輸把夕組快閃記憶體資料線傳過來的資料作並串轉換( 由並歹J匯抓排界面轉換成丰列匯流排界面），把多組信號 轉成匯抓排k號’.然後再把匯流排上的資料傳輸給介面控 制器；或者把介面控制器傳來的數據傳職料匯流排，然 後作串並轉換（&由串列匯流排界面轉換成並列匯流排界面） 把匯抓排:貝料为成多組獨立並行的快閃記憶體資料。 圖2所示爲本發明快閃記憶體控制器與習知的快閃記 隐體k制器的比較般的快閃記憶體儲存裝置（圖办))的 陕閃。己隱體個數爲1個或者2個，快閃記憶體控制器對它 們的控制透過一組信號線，資料的傳輸透過一組資料線； 而本發明控制的快閃記憶體個數理論上沒有上限，數量可 以包括2，4，8 ’ 16...，圖2⑻所示為一個4行*列的快閃 10 200915082 記憶體陣列，它們跟控制器之間透過4組相立的控制 信號線以纟4組資料線進行資訊的傳遞。在這裏各組庐 號線之間是相互獨立的，每_列快閃記憶體共用—組信號 線’-次操作過程中，4列最多只能有―個快閃記憶體晶 片參與操作，每組㈣線中都有兩位元的選擇信號，決定 本列這次操作所選擇的快閃記憶體。 資料線是各自獨立的4组8位元資料線，因此，在快 閃記憶體控制器晶片裡得到的資料匯流排的速率就會是四 組快閃記憶體資料線速率的和，這樣，匯流排速率相對一 般的隨身碟來說，大約是它們的4倍。在這裏資料線的 組數取決於陣列的列個數，理論上列個數越多，資料匯流 排速率越高，介面傳輸的有效速率也越高；但是，實際上 並非如此田列個數多於4時，這種陣列式快閃記憶體在 資料傳輸中的瓶頸，就會轉移到介面上，受介面時序限制 ，會有一個速率的上限，gp USB2〇介面紅的有效資料速 率。一般而言所連接的快閃記憶體列數不超過··儲存裝置 介面速率除以l〇MBps後的整數值。 爲了更理解本發明，透過4χ4快閃記憶體陣列的實施 例並結合附圖3進行詳細介紹。 陣列式的快閃記憶體控制器架構示意圖如圖3所示， 圖中5就是包含了快閃記憶體控制器的晶片，晶片可以是 嵌入式 CPLD(Complex Programmable Logic Device)或者場 可程式閘陣列（Field Programmable Gate Array,FPGA)，也可 以疋ASIC。6爲晶片5跟上層介面控制器之間進行指令傳 11 200915082 遞的信號流（即對外控制匯流排），當介面控制器讀取了主 機指令之後’會把指令傳輸給圖巾7所示的指令解析器。 信號流6主要包括操作類型、操作的長度以及操作的位址 同夺還匕括扣々解析器7回傳給介面控制器的中斷請 求。指令解析器7收到主機指令之後，會把它解析成指令 < 丁列，’且17組的個數取決於快閃記憶體陣列丨6的列數（如 圖中FI、F2、F3、F4)以及傳輪控制器12，再經過圖中8 所標示的對内控制信號匯流排，將資料匯流排控制信號9 傳給傳輸控制器12，同時將快閃記憶體控制單元控制信號 佇列18傳給相對應的快閃記憶體控制單力19(即圖中以 、C2、C3、C4) ’其中，控制信號匯流排8還包括了傳輸控 制器12以及快閃記憶體控制單元19回傳給指令解析器7 的錯誤資訊、中斷奢·却β 4 品从Λ & 斲貝訊以及操作失敗等信號，然後指令解 析器7根據這些信號產生中斷請求，發給介面控制器。 。另外’傳輸控制器12的主要作用是控制匯流排資料流 程的傳輸，把㈣記憶體陣列16傳過來的4組資料信號Μ 透過對内資料匯流排14轉成匯流排資料13，然、後再把匯流 排資料13傳輸給對外資料匯流排u;或者把介面控制器傳 來的對外匯流排資料u傳到對内資料匯流排14，，然後根據 快閃記憶體晶片控制信號把匯流排資料13分成多組獨立並 行的快閃記憶體資料信號15;同時，傳輪控制器12需要透 過狀態信號線Η)與介面控制器進行信號傳遞，透過信號線 的狀態判斷介面控制器内的觸模組狀態是否滿足要求， 來決定是否進行資料的傳遞操作以及產生對刚◦模組的操 12 200915082 作信號。 快閃記憶體控制單元19的 體陣列16’同時把快閃記 ：：_記憶 錯誤中斷信號回傳給指令解析…广乍過程中產生的 1Q 解析盗7。快閃記憶體控制單元 19根據收到的信號佇列向 浐a，如要a。 南要控制的快閃記憶體發出 自獨立的Ί貝取操作’被操作的快閃記憶體就會透過各 德，玺+内貢料匯流排14，然 的數據二二工制器12發出的控制信號，將資料匯流排14 !=Γ面控制器；如果是寫入操作，傳輸控制器12 會根據收到的指令將資料從 Μ14,妙π 了叶攸"面控制益傳到對内資料匯流 貝取貝科’透過各自獨立的資料後 將讀取的資料寫入快間記憶體。 ㈣線 圖中20所示爲快閃記情體批去丨丨吳卵& 間的控制信號組，每閃記憶體陣列之 錢4 4。 ，’'⑴工制㈣包括對快閃記憶體的 Γ;5:，知作類型’操作長度以及回傳的錯誤中斷訊息 二排Γ㈣記憶體陣列跟快閃記憶體控制器對内資 Π 的資料信號組，是並行獨立的…位元 貝料、，泉 > 料匯流排14上得到的資料、# f β MM 4速率是這4組資料線 速率的:，因此可以有效提高匯流排的資料傳輸速率。 ”列中以4列4仃的快閃記憶體陣列爲例，對本 發明作了說明性的描述。此外， -T1UM Μ & - 發月的快閃記憶體陣列 可以被擴展舄行，其…以爲2,4 8，m可以 爲1 ’ 2 ’ 4··· ’之類的多種快閃記憶體陣列組合，這些類似 13 200915082 的;變化都是在本發^要概念，這些對於熟知㈣之人士 來-兒都疋顯而易見的，故仍屬本創作所涵蓋的範圍。此外 ’本發明提出的快閃記憶體控制器可以透過ASIC、CPLD 或者FPGA等來實現。 綜上所述，本發明提出的快閃記憶體控制器能控制多 個快閃記憶體組成的快閃記憶體陣列16，透過多組獨立的 L號線和資料線’實現每組獨立操作以及資料平行傳輸， 達到大容量快閃記憶體裝置的高速率讀寫目的，故確實能 達成本發明之目的。 淮以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明中請:利 範圍及發明說明内容所作之簡單料效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是快閃記憶體儲存裝置的基本架構圖； 圖2是本發明快閃記憶體控制器與習知的 控制器的對比示意圖；及 圖3是本發明較佳實施例的快閃記憶體控制器示意圖 14 200915082 【主要元件符號說明】 5 晶片 6 信號流 7 指令解析器 8 控制信號匯流排 9 貧料匯流排控制信號 10 狀態信號線 11 對外資料匯流排 12 傳輸控制器 13 匯流排資料 14 對内資料匯流排 15 資料信號 16 快閃記憶體陣列 17 指令仔列組 18 控制信號佇列 19 快閃記憶體控制單元 20 控制信號組 15The invention relates to a flash memory controller, in particular to a multi-channel parallel flash memory controller capable of controlling multiple flash memories. Prior Art At present, with the semiconductor medium storage device (4) panning, a variety of storage devices and multiple storage devices have appeared. Among them, the most widely used portable storage device is the flash drive. The storage medium used is mainly Nand Flash in Flash. This Nand Flash is sold and erased in 5 processes. In the middle, you need to occupy a certain amount of =. With the continuous development of various softwares, users have more and more requirements for the amount of data to be stored, and the capacity of flash memory storage devices has also increased. The time that flash memory needs to wait during operation also follows the operation. The increase in the number of people has become longer and longer', which has made users less and more intolerable. This kind of portable flash memory storage device generally uses a USB interface (communication column bus interface), and the universal usb2 protocol can support a read/write speed of 480 Mbps, excluding the data processing frequency occupied by the bus protocol. Wide, the actual available read and write speed can reach 48MBps. The commonly used single-channel flash drive is generally 1 〇 MBps during read operations, and the write operation rate is generally only 8 MBps. Even with the improved dual-channel high-speed flash drive, the read operation rate will not exceed 2 〇 MBps. The operating rate will not exceed 15MBPs. Obviously, the rate of reading and writing of the flash drive is very different from the operating rate allowed by the USB 2.0 protocol. Therefore, in theory, 200915082 = 4 in 1 is also caused by the flash memory to read and write and Wiping and other operations require taking the cause. When the user is reading the data, the ^ 2 needs to be occupied - when: _ as the size of the data block is proportional = the longer the time, the fast == rate bottleneck. Λ J limits the overall speed In addition, the Continental patent “Multi-channel flash memory controller, core=preparation (publication number CN 1790308A) proposes a multi-pass concept, but it does not achieve true multi-channel parallel operation. So that there is a flash memory chip = there is a task to complete the operation, all other groups can not start a new operation, there is still a lack of technology - a multi-channel independent working flash memory controller [invention] SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a flash memory controller which effectively improves the read/write speed of a flash memory and solves the bottleneck problem that occurs in an existing flash memory chip during operations such as reading and writing. Therefore, the flash memory controller of the present invention is for controlling a flash memory array, the flash memory array is composed of a plurality of sets of flash memory, and the flash memory controller includes: An instruction parser, a transfer controller, and a plurality of flash memory control units; the instruction parser performs human parsing and instruction allocation 'the instruction parser through a control sink The flow row and the transmission controller and the plurality of flash memory control units independently transmit control information; each of the flash memory control units respectively transmits a separate control signal transmission channel and each group of flash memory through 200915082 The body is connected to complete the transmission of the control signal; the transmission controller transmits data through the data bus and each group of flash memory. Preferably, the specific process of transmitting the control information by the instruction parser and the transmission controller is The instruction parser parses the data control instruction into a data bus control signal sent to the transmission controller, and the transmission controller performs signal backhaul on the instruction parser. Preferably, the instruction parser The specific process of transmitting control information with the flash memory control unit is: the instruction parser parses the control instruction into a plurality of sets of command queues, and assigns each set of command queues to the flash memory control units. Each of the flash memory control units performs signal backhaul to the instruction parser. Preferably, the flash memory control unit The specific process of the control signal transmission of each group of flash memory is: the flash memory control unit generates a flash memory operation signal according to the received command to control the corresponding flash memory. Preferably, Each of the flash memory control units is connected to a plurality of the flash memory, and the control signal transmission channel is a common address of the instruction address, and is used by the address and the instruction to determine the flash memory. The operation of the control unit on the flash memory and the address of the operation. Preferably, the data transmission of the transmission controller and each group of flash memory is specifically performed by: the transmission controller according to the instruction The control signal sent by the parser and the state of the FIFO module and the flash memory in an interface controller, and the transmission of the external data bus and the inbound data bus data are controlled by serial/parallel conversion. Preferably, the number of 200915082 of the flash memory control unit does not exceed the following values. The interface rate of the storage device is divided by the integer value after 1. Preferably, for the USB 2.0 interface storage device, the number of the flash memory control units is not more than four. Preferably, the flash memory controller is implemented through an ASIC, a CPLD or an A. The effect of the present invention is that the flash memory control benefit of the present invention utilizes a multi-channel independent working implementation scheme, and the high-speed flash memory storage realized by the flash § hex memory controller of the present invention, the bean interface The data transfer rate is generally determined by the data transfer rate of the flash memory chip and the surface protocol. When the data transfer rate of the interface protocol is large enough, the memory interface data transfer rate is generally the number of flash memory chip arrays. Multiply by 1GMBPS; as the number of flash memory arrays increases, the bottleneck of memory data transfer rate will gradually concentrate on the interface protocol of the memory, which is limited by the interface protocol data transfer rate. In the current commonly used usB2Q interface = body's interface information is the rate of data transfer, and in the read and write operations, taking into account the operational agreement will take up part of the data transmission rate, can = valid data The transmission rate is face-to-face, therefore, the size of the flash memory 2 is selected to be 4 rows and 4 columns. The read operation rate of the tested storage device reaches 35 MBPS or more, and the write operation reaches 25 MBps or more. The read/write rate of the body effectively solves the bottleneck problem caused by the read/write operation process existing in the above (4) memory error storage device. [Embodiment] The foregoing and other technical contents, features and effects of the present invention are in 200915082. The detailed description of the preferred embodiment with reference to the drawings will be clearly understood. As shown in Figure 1, the basic architecture of the flash memory storage device i, the interface between the 1 sec hidden storage device and the host computer, can use the usb2 interface protocol. The interface controller is connected between the flash memory controller and the interface as a signal transmission and data transmission between the host and the flash memory controller. The flash memory controller can generally be designed in a chip, and its main function is to perform the command interpretation of the host command according to the return signal of the flash memory array to generate a command signal to control the flash memory to be operated. . The flash memory array is mainly used to store user data, and (4) the design contains different flash memory numbers. The flash memory controller of the invention can control a flash memory array composed of a plurality of flash memories, and realizes independent operation of each group and parallel transmission of data through multiple sets of independent signal lines and data lines to achieve large capacity. The rate of reading and writing of the flash z-block device. The flash memory controller mainly includes a .-instruction parser, a transfer controller, and a plurality of flash memory controls. The instruction parser is the main control module for the instruction parsing and instruction allocation. The instruction parser is based on the status signal of the flash memory returned by the internal flashback 5 control unit. The instruction is parsed into a plurality of sets of instructions. In the middle, the main valley included in the instruction list has flash memory information to be operated, operation content, internal address to be operated, and operation bit, and the control bus is transmitted through the control bus. The instruction sequence is assigned to the flash memory control unit; at the same time, the instruction parser also generates a control signal to the transmission controller to control the transmission of the data bus, and the control & Internal control bus to transmit _ ^ 7 7 analysis 11 will also be based on the transmission controller and flash memory I 1 ° ° back to the wrong block information interrupt information and operation failure signals, etc. Interface controller. When the flash memory control list analyzes the spoofed instruction queue, it generates '' according to the instruction. After the operation, control the corresponding target flash memory, read the greedy information of the fast-hidden D-record, pass it to the internal data bus, and then transfer it to the external data bus by the transmission controller. Or read the data on the internal data bus to write the data to the flash memory through multiple sets of independent flash memory data lines. The main function of the transmission controller is to decode according to the instructions. The data of the status control data bus of the F_ (First 扒 (8) ut) module and the flash g mn memory chip in the interface controller: the data of the flash memory data line The data is converted into a serial-to-serial conversion (converted from the interface of the J-sink to the Fengehui busbar interface), and the multiple sets of signals are converted into the sinking k-number. Then the data on the busbar is transmitted to the interface controller; Or the data transmitted from the interface controller is transferred to the bus, and then converted into a serial-to-parallel conversion (& is converted from a serial bus interface to a parallel bus interface) to capture the sink: the bunker is in multiple sets of independent parallel Flash memory data. Fig. 2 is a view showing the flash memory of the flash memory storage device (pictured) of the flash memory controller of the present invention and the conventional flash memory hidden controller. The number of hidden bodies is one or two, and the flash memory controller controls them through a set of signal lines, and the data is transmitted through a set of data lines; and the number of flash memory controlled by the present invention is theoretically There is no upper limit, the number can include 2, 4, 8 '16..., and Figure 2 (8) shows a 4-line* column flash 10 200915082 memory array, which communicates with the controller through 4 sets of opposite control signals. The line transmits information by means of 4 sets of data lines. Here, each group of nickname lines is independent of each other, and each _column flash memory share-group signal line'---------------------------------------- The group (4) line has a two-element selection signal that determines the flash memory selected for this operation. The data lines are independent sets of 4 octet data lines. Therefore, the data bus speed obtained in the flash memory controller chip is the sum of the four sets of flash memory data line rates, thus, the convergence The discharge rate is about four times that of a normal pen drive. The number of groups of data lines here depends on the number of columns in the array. The more columns are theoretically listed, the higher the data bus rate and the higher the effective rate of interface transmission. However, in reality, this is not the case. At 4 o'clock, the bottleneck of the array flash memory in the data transmission will be transferred to the interface. Due to the interface timing limitation, there will be an upper limit of the rate, and the effective data rate of the gp USB2 interface interface red. In general, the number of connected flash memory arrays does not exceed the storage device interface rate divided by the integer value after l〇MBps. To better understand the present invention, an embodiment of a 4χ4 flash memory array is described in detail with reference to FIG. The schematic diagram of the array flash memory controller architecture is shown in Figure 3. In the figure, 5 is the chip containing the flash memory controller. The chip can be an embedded CPLD (Complex Programmable Logic Device) or a field programmable gate array. (Field Programmable Gate Array, FPGA), or ASIC. 6 is the signal flow between the chip 5 and the upper interface controller 11 200915082 (ie, the external control bus), after the interface controller reads the host command, 'the command will be transmitted to the towel 7 Instruction parser. The signal stream 6 mainly includes the type of operation, the length of the operation, and the address of the operation. The interrupt request is returned to the interface controller. After receiving the host instruction, the instruction parser 7 parses it into the instruction < butyl column, 'and the number of 17 groups depends on the number of columns of the flash memory array 丨6 (as shown in the figure, FI, F2, F3, F4) and the transmission controller 12, and then through the internal control signal busbar indicated by 8 in the figure, the data bus control signal 9 is transmitted to the transmission controller 12, and the control signal of the flash memory control unit is also listed. 18 is transmitted to the corresponding flash memory control unit force 19 (ie, C2, C3, C4 in the figure), wherein the control signal bus 8 further includes the transmission controller 12 and the flash memory control unit 19 The error information transmitted to the instruction parser 7 is interrupted, and the signal is generated from the Λ & 斲 讯 and the operation failure, and then the instruction parser 7 generates an interrupt request based on these signals and sends it to the interface controller. . In addition, the main function of the transmission controller 12 is to control the transmission of the bus data flow, and the four sets of data signals transmitted from the (four) memory array 16 are converted into the bus data 13 through the internal data bus 14 and then Transfer the bus 13 data to the external data bus u; or pass the foreign exchange flow data u from the interface controller to the internal data bus 14, and then the bus data according to the flash memory chip control signal 13 Divided into a plurality of independent parallel flash memory data signals 15; at the same time, the transmission controller 12 needs to transmit signals through the state signal line 与) and the interface controller, and determine the touch modules in the interface controller through the state of the signal lines. Whether the status meets the requirements, to determine whether to carry out the data transfer operation and generate a signal to the module 12 200915082. The body array 16' of the flash memory control unit 19 simultaneously returns the flashing ::: memory error interrupt signal to the 1Q parsing pirate 7 generated during the command parsing process. The flash memory control unit 19 is listed to 浐a according to the received signal, if it is a. The flash memory to be controlled by the south is sent from the independent mussel taking operation. The operated flash memory will pass through the control of each of the German, 玺+ inner tributary bus 14, and the data is generated by the second and second controllers 12. Signal, the data bus 14 ! = face controller; if it is a write operation, the transmission controller 12 will transfer the data from the data according to the received command, 妙 了 攸 攸 quot quot 面 面 面 面 面 面 面Confluence Baye takes Beko's data into the fast memory after reading the independent data. (4) Line 20 shows the control signal group between the flash eggs and the flash, and the money for each flash memory array is 4 4 . , ''(1)Working system (4) includes Γ for flash memory; 5: Know the type 'operation length and return error interrupt message two rows 四 (4) memory array and flash memory controller for domestic assets The data signal group is parallel and independent...bit material, spring> data obtained on the material bus 14 and #f β MM 4 rate are the rate of the four data lines: therefore, the bus bar can be effectively improved. Data transfer rate. The present invention is described by taking a four-column 4 仃 flash memory array as an example. In addition, the -T1UM Μ &- s flash memory array can be extended... Think that 2,4 8,m can be a combination of multiple flash memory arrays such as 1 ' 2 ' 4··· ', these are similar to 13 200915082; the changes are in the concept of this issue, these are familiar with (4) The person-to-child is obvious, so it is still covered by this creation. In addition, the flash memory controller proposed by the present invention can be implemented by ASIC, CPLD or FPGA, etc. In summary, the present invention proposes The flash memory controller can control a flash memory array 16 composed of a plurality of flash memories, and realizes independent operation of each group and parallel transmission of data through a plurality of independent L-line and data lines to achieve large capacity. The high-rate read/write purpose of the flash memory device can achieve the object of the present invention. The above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto. According to the invention Please note that the simple changes and modifications made by the scope of the invention and the description of the invention are still within the scope of the patents of the invention. [Simplified illustration] Figure 1 is the basic architecture diagram of the flash memory storage device; A schematic diagram of a flash memory controller of the present invention and a conventional controller; and FIG. 3 is a schematic diagram of a flash memory controller according to a preferred embodiment of the present invention. 14 200915082 [Signal Description of Main Components] 5 Chip 6 Signal Flow 7 Command parser 8 Control signal bus 9 Lean stock bus control signal 10 Status signal line 11 External data bus 12 Transmission controller 13 Bus data 14 Internal data bus 15 Data signal 16 Flash memory array 17 Command Trickle group 18 control signal queue 19 flash memory control unit 20 control signal group 15