CN102591823A

CN102591823A - NAND flash controller with instruction queue function

Info

Publication number: CN102591823A
Application number: CN2011100095008A
Authority: CN
Inventors: 迟志刚
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2011-01-17
Filing date: 2011-01-17
Publication date: 2012-07-18

Abstract

The invention provides a NAND flash controller with an instruction queue function, which is composed of a micro controller, a system interface controller, a system-side DMA (direct memory access) controller, a system memory access arbitration logic unit, a system memory, a NAND flash instruction queue memory, a NAND flash instruction queue execution control logic unit, a NAND flash DMA controller, a NAND flash data cache and a NAND flash interface controller. The whole implementation process of NAND flash instruction is controlled completely by the NAND flash instruction queue execution control logic unit, and participation of the micro controller is not needed. The controller of the invention can greatly simplify the programming design of a system, and improve the instruction execution speed of the system, thereby improving system performance.

Description

A kind of Nandflash controller with instruction queue function

Technical field

The present invention relates to a kind of Nandflash controller, relate in particular to a kind of Nandflash controller with instruction queue function.

Background technology

Nandflash has obtained the development of advancing by leaps and bounds in recent years, to MLC (multiple field storage) technology of 2/unit even 3/unit, the production technology of Nandflash is also constantly progressive simultaneously by SLC (single-layer type storage) technical development of 1/unit.Along with the development of technology, the Nandflash capacity constantly increases, and the cost of unit capacity also significantly reduces, and the field of using Nandflash is also more and more.Along with the development of Nandflash technology, the instruction of Nandflash is more and more, and the hardware designs of Nandflash controller becomes increasingly complex, and increasing instruction has simultaneously increased the Design of software complexity.

Based on the problems referred to above; How can in the design process of Nandflash controller, find a kind of scheme preferably, it is many to solve current Nandflash controller steering order; The situation that execution speed is slow can the simplified system software design become the problem that the present invention will solve again.

Summary of the invention

The object of the invention is to provide a kind of Nandflash controller with instruction queue function; Through in system hardware, increasing the instruction queue design; Improve the execution speed of Nandflash controller, thereby simplify the program design of Nandflash controller, improve the entire system performance.

A kind of Nandflash controller with instruction queue function is carried out steering logic unit, Nandflash dma controller, Nandflash data buffer area and Nandflash interface controller by microcontroller, system interface controller, system end dma controller, system memory accesses arbitration logic unit, system storage, Nandflash instruction queue storer, Nandflash instruction queue and is constituted.

Microcontroller, system master system unit, each unit in the control system;

System interface controller is used for carrying out data transmission with specific protocol and main control end, and specific protocol comprises IDE, USB, SATA and PCIE etc.;

System end dma controller (visit of Direct Memory Access direct memory) is used for the data transmission between system interface controller and the system storage;

The system memory accesses arbitration logic unit is used to arbitrate microcontroller, system interface controller and the Nandflash controller access request to system storage;

System storage is used for keeping in the data of transmitting between storage system end and Nandflash controller, also is used to deposit current data and reads and writes employed address mapping table;

Nandflash instruction queue storer is used for depositing the required information of Nandflash execution process instruction, comprises instruction type, row address, column address, size of data, system memory addresses etc.;

The Nandflash instruction queue is carried out the steering logic unit, is used for the execution according to the information control command of Nandflash instruction;

The Nandflash dma controller is used for the data transmission of control system storer and Nandflash data buffer area;

The Nandflash data buffer area is used for buffer memory and reads from system storage but have little time to write the data of Nandflash, also is used for buffer memory and reads from Nandflash but have little time the data of writing system storer;

The Nandflash interface controller, the data transmission between control Nandflash controller and the Nandflash array.

When system receives the request of visit Nandflash; Access request is split into the reading and writing of Nandflash or the instruction of wiping, write the Nandflash instruction queue and notify the Nandflash instruction queue to carry out the instruction that the steering logic unit begins to carry out Nandflash.

The Nandflash instruction queue is carried out the state that the Nandflash that will visit is at first checked in the steering logic unit, if the free time then sends to Nandflash with the Nandflash instruction.If be not idle, need wait for that then Nandflash becomes the free time, and then the Nandflash instruction is sent to Nandflash.

After Nandflash instruction queue execution steering logic unit sends to Nandflash with instruction; After Nandflash is ready to receive data or sends data, start the Nandflash dma controller and write data perhaps from the Nandflash sense data to Nandflash.

The whole implementation of Nandflash instruction is carried out the steering logic unit controls by the Nandflash instruction queue fully, need not the participation of microcontroller.The Nandflash instruction queue is carried out the control of steering logic unit can more efficiently carry out the Nandflash instruction fast, does not need microcontroller to participate in the control that the Nandflash instruction is carried out, and program design that can simplified system improves instruction execution speed.

Description of drawings

Fig. 1 has the Nandflash controller circuit structure figure of instruction queue function

Nandflash state redirect synoptic diagram in Fig. 2 Nandflash controller read/write/erasing instruction

Specific embodiments

Below in conjunction with each accompanying drawing content proposed by the invention is carried out detailed description.

The Nandflash instruction queue degree of depth depends on the quantity of the Nandflash instruction that the Nandflash controller can carry out simultaneously, generally equals the quantity of the Nandflash that the Nandflash controller connected.The Nandflash command content is an example in the following table:

Table 1Nandflash command content

As above shown in the table, the content of each Nandflash instruction takies 16 bytes altogether.

The all corresponding mode bit register of each Nandflash instruction, the state of indicator formation.When system write the Nandflash instruction queue with a Nandflash instruction, just corresponding status register put 1, after Nandflash instruction queue execution steering logic executes a Nandflash instruction, the attitude register of correspondence was put 0.System is before writing instruction queue with the Nandflash instruction; Whether need inspection is 0 Nandflash instruction queue mode bit register; If have and then select a correspondence position to write, need not wait for that then any Nandflash instruction queue mode bit register becomes 0 if having.

Nandflash is in different state in a Nandflash execution process instruction, the Nandflash instruction queue is carried out the steering logic unit need decide which type of operation Nandflash is taked according to the residing state of Nandflash.Fig. 2 has provided the Nandflash write command, read instruction, wiped residing state and precedence thereof in the execution process instruction, and is as shown in table 2 to the explanation of each state among the figure:

Status Name	State description
		Idle	Nandflash does not have instruction to be carried out
Receive instruction	Nandflash is receiving instruction
		Wait for R/B	Wait for that the ready/busy signal becomes 1 from 0
Deng pending data	Nandflash waits for and receives or send data
		Data transmit	Nandflash receives or sends data

Residing state description in each implementation of table 2Nandflash

Provided the condition of each state redirect in the following table 3:

Table 3 state redirect condition stub

System will put 1 with the Nandflash instruction queue status register of correspondence after will writing Nandflash instruction queue storer to the instruction that the reading and writing of Nandflash are perhaps wiped.

After the Nandflash instruction queue is carried out the steering logic unit and detected Nandflash instruction queue status register and become 1 by 0, from the Nandflash instruction queue, read out the information of Nandflash instruction.

The Nandflash instruction queue is carried out the steering logic unit according to the definite Nandflash that will visit of the row address of Nandflash instruction.At first check the state of the Nandflash that will visit, if the free time then sends to Nandflash with the Nandflash instruction.If be not idle, need wait for that then Nandflash becomes the free time, and then the Nandflash instruction is sent to Nandflash.

After Nandflash instruction queue execution steering logic unit sends to Nandflash with instruction; Nandflash such as need are ready to receive data or send after the data, and configuration Nandflash dma controller writes data or sense data from the Nandflash storer to the Nandflash storer.

In the process that Nandflash instruction is carried out, carry out the steering logic unit controls by the Nandflash instruction queue fully, participation that need not microcontroller.With respect to microcontroller, the Nandflash instruction queue is carried out the steering logic unit controls can more efficiently carry out the Nandflash instruction fast.Owing to do not need microcontroller to participate in the control that the Nandflash instruction is carried out, the software program design of system also obtains simplifying, and improves the execution speed of system, and then improves system performance.

Claims

1. the Nandflash controller with instruction queue function is characterized in that comprising Nandflash instruction queue storer and Nandflash instruction queue and carries out the steering logic unit.

2. a kind of Nandflash controller as claimed in claim 1 with instruction queue function; It is characterized in that said Nandflash instruction queue storer deposits information required in the Nandflash execution process instruction, comprise instruction type, row address, column address, size of data, system memory addresses.

3. according to claim 1 or claim 2 a kind of Nandflash controller with instruction queue storer is characterized in that said Nandflash instruction queue storer is the interface between system software and the hardware.

4. a kind of Nandflash controller as claimed in claim 1 with instruction queue function; It is characterized in that the state of the Nandflash that the inspection of said Nandflash instruction queue execution steering logic unit elder generation will be visited, send to Nandflash if the free time then instructs Nandflash.

5. a kind of Nandflash controller as claimed in claim 1 with instruction queue function; It is characterized in that the whole implementation of said Nandflash instruction queue execution steering logic unit controls Nandflash instruction, need not microcontroller participation in the system.

6. a kind of Nandflash controller with instruction queue function as claimed in claim 1 is characterized in that said Nandflash controller and main control end communication interface comprise SATA, USB, PCIE, PATA.