CN101324867A - Device and method for managing data based on semiconductor storage medium - Google Patents
Device and method for managing data based on semiconductor storage medium Download PDFInfo
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Abstract
The invention provides a data management device based on the semiconductor storage medium, which is used for accepting and executing control commands of at least one processor, and performing data access operation to at least one storage medium. The data management device comprises an external communication interface unit communicated with at least one processor; an external storage interface unit for performing data access to at least one storage medium; and a controlling unit for controlling the operation of the external communication interface unit and the external storage interface unit. The invention also provides a data management method. The organizational management is performed to the semiconductor storage media in various electronic products by using the data management device, the data management device can be compatible with the prior and future continuously promoted various semiconductor storage media, the upgrading is simple, and the updating of the semiconductor storage medium is adapted without changing the interface design; the purpose that the external communication interface adopts logical mapping for addressing is realized; the implementing is easy and the large-scale production is convenient.
Description
Technical field
The present invention relates to data processing field, particularly the data administrator of based semiconductor storage medium and management method.
Background technology
Semiconductor storage medium is mainly used in portable type electronic product and embedded device field now, and these products or equipment all need to store lot of data, especially video, voice data.Along with the application of these products or equipment more and more widely, function from strength to strength, semiconductor storage medium is also in develop rapidly, capacity, integrated level, production technology, technology, Media density are also everyday promoting, otherness between the semiconductor storage medium of different brands, model, technology, capacity, technology is increasing, and is compatible more and more difficult; Therefore the trend that performances such as semiconductor storage medium exists the lost of life, erasable number of times to reduce on the other hand, increase bad position reduce have higher requirement to the management of the management of bad piece and data check, data security, abrasion equilibration, addressing technique, file system.
Prior art generally makes semiconductor storage medium 30 directly accept the control of processor 20 referring to Fig. 1, carries out work according to the instruction of processor 20.Processor comprises system processor such as SOC, RISC, CISC, DSP or MCU; Perhaps comprise multimedia processor such as MP3, MP4, MP5, learning machine or mobile phone application coprocessor.Because the problem that above-mentioned semiconductor storage medium development brings makes processor 20 that following difficulty arranged aspect the semiconductor storage medium 30 of supporting different brands, model, technology, capacity, technology:
1, can't use unified driver to different semiconductor storage mediums;
2, for the storage medium of multiple brand, multiple model, need a large amount of tests to guarantee compatibility and the supporting dynamics of processor to semiconductor storage medium, cause to delay launch, increase cost of products;
3, can not guarantee to support the semiconductor storage medium of following listing, increase the risk of product solution, might cause and user or supplier between dispute;
4, because data check work is mainly finished by hardware, the difficulty increase of data check makes processor need continuous Renewal Design, just can finish data check work; Need the very long cycle and existing processor upgrade is promptly expensive, can't satisfy cost control and the requirement of market reaction fast.
5, processor will be handled more more complex calculations and data, has both required the read or write speed of double conductor storage medium faster, wishes that again the resource that the managing semiconductor storage medium consumed is few as far as possible, and management is more simplified.
Summary of the invention
The objective of the invention is to, a kind of data administrator and management method of based semiconductor storage medium is provided, realize the management of logic addressing and storage medium, compatible multiple semiconductor storage medium.
The control command of at least one processor is accepted and carried out to the data administrator of described based semiconductor storage medium, and at least one storage medium is carried out data access operation, comprising: with the external communication interface unit of at least one processor communication; At least one storage medium is carried out the exterior storage interface unit of data access; Control the control module of external communication interface unit and the work of exterior storage interface unit respectively.
Above-mentioned data administrator also comprises unifies to be the firmware of logic addressing mode with the data access addressing mode.This firmware comprises: the memory management and the driver layer of at least one storage medium being carried out master data accessing operation and management.
Above-mentioned firmware also comprises: realize the logic and the storage medium management of external system, provide the storage medium conversion layer of logic addressing mode interface at least one processor, the storage medium conversion layer calls memory management and driver layer is carried out data access operation at least one storage medium.
Above-mentioned data administrator comprises that also the interface that is used for being connected with processor adopts unified logical storage bus, adopts the mapping of logical address piece on agreement, by logical address and physical address translations, realizes the access to the storage medium of physical address piece mapping.
Above-mentioned data administrator provides startup or moves required data and/or information to processor according to the control of processor.
The present invention also proposes a kind of data managing method, is used for the control command that at least one processor was accepted and carried out to data administrator, and at least one storage medium is carried out data access operation, comprising: the step of receiving processor control command; Logical address is converted into the step of physical address; Storage medium is carried out the step of data access operation according to physical address.
The step of receiving processor control command and/or adopt unified logical storage bus to carry out wherein to the step that storage medium carries out data access operation.
The data administrator of based semiconductor storage medium provided by the invention and management method can not need the design of original system of change or product because of the upgrading of semiconductor storage medium applicable to the Organization And Management of semiconductor storage medium among various electronic products such as USB Flash Drive, flash disk, flash card, MP3/MP4/MP5 player, learning machine, the SSD; Not only compatible existing multiple semiconductor storage medium, the also compatible following new semiconductor storage medium of constantly releasing; Data communication interface standard between processor and the semiconductor storage medium pre-defines, and upgrading is simple, does not need to change the renewal that Interface design adapts to semiconductor storage medium; Realized that more external communication interface adopts the logical mappings addressing, replaced the surperficial simple of prior art and the physical mappings addressing mode of practical operation complexity.The data administrator and the management method of based semiconductor storage medium provided by the invention are easy to implement, continue to use processor in the prior art to the operating physical interface of semiconductor storage medium and do not need to revise the Interface design of described processor, easy-to-use flexibly, be convenient to large-scale production.
Description of drawings
Fig. 1 is a prior art constructions synoptic diagram of the present invention;
Fig. 2 is the structural representation of first embodiment of the invention;
Fig. 3 is the example of a kind of forward mapping relations of first embodiment of the invention table;
Fig. 4 is the example of a kind of reverse mapping relations table of first embodiment of the invention;
Fig. 5 is the structural representation of second embodiment of the invention;
Fig. 6 is that second embodiment of the invention is unified logical storage flash memory encapsulation synoptic diagram;
Fig. 7 is the structural representation of third embodiment of the invention;
Fig. 8 is the data administrator encapsulation synoptic diagram of third embodiment of the invention;
Fig. 9 is the data management system new architecture and the former framework contrast synoptic diagram of fourth embodiment of the invention;
Figure 10 is the read data operating process synoptic diagram of fourth embodiment of the invention to storage medium;
Figure 11 is the data writing operation schematic flow sheet of fourth embodiment of the invention to storage medium;
Figure 12 is the parameter acquiring schematic flow sheet of fourth embodiment of the invention to storage medium.
The realization of the object of the invention, functional characteristics and advantage will be in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
With reference to Fig. 2, the structural representation of first embodiment of the invention is shown.The data administrator 100 of present embodiment is communicated by letter with processor 20, accepts and carry out the control command of processor 20, storage medium 30 is carried out data access operation, and execution result is returned to processor 20.The data administrator 100 of present embodiment comprises control module 101, external communication interface unit 102 and exterior storage interface unit 103, control module 101 is controlled external communication interface unit 102 and 103 work of exterior storage interface unit respectively, communicate by letter with processor 20 in external communication interface unit 102,103 pairs of storage mediums of exterior storage interface unit 30 carry out data access operation.
According to practical application request, present embodiment also can comprise the storage unit 104 (figure does not show) that cooperates control module 101 work, is used for required program file, firmware and/or the data of storage control unit 101 operations.
The control module 101 of present embodiment data administrator 100 adopts MCU or the CPU that has firmware; External communication interface unit 102 communicates by any one interface in UniNAND, USB (Universal SerialBus), SATA (Serial ATA Bus), PATA (Parallel ATA Bus), HDMI, eSATA, IEEE1394, PCIe, ceATA, SCSI, IDE, SD serial card interface, MMC serial card interface, MS serial card interface, CF card, X-D interface, pcmcia interface, the Radio interface protocols with processor 20.And 103 pairs of storage mediums 30 of said external storage interface unit are by any one or the multiple line data accessing operation that is combined in NAND interface, AG-AND interface, ONFI interface, OneNAND, the NOR interface.
Above-mentioned AG_AND interface is meant the interface that AG_AND Flash chip is adopted, and this chip is produced by the auspicious Sa science and technology of Japan; ONFI is the leading nand flash memory of Intel and the Interface Standard of control wafer, the existing ONFI1.0 standard of having issued; And the OneNand interface is meant the interface that OneNand Flash chip is adopted, and this chip is produced by Korea S Samsung.
The processor 20 of present embodiment support can be that host-processor such as CPU, system processor such as SOC, RISC, CISC, DSP or MCU or multimedia processor such as MP3, MP4, MP5, learning machine, mobile phone are used any one in the coprocessor etc.
The storage medium 30 of present embodiment support is any one or the multiple combination in the storage mediums such as nand flash memory, AG-AND flash memory, NOR flash memory, NROM, EEPROM, MRAM, PRAM, FRAM, Milliepede, OUM.
In the present embodiment, data administrator 100 also comprises firmware, and this firmware can be arranged in the control module 101, also can be arranged in the storage unit 104.Present embodiment carries out layering to unify addressing mode to firmware.When considering firmware design, distinguish the algorithm of the logic read-write and the storage medium management of basic read/write/wiping operation and external system, present embodiment is to realizing the program of the basic read/write of storage medium/wiping operation, be called MMD layer (memory management and driver, Memory Management ﹠amp; Driver); To the logic of realization external system and the program of storage medium 30 management, be referred to as MTL layer (storage medium conversion layer, Media Translation Layer).The supervisor call MMD layer interface of MTL layer carries out the access of data.Firmware also is provided with the interface processing layer, realizes the processing of firmware interface agreement, the order that be used to resolve, host-processor sends by interface, the transmitting-receiving of address date.Specifically, the interface processing layer is responsible for receiving order, address and data, and is responsible for giving MTL layer firmware handle these information analysis.The interface processing layer is given host-processor the data transmission that processing obtains according to the mode of agreement agreement simultaneously.
Wherein the MTL layer is provided with storage medium conversion layer interface, but be used for application program to external host processor provide one continuous, not bad piece, be the address space and the access interface of unit random access with the sector, i.e. the storage of logical block mapping.The supervisory routine that the MTL layer is set in the firmware is to be used to eliminate the deficiency that the inherent characteristic of the storage medium of part kind such as the physical mechanism of FLASH itself (transmitting control command, address and data message with the I/O interface) is brought, and allows the existing system application program in the mode that is similar to disk storage medium be carried out the logic read-write operation.The supervisory routine of MTL layer realizes tasks such as initialization, bad block management (management of static state and dynamic bad piece), abrasion equilibration, bad piece replacement, garbage reclamation, storage medium conversion layer interface.
The order that data administrator 100 receiving processors 20 send, according to the logic addressing mode in the order, the logical address of appointment in the order is converted to and storage medium 30 physical address corresponding fill order again, the piece of appointment in the storage medium 30 is made the data accessing operation.Logically, the storage medium conversion layer in data administrator 100 firmwares provides the interface of logic read-write, and firmware accepts also to resolve read-write operation or other supported operations, and is converted to the operations such as reading and writing, wiping of specific physical storage medium 30.
The above-mentioned specific practice that LBA (Logical Block Addressing) is converted to physical block address is to set up and safeguard mapping relations table between physical address and the logical address, and table carries out address mapping in view of the above.Owing to have bad piece in the middle of some storage medium, with the NAND flash in the flash memory (Flash Memory) is example, development along with NANDflash, technology by micron to deeply/ultra micro rice development, develop into MLC (Multi-Level Cell) even 4LC from SLC (Single Level Cell), the figure place of being stored on the same units area is also more and more, and the possibility that produces bad piece increases to some extent.The piece of mentioning herein (Block) is a notion based on n sector (Sector=512Byte+ redundancy), and the piece of semiconductor storage medium may be defined as (16K+512) byte, (32K+1k) byte, (64K+2k) byte, (128K+4K) Byte, (256K+8K) byte, (512K+16K) byte or the like capacity usually.
For guaranteeing that data access operation is not subjected to the influence of above-mentioned bad piece, should remove the mapping of these bad pieces, the piece that makes all logical address physical address corresponding point to has been piece entirely, be can work with stable, can select for use two kinds of structures to set up the mapping relations table for this reason.Fig. 3 illustrates the example of a kind of forward mapping relations of present embodiment table, and the forward mapping is meant with the logical address to be index number, is the mapping mode of index content with the physical address.Correspondingly, hurdle, a forward mapping relations table left side is a logical address, arranges in order; Right hurdle is a physical address, and the logical address on the corresponding left side is respectively listed the whole corresponding good pieces of physical address in the table in, bad piece physical address corresponding (this moment m=n that is not listed in the table.N is more than or equal to m if bad piece is listed in the table).And Fig. 4 is the example of a kind of reverse mapping relations table of present embodiment, and oppositely mapping is to be index number with the physical address, is the mapping mode of index content with the physical address, correspondingly, oppositely the left hurdle of mapping relations table is a physical address, arranges in order, but skips some bad pieces; Right hurdle is a logical address, and the physical address on the corresponding left side is therefore by non-series arrangement.The corresponding good piece of part physical address in this table, the corresponding bad piece of another part physical address is also done to identify so that distinguish (m is more than or equal to n in Fig. 4) with good piece especially.
On firmware structure, aforesaid way calls the MTL layer, and the MTL layer calls MMD layer access storage media 30 then.Interface processing layer, MTL layer, MMD layer are coordinated the logical operation of existing system to storage medium 30, or external host processor is converted to physical operations to physical block in the storage medium 30 by the USB/SATA interface to the logical operation of physical block in the storage medium 30.
Way and prior art that present embodiment is made the data accessing operation according to physical address to designated memory cell are similar, so do not give unnecessary details.Address mapping, mapping table maintenance and data access operation are all finished by processor 20 in the prior art, and present embodiment is finished above-mentioned part or all of work by the control module 101 of data administrator 100, has alleviated the processing burden of processor 20 greatly.
Above-mentioned physical addressing mode or physical block addressing (PBA, Physical Block Addressing) be meant with the design of physical storage device with make relevant a kind of geocoding rule.A physical address, corresponding fixing, an immutable physical memory cell, each physical memory cell all has its physical address corresponding.This geocoding mode usually all can be because of the volume change of physical storage device, manufacturing process variations and changing, its physical address calculates other a kind of address by a fixing mathematical formulae, is another form of expression of physical address of this equipment equally.And logic addressing or LBA (Logical Block Addressing) (LBA, Logic Block Addressing) are and the design and the irrelevant a kind of geocoding rule of manufacturing of physical storage device, and one or more memory devices can be used with a kind of geocoding rule.This geocoding rule is general can not to be changed because of the variation of the design of memory device and manufacturing process, and the real physical memory cell of its of a logical address correspondence can be fixing, also can be dynamic change.Usually the logic addressing can not calculate the physical address of its corresponding physical memory cell by a fixing data formula, and the logic addressing generally uses enquiry form or data base method to obtain the physical address of its corresponding physical storage unit.
Second embodiment is proposed on the first embodiment basis, Fig. 5 illustrates the structural representation of second embodiment, data administrator 110 according to the control command of processor 20 respectively (but timesharing and carry out simultaneously) first storage medium 31, second storage medium 32 are carried out data access operation until the N storage medium, and execution result are returned to processor 20.The data administrator 110 of present embodiment comprises control module 111, external communication interface unit 112 and exterior storage interface unit 113, control module 111 is controlled external communication interface unit 112 and 113 work of exterior storage interface unit respectively, communicate by letter with processor 20 in external communication interface unit 112, exterior storage interface unit 113 carries out data access operation to first storage medium 31, second storage medium 32 until the N storage medium respectively.Processor 20 can be that host-processor such as CPU, system processor such as SOC, RISC, CISC, DSP or MCU or multimedia processor such as MP3, MP4, MP5, learning machine, mobile phone are used any one in the coprocessor etc.
According to practical application request, present embodiment also can comprise the storage unit 114 that cooperates control module 111 work, is used for required program file, firmware and/or the data of storage control unit 111 operations.
The organization plan and the last embodiment of the control module 111 of present embodiment data administrator 110, external communication interface unit 112 and storage unit 114 are similar, so do not give unnecessary details.
The external communication interface unit 112 of present embodiment is to be connected with processor 20 from pattern-Slave Mode, and exterior storage interface unit 113 connects each storage medium by bus respectively with holotype-Master Mode, be connected until passage n with passage 1, passage 2 between external communication interface unit 112 and the exterior storage interface unit 113, independent storage medium of the corresponding connection of each passage, passage 1 corresponding first storage medium 31, passage 2 corresponding second storage mediums 32 are until the corresponding N storage medium of passage n n.Each passage can be universal serial bus or parallel bus, and the parallel bus width is chosen as 1,2,4,8,16,32,64,128 or 256 etc.
Preferably, the interface between present embodiment external communication interface unit 112 and the processor 20 adopts the interface standard of NAND Flash as physical interface, is the LBA pattern but utilize this physical interface to use logical mappings with extraneous agreement of carrying out data manipulation; Then be pure NAND flash interface between exterior storage interface unit 113 and each storage medium in addition, and the use physical mappings is the PBA pattern.
Under above-mentioned hyperchannel working method, each passage can adopt a kind of highway width in universal serial bus or the parallel bus, and each passage can be operated in different buses or highway width; Certainly adopt identical bus type and identical highway width can make simplicity of design, and can adopt identical semiconductor storage medium, whole performance can be relative higher with cost performance.
When external communication interface unit 112 transmits data, can adopt timesharing transmission mode and/or parallel transmission mode.Whether the performance of transmission data comprises access, read or write speed etc., is subjected to selected bus type and width and concrete storage medium, and changed by factor affecting such as the mixing of various buses and medium.Preferably when adopting identical bus type and width, adopt in each passage the parallel access mode can more simple and efficient rate, in the case, selected a plurality of storage medium is preferably unified model, for example is all the same 8Gbit Flash Memory of Samsung; If the storage medium of a plurality of producers can be compatible, also can mix the storage medium that uses each producer.If select the storage medium of different interfaces or the storage medium of different capabilities, when for example needing to connect NOR Flash, NAND flash or serial EEPROM, just should pay the utmost attention to the timesharing transmission manner and carry out data access.
The unified logical storage bus (hereinafter to be referred as UniNand) that provides present embodiment realizes the processing to n storage medium.Unified logical storage bus definition is: bus transfer is divided into master and slave end, and main the end initiated transmission, from the main sort command of end response, and passes through preparation/busy signal line and gives the master end with idle and busy feedback of status; Combination decision by many control lines is current be read data or write data, decision transmission be order, address, valid data, command parameter and/or packet etc.; The figure place (greater than the transmission of a data figure place) of data parallel transmission decides according to selected highway width.For example bus cycles can be transmitted the data of 1Byte (8bit) or 1WORD (16Bit).In fact unified logical storage bus is exactly to be defined as unified logical storage interface, it is between processor and the data administrator, it on physical signalling (electric) signal with the NAND interface compatibility, but be a kind of NAND interface of fully having expanded on agreement, compatibility comprises the multiple interfaces of NAND interface, it be a kind of be that input is converted to the agreement of physical mappings again with the logical mappings, different manufacturers, different capabilities, the physical block address mapping (mPBA) of a plurality of semiconductor storage medium chips of distinct interface agreement is converted to unity logic block address mapping (sLBA)
Specifically, the control command that differences such as manufacturer, technology, technology may cause storage medium is difference to some extent, and capacity volume variance may cause the address byte of storage medium beyond count identical.With the flash media is example, and Samsung K9F5608 series read data mode is: control command 0x00H, the address of 3 bytes adds read signal again.But K9F1G08 series read data mode is: control command 0x00H, the address of 4 bytes, control command 0x30H, read signal.Prior art realizes corresponding driving at the MMD layer at these differences.And the MMD layer integrates these differences and provides unified interface to the MTL layer, makes the MTL layer can visit the data of any physical address, and is indifferent to control command sequence and address word joint number.Though it should be noted that the application of the superiors all be with the sector or the page or leaf be that unit reads and writes data, but the used deposit data of the supervisory routine of general MTL layer is in redundant data region, so the supervisory routine of MTL layer need be carried out data manipulation to the redundant data region (SPARE AREA) of FLASH, so the MMD layer also needs byte address is provided and be not only the access ability of page address.
The unified logical storage bus of present embodiment can be supported multiple storage medium, (Physical Block Addressing) changes logic addressing mode (Logic BlockAddressing) into by original physical addressing mode, share in the prior art processor to the complex management of storage medium, alleviated the processing load of processor, but carry out bad block management, error-checking and the abrasion equilibration (Wear-leveling) of storage medium, processing such as ZoneTable by the control module 111 of present embodiment.
The basic physical interface modes of the compatible physically nand flash memory of the unified logical storage interface of present embodiment definition, CE_ promptly is provided (sheet choosing, low effectively), ALE (address latch enable signal), CLE (command latch enable signal), RD_ (read enable signal, low effectively), WR_ (writes enable signal, low effectively), signals such as FRB_ (being ready to or busy signal, busy) and BDB Bi-directional Data Bus DATA0-DATA7 for low.
The mode of operation of unified logical storage interface has multiple; comprise reading mode, WriteMode, data entry mode, data output mode, busy pattern, write-protect pattern and standby mode; model selection by sheet choosing, address latch enable signal, command latch enable signal, read enable signal, write enable signal and preparation and busy signal and determine that jointly its model selection rule is as shown in the table:
Unified logical storage interface is according to above-mentioned mode of operation, and the data interpretation that bus is received is found this corresponding order for order the time (CLE enables) from order predefine registers group.And then, promptly make different responses, and the order that receives is saved in the buffer area of appointment according to different orders according to carrying out on request immediately to defined the executing the task of this order in advance.
When the data interpretation of receiving when bus is the address (ALE enables), then preserve this address in preassigned buffer area.The data interpretation of receiving when bus is when being exactly data, preserve these data in preassigned data buffer area, write down the byte number of the data of receiving simultaneously, when inside temporarily can not receive data again, then immediately at FRB_ pin output low level signal (the busy meaning).
Utilize above-mentioned mode of operation, the unified logical storage interface of present embodiment can work in three levels, the complete compatible NAND interface of first level, simulation NAND flash accepts and carries out NAND flash orders such as page read, pageprogram, read id, block erase.Second level expansion transmission command, the address is a logical address, the data of transmission are operational order parameters needed or the data that need transmission.The order of expansion back transmission not only can be the operational order of NAND flash, also can be that scsi command can also be self-defining order.Tri-layer growth data district again on the basis of second level, the data by order and address phase transmission show that the data of this data transmission wrap for order.Order Bao Ze comprises information such as order, address, data, with certain format permutation.Array format can pre-define, and also can pass through parameter change.
The data administrator 110 of present embodiment may connect the storage medium of multiple manufacturer, multiple model simultaneously, need make initialization identification, arrangement, integration work to storage medium, identify all the bad pieces in each storage medium, set up administrative mechanisms such as bad block table, configuration information table, address mapping table.The specific operation process of above-mentioned identification, integrating semiconductor storage medium comprises:
Information such as the address of step 3, the good piece that detects and note the storage medium the inside and bad piece, number;
The related tables of step 5, record or storage flash memory is in storage medium.
Behind identification, integrating semiconductor storage medium, unified logical storage controller powers at every turn and reads in relevant information such as bad block table, address mapping table, configuration information table by the mode of making by oneself, and reads in information such as initializing variable, internal memory.
In the said process, step 3 can be selected for use several different methods to detect flexibly and note bad piece, and the concrete grammar of present embodiment identification, bad piece of correction is as follows:
Method one, general producer had all made special mark when storage medium dispatched from the factory, and can find out relevant bad piece according to the mark of this producer's definition;
Method two, at the not bad piece mark of storage medium, or it is used, under the inaccurate situation of bad piece mark, can wipe the content of storage medium the inside earlier, with some special data as 55, negating of AA or random number and it write storage medium and read out comparison again, finds out bad piece with this.
Method three, use ECC method of calibration detect bad piece.To the piece that needs detect, control module 111 calculates the data sample check code (producing check code in data transmission procedure automatically) of this data block size.Again the data sample of this data block size and check code are written in the piece that will detect of storage medium in the lump, from this piece, data are read out then, use data sample and its original check code of this data block size of ECC control verification, whether current data of reading are judged and obtained to control module 111 identical with the data that write last time, if inequality, 111 of control modules need to judge several places difference.The checking feature of supposing ECC is bit number N (N＞0), and promptly ECC can only the maximum bad figure places of verification be not more than the piece of N position; Suppose that the bit number that ECC finds that current block has been gone bad is m, then detected bad piece number can be divided into following three kinds of situations:
1, m＞N, this piece must be bad pieces, because exceeded the limit of power of ECC verification.
2, m=N, the checking feature of ECC reaches the limit of, if having bad position to produce again then can't verification.
3, m＜N, ECC have checking feature that the bad figure place complete verification of m position is come.
For better storage medium being managed, present embodiment also provides bad block management (Bad BlockManagement=BBM) mechanism, except when dispatching from the factory by the bad piece of benchmark, whether the piece that also can identify firm operation after storage medium is write or wiped by the state that reads storage medium degenerates or degenerates.When if but the ECC checking algorithm finds to have bad figure place and bad figure place to approach the figure place N of maximum verification then this piece degenerating or be about to become bad piece, be judged to be and degenerate if having no idea to correct then this piece, then need in bad block table, come out by mark with the ECC verification.Firmware provides the logical address that a kind of mechanism transmits the upper strata to be converted into the corresponding physical address of flash memory.When read data, find physical address corresponding according to logical address.When write data, obtain physical address according to the algorithm of firmware from logical address after, the corresponding relation of new logical addresses and physical address more.
After finding bad piece, present embodiment is damaged piece (Bad Block Replacement=BBR) the machine-processed first kind of situation handling bad piece of replacing: after certain one page write data of a certain toward storage medium, can know by reading the storage medium state whether write operation is successful, judge thus whether this piece is bad, if write operation is failed then this piece will be marked as bad piece, because certain one page is write the data that failure does not influence other page in same in the piece, so need be the copying data in these pages in new piece.Because part storage medium for example flash media has by page or leaf and writes, the characteristic of wiping by piece, a web update and will wipe this piece time the in to the flash media piece, also need to replace in other page copy to one new piece by piece, promptly just at last a page or leaf broken, also need whole is replaced.
To damage the piece mechanism of replacing handle second kind of situation of bad piece and be: if when reading certain one page, find this page bad figure place surpassed the scope that ECC can verification, judge that this page or leaf is bad, then the same principle also needs to carry out the replacement of bad piece
Damaging the piece mechanism of replacing handles the third situation of bad piece and is: even if ECC can verification come but near or reach the limit of verification, this piece can't have been come at any time in verification, maximum verification 4Bit of ECC for example, and gone bad 4bit this moment, also can in the light of actual conditions take measures and to replace or to delay and replace with reference to above-mentioned way immediately this page as accurate bad piece.
Because the part storage medium is the characteristic of flash media for example, write operation can only carry out in sky or the unit of having wiped, and with respect to read-write operation, the time of erase operation is very long.So present embodiment does not write data after being that the piece at data place is wiped again when new data more, but look for a new free block to write data, previous piece is labeled as gives up, system's free time, wipe those and be labeled as the piece of giving up, promptly reclaim the piece that these are rejected, be called garbage reclamation (Garbage Collection) mechanism.
Present embodiment also provides abrasion equilibration (Wear Leveling) mechanism, allow each piece that impartial erasable chance is arranged as far as possible, can not lose whole storage medium chip because certain piece or a spot of break down, prolong the storage medium life-span, improve the storage medium durability.The principle of abrasion equilibration mechanism is that new data are write the minimum free block that was used, the data that remain unchanged for a long period of time are copied in the more piece of other erasable number of times, and the less piece of the erasable number of times that the data that remain unchanged for a long period of time originally took then makes way for the data of frequent updating and uses.
Bad block table, address mapping table and configuration information table and first embodiment that above-mentioned steps 4 forms are similar, wherein configuration information table is the set of a firmware operational factor, it can be a string continuous byte, the value of the different variablees of different byte representations, write storage medium or other positions by storage medium volume production machine, storage medium reads in this allocation list at every turn when powering on, the value of variable in the initialization firmware.Can allow firmware support different manufacturers, different capabilities, the storage medium of different medium by regulating these parameters.Simultaneously can allow product show different performances, support different functions.By allocation list, can dispose the state of (programming) firmware, also by changing the state of firmware, might revise the value of configuration register simultaneously.By configuration information table, can make firmware and hardware combinations be operated in different patterns, thereby support different storeies, for the external world provides different interfaces, support different agreements simultaneously, show different functions.Configuration information table does not temporarily have concrete norm, and the common information that comprises at present has product information, product function adjusting and memory state parameter etc., and following table is the configuration information table example of present embodiment:
| Name | Side-play amount | Byte number | |
| Labeling head | |||
| 0 | 4 | Represent the beginning of this allocation | |
| Id number | |||
| 4 | 2 | The numeral of identification product | |
| Type of memory | 6 | 1 | The type of indicative of memory |
| The memory chip number | 7 | 1 | The physical magnitude of expression storer |
| The memory block number | 8 | 1 | Represent piecemeal (Block) number in the every storer |
| Encrypt | 9 | 1 | Whether expression supports |
| Capacity | |||
| 10 | 1 | The useful capacity of expression storer | |
| Coppy_back supports | 11 | 1 | Whether expression supports the copyback order |
| Simulation SRAM interface | 12 | 1 | Whether expression can use the SRAM interface accessing |
| Unified logical storage interface | 13 | 1 | The unified logical storage interface of expression |
Present embodiment is realized the back to integration, and data administrator and a plurality of storage medium are integrated into a functional unit even are integrated into chip or the module of multi-disc encapsulation (MCP).Can be referred to as unified logical storage flash memory (UniNAND Flash) after the integration, the storage medium that it seems ordinary on the surface, but the agreement and the mode of operation of the inside change fully, are a kind of novel memory devices that is different from storage medium before.When Data Management Unit and a plurality of storage medium are incorporated into a chip or an encapsulation (MCP encapsulation), its outward appearance and existing common storage are similar, but the agreement of interface but is the interface access protocol that follows logic and shine upon, just unified logical storage interface protocol.
With reference to Fig. 6; data administrator and storage medium are integrated the unified logical storage flash memory that encapsulation obtains; the unified logical storage interface that is connected with processor 20 comprises the ALE address latch enable signal; CLE command latch enable signal; the CE_ chip select signal, WR_ write signal, RD_ read signal; the WP_ write protect signal, FRB_ flash memory busy signal and DATA[0:n] data bus signal (n is 7 or 15 usually).
On the second embodiment basis, for satisfying the support to more different processors, the present invention proposes the 3rd embodiment.Fig. 7 illustrates the structural representation of data administrator the 3rd embodiment of the present invention, data administrator 120 is connected until M processor m with first processor 21, second processor 22 respectively, according to the control command of these processors first storage medium 31, second storage medium 32 are carried out data access operation (but timesharing or parallel work-flow) until the N storage medium respectively, and execution result is returned to first processor 21, second processor 22 respectively until M processor m.The data administrator 120 of present embodiment comprises control module 121, external communication interface unit 122 and exterior storage interface unit 123, control module 121 is controlled external communication interface unit 122 and 123 work of exterior storage interface unit respectively, communicate by letter until M processor m with first processor 21, second processor 22 respectively in external communication interface unit 122, exterior storage interface unit 123 carries out data access operation to first storage medium 31, second storage medium 32 until the N storage medium respectively.
The control module 121 of present embodiment comprises control module 1211, DMA control module 1212, verification module 1213, storage medium control module 1214 and bus, and these module co-ordinations realize the data double-way exchange between unified logical storage interface and the NAND_IF interface; Also can realize the data double-way exchange between USB (Universal SerialBus=USB (universal serial bus)) interface and the NAND_IF interface; Can also realize the data double-way exchange between other standard interfaces and the NAND_IF interface; Also can utilize the allotment of priority mechanism realization to a plurality of processors.
Exterior storage interface unit 123 comprises NAND interface controller (NIFC), the sequential of the responsible interface physical piece of NAND interface controller (NIFC) and level etc., as the needed power supply of storage medium such as 3.3V, 2.5V or 1.8V can directly be provided, the different bus data width of while supporting interface is as 1,2,4,8,16,32,64,128 or 256.And a kind of embodiment of unit 1214 storage medium control modules is exactly flash media controller (FMC), and it is responsible for the part of interface logic, and functions such as agreement and control are as read/write data, transmission order, query State or the like.
The external communication interface unit 122 of present embodiment comprises an above interface and bus, for example unified logical storage interface 1221 and general-purpose serial bus USB interface 1222; The processor type of exterior storage interface unit 123, storage unit 124, firmware and support and storage media types and last embodiment are similar, so do not give unnecessary details.
The external communication interface unit 122 of present embodiment with from pattern (Slave Mode) respectively with first processor 21, second processor 22 connects until M processor m, and exterior storage interface unit 123 connects each storage medium by bus respectively with holotype (Master Mode), use passage 1 between external communication interface unit 122 and the exterior storage interface unit 123, passage 2 connects (passage is the place of data stream process) until passage n, independent storage medium of the corresponding connection of each passage, passage 1 corresponding first storage medium 31, passage 2 corresponding first storage mediums 32 are until the corresponding N storage medium of passage n n.Each passage can be universal serial bus or parallel bus, and highway width is chosen as 1,2,4,8,16,32,64,128 or 256 etc.
When flash media controller FMC writes full data by NAND interface controller NIFC or whenever writes 256 or 512 bytes or be equivalent to a sectors of data in a page or leaf of NAND storage medium, the verification module 1213 of present embodiment generates a former check code automatically, the byte number of former check code is by concrete ECC algorithm decision (being no more than the length of redundant data region), as the Reed-Solomon algorithm, BCH algorithm etc.This check code is saved in the redundant data region of this page (Page) or follows back (follow at once in per 256 or 512 byte back and can improve flash reading and writing speed) in per 512 bytes immediately.And in the time of reading of data from the page or leaf of NAND Flash, per 256 or 512 bytes can generate a check code by verification module 1213, are referred to as new check code.In the time of verification, according to the check code that generated by verification module 1213 during write data last time, the former check code that is generated for this 256 or 512 byte of promptly reading former check code or read from 256 or 512 byte back from redundant area carries out the step-by-step XOR with new check code.If the XOR result is 0, then there is not mistake in expression or the mistake that can't detect occurred; If be not 0, then expression has made mistakes and can be by verification module 1213 and control module 121 error correction together.
ECC (the Error Correction Code) algorithm that adopts in the described verification module 1213 can be that Hamming code (Hamming code) is used in 512 byte verifications, 1 bit-errors, or Reed-Solomon sign indicating number (RS code) is often used in verification 2-6 bit-errors in 512 bytes, or BCH code (Bose-Chaudhuri-Hocquengham) is used for more than 512 byte verifications, 8 dislocation error codes, and these algorithms all are subjected to what the restriction of byte number of redundant area.
The unified logical storage bus that present embodiment provides has increased the support to various processors on the second embodiment basis; the mode of operation of unified logical storage interface includes but not limited to reading mode, WriteMode, data entry mode, data output mode, busy pattern, write-protect pattern and standby mode, model selection by sheet choosing, address latch enable signal, command latch enable signal, read enable signal, write enable signal, signal such as ready and busy signal determines jointly.
Present embodiment is realized the back to integration, promptly data administrator and a plurality of storage medium is integrated into a functional unit even is integrated into a chip or the module of MCP encapsulation.Can be referred to as unified logical storage flash memory after the integration, the storage medium that it seems ordinary on the surface, but the agreement and the mode of operation of the inside change fully, are a kind of new memory spares that is different from storage medium before.When Data Management Unit and a plurality of storage medium are incorporated into a chip or an encapsulation (for example MCP encapsulation), its outward appearance and existing common storage are similar, but the agreement of interface but is the interface access protocol that follows logic and shine upon, just unified logical storage interface protocol and/or USB interface agreement.The signal of interface comprises that address latch enables ALE, command latch enable CLE, chip enable CE_, reads enable signal RD_, writes enable signal WR_, ready or busy signal FRB_, write protect signal WP_, data bus DATA7-DATA0 (being assumed to be 8 bit wides, is DATA15-DATA0 in the time of 16) and usb signal USBD+ and this a pair of analog difference signal line of USBD-.
With reference to Fig. 8; data administrator is encapsulated separately; when data administrator is connected with storage medium; its interface comprises the iALE address latch enable signal, iCLE command latch enable signal, iCE_[0:m] m chip/channel selecting signal; the iWR_ write signal; iRD_ read signal, iWP_ write protect signal, iFRB_ flash memory busy signal and iDATA[0:n] data bus signal (among the figure be example with n=7).Simultaneously; unified logical storage interface is used for being connected with first processor 21; unified logical storage interface comprises ALE address latch enable signal signal; CLE command latch enable signal; the CE_ chip select signal, WR_ write signal, RD_ read signal; WP_ write protect signal, FRB_ flash memory busy signal and DATA[0:n] data bus signal (among the figure be example with n=7).USB interface is used for being connected with second processor 22, and USB interface is provided, and signal comprises USBD+ and USBD-.Can also comprise other interface standards, be connected, signal is provided with other processors.
Present embodiment realizes that the step of concrete write operation is as follows:
After step 2, the interrupt response, unified logical storage bus is resolved the write operation order of receiving, and is different with the mode of operation of flash memories because this operation belongs to logical write operation, and firmware can convert it to flash memory particular manner of operation.When write operation arrived flash memories, if piece (Block) position of being write includes valid data, then new data can't be write direct, and change step 3 in this case over to; If the piece that writes does not have occupied words, data of writing direct and receiving then at this new piece;
Present embodiment realizes that the step of concrete read operation is as follows:
The order in the buffer zone is resolved in the interruption of step 2, the unified logical storage interface of processor response.Owing to receive that read operation and flash memory are different, so firmware can convert it to the read operation of storage medium array.The address that read command is read is a logical address, and firmware needs the conversion between completion logic address and the physical address.Control module 121 is carried out the read operation of storage medium arrays, reads the data in the physical address after the conversion and is kept in the buffer zone.In this process, FRB_ is in low level, and indication control module 121 is in busy state;
After step 3, FRB_ recovered high level, unified logical storage interface was in data output mode, and control module 121 is write the data in the buffer zone on the unified logical storage interface under the triggering of the negative edge of each RD_.
Mechanism such as the process of the principle of work of present embodiment, initialization and identification, integration storage medium, method of calibration, bad block management and replacement, abrasion equilibration are all similar with last embodiment, so do not give unnecessary details.
Now propose the 4th embodiment, propose data management system based on the foregoing description.Shown in Figure 9ly go out the data management system new architecture that present embodiment proposes and contrast synoptic diagram with former framework.In former framework 1000, set up processor system 1100 by processors such as SOC, comprise application layer (the superiors) in its software architecture, the middle level comprises operating system and file system, bottom then comprises MTL layer and MMD layer, and the upper strata cooperates the back to drive semiconductor storage medium 1200 by bottom with the middle level.And in the new framework 2000, comprise application layer (the superiors) in the software architecture of processor system 2100, the middle level comprises operating system and file system, and bottom then drives for unified logical storage, and the upper strata cooperates the back to drive the data administrator 2300 of present embodiment by bottom with the middle level.Data administrator 2300 is used for reference the partial function of coming to realize processor system 2100 to the bottom functions of modules MTL of original processor system 2100 and MMD, realizes driving semiconductor storage medium 2200.Data administrator 2300 in the present embodiment can adopt aforementioned first embodiment, second embodiment or the 3rd embodiment to realize, so do not give unnecessary details.
Because program is deposited with ROM or NOR flash and so in the prior art, so startup and working procedure also carry out in ROM or NOR flash.Yes for its advantage simply, starts soon, and this also is traditional way.But the new problem that produces has a lot, particularly to present handheld device, shared space and and high cost all be the problem place of maximum.Therefore how to utilize the NAND Flash of store data to deposit program, but also can just have the space of saving, save advantages such as cost and power saving by working procedure.After the method that adopts present embodiment, above problem has just solved fully.
After SOC (containing multimedia processor) and unified logical storage flash memory power on, the unified logical storage bus of SOC wait is sent Ready signal (being standby ready signal), in case unified logical storage bus is sent the Ready signal, the hardware of SOC or its inner built-in ROM (comprise MaskROM, OTP, EPROM, EEPROM, NOR Flash etc., generally smaller) can provide standard N AND FLASH read command and address signal, the hardware sequential machine of the logical storage of seeking unification flash memory moves the storage area (being generally SRAM or DRAM etc., can be inner or outside at SOC) of the executable program that the driver system of downloading to of the startup sign indicating number of SOC (Boot-up code) and the unified logical storage flash memory of driving sets in advance automatically for processor.
Each basic long measure for downloading is the long measure that 512Byte or 2Kbyte etc. pre-define, and the length of Boot code can be one or more basic long measures.Boot Code comprises the required part or all of run time version of SOC system initialization, also comprises the driver of unified logical storage flash memory, also comprises system program (SystemProgram) and data that next step will load from unified logical storage flash memory.
The code length of being downloaded can set in advance or makes an appointment by unified logical storage flash memory.Download finishes back SOC can be programmed counting pointer PC sensing Boot code place, begin to carry out this section code, Boot Code begins the SOC system is carried out initialization like this, and the driver that can call unified logical storage flash memory simultaneously continues from unified logical storage flash memory the loading system program to executable storage areas such as SRAM or DRAM.
After loading System Program finishes, can jump to System Program executive routine immediately, at this moment System Program can be used as a memory device to unified logical storage flash memory.Promptly visit the data storage areas of unified logical storage flash memory by unified logical storage driver.And be to adopt the mode of logical mappings (LBA) to carry out, simpler than the mode access of physics, convenient and efficient, and compatible good.The size of the packet of its access can be based on 512Byte or its multiple, also can be that 528Byte or its multiple carry out access.
When unified logical storage flash memory had startup (Boot-up) function, it had the zone of three store data at least.Be Boot Code (comprising unified logical storage driver) zone, system's main program code (System Program) district (being used as deposit data), and clear data zone (the most basic data storage areas).
After adopting unified logical storage bussing technique, also have a very important situation to be greatly improved, prior art is as Flash Memory (particularly MLC Flash) in the time of can not guaranteeing that zero piece (Block) does not have bad bit to exist fully, being Boot up or starting from Flash is exactly a very difficult thing, and Default is exactly the zero page or leaf (Page) of zero piece during startup.Because program can not have any mistake, otherwise will cause catastrophic consequence when having bad position to exist.Present embodiment has solved this problem, the serious consequence of having avoided bad position to cause.
Figure 10 illustrates the read data operating process of present embodiment to storage medium, processor is when read data specifically, provide earlier start logical sector address and to read sector number, read the sector one by one then, whether ready the centre have state to prepare judgement, till running through all sectors.
Figure 11 illustrates the data writing operation flow process of present embodiment to storage medium, processor is when write data specifically, the sector number that start logical sector address is provided earlier and will writes, the sector writes one by one then, whether ready the centre have state to prepare judgement, till having write all sectors.
Figure 12 illustrates the parameter acquiring flow process of present embodiment to storage medium, specifically, when processor obtains the parameter of unified logical storage bus standard, the initial logical address that provides parameter to deposit earlier, carry out reading of parameter one by one then, till running through all parameters.It is information and ID itself of capacity, hardware version, firmware version, FlashMemory producer and the chip-count of external flash memory etc. that unified logical storage bus apparatus ID number, effective logic sector number are arranged in the middle of these parameters.
The above only is the preferred embodiments of the present invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (10)
1. the control command of at least one processor is accepted and carried out to the data administrator of a based semiconductor storage medium, and at least one storage medium is carried out data access operation, comprising:
External communication interface unit with described at least one processor communication;
Described at least one storage medium is carried out the exterior storage interface unit of data access;
Control the control module of external communication interface unit and the work of exterior storage interface unit respectively.
2. data administrator according to claim 1 is characterized in that, also comprises:
The unification of data access addressing mode is the firmware of logic addressing mode.
3. data administrator according to claim 2 is characterized in that, described firmware comprises:
Described at least one storage medium is carried out the memory management and the driver layer of master data accessing operation and management.
4. data administrator according to claim 3 is characterized in that, described firmware also comprises:
Realize the logic and the storage medium management of external system, provide the storage medium conversion layer of logic addressing mode interface to described at least one processor, described storage medium conversion layer calls described memory management and driver layer is carried out data access operation to described at least one storage medium.
5. data administrator according to claim 4 is characterized in that, described storage medium conversion layer to a described storage medium carry out that initialization, bad block management, abrasion equilibration, bad piece are replaced, one or more operations in the garbage reclamation.
6. data administrator according to claim 2 is characterized in that, also comprises:
The interface that is used for being connected with processor adopts unified logical storage bus, adopts the mapping of logical address piece on agreement, by logical address and physical address translations, realizes the access to the storage medium of physical address piece mapping.
7. data administrator according to claim 6 is characterized in that, the interface signal standard that is connected with described at least one storage medium comprises one or more in NAND interface, AG-AND interface, ONFI interface, OneNAND, the NOR interface.
8. data administrator according to claim 6 is characterized in that, described data administrator provides startup or moves required data and/or information to described processor according to the control of described processor.
9. a data managing method is used for the control command that at least one processor was accepted and carried out to data administrator, and at least one storage medium is carried out data access operation, comprising:
The step of receiving processor control command;
Logical address is converted into the step of physical address;
Described storage medium is carried out the step of data access operation according to described physical address.
10. data managing method according to claim 9 is characterized in that, the step of described receiving processor control command and/or adopt unified logical storage bus to carry out to the step that described storage medium carries out data access operation.
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