20090738: 九、發明說明·· 【發明所屬之技術領域】 、本發明是關於一種測試裝置、測試方法及元件的製造 ，法:特別是關於一種對元件進行測試的測試裝置，利用 ^冽忒裴置對元件進行測試的測試方法，及利用該測試 置進行測試並分選之元件的製造方法。 、 【先前技術】 在習知技術巾，當對半導體·等制試元件進 ，、’已知有-種藉由對被測試元件施加規定的測試;J ，技並測定來自被測試元件的響應信號，從而狀被ς 好壞的方法。例如，當在_試元件上施加根據^ 自===測試信號時，藉由判定來 ^的期雜—致，而對被職元件的動作是否正常進ί 利文獻_如下述專 裳置中，被測試元件和裝置主，^文獻1所記述的測試 方式進行連接。因此，在被測所謂的單傳輸配線 =來自被概物_物_=== 號公Γ讀1 :日轉解物奴如細 上述的測試裝置在切換 _ 、被H件的終端的輪出入 200907385 之測試時，即使接著應輸入到被測試元件的測試信號與從 被測試元件所輸出的響應信號，在配線上形成重疊，也可 藉由從該響應信號中抵消響應信號所包含的測試信號的成 分’而正確地偵測本來的響應信號。因此，上述的測試裝 置在進行例如被測試元件的記憶體的讀出/寫入切換測試 時’可在偵測與從記憶體所讀出的讀出數據相稱的讀出信 號期間，將與應寫入該記憶體中的寫入數據相對應的寫入 信號’不需待機時間而施加在被測試元件上。 但是’上述測試裝置由於具有偵測信號的比較處理及 生成該比較處理中所利用的比較信號的電路，所以存在全 體的電路構成變得複雜之課題。而且，上述的測試裝置在 對具有不同阻抗的被測試元件進行測試的情況下，需要使 被測試元件的阻抗和傳送線路自身的阻抗相匹配。 【發明内容】 因此，本發明的目的是提供—種能夠解決上述課題的 測試裝置、測試方法及元件的製造方法。該目的是藉由申 ϋ 料利範圍中的獨立項所記述之特徵的組合而達成。而 且，從屬項規定本發明的更加有利的具體例子。 本發明的第1形態提供一種測試襄置，為一種對被測 試元件進行賴關試裝置，包括：信錄出部，其通過 第1配線而與被測試元件的終端相連接’並在終端上施加 測^言號；信號侧部，其通過與信號輸出部共通的第i :線==接甘並對從終端所輸出的響應信號進行债 測，以及U ’其根據將響應信號與期待值進行比較的 200907385 結果’而判定響應信號的好壞；而且，信號輪出部在從终 端所輸出的響應信號通過第i配線而向信號偵測部進行傳 播的同時，在終端上施加測試信號；而且，判定部對信譽 偵測部所制的響應錢巾的_難仙重合的部^ 禁止不良判定。 而且，本發明的第2形態提供一種測試方法，為— 利用測試裝置來對被測試元件進行測試的測試方法，包 括j號輸出階段’其在被測試元件的終端上施加測試信 號；信號偵測階段，其通過與測試信號共通的配線，對^ ^端輪出的響應信號進行偵測；以及判定階段，其根 響，信號與期待值進行比較的結果，而欺該響應信號的 好壞；而且，在錢輸出階段，是在從終端所輸出的塑應 信，進行_的同時，在終端上絲測試錄；而且 判定階段，是對在錢_階段所侧的響應信號中的盘 測試信號相重合的部分，禁止不良判定' 、 而且’本發明的第3形態提供一種製造方法為一種 製造元件的製造方法，包括：製造階段，其製造前述元件； 、及刀選卩0段’其利用本發明的第丨形態所記述的測試裝 置，對所製造的元件進行測試並分選。 另外上述發明的概要並未列舉本發明的必要特徵的 王0P，匕們的特徵群的子集也可又形成發明。 【實施方式】 ,以下，通過用於實施發明的最佳形態（以下稱作實施 开/態）來對本發料行綱，但以下的實施形態並不對關 200907385 於申請專利範圍的發明進行限定，而且，實施形態中所說 明之特徵的組合的全部也未必是發明的解決方法所必須 的0 圖1所示為關於本發明的實施形態之測試裝置丨〇的全 體構成。測試裝置10為對1C或LSI等被測試元件600進 行測試的裝置，如圖1所示，包括測試頭40、性能板5〇、 控制裝置和記憶體控制部80。測試頭4〇包括時序產生 器20、圖案產生器30、判定部60、信號輪出部1⑻、信號 偵測部300、阻抗匹配部400及基準電壓施加部5〇〇。性能 板50具有例如1C插座（未圖示）’用於搭載被測試元件 600。該麟裝置1G藉由實行勤規定_試程式，而在 被測試元件_上施加根據與剌馳式域應的測試圖 案所生成_試信號’且根據來自該被職元件獅的響 應信號的賴值和根據上勒m目$的 果，來判定被測試元件600的好壞。 控制裝置7G向測朗4Q及記鐘控20090738: IX. INSTRUCTION DESCRIPTION · TECHNICAL FIELD OF THE INVENTION The present invention relates to a test apparatus, a test method, and a component manufacturing method, and more particularly to a test apparatus for testing components, using A test method for testing a component, and a method of manufacturing a component that is tested and sorted using the test. [Prior Art] In the conventional technical towel, when testing components such as semiconductors, etc., it is known that a predetermined test is applied to the device to be tested; J, and the response from the device under test is measured. The signal, and thus the way it is smashed. For example, when a test signal according to ^== is applied to the _ test component, it is determined whether the action of the active component is normal by judging the period of the error, and the document is as follows: The device under test is connected to the device master and the test method described in Document 1. Therefore, in the so-called single transmission wiring to be measured = from the general object _ thing _ === Γ 1 : : : : : : : : : : : : : : : 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述In the test of 200907385, even if the test signal to be input to the device under test and the response signal output from the device under test are overlapped on the wiring, the test signal included in the response signal can be cancelled by the response signal. The component 'is correctly detected the original response signal. Therefore, the above test device can perform a read/write switching test of the memory of the device under test, for example, during the detection of a read signal commensurate with the read data read from the memory. The write signal corresponding to the write data written in the memory is applied to the device under test without waiting time. However, since the above test apparatus has a circuit for comparing the detection signals and a circuit for generating the comparison signals used in the comparison processing, there is a problem that the overall circuit configuration is complicated. Moreover, in the case where the above test apparatus tests the elements to be tested having different impedances, it is necessary to match the impedance of the elements to be tested with the impedance of the transmission line itself. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a test apparatus, a test method, and a method of manufacturing an element capable of solving the above problems. This objective is achieved by a combination of features described in separate items in the scope of the application. Moreover, the dependent items specify a more advantageous specific example of the invention. A first aspect of the present invention provides a test apparatus for performing a test device for a device under test, comprising: a letter recording portion that is connected to a terminal of the device to be tested by a first wire and is on the terminal Applying a test signal; the signal side portion, through the ith: line == common to the signal output portion, and performing a debt test on the response signal output from the terminal, and U' based on the response signal and the expected value Comparing the result of the comparison of "200,907,385" and determining whether the response signal is good or not; and the signal wheeling portion applies a test signal to the terminal while the response signal outputted from the terminal propagates through the ith line to the signal detecting portion; Further, the determination unit prohibits the failure determination of the portion of the response money sheet that is made by the reputation detecting unit. Moreover, the second aspect of the present invention provides a test method, which is a test method for testing a device to be tested by using a test device, including a j-stage output stage, which applies a test signal to a terminal of the device to be tested; In the stage, the signal corresponding to the test signal is used to detect the response signal of the round end; and the determination stage, the root signal, the result of comparing the signal with the expected value, and the quality of the response signal is deceived; Moreover, in the money output stage, at the same time as the plastic response letter output from the terminal, while the _ is being performed, the test is recorded on the terminal; and the determination phase is the disk test signal in the response signal on the side of the money_phase. In the third aspect of the present invention, a manufacturing method is a manufacturing method for manufacturing a component, comprising: a manufacturing stage in which the above-described components are manufactured; and a knife-selection section The test device described in the third aspect of the present invention tests and sorts the manufactured components. Further, the summary of the above invention does not exemplify the essential features of the present invention, and a subset of our feature groups may also be invented. [Embodiment] Hereinafter, the present invention will be described in terms of the best mode for carrying out the invention (hereinafter referred to as "implementation of the open state", but the following embodiments do not limit the invention of the patent application scope. Further, all of the combinations of the features described in the embodiments are not necessarily required for the solution of the invention. Fig. 1 shows the overall configuration of the test apparatus 关于 according to the embodiment of the present invention. The test apparatus 10 is a device for testing a device under test 600 such as 1C or LSI. As shown in Fig. 1, the test device 10 includes a test head 40, a performance board 5, a control device, and a memory control unit 80. The test head 4 includes a timing generator 20, a pattern generator 30, a determination unit 60, a signal wheeling unit 1 (8), a signal detecting unit 300, an impedance matching unit 400, and a reference voltage applying unit 5A. The performance board 50 has, for example, a 1C socket (not shown) for mounting the device under test 600. The lining device 1G applies a _test signal generated according to a test pattern corresponding to the kinetic domain on the device under test _ by the implementation of the stipulation _ test program, and according to the response signal from the lion of the employed component The value and the result of the upper element M are used to determine the quality of the device under test 600. Control device 7G to test 4Q and clock control
於對被職元件_進㈣試的較触式 20為產生週期信號的電路，其中， 汁座玍 成測試圖案的特定的反復週期。由:序產""^有用於生 週期信號是供關_產^ = ^ 所產生的 = 的上述蚊的程式，並根 號，生成_案。: 號輸出部丨⑼。該職”為 200907385 列的邏輯_ ’包含了為了對被測試元件_ 賦予該被測試元件__試信號所應具有之圖案數ς。 信號輸出部100通過第i配線51而與被測試元 的終端620進行電氣連接。該信號輸出部1〇〇且 形器i20、可變延遲電路14〇、驅動器16〇及第】配線侧 阻180，以生成施加在被測試元件㈣上的測試信號。波 形成形器12G根據從圖案產生!130所發送的測試圖案而生 f 成測試信號，並發送_動器_。可變延遲電路⑽對 波形成形器120所生成的測試信號，依據測試圖案而賦予 預先設定之大小的延遲。驅動n⑽使從波形成形器12〇 所發送❹m信號，騎第丨配線51 _加至被測試元件 600的終端_。在這裏，賴信號為具有肖測試圖案的每 位元的邏輯值相對應之電壓位準的脈衝信號。測試信號 在例如指定的時序，在與測試圖案的邏輯Η及邏輯L的各 個相對應之大小的電壓值之間進行變化。第i配線侧電阻 180具有與第1配線51的特性阻抗的實部電阻值相等之大 ϋ 小的電阻值。因此，使信號輸出部100的輸出阻抗和第！ 配線51的特性阻抗相匹配。 知號偵測部300通過與信號輸出部1〇〇共通的第j配 線51，而與被測試元件6〇〇的終端62〇相連接。該信號偵 測部300具有比較器320、閂鎖電路34〇及可變延遲電路 360 ’並對從被測試元件600的終端62〇通過第呈配線5ι 所施加的響應信號進行偵測。比較器32〇在接收到響應信 號後，對該響應信號的邏輯值進行偵測。這裏，對從時序 11 200907385 ° 賦予該閂鎖電路340的週期信號，利用可變延遲 库 362來職予規定的相位量延遲。閂鎖電路340在從時 器2〇所給予的週期信號的邊緣時序，取入該比較器 2〇所债’則的響應信號的邏輯值。閃鎖電路340將所取入 的響應彳§號的邏輯值發送到判定部60。 阻抗匹配部400通過與第1配線51不同的第2配線 =，而^被測試元件6〇〇的終端62〇進行電氣連接。該阻 抗匹配部4GG具有第2配線侧電阻·。第2配線側電阻 420為了使與被測試元件600的終端620相連接的第1配 線51及第2配線52合在一起之傳送線路的特性阻抗，與 被測試兀件600的終端620所具有（被測試元件600侧） 的阻抗相匹配’而具有適當大小的電阻值。第2配線侧電 阻420為可將例如電阻值的大小設定為規定值的可變電阻 器，是依據被測試元件6〇〇的終端620所具有的阻抗而設 定電阻值的大小。 基準電壓施加部500是與第2配線52的一端形成電氣 連接。該基準電壓施加部500在將第1配線51及第2配線 52合在一起的傳送線路上，施加大小Vth的定電壓。因此， 從仏號輸出部1〇〇施加在被測試元件600的終端620上的 上述測試信號，及從被測試元件6〇〇的終端620通過第1 配線51而賦予信號偵測部3〇〇的上述響應信號，具有以例 如大小Vth的電壓為基準的脈衝波形。另外，上述第1配 線51及第2配線52也可使至少一部分為同轴電纜。 判定部60對根據從圖案產生器30所發送的測試圖案 12 200907385 圖案的期待值相一致 ，值是否與挪試 記憶體控制部8。是與被測試壞。 電乳連接。記憶體控制部80在從 7、，ά_進行 f 被測試元件600進行測試的上:裝置70發送用於對 該測試程式。記憶體測試程式時，執行 序，對被測試元件 所指定的時 51而夕讀體控制部8G被賦予與通過第1配線 1二給予信號侧部3〇〇的上述響應信號相同之響應信 響應信號進行侧。記憶體控制部8G根據該^ j就的偵測結果，使對被測試元件_的終端63〇供仏 .j 上迷命令的時序及在信號部刚上施加測試信號的時序;3 只延遲規定的間隔。 如以上所說明的，測試裝置10可藉由執行上述規定的 測試程式而判定該被測試元件600的好壞。另外，記憶體 控制部80在對被測試元件_進行測試的情況下，也可根 據用戶所指定的時序，而對被測試元件6〇〇供給必要的指 令。 測試裝置10在對被測試元件6〇〇内的記憶體640進行 測試的情況下，按照例如記憶體640的記憶區域的讀出测 13 200907385 -----χ--- 试及該§己憶區域的讀出/寫入切換測試的順序而實施測 試。以下對各測試具體地進行說明。 圖2為利用測試裝置1 〇所進行的記憶體640的記憶區 域的讀出測試之時序圖。在圖2中，（a)、（B)及（C) 的各信號波形為圖1中利用A、B及C的符號以及箭形符 號所示之位置的波形。亦即’測試裝置10的（A)的波形 為信號輸出部100的輸出端的信號波形，（B)的波形為 被測試元件600的終端620的信號波形，（C)的波形為 信號偵測部300的輸入端的信號波形。 在被測試元件600為例如DRAM的情況下，在被測試 元件600中的記憶體640之記憶區域的讀出測試中，記憶 體控制部80對被測試元件600的終端630供給讀出指令。 該讀出指令包含：指定該記憶體64〇的列地址，並使記憶 體640的被指定的那一列的記憶體單元有效(active)化之指 令；指定行地址，並讀出有效化的那一列的記憶體單元中 的、被指定的行的數據之指令。當從記憶體控制部80對被 測試元件600供給該讀出指令時，讀出被測試元件6〇〇内 的記憶體640中的所指定之地址的數據，並作為讀出數據 711S而從被測試元件6〇〇的終端62〇輸出。該讀出數據 711S如圖2所不，是具有以例如大小為Vth的電壓作為基 準且正負的大小相等的振幅，並從被測試元件600的終端 620在時間Tr期間輪出之數據信號。 ^ 從被測試元件600的終端620所輸出的讀出數據 711S，通過第1配線51而傳送並由信號偵測部3〇〇進行 14 200907385 偵測。此時，從被測試元件600的終端620到信號偵測部 300為止之讀出數據7US的傳送時間為ΔΤ1 。而且，此時 由於從信號輸出部100未輪出信號’所以信號輸出部1〇〇 的輸出端的電壓為Vth，保持一定。因此，該讀出數據711S 從被測試元件600的終端62〇輸出，並在ΔΤ1後於信號偵 測部300處原樣不變地被偵測。判定部6〇在將與讀出數據 7iis對應的數據’於本讀出測試之前寫入到記憶體64〇的 { ' 上，指定的地址中時的該數據予以儲存，並根據該數據的 邏輯值和在信號偵測部300中所偵測的讀出數據 711S 的 邏輯值之比較結果，判定該讀出數據7US的好壞，且根 據該判定結果，判定記憶體64〇中的上述一地址是否適當 地存儲著數據。 圖3所不為該測試裝置1〇所進行之記憶體64〇的記憶 區域的讀出/寫入切換測試的時序圖。在圖3中，（A)、 (B)及（C)的各信號波形與圖2相同，為圖】中的a、 B及C的符號以及箭頭所示之位置的波形。 U 在記憶體64G的記憶區域的讀出/寫人切換測試中，記 隐=控制部80對被測試元件6〇〇 #終端63〇供給讀出指 令。該讀出指令是與上賴$測試巾記憶體控制部8〇所供 給的讀出指令相同的指令。因此，當從記憶體控制部8〇 =被測試疋件600供給上述讀出指令時，讀出該記憶體64〇 的與上述4出K所指定的地址相同之地址的數據，並 作為讀出數據712S而從被測試元件_的終端62〇輸出。 ^賣出數據712S如圖3所不’為與例如上述讀出數據7ns 15 200907385 相同的數據信號。 另外’在讀出/寫入切換測試中，記憶體控制部8〇所 供給的讀出指令，是與上述讀出測試中記憶體控制部8〇 所供給的讀出指令不同的指令。在這種情況下，讀出與例 如被測試元件600内的記憶體64〇中的上述讀出測試中所 指定之地址不同的地址的數據。 記憶體控制部80在供給該讀出指令後’再對被測試元 件600的終端630供給寫入指令。信號輸出部100將應寫 入被測試元件600的記憶體64〇中的寫入數據721S，在規 定的時序施加至該被測試元件60〇的終端62〇上。在被測 試元件600的終端62〇上所施加的寫入數據72is如圖3 所示，具有以例如大小為Vth的電壓作為基準且正負相等 的大小的振幅，並從信號輸出部1〇〇在時間Tw期間輸出 之數據信號。 另外，在本實施形態中，寫入數據721S的脈衝的數 目及週期是與上述讀出數據712S相等，但並不限定於此。 而且，寫入數據721S是一種信號以用於在寫入測試中， 對被測試元件600内的記憶體640的指定的地址，測試是 否正確地寫入與該寫入數據721S相對應的數據，該寫入 數據721S的振幅也可小於上述讀出數據712S。 從記憶體控制部8 0對被測試元件600所供給的上述寫 入指令，包括：指定記憶體640的列地址，並使記憶體640 的被指定的那一列的記憶體單元有效化之指令；以及指定 行地址，並向該有效化的那一列的記憶體單元中的、被指 200907385 定的行寫入數據之指令。當對被測試元件6〇〇供給上述寫 入指令，且在被測試兀件600的終端62〇上施加寫入數據 721S時，該寫入數據721S被寫入到被測試元件6〇〇内的 記憶體640的指定地址中。 另外，信號輸出部100在被測試元件600的終端62〇 上施加寫入數據721S時的時序’亦即上述規定的時序， 是與記憶體控制部80對被測試元件6〇〇供給該寫入指令時 f' 的時序相對應地被没疋。上述規定的時序是設定為與例如 對被測试元件600的終端630供給上述寫入指令時之時序 相同的時序。而且，上述規定的時序的設定是設定成下述 方式，即，被測試元件600輸出該讀出數據712S以後， 以被測試元件600的規格所確定的最小間隔，使寫入數據 721S施加在被測試元件600的終端62〇上。另外，在本實 施形態中，上述最小間隔為△ T2。因此，在被測試元件6〇〇 的終端620處，如圖3所示，該讀出數據712S在時間Tr 期間從終端620輸出後，只是經過的間隔，而在時間 (/ Tw期間使寫入數據721S施加在終端620上。 在記憶體640的指定之地址上所寫入的寫入數據 721S，藉由在上述讀出/寫入切換測試之後再實施追加的讀 出測試，可作為讀出數據而讀出，並在信號偵測部3〇〇 ; 進行偵測。判定部60根據在上述追加的讀出測試中從該呓 憶體640所讀出的寫入數據721S的邏輯值，而判定^ 述讀出/寫入切換測試中是否向記憶體64〇中正確地寫入 了寫入數據721S，且從該結果來判定記憶體64〇的上&一 17 200907385 地址是否具有適當的讀出/寫入切換特性。 這樣’測試裝置ίο藉由在上述讀出測試之後，按照讀 出/寫入切換測試的順序而實施測試，可在信號偵測部300 中’與寫入數據721S在時間上不重疊地偵測從被測試元 件600内的記憶體640中所讀出的讀出數據711S。而且， 測試裝置10在上述讀出/寫入切換測試中，藉由在讀出該 記憶體640的數據之後，以被測試元件6〇〇的規格所確定 的最小間隔，而在記憶體64〇中寫入數據，藉此可判定記 憶體640是否具有適當的讀出/寫入切換特性。 另外，在上述s賣出/寫入切換測試中，寫入數據 從信號輸出部100通過第i配線51到施加在被測試元件 600的終端620上為止之該寫入數據721S的傳送時間在 從被測試元件_的終端_聽號制部為止之傳 送線路的長度與從信號輪出部1G0到被測試元件600的终 2:20為止之傳送線路的長度大致相同的情況下，從信號 輸出部1〇〇到被測試元件6〇㈣終端62止之 ϊίΓ 號測部300之間的傳送線路的長度，盘從 ^輸出部100及信號摘測部細到被 端620為止之傳送線路的長度相比非常小 而從信錄ώ部1GG輪狀後，幾乎沒麵時: 摘測部300進行债測。 、由仏就 而且，在信號偵挪部3〇〇中，是從被 終端㈣所輸出的讀出數據在只延遲△ η而輪入^ 18 200907385 後，再輸入從信號輸出部100所輸出的寫入數據721S。因 此，在彳§號偵測部300中，如圖3所示，與在時間Tr’期 間所偵測的讀出數據712S及在時間Tw，期間所偵測的寫 入數據721S —起，還偵測到讀出數據712s的一部分與寫 入數據721S的一部分相重合之信號成分（以下稱作〔重 疊成分731S〕）。因此，判定部6〇在判別信號偵測部3〇〇 中所偵測的續出數據712S的邏輯值的一部分為與重疊成 分731S相對應的邏輯值之情況下，不管與該重疊成分731S 對應的邏輯值是否為不適當的值’都禁止該被測試元件 600為不良的判定。藉此，即使在由於讀出數據712S的一. 部分和寫入數據721S的一部分相重合，而使所偵測的讀 出數據712S的一部分為不適當的值之情況下，該測試裝 置10也不會作出偵測到的讀出數據712S的邏輯值自身為 不良的邏輯值之錯誤的判定。 另外，記憶體控制部80也可執行特定的測試程式，並 根據該測試程式所指定的時序，而對被測試元件6〇〇内的 記憶體640供給讀出指令及寫入指令。例如，在上述特定 的測試程式為對被測試元件600内的記憶體64〇連續實施 上述讀出/寫入切換測試之程式的情況下，與記憶體控制部 8〇所供給的一讀出指令相對應之一讀出數據，和在該一讀 出指令之後的與記憶體控制部80所供給的一寫入指令相 對應之一寫入數據’有時在信號偵測部300中至少一部分 相重合地被偵測出。在這種情況下，記憶體控制部8〇也二 偵測與輪入到信號偵測部300的上述讀出數據及寫入數據 19 200907385 相同之讀出數據及寫入數據，並根據該偵測結果’使對被 測試元件600内的記憶體64〇供給該一寫入指令的時序’ 及信號輸出部100在被測試元件6〇〇的終端620上施加該 一寫入數據的時序被延遲，以使該一讀出數據和該一寫入 數據在信號偵測部300中不會重合。 而且’在記憶體控制部80執行上述特定的測試程式並 連續實施上述讀出/寫入切換測試的情況下，如記憶體控制 部80使對被測試元件6〇()内的記憶體64〇供給上述一寫入 指令之時序’及信號輸出部100在被測試元件600的終端 620上施加上述一寫入數據之時序延遲，則也可在從該一 寫入指令，只間隔上述測試程式所指定的上述一讀出指令 及該一寫入指令的間隔之前，對記憶體64〇供給新的讀出 才曰·τ在這種情況下，即使與上述新的讀出指令對應的讀 出數據中的、與該寫人數據重合的部分在信㈣測部300 被债測出，判定部6G較佳是也禁止對該重合的部分進行好 壞的判定。The contact type 20 for the on-the-job component is a circuit for generating a periodic signal in which the juice holder is subjected to a specific iteration period of the test pattern. By: Pre-production ""^ There is a program for the above-mentioned mosquitoes that is used for the production cycle signal, and the root number is generated. : No. Output section 9 (9). The logic _ of the column "200907385 column includes the number of patterns to be given to the device under test _ the test element __ test signal. The signal output portion 100 passes through the ith wiring 51 and the element to be tested The terminal 620 is electrically connected. The signal output unit 1 includes a shaper i20, a variable delay circuit 14A, a driver 16A, and a first wiring side resistor 180 to generate a test signal applied to the device under test (4). The shaper 12G generates a test signal based on the test pattern transmitted from the pattern generation !130, and transmits a tester_. The test signal generated by the variable delay circuit (10) to the waveform shaper 120 is given in advance according to the test pattern. The delay of the size is set. The drive n(10) causes the ❹m signal sent from the waveform shaper 12A to be applied to the terminal _ of the device under test 600. Here, the ray signal is a bit per sigma test pattern. The logic value corresponds to the voltage level of the pulse signal. The test signal is, for example, at a specified timing, between voltage values corresponding to the respective values of the logic of the test pattern and the logic L. The i-th wiring side resistor 180 has a large resistance value equal to the real resistance value of the characteristic impedance of the first wiring 51. Therefore, the output impedance of the signal output unit 100 and the characteristic impedance of the first wiring 51 are made. The known signal detecting unit 300 is connected to the terminal 62 of the device under test 6〇〇 via the jth line 51 common to the signal output unit 1. The signal detecting unit 300 has a comparator 320 and a latch. The lock circuit 34 and the variable delay circuit 360' detect the response signal applied from the terminal 62 of the device under test 600 through the first wiring 5ι. The comparator 32 receives the response signal and responds to the signal. The logic value of the signal is detected. Here, the periodic signal given to the latch circuit 340 from the timing 11 200907385 ° is subjected to a predetermined phase amount delay by the variable delay library 362. The latch circuit 340 is in the slave unit 2 The edge timing of the periodic signal given by 〇 is taken in the logical value of the response signal of the comparator 2. The flash lock circuit 340 transmits the logical value of the acquired response 彳 § to the determination unit 60. Impedance matching unit 400 The second wiring different from the first wiring 51 is electrically connected to the terminal 62 of the test element 6A. The impedance matching unit 4GG has a second wiring side resistance. The second wiring side resistor 420 is used. The characteristic impedance of the transmission line in which the first wiring 51 and the second wiring 52 connected to the terminal 620 of the device under test 600 are combined, and the impedance of the terminal 620 of the device under test 600 (on the side of the device under test 600) The second wiring side resistor 420 is a variable resistor that can set, for example, the magnitude of the resistance value to a predetermined value, and is based on the impedance of the terminal 620 of the device under test 6〇〇. And set the size of the resistance value. The reference voltage application unit 500 is electrically connected to one end of the second wiring 52. The reference voltage application unit 500 applies a constant voltage of a magnitude Vth to a transmission line in which the first wiring 51 and the second wiring 52 are combined. Therefore, the test signal applied from the nickname output unit 1 to the terminal 620 of the device under test 600 and the terminal 620 of the device under test 6 赋予 are supplied to the signal detecting unit 3 via the first wiring 51. The above response signal has a pulse waveform based on, for example, a voltage of a magnitude Vth. Further, at least a part of the first wiring 51 and the second wiring 52 may be a coaxial cable. The determination unit 60 matches the expected value of the pattern according to the test pattern 12 200907385 transmitted from the pattern generator 30, and whether or not the value matches the memory control unit 8. It is bad with being tested. Electric milk connection. The memory control unit 80 transmits the device 70 for testing the test program from the test element 600. In the memory test program, the execution sequence is the same as the response signal specified by the first wiring 1 and the signal side 3 通过. The signal is on the side. The memory control unit 8G causes the terminal 63 of the device under test _ to supply the timing of the command on the 仏.j and the timing at which the test signal is applied to the signal portion, based on the detection result of the ;j; Interval. As explained above, the test apparatus 10 can determine the quality of the tested component 600 by executing the test program specified above. Further, when the device under test _ is tested, the memory control unit 80 may supply necessary instructions to the device under test 6 根 according to the timing specified by the user. When the test device 10 tests the memory 640 in the device under test 6 ,, according to, for example, the readout of the memory region of the memory 640 13 200907385 -----χ--- try and the § The test is performed in the order of the read/write switching test of the area. Each test will be specifically described below. Fig. 2 is a timing chart showing the readout test of the memory area of the memory 640 by the test apparatus 1. In Fig. 2, the signal waveforms of (a), (B), and (C) are waveforms of the positions indicated by the symbols A, B, and C and the arrows in Fig. 1. That is, the waveform of (A) of the test device 10 is the signal waveform of the output end of the signal output unit 100, the waveform of (B) is the signal waveform of the terminal 620 of the device under test 600, and the waveform of (C) is the signal detecting portion. Signal waveform at the input of 300. In the case where the device under test 600 is, for example, a DRAM, the memory control unit 80 supplies a read command to the terminal 630 of the device under test 600 in the readout test of the memory area of the memory 640 in the device under test 600. The read command includes: an instruction to designate a column address of the memory 64〇, and to activate a memory unit of the specified column of the memory 640; specify a row address, and read the validated one. An instruction for the data of the specified row in a column of memory cells. When the read command is supplied from the memory control unit 80 to the device under test 600, the data of the designated address in the memory 640 in the device under test 6 is read out and is read as the read data 711S. The terminal 62 of the test element 6 is output. The read data 711S, as shown in Fig. 2, is a data signal having an amplitude equal to the magnitude of positive and negative voltages, for example, a voltage of magnitude Vth, and which is rotated from the terminal 620 of the device under test 600 during time Tr. The read data 711S output from the terminal 620 of the device under test 600 is transmitted through the first wiring 51 and is detected by the signal detecting unit 3 2009 14 200907385. At this time, the transmission time of the read data 7US from the terminal 620 of the device under test 600 to the signal detecting portion 300 is ΔΤ1. Further, at this time, since the signal is not rotated from the signal output unit 100, the voltage at the output end of the signal output unit 1A is Vth and is kept constant. Therefore, the read data 711S is output from the terminal 62 of the device under test 600, and is detected as it is after the ΔΤ1 at the signal detecting unit 300 as it is. The determination unit 6 储存 stores the data corresponding to the read data 7iis in the specified address on the { ' of the memory 64 之前 before the present read test, and stores the data according to the data. The value is compared with the logical value of the read data 711S detected in the signal detecting unit 300, and the read data 7US is judged to be good or bad, and based on the determination result, the one address in the memory 64 is determined. Whether the data is stored properly. Fig. 3 is a timing chart showing the read/write switching test of the memory area of the memory 64〇 performed by the test apparatus. In FIG. 3, the signal waveforms of (A), (B), and (C) are the same as those of FIG. 2, and are the symbols of a, B, and C in the figure, and the waveforms of the positions indicated by the arrows. U In the read/write switching test of the memory area of the memory 64G, the acknowledgment=control unit 80 supplies a read command to the device under test 6 〇〇 #terminal 63 。. This read command is the same command as the read command supplied from the test tape memory control unit 8A. Therefore, when the read command is supplied from the memory control unit 8 〇 = the test element 600, the data of the address of the memory 64 相同 which is the same as the address specified by the above-mentioned K is read and read as The data 712S is output from the terminal 62 of the device under test_. The sell data 712S is the same data signal as the above-described read data 7ns 15 200907385, as shown in FIG. Further, in the read/write switching test, the read command supplied from the memory control unit 8 is a command different from the read command supplied from the memory control unit 8A in the read test. In this case, data of an address different from the address specified in the above-described read test in the memory 64 of the device under test 600 is read. The memory control unit 80 supplies a write command to the terminal 630 of the device under test 600 after the read command is supplied. The signal output unit 100 applies the write data 721S to be written in the memory 64 of the device under test 600 to the terminal 62 of the device under test 60A at a predetermined timing. The write data 72is applied to the terminal 62 of the device under test 600 has an amplitude of a magnitude equal to positive and negative with a voltage of, for example, Vth as a reference, and is slid from the signal output unit 1 as shown in FIG. The data signal output during time Tw. Further, in the present embodiment, the number and period of the pulses of the write data 721S are equal to the read data 712S, but the present invention is not limited thereto. Moreover, the write data 721S is a signal for testing whether the data corresponding to the write data 721S is correctly written to the designated address of the memory 640 in the device under test 600 in the write test. The amplitude of the write data 721S may also be smaller than the read data 712S. The write command supplied from the memory control unit 80 to the device under test 600 includes an instruction to designate a column address of the memory 640 and validate a memory cell of the specified column of the memory 640; And specifying a row address, and writing an instruction to the row in the memory unit of the validated column that is pointed to the line 200190738. When the write command is supplied to the device under test 6 , and the write data 721S is applied to the terminal 62 of the test component 600, the write data 721S is written into the device under test 6 〇〇. The specified address of the memory 640. Further, the timing at which the signal output unit 100 applies the write data 721S to the terminal 62 of the device under test 600, that is, the predetermined timing, is the supply of the write to the device under test by the memory control unit 80. The timing of f' at the time of instruction is correspondingly unsuccessful. The predetermined timing is set to be the same timing as when the write command is supplied to the terminal 630 of the device under test 600, for example. Further, the predetermined timing is set such that after the test element 600 outputs the read data 712S, the write data 721S is applied to the minimum interval determined by the specifications of the test element 600. The terminal 62 of the test component 600 is turned on. Further, in the present embodiment, the minimum interval is ΔT2. Therefore, at the terminal 620 of the device under test 6 ,, as shown in FIG. 3, the read data 712S is outputted from the terminal 620 during the time Tr, only the elapsed interval, and the write is performed at the time (/Tw). The data 721S is applied to the terminal 620. The write data 721S written at the designated address of the memory 640 can be read out by performing an additional read test after the above-described read/write switching test. The data is read and detected by the signal detecting unit 3. The determining unit 60 determines the logical value of the write data 721S read from the memory 640 in the additional read test. It is determined whether or not the write data 721S is correctly written into the memory 64A during the read/write switching test, and it is determined from the result whether the upper & one 17 200907385 address of the memory 64 has an appropriate address. The read/write switching characteristic is such that the 'test device ί' performs the test in the order of the read/write switching test after the above-described readout test, and can be 'in the signal detecting section 300' with the write data 721S. Detecting from time to time without overlapping The read data 711S read from the memory 640 in the element 600. Further, in the above read/write switching test, the test apparatus 10 uses the tested element after reading the data of the memory 640. The minimum interval determined by the specification of 6〇〇, and data is written in the memory 64〇, thereby determining whether the memory 640 has an appropriate read/write switching characteristic. In addition, the above s is sold/written. In the entry switching test, the transfer time of the write data from the signal output portion 100 through the i-th wiring 51 to the write data 721S applied to the terminal 620 of the device under test 600 is at the terminal_from the terminal to be tested_ When the length of the transmission line from the system is substantially the same as the length of the transmission line from the signal wheeling portion 1G0 to the end 2:20 of the device under test 600, the signal output unit 1 is connected to the device under test 6〇. (4) The length of the transmission line between the terminals 62 and the number of the transmission lines between the number measuring unit 300 and the length of the transmission line from the output unit 100 and the signal extraction unit to the end 620 is very small, and the length of the transmission line is very small. After 1GG round, almost no face: The measurement unit 300 performs the measurement of the debt. In the signal detection unit 3, the read data outputted from the terminal (4) is input after being delayed by only Δη and rounded into ^18 200907385. The write data 721S output from the signal output unit 100. Therefore, in the 彳§ detecting unit 300, as shown in FIG. 3, the read data 712S detected during the time Tr' and at the time Tw, The write data 721S detected during the period also detects a signal component (hereinafter referred to as [overlapping component 731S]) in which a part of the read data 712s overlaps with a part of the write data 721S. Therefore, when a part of the logical value of the renewed data 712S detected by the determination signal detecting unit 3A is a logical value corresponding to the overlapping component 731S, the determination unit 6 does not correspond to the overlapping component 731S. Whether the logical value of the value is an inappropriate value 'all the test element 600 is prohibited from being bad. Thereby, even in a case where a part of the read data 712S overlaps with a part of the read data 712S and a part of the detected read data 712S is an inappropriate value, the test apparatus 10 also The determination that the detected logical value of the read data 712S itself is an erroneous logical value is not made. Further, the memory control unit 80 can execute a specific test program, and supply a read command and a write command to the memory 640 in the device under test 6 in accordance with the timing specified by the test program. For example, in the case where the specific test program described above is a program for continuously performing the above-described read/write switching test on the memory 64 in the device under test 600, a read command supplied from the memory control unit 8A is used. One of the corresponding data is read, and one of the write instructions corresponding to a write command supplied from the memory control unit 80 after the read command is sometimes at least a part of the signal detecting unit 300. Coincidentally detected. In this case, the memory control unit 8 also detects the read data and the write data which are the same as the read data and the write data 19 200907385 that are wheeled into the signal detecting unit 300, and according to the detect The result of the measurement 'the timing of supplying the memory 64 〇 in the device under test 600 to the write command' and the timing at which the signal output unit 100 applies the write data to the terminal 620 of the device under test 6 被 are delayed. Therefore, the read data and the write data do not overlap in the signal detecting unit 300. Further, when the memory control unit 80 executes the above-described specific test program and continuously performs the above-described read/write switching test, the memory control unit 80 causes the memory 64 in the device under test 6 to be 〇. When the timing of supplying the write command and the timing delay of the signal output unit 100 applying the write data to the terminal 620 of the device under test 600, only the test program may be spaced from the write command. Before the interval between the specified one of the read command and the one of the write command, a new read port τ is supplied to the memory 64 在. In this case, even the read data corresponding to the new read command is read. The portion overlapping with the writer data is measured by the credit (four) measurement unit 300, and the determination unit 6G preferably also prohibits the determination of the coincidence portion.
L 本發明已哺佳實施_露如上，·並非用以 二“明i任何熟f此技藝者’在不脫離本發明之精神 和範圍内，虽可作些許之更動與 範圍當視後附之中請專利_所衫者為ί發保遵 【圖式簡單說明】 巧早 圖 成 1所不為本發_實施形態之測試I置職全體構 圖 2所示為利用測試裝置10所進行之記憶體 640的記 20 200907385 憶區域的讀出測試的時序圖。 圖3所示為利用測試裝置10所進行之記憶體640的讀 出/寫入切換測試的時序圖。 【主要元件符號說明】 10 :測試裝置 20 :時序產生器 30 :圖案產生器 40 :測試頭 50 :性能板 51 :第1配線 52 :第2配線 60 :判定部 70 :控制裝置 80 :記憶體控制部 100 :信號輸出部 120 :波形成形器 140 :可變延遲電路 160 :驅動器 180 :第1配線側電阻 300 :信號偵測部 320 :比較器 340 :閂鎖電路 360 :可變延遲電路 400 :阻抗匹配部 21 200907385 420 :第2配線側電阻 500 :基準電壓施加部 600 :被測試元件 620、630 :終端 640 :記憶體 711S、712S :讀出數據 721S :寫入數據 731S :重疊成分L The present invention has been implemented as a result of the above-mentioned, and is not intended to be used in the spirit and scope of the present invention, although some modifications and scopes may be attached thereto. The patent is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Note 20 of the body 640 200907385 Timing diagram of the readout test of the memory area. Fig. 3 is a timing chart of the read/write switching test of the memory 640 by the test apparatus 10. [Description of main component symbols] 10 : Test device 20 : Timing generator 30 : Pattern generator 40 : Test head 50 : Performance board 51 : First wiring 52 : Second wiring 60 : Determination unit 70 : Control device 80 : Memory control unit 100 : Signal output unit 120: Waveform shaper 140: Variable delay circuit 160: Driver 180: First wiring side resistor 300: Signal detecting unit 320: Comparator 340: Latch circuit 360: Variable delay circuit 400: Impedance matching unit 21 200907385 420 : 2nd wiring side resistor 500 : Reference voltage application Addition unit 600: Tested component 620, 630: Terminal 640: Memory 711S, 712S: Read data 721S: Write data 731S: Overlapping component
22twenty two