JP2007170940A - Test method of semiconductor element and semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit acquisition of correct result determination even when a test pattern from a semiconductor test device conflicts with a read signal from a semiconductor element in a consecutive data input/output test of the semiconductor element. <P>SOLUTION: In the test method of the semiconductor element 5 provided with an input/output circuit, when a writing signal conflicts with a read signal, expectation values are corrected according to a level difference between the expectation values of the writing signal and the read signal, and the corrected expectation values are compared with conflicting data for determination. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor element test method and a semiconductor test apparatus, and more particularly to a semiconductor element test method and a semiconductor test apparatus provided with a bidirectional input / output circuit.

  The semiconductor element includes logic circuits therein, and a function test is performed to check whether these logic circuits have a logical function as designed. The function test is performed by placing a test jig (test board) on a semiconductor test apparatus and inserting a semiconductor element to be measured into the test jig. A test pattern from the semiconductor test apparatus is input as a write signal to the semiconductor device to be measured, and a read signal is output from the semiconductor device to be measured. A pass / fail judgment is made by comparing and comparing the read signal and the expected value with a semiconductor test apparatus. Here, the expected value is the logic pattern expected to be output corresponding to the test pattern when the logic circuit in the semiconductor device under test has the logical function as designed, and the level. is there.

  However, the semiconductor element is provided with an input / output circuit in which an input circuit and an output circuit are shared, and wiring from the semiconductor test apparatus to these input / output circuits in the semiconductor element is connected by one single wiring. ing. Further, the test pattern is continuously output as a write signal from the semiconductor test apparatus to the semiconductor device to be measured, and the read signal is output from the semiconductor device to be measured correspondingly. In such a single wiring connection of the input / output pins of the semiconductor test apparatus, there is a problem that a write signal from the semiconductor test apparatus and a read signal from the semiconductor element collide in the test jig wiring.

  Since the data input / output test in the semiconductor element is continuously performed, the write signal from the semiconductor test apparatus and the read signal from the semiconductor element may collide in the test jig wiring. When the write signal and the read signal collide, the level becomes an intermediate level, and there is a problem that the read signal cannot be determined correctly. For this reason, it is a restriction of semiconductor test equipment. If you want to perform continuous data input / output test, you need to use semiconductor test equipment and test jigs with two input / output pins for input and output. There are problems such as restrictions on jigs and tools and increased costs.

  There are the following Patent Documents 1 to 4 as prior patent documents relating to a test method of a semiconductor element having an input / output circuit. In Patent Document 1 (Japanese Patent Laid-Open No. 10-123218), when a test pattern and a read signal collide, a collision detection unit is provided to detect a data collision. When data collision is detected by the collision detection unit, the test pattern output timing is delayed to avoid data collision. In Patent Document 2 (Japanese Patent Laid-Open No. 04-262440), an error signal is generated when a test pattern and a read signal collide with each other. In Patent Document 3 (Japanese Patent Laid-Open No. 59-090066), a test pattern output or a read signal from a semiconductor element is output in accordance with control of a gate-on signal. In Patent Document 4 (Japanese Patent Laid-Open No. 04-098168), a test pattern is output by a driver clock, and a read signal is performed by a comparator strobe signal delayed by a round trip time.

  In these above-mentioned prior patent documents, a data collision is detected and an error signal is output, or a test pattern is delayed to avoid the collision. The present invention relates to a technique for adjusting the timing of a test pattern and a read signal by a control signal so as not to collide. There is no description regarding a technique in which a read signal is extracted from data in which a test pattern and a read signal collide in the present application and compared with an expected value. The solution method in the present application and the solution method in the prior patent document are technologies based on completely different technical ideas.

JP-A-10-123218 Japanese Patent Laid-Open No. 04-262440 JP 59-090066 A Japanese Patent Laid-Open No. 04-098168

  As described above, in a test of a semiconductor element equipped with an input / output circuit, a write signal (test pattern) from a semiconductor test device and a read signal from the semiconductor element collide with each other in the test jig wiring, so that a correct result can be determined. There is no problem.

  The purpose of the present application is to compare the collision data in which the write signal and the read signal collide with the corrected expected value in the period in which the write signal to the semiconductor element and the read signal from the semiconductor element collide, in view of the problems described above. An object of the present invention is to provide a semiconductor element test method and a semiconductor test apparatus which can be determined.

  In order to solve the above-described problems, the present invention basically employs the techniques described below. Needless to say, application techniques that can be variously changed without departing from the technical scope of the present invention are also included in the present application.

  In the semiconductor element testing method of the present invention, the semiconductor element includes an input / output circuit, and when the write signal from the semiconductor test apparatus and the read signal from the semiconductor element to be measured collide with each other, the expected expected value is corrected. The level of the read signal is determined by comparing the value with the collision data of the write / read signal.

  In the semiconductor element testing method of the present invention, the corrected expected value is generated by correcting the expected value based on a level difference between the expected value and the write signal.

  In the semiconductor element testing method of the present invention, it is determined whether the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig, and if the timing difference is within the wiring delay time, It is determined that the write signal and the read signal collide with each other.

  In the semiconductor element testing method of the present invention, if the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig, it is determined that the write signal and the read signal collide, The corrected expected value is characterized in that the expected value is corrected by a level difference between the expected value and the write signal.

  The semiconductor element testing method of the present invention is characterized in that the expected value and the read signal are compared and determined when the write signal and the read signal do not collide.

  The semiconductor test apparatus of the present invention generates a corrected expected value in which an expected value is corrected when a write signal from the semiconductor test apparatus collides with a read signal from a semiconductor element having an input / output circuit. An expected value generation circuit is provided, and the level of the read signal is determined by comparing the corrected expected value with the collision data of the write / read signal.

  In the semiconductor test apparatus of the present invention, the expected value generation circuit includes a correction period setting circuit, and the correction period setting circuit is configured when the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig. Is characterized by activating a correction period setting signal.

  In the semiconductor test apparatus of the present invention, the expected value generation circuit further includes a difference calculation circuit, and when the correction period setting signal is activated, the difference calculation circuit determines a level difference between the expected value and the write signal. Is calculated.

  In the semiconductor test apparatus of the present invention, the expected value generation circuit further includes an expected value correction circuit, and when the correction period setting signal is activated, the expected value correction circuit corrects the expected value by the level difference. The expected correction value is output, and when the correction period setting signal is inactive, the expected value is output.

  In the semiconductor test apparatus of the present invention, the semiconductor test apparatus further includes a comparator that compares the output from the expected value correction circuit with the read signal or the collision data.

  According to the configuration of the present invention, the test pattern from the semiconductor test apparatus collides with the read signal from the semiconductor element in the continuous data input / output test of the semiconductor element in the single wiring connection of the input / output pin of the semiconductor test apparatus. Even in this case, it is possible to obtain a semiconductor element test method and a semiconductor test apparatus that enable correct result determination.

  Hereinafter, a semiconductor element testing method and a semiconductor testing apparatus according to the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic diagram of a test system using a semiconductor test apparatus according to the present invention, and FIG. 2 is a signal waveform diagram thereof.

  This will be described with reference to the schematic diagram of the test system in FIG. The test jig 3 attached to the semiconductor test apparatus 1 is provided with a socket, for example, and a semiconductor device 5 to be measured is inserted into the socket, and a function test is performed. The input / output pin 2 of the semiconductor test apparatus 1 and the input / output pin 6 of the semiconductor element 5 to be measured are connected by the wiring 4 of the test jig 3.

  The input / output pin 2 of the semiconductor test apparatus 1 includes a driver 11 as an output channel for outputting a write signal to the semiconductor element and a comparator 12 as an input channel for inputting a read signal from the semiconductor element. . The driver 11 receives a test pattern, a write level (Vi), and a write trigger signal (DRE), and sends a write signal from the input / output pin 2 to the semiconductor element 5 to be measured. The comparator 12 receives the read signal from the semiconductor device 5 to be measured and the expected value or the corrected expected value from the expected value generation circuit 13, compares and determines both of them, and outputs the result as a determination result.

  Furthermore, the present invention includes an expected value generation circuit 13. The expected value generation circuit 13 includes a correction period setting circuit 14, a difference calculation circuit 15, and an expected value correction circuit 16. The correction period setting circuit 14 receives the write trigger signal (DRE), the wiring delay time data, and the read strobe signal (STRB), and outputs the correction period setting signal to the difference calculation circuit 15. The wiring delay time data is the wiring delay time between the input / output pin 2 of the semiconductor test apparatus 1 and the input / output pin 6 of the semiconductor element 5 to be measured. Since the setting of these wiring delay times differs depending on the test jig / tool, data is set and set when the test jig / tool is designed or when the semiconductor test apparatus is calibrated.

  When the timing difference between the read strobe signal (STRB) and the write trigger signal (DRE) is within the wiring delay time, the read signal from the semiconductor device 5 to be measured and the write signal from the semiconductor test apparatus 1 collide on the wiring 4. It will be. Therefore, the correction period setting circuit 14 activates a correction period setting signal for correcting the expected value level. When the timing difference between the read strobe signal (STRB) and the write trigger signal (DRE) is equal to or longer than the wiring delay time, the read signal and the write signal do not collide. Therefore, correction is unnecessary and the correction period setting signal is inactivated.

  The difference calculation circuit 15 receives the correction period setting signal, the test pattern, the write level (Vi), and the expected value level (Vo), and outputs the output to the expected value correction circuit 16. When the correction period setting signal is in the activation period, it is necessary to correct the expected value. Therefore, a level difference (ΔVo = Vo−Vi) between the expected value level (Vo) and the test pattern writing level (Vi) is calculated. The level difference (ΔVo) is output from the difference calculation circuit 15. The expected value correction circuit 16 corrects the expected value level (Vo) to the corrected expected value level (Vo ′ = Vo−ΔVo) using the inputted level difference (ΔVo). The corrected expected value (Vo ′) corrected is output to the comparator 12. The comparator 12 compares the corrected expected value (Vo ′) with the read signal from the semiconductor element 5 for determination.

  When the correction period setting signal is inactive, it is not necessary to correct the expected value. Therefore, the difference calculation circuit 15 does not perform calculation. The expected value correction circuit 16 outputs the expected value level (Vo) as it is as the corrected expected value level (Vo ′ = Vo). The comparator 12 compares the expected value with the read signal and outputs a determination result. Hereinafter, the expected value level and the corrected expected value level may be simply referred to as an expected value and a corrected expected value.

  When data collision does not occur in this way, a comparison determination between the read signal and the expected value is performed. On the other hand, when a data collision occurs, a corrected expected value corrected based on the difference between the expected value and the write level is generated, and a comparison determination between the collision data of the read / write signal and the corrected expected value is performed. By correcting the expected value level, the comparator 12 can correctly determine the output even when the write signal and the read signal collide.

  FIG. 2 shows signal waveforms in (A) a read data period, (B) a read / write data collision period, and (C) a write data period. The high level VoH and low level VoL of the read signal in the read data period (A) are set to the high level Voh and low level Vol of the expected value level. The high level VoH ′ and low level VoL ′ of the collision data in the read / write data collision period (B) are set to the high level Voh ′ and the low level Vol ′ of the expected correction value level. The high level ViH and low level ViL of the write signal in the write data period (C) are set.

  The level of the read signal from the semiconductor element 5 in the read data period (A) is determined by the expected value level (high level Voh, low level Vol). In this case, the expected value level is not corrected, and the determination is performed based on the normal expected value. Here, the expected value level is set so that the read signal high level VoH> the expected value level high level Voh, and the read signal low level VoL <expected value level low level VoL, and comparison determination is performed.

  In the read / write data collision period (B), the read signal and the write signal collide to change the high level and the low level. Therefore, it is necessary to correct the expected value level. The level to be corrected is a level difference (ΔVo = Vo−Vi) between the expected value level (Vo) and the write level (Vi). The corrected expected value level is set as high level Voh ′ = Voh−ΔVo and low level Vol ′ = Vol + ΔVo.

  In particular, a problem occurs when the write signal from the semiconductor test apparatus and the read signal from the semiconductor element 5 are at different levels. When the read signal is at the high level VoH and the write signal is at the low level ViL, the high level is lowered by the difference (VoH−ViL) and becomes the high level VoH ′ of the low collision data. At this time, the expected value level high level Voh ′ is set so that high level VoH ′> expected value level high level Voh ′. When the read signal is at the low level VoL and the write signal is at the high level ViH, the read signal is pulled up by the difference (| VoL−ViH |) and becomes the low level VoL ′ at the time of a high collision. At this time, the expected value level low level Vol 'is set so that low level VoL' <expected value level low level Vol '.

  When both the write signal from the semiconductor test apparatus and the read signal from the semiconductor element 5 are at a high level (ViH, VoH) or low level (ViL, VoL), they indicate a sufficient high or low level, respectively (not shown). ) Therefore, the high level and the low level at the time of the collision satisfy the corrected expected value level high level (Voh ′) and low level (Vol ′), so that comparison and determination can be made. Thus, at the time of read / write data collision, the read signal can be determined by setting the expected value level at the time of collision corresponding to the difference between the expected value level of the read signal and the level of the write signal. The expected correction value level (high level Voh ′, low level Vol ′) at the time of collision can be set at the time of program creation. The write data period is a period during which a write signal is sent from the semiconductor test apparatus to the semiconductor element to be measured, and no determination operation is performed.

  As described above, when the timing difference between the read strobe signal (STRB) and the write trigger signal (DRE) is within the wiring delay time, the read signal and the write signal collide. Accordingly, the correction period setting circuit 14 activates a correction period setting signal for correcting the expected value. At the time of a collision in which a write signal and a read signal are input at the same time, the difference calculation circuit 15 calculates a level difference between the write signal level and the expected value of the read signal. The judgment value correction circuit 16 corrects the expected value based on the level difference to obtain a corrected expected value. When the correction period setting signal is activated, output determination is continuously performed with the corrected expected value. With these configurations, output determination can be performed even when the read signal and the write signal collide.

  The above example is a case where the wiring length of the test jig and the input / output timing of the test contents are known in advance. However, if the user can set arbitrary timing by programming etc. and the expected value can be changed continuously, it will be possible to deal with unknown test jigs and tools. In the present invention, the case where the levels of the read signal and the write signal are different has been described. However, the present invention can be similarly applied to cases where the signal level is the same and the driving capability is different.

  Although the present invention has been specifically described as an embodiment, the present invention is not limited to the above description, and various modifications can be made without departing from the spirit of the present invention. Further, the above description includes inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as an invention as long as a predetermined effect can be obtained.

1 is a schematic diagram of a test system using a semiconductor test apparatus of the present invention. FIG. 2 is a signal waveform diagram in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor test device 2, 6 Input / output pin 3 Test jig (test board)
4 Wiring 5 Semiconductor element 11 Output channel (driver)
12 input channels (comparators)
13 Expected Value Generation Circuit 14 Correction Period Setting Circuit 15 Difference Operation Circuit 16 Expected Value Correction Circuit

Claims (10)

  In a test method of a semiconductor element provided with an input / output circuit, when a write signal from a semiconductor test apparatus collides with a read signal from a semiconductor element to be measured, a corrected expected value obtained by correcting the expected value and a write / read signal A method for testing a semiconductor device, wherein the level of the read signal is determined by comparing the data with the collision data.   2. The semiconductor element testing method according to claim 1, wherein the corrected expected value is generated by correcting the expected value based on a level difference between the expected value and the write signal.   It is determined whether the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig. If the timing difference is within the wiring delay time, the write signal and the read signal collide with each other. The semiconductor element testing method according to claim 1, wherein the determination is performed.   When the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig, it is determined that the write signal and the read signal collide, and the corrected expected value is the expected value and the write 2. The method of testing a semiconductor device according to claim 1, wherein the expected value is corrected based on a level difference from a signal.   2. The method of testing a semiconductor device according to claim 1, wherein when the write signal and the read signal do not collide, the expected value and the read signal are compared and determined.   In a semiconductor test apparatus, when a write signal from the semiconductor test apparatus collides with a read signal from a semiconductor element to be measured equipped with an input / output circuit, expected value generation that generates a corrected expected value by correcting the expected value A semiconductor test apparatus comprising: a circuit; comparing the expected correction value with collision data of a write / read signal to determine a level of the read signal.   The expected value generation circuit includes a correction period setting circuit, and the correction period setting circuit activates the correction period setting signal when the timing difference between the write trigger signal and the read strobe signal is within the wiring delay time in the test jig. The semiconductor test apparatus according to claim 6, wherein:   The expected value generation circuit further includes a difference calculation circuit, and when the correction period setting signal is activated, the difference calculation circuit calculates a level difference between the expected value and the write signal. The semiconductor test apparatus according to claim 7.   The expected value generation circuit further includes an expected value correction circuit, and when the correction period setting signal is activated, the expected value correction circuit outputs the corrected expected value obtained by correcting the expected value by the level difference. 9. The semiconductor test apparatus according to claim 8, wherein when the correction period setting signal is inactive, the expected value is output. The semiconductor test apparatus according to claim 9, further comprising a comparator that compares an output from the expected value correction circuit with the read signal or the collision data.

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