JP3555934B2 - Test device and test method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test apparatus and a test method, and more particularly, to a test apparatus and a test method for inspecting a possibility of malfunction occurring between a plurality of buses of a multi-port memory.
[0002]
[Prior art]
A multi-port memory is known as a memory in which a write operation and a read operation are performed simultaneously and synchronously. Japanese Patent Application Laid-Open No. 7-73698 discloses a method for inspecting an operation failure at the time of contention when the same memory cell is simultaneously accessed for reading and writing from different buses. Even when reading is performed only by the writing operation, the memory performs comparison and verification of both writing and reading data at the same time, and performs a test. This memory avoids an increase in test time due to repeatedly executing a test corresponding to the memory size. . Japanese Patent Application Laid-Open No. 8-315598 discloses a technique capable of executing a timing margin test at high speed and with high accuracy by using a timing generation circuit controlled by a BIST circuit (built-in self-test). . In this known technique, either a write or read margin test is performed.
[0003]
FIG. 15 shows a known inspection circuit for indirectly inspecting the appropriateness / inappropriateness of the circuit design of the bus by judging whether the input / output values of the data of the two-port RAM match or not using the BIST circuit. Read data 104 which is simultaneously read from the two-port RAM 102 corresponding to the write data 103 written to the two-port RAM 102 by both read and write clock signals generated by the BIST 101 formed on the same substrate, and originally read properly. The comparator 106 compares the expected output value 105, which is the proper read value that should be. As a result of the comparison, the bus line circuit malfunctions due to the capacitive coupling between the two bus lines when the write bus for transferring the write data and the read bus for transferring the read data in the two-port RAM are arranged close to each other. Appropriate / inappropriate is determined.
[0004]
Such a known technique aims at speeding up the inspection, but a basic viewpoint of directly inspecting the influence of the coupling between adjacent bus lines due to the wiring interval and interlayer thickness depending on the physical state between the buses. It is not possible to check in advance for the possibility of malfunction at the simultaneous operation timing of read operation and write operation, and it is possible that a product that passed the inspection by the manufacturer without such a viewpoint will malfunction after user acceptance. Found by that user. It is desired to directly inspect the physical state between the bus lines in addition to the inspection in a known manner.
[0005]
[Problems to be solved by the invention]
The above-described verify test for a conventionally known multi-port memory performs a read operation from the same memory cell after writing data to the memory cell. An operation test could not be performed in a situation where the read timing at which data is loaded overlaps with the timing.
An object of the present invention is to provide a test apparatus and a test method for directly inspecting a physical state between bus lines.
[0006]
[Means for Solving the Problems]
Means for solving the problem are expressed as follows. The technical items appearing in the expression are appended with numbers, symbols, etc. in parentheses (). The numbers, symbols, and the like refer to technical items that constitute at least one embodiment or a plurality of the embodiments of the present invention, in particular, the embodiments or the examples. Corresponds to the reference numbers, reference symbols, and the like assigned to the technical matters expressed in the drawings corresponding to. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or the examples.
[0007]
The test method according to the present invention provides a desired signal to a plurality of adjacent signal lines (WT, RT), and compares the signal on at least one of the signal lines with an expected value to determine an electrical interaction between the two signal lines. Including detecting. Physical interactions between multiple signal lines are directly verified. The determination as to whether or not a malfunction occurs is a presumed judgment based on a comparison of input / output data and is not reliable. However, there is no room for estimation in direct verification of physical interaction. With such a test, for example, a more realistic test of a two-port RAM can be performed.
[0008]
The transmission timing of the signal given to each signal line is shifted in a relatively stepwise manner, and the time width in which the signals given to each signal overlap on the signal line is changed in a stepwise manner. An inspection is performed. Specifically, one of the signal lines is a read bus and the other is a write bus.
[0009]
One of the plurality of signal lines is a read bus (RT, RB) and the other is a write bus (WT, WB). Inspection of the two-port RAM (2) can be performed precisely. In this case, the read bus and the write bus correspond to two ports of a one-column two-port RAM. The read bus and the write bus correspond to one port of one column of the one-column two-port RAM and one port of the other one column of the one-column two-port RAM, respectively. Interactions on different columns are also checked for safety.
[0010]
The test apparatus according to the present invention includes a BIST circuit (1) and a two-port RAM (2), and two ports of the two-port RAM (2) correspond to an internal read bus and an internal write bus, respectively. 1) supplies each address and clock at the time of reading and writing, and data at the time of writing to the 2-port RAM (2), and stores the data read from the 2-port RAM (2) and a preset expected value. And a comparison circuit (12) for comparing and outputting a comparison result. The BIST circuit (1) includes a timing adjustment circuit (21) for relatively shifting the timing of both the read clock as the operation timing of the internal read bus and the write clock as the operation timing of the internal write bus stepwise. Including.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Corresponding to the figure, in the embodiment of the test apparatus according to the present invention, a BIST circuit is provided together with a multi-port memory. The BIST circuit 1 is connected to a two-port RAM 2 as shown in FIG. The BIST circuit 1 includes a control circuit 3 and a pattern generation circuit 4. The test signal TEN · TIN is input to the control circuit 3 as in the related art. The control circuit 3 causes the pattern generating circuit 4 to generate the patterned write address 5 and write data 6 in a time-corresponding (synchronous) manner with the write clock 7 based on the test signal TEN · TIN.
[0012]
The write address 5 and the write data 6 are input to the two-port RAM 2 at the timing of the write clock 7, and the write data 6 is written to the two-port RAM 2. The control circuit 3 stores the read data 9 written before writing into the two-port RAM 2 in the read address 10 in accordance with the read clock 8 generated by the pattern generating circuit 4 at the same time as the write clock 7. Is read based on The pattern generation circuit 4 receives a control command from the control circuit 3 and generates an output expected value 11 which is a data value appropriately predicted corresponding to the write data 6.
[0013]
Further, a comparison circuit 12 is provided. The read data 9 and the expected output value 11 are input to the comparison circuit 12. The comparison circuit 12 outputs the comparison result signal 13, and the comparison result signal 13 is input to the control circuit 3 and output from the control circuit 3 as TOUT. The write bus line to which the write data 6 is transmitted is provided on the same semiconductor substrate in proximity to the read bus line to which the read data 9 is transmitted. When reading and writing are performed simultaneously, the read bus line and the write bus line have a large or small capacitance value of physical capacitance coupling (C-coupling) between the bus lines via an interlayer insulating film or the like between the bus lines. Due to the difference, the data values that intersect each other may or may not interfere with each other. The presence or absence of such mutual interference is determined by the above-described comparison of BIST. Depending on the degree of overlap of the write data and the read data on both bus lines, the timing of which is controlled by the write clock TCKA and the read clock TCKB, mutual interference or no mutual interference may occur. Further, depending on whether both signals between adjacent bus lines have the same logical signal value (0 or 1) or different logical signal values, mutual interference or non-interference may occur.
[0014]
Further, the pattern generation circuit 4 includes a timing adjustment circuit 21. The timing adjustment circuit can shift the timing of both the read and write clocks relatively stepwise.
[0015]
FIG. 2 shows input / output signals of the BIST circuit 1 and symbols used in the description to be described later. TWA: write address 5, TWCK: write clock 7, TWD: write data 6, TRA: read address 10, TRCK: read clock 8, TDB: read data 9.
[0016]
FIG. 3 shows a physical map image of the test checker data written on the two-port RAM. The n-bit data is written to the two-port RAM. The unit bit is formed by four columns. As shown in FIG. 4, the left side of one column and two ports are non-inverted signals RT and WT of a read line and a write line. On the right side are the inverted signals WB and RB for the write and read lines. The square indicates one bit of the memory cell. The test data is given addresses from # 00 to # 71. The left elliptical line indicates that interference occurs when the lead line RT and the write line WT are adjacent to each other, and the right elliptical line indicates that interference occurs when the lead line WB and the write line RB are adjacent to each other. ing. There is also the possibility of interference between the areas enclosed by the two ellipses. The two lines having a high possibility of interference are predicted to be a read line and a write line of the same column.
[0017]
FIGS. 5 to 12 show a series of test sequences that are started by changing TCTL from 1 to 0 and are continuously executed by the BIST circuit. FIG. 5 shows a test sequence 2-1. The data values of TWD and TDB do not change in the drawing. However, in the write bus and read bus in the 2-port RAM, a data transfer period in which the bus precharge or an active period within one clock period is synchronized with the write clock and the read clock, and a data transfer period between this transfer period and the next clock. There is an equalizing period between the transfer periods. In the latter period, the bus is normally set at the power supply voltage / 2. These transfer periods are synchronized with the write clock and the read clock.
[0018]
The read clock TRCK is input to the 2-port RAM such that the phase slightly advances every clock with respect to the write clock TWCK. The write data TWD is “FF” at address # 04, and the read data TDB is “00” at address # 00. When the read clock TRCK completely matches the write clock TWCK, the data on the read bus line changes due to the capacitive coupling between the write bus line and the read bus line in the 2-port RAM, and the read data TDB is changed. The output value is abnormal and the comparison result signal TOUT is an abnormal output value.
[0019]
FIG. 6 shows test sequence 2-2. The read clock TRCK is input to the ram memory such that the phase slightly advances every clock with respect to the write clock TWCK. The write data is “FF” at address # 04, and the read data is “FF” at address # 0C, unlike FIG. When the read clock TRCK completely matches the write clock TWCK, the read data indicates an output value abnormality, and the comparison result signal TOUT has an abnormal output value.
[0020]
FIG. 7 shows test sequence 2-3. The read clock TRCK is input to the 2-port RAM such that the phase slightly advances every clock with respect to the write clock TWCK. The write data is “00” at address # 10, and the read data is “00” at address # 00. Unlike FIG. 6, both data are 00. When the read clock TRCK completely matches the write clock TWCK, the read data indicates an output value abnormality, and the comparison result signal TOUT has an abnormal output value.
[0021]
FIG. 8 shows test sequence 2-4. The read clock TRCK is input to the 2-port RAM such that the phase slightly advances every clock with respect to the write clock TWCK. The write data is “00” at address # 4, and the read data is “FF” at address # 0C, unlike FIG. When the read clock TRCK completely matches the write clock TWCK, the read data indicates an output value abnormality, and the comparison result signal TOUT has an abnormal output value.
[0022]
5 to 8 show tests using the same bus in the same column for data transfer. 9 to 12 show test sequences 3-1, 3-2, 3-3 and 3-4, and show tests using different buses in columns different from those in FIGS.
[0023]
FIG. 13 shows an embodiment of a test method according to the present invention, and shows a process thereof. Prior to the start of the test, a checker pattern as shown in FIG. 3 is written to the 2-port RAM in step S1. In step S2, the counter C1 is set. The counter C1 is a number that is set for the data string in the digit line direction of the column, and is shown as the number of data strings in the column height direction (vertical direction) in FIG. The counter C1 is 18.
[0024]
Next, in step S3, the counter C2 is set. The counter C2 is a number that is set for the data string in the word line direction of the column, and is shown as the number of data strings in the horizontal direction in FIG. The counter C2 is 4 × n. In step S4, the write address TWA, the read address TRA, and the write data TWD are set. In step S5, the counter C3 is set. The counter C3 indicates the number of times the test is executed for the same interference inspection target address.
[0025]
In step S6, the counter C4 is set. The counter C4 sets a delay of the above-described clock signal phase of the read clock TRCK with respect to the write clock TWCK. In step S7, by repeating this, a read clock TRCK whose phase is gradually delayed or advanced with respect to each of the plurality of write clocks is generated. With the plurality of read clocks set in step S7, the interference between the two set data is checked. The inspection is executed by comparing the read data with the expected output value in step S9 as described above. If the expected output value is abnormal, an NG flag is set to indicate an abnormality (step S10), and the inspection program ends.
[0026]
Until the counter C3 becomes zero in step S11, the processes of steps S6 to S9 are repeated the number of times set in the counter C3. After the repetition, the inspection target position (inspection target data) is shifted in the horizontal direction in step S12. The interference test described above is performed on the data. When the interference test is completed for all data pairs at the same digit line direction position, the digit line direction position is shifted by one in the digit line direction. The data is shifted to the digit line direction position by the number of the counter C1, the above-described inspection is performed on all data, and the interference test ends for the set checker pattern.
[0027]
FIG. 14 shows an interference test for a reverse pattern of the above-described checker pattern. The inversion test is executed by the same program as the program in FIG. As described above, the interference test is promptly executed for all data pairs formed from the write data and the read data in which the test pattern and its inverted pattern are expected to have interference. A first coherence between data "1" and data "1", a second coherence between data "0" and data "0", and a third coherence between data "1" and data "0". , The degree of coherence between the data “0” and the fourth coherence of data “1” cannot be generally predicted. Since it is important to consider that the coherence depends on the physical individuality of each transistor, it is preferable to perform a brute force verification test in all combinations as described above. Further, it is important that the interference depending on the degree of overlap of the timing time widths by shifting the timing is directly measured physically.
[0028]
【The invention's effect】
The test apparatus and the test method according to the present invention can directly inspect the physical state between the bus lines at the same time, and the reliability of the inspection accuracy is high. Since the actual data is directly inspected physically, the reliability is higher.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing an embodiment of a test apparatus according to the present invention.
FIG. 2 is a circuit block diagram showing a part of FIG. 1;
FIG. 3 is a data table showing test checker patterns.
FIG. 4 is a physical image diagram showing an interference area.
FIG. 5 is a time flow diagram showing another test sequence.
FIG. 6 is a time flow diagram showing still another test sequence.
FIG. 7 is a time flow chart showing still another test sequence.
FIG. 8 is a time flow diagram showing still another test sequence.
FIG. 9 is a time flow chart showing still another test sequence.
FIG. 10 is a time flow diagram showing still another test sequence.
FIG. 11 is a time flow chart showing still another test sequence.
FIG. 12 is a time flow diagram showing still another test sequence.
FIG. 13 is an operation flowchart showing an embodiment of the test apparatus according to the present invention.
FIG. 14 is an operation flowchart showing another embodiment of the test apparatus according to the present invention.
FIG. 15 is a circuit block diagram showing a known inspection device.
[Explanation of symbols]
1: BIST circuit 2: 2-port RAM
12 comparison circuit 21 timing adjustment circuit WT, RT multiple data lines RT, RB read bus (lead wire)
WT, WB: Light bus (light line)

Claims (2)

A read line for transferring read data read from one port under timing control; and a write line for transferring write data to be written from the other port under timing control, wherein the arrangement of the read line and the write line is adjacent to each other. Multi-port memory testing methods
For the multi-port memory, the read timing of reading previously written data to the read line and the write timing of applying write data to the adjacent write line are shifted relatively stepwise, so that the read line The time width at which the transmission timing of the read data and the transmission timing of the write data respectively given above and above the write line overlap is changed stepwise, and at least one of the read line and the write line is changed at each stage. Detecting an electrical interaction between the read line and the write line by comparing a signal on the signal line with an expected value. Includes a lead wire for transferring the read data to be read out from one of the ports is timing control, and a write line is by Retiming control the write clock transfers the write data to be written from the other port by the read clock, the The multi-port memory in which the arrangement of the read line and the write line is adjacent to each other, by comparing a signal on at least one signal line of the read line and the write line with an expected value, A test apparatus including a test circuit for detecting an electrical interaction between the light lines,
With respect to the multiport memory, both the read clock, which is a timing for reading pre-written data on the read line, and the write clock, which is a timing for applying write data to the adjacent write line, are relative to each other. A timing adjustment circuit that changes stepwise the time width in which the transmission timings of the read data and the write data respectively given on the read line and the write line overlap with each other. Including
The test circuit compares the signal on at least one of the read line and the write line with an expected value at each stage to provide an electrical interaction between the read line and the write line. Test equipment to detect.

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