JP4601305B2 - Semiconductor device - Google Patents

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JP4601305B2
JP4601305B2 JP2004054242A JP2004054242A JP4601305B2 JP 4601305 B2 JP4601305 B2 JP 4601305B2 JP 2004054242 A JP2004054242 A JP 2004054242A JP 2004054242 A JP2004054242 A JP 2004054242A JP 4601305 B2 JP4601305 B2 JP 4601305B2
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circuit
memory
signal
register
test
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JP2005243176A (en
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孝 四方
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富士通セミコンダクター株式会社
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012Marginal testing, e.g. race, voltage or current testing of timing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop

Description

  The present invention generally relates to a semiconductor device including a memory test circuit, and more particularly to a semiconductor device including a memory test memory BIST circuit and a voltage control method using the memory BIST circuit.

  In a semiconductor device such as a processor in which one or a plurality of memories are mounted, a SCAN chain is generally used to perform an operation test on each memory from a limited number of external terminals. The SCAN chain is a chain that inputs data serially from the outside and propagates the data. A serially connected flip-flop is provided on the SCAN chain, and an input test pattern for each memory is set by serially storing data from a tester outside the semiconductor device into the flip-flop. The result of the operation test for each memory is output to the outside through the SCAN chain, and the tester determines the quality of the test operation.

  In such a method using the SCAN chain, data is set according to the clock frequency of the external tester, but the clock frequency of the external tester is generally much lower than the actual operating frequency inside the semiconductor device. is there. Therefore, there is a problem in that a huge amount of time is spent on the operation test of the memory, and a malfunction that becomes apparent only at the actual operating frequency of the semiconductor device cannot be detected. Such malfunctions include those caused by defects that affect the delay time such as contact defects.

Further, there is a system in which a memory BIST (Built-In-Self-Test) circuit is provided around each memory, and this memory BIST circuit realizes a test pattern generation to a test result determination (for example, Patent Documents 1 to 3). . However, even when the memory BIST circuit is used, the memory BIST circuit is connected to the SCAN chain, and data writing for controlling the memory BIST circuit is executed from the outside via the SCAN chain. Therefore, the control of the memory BIST circuit is executed according to the clock frequency of the external tester, and the operation of the memory BIST circuit itself is also executed according to this clock frequency. As a result, the operation test of the memory still takes time, and there is a problem that a malfunction that becomes apparent only at an actual operation frequency cannot be detected.
JP 2000-163993 A JP 2003-346498 A JP 2000-200904 A

  Even if the memory BIST circuit is designed so that it can be tested at the original operating frequency of the semiconductor device by using a PLL or the like, in the conventional method, the data write for controlling the memory BIST circuit is performed from the outside via the SCAN chain. Will run through. Therefore, in the memory BIST circuit, a dedicated circuit configuration that can realize the frequency switching from the low-speed scan clock to the high-speed PLL clock without any problem in timing is necessary.

  In view of the above, the present invention provides a semiconductor device including a memory BIST circuit capable of detecting a defect that becomes apparent at an actual operating frequency of the semiconductor device without requiring a complicated circuit design associated with clock switching. For the purpose.

  In addition, it is not preferable in terms of area to provide the memory BIST circuit for each memory, and it is desirable that the memory BIST circuit be integrated in one place in the semiconductor device. When an attempt is made to test all the memories in the semiconductor device chip with one memory BIST circuit, it is necessary to be able to flexibly support the bit, word, and column configurations of each memory. Patent Document 1 discloses an invention that reduces the circuit scale by providing one memory BIST circuit capable of generating the maximum BIST pattern of bits and words. However, the design changes each time a product with a different memory configuration is developed. There is a problem that it is necessary, and when there is a bit that is not used in a specific memory, it is difficult to realize fine control such as masking that bit. Japanese Patent Application Laid-Open No. 2004-228561 describes an invention configured such that a test can be performed with one memory BIST circuit by selectively switching the outputs of a plurality of memories.

  In view of the above, an object of the present invention is to provide a semiconductor device including a memory BIST circuit that can be flexibly adapted to the configuration of each memory while being provided at one location in the semiconductor device. .

  Further, miniaturization of the process technology increases the circuit scale of the semiconductor device and increases the overall power consumption. In particular, the ratio of the leakage current is so large that it cannot be ignored. In order to cope with this, when high-speed processing is not required, the internal power supply voltage is lowered or the internal power supply is stopped. Thus, when the internal power supply voltage is lowered, it becomes an important problem whether or not the internal circuit can operate correctly. In particular, a memory or the like that is easily affected by a voltage may have a significantly worse access time as the voltage drops, and a means for confirming by a program that the memory operates normally even when the voltage drops is necessary. For example, Patent Document 3 discloses a technique for autonomously performing a RAM power margin test and a data retention test when switching the power supply voltage inside an LSI. It is efficient if such a memory operation check can be realized using a memory BIST circuit.

  In view of the above, an object of the present invention is to provide a method for confirming that a memory operates normally when a voltage changes in a semiconductor device including a memory BIST circuit by a program using the memory BIST circuit.

A semiconductor memory device according to the present invention includes a CPU core circuit, a bus connected to the CPU core circuit, a memory BIST circuit that executes a memory test in response to an instruction supplied from the CPU core circuit via the bus, A first signal line for supplying an address signal from the memory BIST circuit to the memory; a second signal line for supplying a data signal from the memory BIST circuit to the memory; and supplying read data from the memory to the memory BIST circuit. And a pipeline register provided on a path of the first to third signal lines, and the first to third signal lines are provided separately from the bus, The memory BIST circuit includes a register accessible from the CPU core circuit via the bus, a control circuit that controls the operation of the memory test according to the contents of the register, The address generation circuit that generates the address signal under the control of the control circuit, the pattern generation circuit that generates the data signal under the control of the control circuit, the read data from the memory and the expected value are compared, and the comparison result is includes a signal analyzing circuit for storing in the register, the the signal analyzing circuit, for the expected value supplied from the pattern generating circuit, delay the Taiminku and clock synchronization by a plurality of stages of buffer registers, the signal analysis circuit includes a series The read data and the series of expected values are immediately asserted when there is a mismatch regardless of the bit position, and when there is a mismatch, the control circuit, the address generation circuit, and the The pattern generation circuit stops the operation while maintaining the internal operation state in response to the assertion of the stop signal. The CPU core circuit obtains information indicating the memory subject to the memory test from the circuit that has stopped the operation, an address address when the mismatch occurs, and information indicating the contents of the memory test being executed. The register is read and read .

According to the semiconductor device of the present invention, since the memory operation can be tested by the normal instruction of the CPU core without using the conventional scan, there is no need to switch the clock, and the memory at the normal operating frequency of the semiconductor device. An operation test can be easily realized. As a result, it becomes possible to effectively detect a delay defect such as a contact defect that does not become apparent in an operation test using a low-speed clock. In addition, various types of memory tests can be easily and quickly executed only by register settings, and only desired operation tests can be selected only by program settings, and only necessary and sufficient minimum operation tests can be performed. Can be realized. In addition, it is possible to easily execute a memory operation test even on-board without using an external tester, and an inspection in an actual product environment in which a semiconductor device is mounted on the board is facilitated. On the board, power supply noise or voltage drop may occur due to various factors. In such a case, it is effective from the viewpoint of ensuring the operation to test the operation of the memory sensitive to the voltage at the actual operation frequency. In addition, the expected value supplied from the pattern generation circuit is delayed in synchronization with the clock by a plurality of stages of buffer registers. With such a configuration, a memory test corresponding to the number of pipeline stages can be performed.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram showing a configuration of a first embodiment of a semiconductor device incorporating a memory BIST circuit according to the present invention.

  The semiconductor device of FIG. 1 is a processor that operates at a high operating frequency such as a PLL output clock. The memory BIST circuit 1, the CPU core 10, the module 13, the bus bridge 16, the on-chip bus 17, the internal peripheral bus 18, and the module 19. , Module 20, control signal line 21, write data signal line 22, and read data signal lines 23 to 26. The CPU core 10 includes an instruction cache RAM 11 and a data cache RAM 12. The module 13 includes a module internal RAM 14 and a module internal RAM 15. The memory BIST circuit 1 is a circuit provided for performing an operation test on the instruction cache RAM 11, the data cache RAM 12, the module internal RAM 14, and the module internal RAM 15. For convenience of explanation, the PLL circuit and other circuits not related to the operation of the memory BIST circuit 1 are omitted.

  The memory BIST circuit 1 includes a register set 2 including registers 2-1 to 2-4, a control circuit 6, an address generation circuit 7, a pattern generation circuit 8, and a signal analysis circuit 9. The memory BIST circuit 1 is provided in a predetermined block inside the semiconductor device. The CPU core 10 accesses the register set 2 of the memory BIST circuit 1 via the on-chip bus 17, the bus bridge 16, and the internal peripheral bus 18. By setting a predetermined control value in the register set 2 by a program instruction from the CPU core 10, the memory BIST circuit 1 can be controlled in accordance with the instruction from the CPU core 10. The register set 2 includes one or a plurality of result storage registers for storing the result of the memory operation test. Whether the memory operation is normal or not only by the CPU core 10 referring to the register value of the result storage register after the test is completed. Can be easily determined.

  The memory BIST circuit 1 operates at an actual high frequency at which the semiconductor device operates, and performs an operation test on each of the RAMs 11, 12, 14, and 15. The control circuit 6 is a state machine and controls the operations of the address generation circuit 7, the pattern generation circuit 8, and the signal analysis circuit 9 based on the register values of the register set 2. The address generation circuit 7 generates an address signal for designating an access position in the RAM and various control signals such as a write enable WE, a chip enable CE, and a DM signal. The pattern generation circuit 8 generates test patterns such as a march pattern, a checkerboard pattern, a stripe pattern, a data mask function test pattern, and a gallop pattern. The generated test pattern is written to the RAM address designated by the address signal of the control signal line 21 via the write data signal line 22.

  Thereafter, data is read from the RAM address specified by the address signal of the control signal line 21 and is taken into the signal analysis circuit 9 via any one of the read data signal lines 23 to 26. The pattern generation circuit 8 generates expected value data corresponding to the performed operation test and supplies it to the signal analysis circuit 9. The signal analysis circuit 9 determines whether or not the operation of the RAM is normal by comparing the read data read from the RAM with the expected value data from the pattern generation circuit 8. The determination result is stored in the result storage register using any one of the registers 2-1 to 2-4 of the register set 2 as a result storage register. The CPU core 10 can know whether or not the operation of the RAM is normal by reading the register value of the result storage register.

  The result storage register may be a single register or a plurality of registers provided for each RAM. When all RAM test results are stored in one result storage register, one bit may be assigned to one RAM, and normality / abnormality may be determined based on “1/0” of each bit of the register value. .

  Here, the RAMs 11, 12, 14, and 15 to be tested can be appropriately selected and executed by providing a memory selection control state in the control circuit 6 that is a state machine. At this time, a configuration may be adopted in which a specific RAM can be designated as a test object by setting the control value of the register set 2 and all the memories can be automatically and sequentially tested.

  The memory BIST circuit 1 may be provided at a specific location inside the semiconductor device in order to reduce the circuit scale, or may be provided as a wrapper circuit for each memory so as to be easily compatible with a conventional ASIC or the like.

  According to the memory BIST circuit according to the present invention described above, the memory operation can be tested by the normal instruction of the CPU core 10 without using the conventional scan. A memory operation test at an operating frequency can be easily realized. As a result, it becomes possible to effectively detect a delay defect such as a contact defect that does not become apparent in an operation test using a low-speed clock. In addition, various types of memory tests can be easily and quickly executed only by register settings, and only desired operation tests can be selected only by program settings, and only necessary and sufficient minimum operation tests can be performed. Can be realized. In addition, it is possible to easily execute a memory operation test even on-board without using an external tester, and an inspection in an actual product environment in which a semiconductor device is mounted on the board is facilitated. On the board, power supply noise or voltage drop may occur due to various factors. In such a case, it is effective from the viewpoint of ensuring the operation to test the operation of the memory sensitive to the voltage at the actual operation frequency.

  Hereinafter, the operations of the address generation circuit 7 and the pattern generation circuit 8 of the memory BIST circuit 1 will be described in more detail.

  As described above, it is not preferable in terms of area to provide the memory BIST circuit for each memory, and it is desirable that the memory BIST circuit be integrated in one place in the semiconductor device. When an attempt is made to test all the memories in the semiconductor device chip with one memory BIST circuit, it is necessary to be able to flexibly support the bit, word, and column configurations of each memory. In the memory BIST circuit 1 according to the present invention, the register set 2 is provided with a register for setting the number of bits of the address signal, the bit width of the data signal, the presence / absence of the data mask function, and the memory type (1 port, 2 port, etc.) The address generation circuit 7 and the pattern generation circuit 8 generate a memory test pattern in accordance with the register setting.

  Specifically, for example, a value indicating an address width is set in a register in the register set 2. Based on the register setting value, the address generation circuit 7 determines an address operation range such as a RAM march test and generates an address signal according to the determined address range. For example, a value indicating the data bit width is set in a register in the register set 2. Based on this register setting value, the pattern generation circuit 8 generates a test pattern.

  FIG. 2 is a diagram illustrating an example of an address pattern generated by the address generation circuit 7. When the address width indicated by the register setting value in the register set 2 is 10 bits and the test method is a march test, as shown in FIG. 2, the address generation circuit 7 sequentially increases in the range from address 0 to address 1023. Generate a signal. FIG. 3 is a diagram illustrating another example of the address pattern generated by the address generation circuit 7. When the address width indicated by the register setting value in the register set 2 is 8 bits and the test method is a march test, as shown in FIG. 2, the address generation circuit 7 sequentially increases in the range from address 0 to address 255. Generate a signal. 2 and 3, Wn indicates the nth write, and Rn indicates the nth read.

  As described above, by setting various parameters such as the address signal width and data signal width of the memory operation test, a general-purpose memory BIST circuit that does not depend on the type of the semiconductor device can be provided. Since a single memory BIST circuit may be provided, the circuit area can be minimized.

  Hereinafter, a modified example of the operation of the signal analysis circuit 9 of the memory BIST circuit 1 will be described.

  For example, when some bits are not used in a tag-RAM or the like used in the CPU core 10 or when the most significant bits of the data RAM are not used, an arbitrary data signal in the signal analysis circuit 9 is used. It is preferable to mask the expected value comparison of the bit positions. In order to realize this, a register for mask control is provided in the register set 2 of the memory BIST circuit 1. In the read data from the RAM, the signal analysis circuit 9 masks the bit position specified by the register setting to 0 or 1, and also masks the bit position specified by the register setting to 0 or 1 for the expected value.

  FIG. 4 is a circuit diagram showing an example of the configuration of the signal analysis circuit 9 having a mask processing function.

  The signal analysis circuit 9 of FIG. 4 includes an encoder 31, mask circuits 32 and 33, an EXOR circuit 34, an OR circuit 35, a flip-flop 36, and a selector 37. The encoder 31 receives a mask setting value from a predetermined register of the register set 2 and encodes it to generate a data mask signal. The selector selects one of the read data signal lines 23 to 26 and supplies the corresponding read data to the mask circuit 32. The mask circuit 32 masks the supplied read data using a data mask signal from the encoder 31. The mask circuit 33 masks the expected value supplied from the pattern generation circuit 8 using the data mask signal from the encoder 31.

  The masked data from the mask circuits 32 and 33 is subjected to an exclusive OR for each bit by the EXOR circuit 34. When both data match completely, all bits are zero. The OR circuit 35 ORs the output n bits from the EXOR circuit 34 and the output n bits from the flip-flop 36 for each bit, and supplies the resulting n-bit output to the flip-flop 36. In this way, by feeding back the output of the flip-flop 36 to the OR circuit 35, when there is a mismatch between the series of read data and the series of expected values even once, the corresponding bit of the output of the flip-flop 36 is “1”. " Thereby, it can be detected that the test target RAM is defective.

  In this way, by using the data mask signal to mask the read data and the expected value data, it is possible to prevent the test from being performed on the bits that do not need to detect the defective operation. In this manner, the yield of the semiconductor device can be improved without detecting a memory failure that does not affect the operation.

  The second embodiment of the semiconductor device according to the present invention will be described below.

  When implemented as a wrapper circuit around the memory like a conventional memory BIST circuit, at least one selector is inserted in the memory input / output path. For example, when such a selector is inserted in the path to the cache RAM of the CPU, the timing of the critical path that is severe in terms of timing may be further deteriorated. Also, as in the first embodiment shown in FIG. 1, providing signal lines individually for the memory BIST test leads to an increase in the number of wirings. Therefore, in the second embodiment described below, a selector is provided at a location in the normal data path where timing is not strict, and the memory can be accessed in a pipeline manner from the memory BIST circuit by switching the polarity of the test signal. Configure.

  FIG. 5 is a diagram showing an example of the configuration of the second embodiment of the semiconductor device including the memory BIST circuit according to the present invention.

  In the semiconductor device of FIG. 5, a bus interface unit 38 is provided in the CPU core 10, and the memory BIST circuit 1 is incorporated in the bus interface unit 38. The bus interface unit 38 includes buffer registers 101 to 106 and selectors 107 to 110. The CPU core 10 further includes an instruction cache RAM 11, a data cache RAM 12, an instruction execution control unit 39, a data operation processing unit 40, and buffer registers 121 to 124.

  The data path used for data transfer during normal operation is switched by each selector and used by the memory BIST circuit 1 during test operation. Test data for the instruction cache RAM 11 is written from the memory BIST circuit 1 to the instruction cache RAM 11 via the selector 107, the buffer register 102, the instruction execution control unit 39, and the buffer register 121. At this time, the pipeline operation is realized by synchronizing each buffer register with the clock. In addition, a path is provided so that read data from the instruction cache RAM 11 can be read by the memory BIST circuit 1 through a pipeline operation. Test data in the data cache RAM 12 is written from the memory BIST circuit 1 to the data cache RAM 12 via the selector 109, the buffer register 104, the data operation processing unit 40, and the buffer register 123. Further, a path is provided so that read data from the data cache RAM 12 can be read by the memory BIST circuit 1 through a pipeline operation. Similarly, the module internal RAM 14 of the module 13 can be tested. Buffer registers 111 and 112 are provided at the input / output portion of the module internal RAM 14.

  A selector select signal in the bus interface unit 38 is generated based on a signal indicating a test operation generated from the memory BIST circuit 1.

  Further, since the normal data path is diverted when the instruction cache RAM 11 is tested, there is a possibility that the RAM test data flows into the instruction execution unit of the instruction execution control unit 39 and causes malfunction such as hang-up. There is. In order to prevent this, the busy signal is asserted from the memory BIST circuit 1 during the memory test, and the instruction execution control unit 39 stops the decoding of the instruction data. After the busy signal is negated after the memory test is completed, the decoding of the instruction data may be resumed.

  According to the second embodiment, a selector is provided at a location in the existing data path where timing is not strict, and the path is switched to the memory BIST circuit 1, so that the memory access timing during normal operation is not particularly deteriorated. . Further, by diverting the existing data path as much as possible, it is possible to reduce the data signal lines dedicated to the memory test, thereby improving the wiring property at the time of layout and reducing the wiring area. Further, when the instruction cache RAM test is performed, the operation of the instruction execution unit is stopped by the busy signal, so that the CPU can be prevented from being hung up.

  The third embodiment of the semiconductor device according to the present invention will be described below.

  When the operating frequency of the semiconductor device increases from several hundred MHz to several GHz, the data transfer from the memory BIST circuit 1 to the memory and the read data transfer from the memory to the memory BIST circuit 1 are relatively long with respect to the clock speed. It takes time and operation becomes difficult in terms of timing. In particular, in the configuration in which the memory BIST circuit 1 is integrated in one place, this problem becomes apparent because there is a distance to the memory position. Therefore, in the third embodiment, a buffer register (pipeline register) is provided in the data supply path from the memory BIST circuit 1 to the memory and the data read path from the memory to the memory BIST circuit 1 to perform a pipeline operation.

  FIG. 6 is a diagram showing an example of the configuration of the third embodiment of the semiconductor device including the memory BIST circuit according to the present invention. In FIG. 6, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.

  In the semiconductor device of FIG. 6, a pipeline register 42 is provided in the signal path of the control signal line 21 and the write data signal line 22. A pipeline register 42 is provided in the signal path of the read data signal lines 23 to 26. Here, since the CPU core 10 is farther from the memory BIST circuit 1 than the module 13, the number of stages of the pipeline register 42 is increased. Thus, by providing the pipeline register 42 in the signal path and synchronizing the signal to the clock in each pipeline register 42, the signal reception end can receive the signal in synchronization with the clock without worrying about the signal delay. it can. At this time, although the clock timing of signal reception at the receiving end is delayed according to the number of stages of the pipeline register 42 inserted in the signal path, the pipeline operation is realized for a series of data sequentially transferred. Therefore, data reading from the memory can be realized at the timing of each successive clock pulse.

  FIG. 7 is a diagram showing an example of the configuration of the signal analysis circuit 9 in the case of the third embodiment. In FIG. 7, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted.

  Since the data read from the RAM is delayed according to the number of pipeline stages, it is necessary to delay the timing of the expected value to be compared inside the signal analysis circuit 9 according to the delay. In the signal analysis circuit 9 in FIG. 7, the expected value supplied from the pattern generation circuit 8 is delayed in synchronization with the clock by the buffer registers 44 in a plurality of stages. An expected value delayed in timing and an expected value of the original timing, which are outputs from each buffer register 44, are input to the selector 43. The selector 43 selects and outputs one of a plurality of inputs according to the select signal. With such a configuration, a memory test corresponding to an arbitrary number of pipeline stages can be performed.

  The selector signal for the selector 43 may be configured such that the number of pipeline stages is set in a register of the register set 2 by a program instruction or the like, and the selector signal is changed according to the set value.

  Below, the further modification of the signal analysis circuit 9 is demonstrated.

  Conventionally, there is no effective failure analysis method for malfunctions based on dynamic factors such as interference of address signal lines inside a memory operating at a high operating frequency. Conventionally, verification with an actual product cannot be performed, and the only way to find out the cause of a defect is to use a SPICE simulation or the like. In the following, a configuration of the signal analysis circuit 9 suitable for failure analysis of a memory operating at a high operating frequency will be described.

  FIG. 8 is a diagram showing an example of the configuration of the signal analysis circuit 9 suitable for failure analysis of a memory operating at a high operating frequency. In FIG. 8, the same elements as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted.

  As described with reference to FIG. 4, when the output of the flip-flop 36 is fed back to the OR circuit 35, the flip-flop 36 is inconsistent with the series of read data and the series of expected values even once. The corresponding bit of the output is “1”. Thereby, it can be detected that the test target RAM is defective. In the configuration of FIG. 8, an OR circuit 46 is further provided to calculate the logical sum of all the bits output from the flip-flop 36 and output the result as a 1-bit signal. This 1-bit output signal is a signal that becomes “1” when there is a mismatch between a series of read data and a series of expected values, regardless of the bit position.

  This signal is supplied as a BIST stop signal to the control circuit 6, the address generation circuit 7, and the pattern generation circuit 8 of the memory BIST circuit 1. In each of these circuits, when the BIST stop signal is asserted to “1”, the operation of the circuit is stopped and the circuit state is maintained as it is.

  By immediately stopping the operation of the memory BIST circuit 1 when a memory failure is detected in this way, the selected memory, the address address being accessed, the type of BIST test being executed, the state of the control state By reading the signal, it is possible to know which stage of the corresponding BIST test is being processed, what value the value of the data read from the RAM is, and the like. The register set 2 is provided with a failure analysis setting register and a failure analysis data read register so that these results can be read out. In the configuration of FIG. 8, the mask circuit for mask processing may be deleted.

  Further, the memory operation test may be continuously resumed by setting the register set 2 by a program instruction or the like. In addition, in order to enable more detailed failure analysis, various parameters for failure analysis are set in a register by a program command or the like, whereby a basic unit of a pattern generated in the memory BIST circuit 1 (continuous write, read-write, (Write-read, data mask function setting, write data setting, expected value setting, etc.) may be generated for a specific address. Further, the control state of the control circuit 6 and the various parameters described above may be set in a register by a program command or the like, and an arbitrary memory operation test may be executed from an arbitrary state.

  Below, the further modification of the signal analysis circuit 9 is demonstrated.

  Some processors that operate at a high operating frequency employ a test method for executing a shipping test or the like by executing a CPU instruction without scanning the logic portion for reasons of timing disadvantages. is there. In the case where the memory BIST circuit of the present invention is applied to such a semiconductor device, the reliability of the memory operation test is impaired unless a failure of the memory BIST circuit itself can be detected.

  When the pattern generation unit of the memory BIST circuit or the circuit of the expected value generation unit itself is defective, a phenomenon such as failure to generate a test pattern normally occurs, so that a failure of the memory BIST circuit itself is also caused by the expected value comparison. Can be detected. However, if the expected value comparator (for example, the EXOR circuit 34 in FIG. 4) is out of order, an appropriate memory failure detection operation is impossible at all, and the failure location cannot be specified at all. Therefore, in this embodiment, the signal analysis circuit 9 is provided with a function of detecting a failure of the expected value comparator.

  FIG. 9 is a diagram illustrating an example of a configuration of the signal analysis circuit 9 having a function of detecting a failure of the expected value comparator. 9, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted.

  The signal analysis circuit 9 in FIG. 9 includes a failure setting circuit 48. The failure setting circuit 48 receives a failure setting control signal. This failure setting control signal only needs to have a minimum number of bits only to indicate the failure bit position. However, when the read data is n bits, for example, an n-bit mask signal for failure setting may be used. It is a simple realization method. If it is desired to cause a specific bit to fail to “0”, a mask signal in which only that bit is “0” and all other bits are “1” is generated, and the failure setting circuit 48 applies to the RAM read data to be masked. Thus, an AND operation for each bit may be executed. As a result, a “0” failure is set only in the designated bit. Further, if a “1” failure is desired, only a specific bit of the mask signal is set to “1”, and an OR operation may be executed instead of an AND operation.

  FIG. 10 is a diagram showing another example of the configuration of the signal analysis circuit 9 having a function of detecting a failure of the expected value comparator. 10, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted.

  In the signal analysis circuit 9 of FIG. 10, the failure setting circuit 48 is provided on the expected value side. Thereby, a desired failure can be generated for a specific bit of the expected value supplied from the pattern generation circuit 8. It is considered that there is no difference in effect between the configuration of FIG. 9 and the configuration of FIG. 10, and any configuration may be adopted.

  By providing the failure setting circuit 48 in the signal analysis circuit 9 in this manner, it is possible to set whether or not the failure is intentionally set in advance before the memory operation test, and to confirm whether or not the failure can be detected correctly. This makes it possible to improve the reliability of the memory test.

  The fourth embodiment of the semiconductor memory device on which the memory BIST circuit according to the present invention is mounted will be described below.

  In the case of a circuit that is designed by a customer and requested to be manufactured instead of being designed by a manufacturer as in ASIC, it is difficult to change the entire circuit design in order to insert the memory BIST circuit. Therefore, a method of inserting a memory BIST wrapper circuit around each memory is desirable. In the fourth embodiment, a memory BIST wrapper circuit is inserted around each memory.

  FIG. 11 is a diagram showing an example of the configuration of the fourth embodiment of the semiconductor memory device on which the memory BIST circuit according to the present invention is mounted. FIG. 11 includes a CPU core 10, a module 13, and a memory BIST control circuit 200. In order to simplify the description and the drawings, other circuits are omitted.

  The memory BIST control circuit 200 includes registers 2-2 to 2-5, a control circuit 6, a parallel / serial interface circuit (I / F) 61, a serial / parallel interface circuit (I / F) 62, and a selector 70. Including. The module 13 includes a module internal RAM 14, a module internal RAM 15, a memory BIST wrapper circuit 49, and a memory BIST wrapper circuit 55. The memory BIST wrapper circuit 49 includes a serial / parallel interface circuit 50, a control circuit 51, a pattern generation circuit 52, a determination circuit 53, a parallel / serial interface circuit 54, and a selector 71. The memory BIST wrapper circuit 55 includes a serial / parallel interface circuit 56, a control circuit 57, a pattern generation circuit 58, a determination circuit 59, a parallel / serial interface circuit 60, and a selector 72. In the fourth embodiment shown in FIG. 11, a memory BIST circuit is constituted by the memory BIST control circuit 200 and the memory BIST wrapper circuits 49 and 50.

  As described above, the memory BIST wrapper circuit 49 and the memory BIST wrapper circuit 55 are provided around the module internal RAM 14 and the module internal RAM 15 in the module 13, respectively. In each of the memory BIST wrapper circuits 49 and 55, the pattern generation circuits 52 and 58 correspond to the pattern generation circuit 8 in FIG. 1 and are controlled by the control circuits 51 and 57. The determination circuits 53 and 59 compare the read data read from the corresponding RAM with the expected value. This expected value is generated by the pattern generation circuits 52 and 58.

  The operations of the memory BIST wrapper circuit 49 and the memory BIST wrapper circuit 55 are controlled by the memory BIST control circuit 200. The memory BIST control circuit 200 operates under the control of the control circuit 6 and controls the entire memory test operation. The memory BIST control circuit 200 serially transmits control data from the parallel / serial interface circuit 61 to the signal line 63 based on the set values of the registers 2-2 and 2-4.

  The serial / parallel interface circuit 50 of the memory BIST wrapper circuit 49 receives a control signal from the memory BIST control circuit 200. Based on this control signal, the control circuit 51 of the memory BIST wrapper circuit 49 controls the memory test operation for the module internal RAM 14. The selector 71 selects normal path data during normal operation, and selects data from the pattern generation circuit 52 during test operation. Based on the read data from the module internal RAM 14 and the expected value, the determination circuit 53 determines whether or not the module internal RAM 14 is defective. The determination result, the determination end signal, and / or various read data at the time of failure analysis are serially transmitted from the parallel serial interface circuit 54 to the memory BIST control circuit 200 via the signal line 64. The operation of the memory BIST wrapper circuit 55 is the same.

  The selector 70 of the memory BIST control circuit 200 selects either the signal line 64 or the signal line 65 corresponding to the RAM to be tested, and supplies the selected signal to the serial / parallel interface circuit 62. Various information obtained as a result of the operation test is stored in the registers 2-3 and 2-5, and is read out by access from the CPU core 10.

  Since the memory BIST wrapper circuits 49 and 55 implement a memory operation test by inserting a selector into the normal paths of the module internal RAM 14 and the module internal RAM 15, there is no need to change the logic inside the module 13. Therefore, the present invention can be easily applied to semiconductor devices such as ASIC types.

  Also, various control commands from the memory BIST control circuit 200 can be distributed with a small number of signal lines of 1 to several bits via the serial interface, and further, test results and various read data for failure analysis can be transmitted via the serial interface. Reading with a few signal lines of a few bits is possible. As a result, the number of interface signals between the memory BIST control circuit 200 for overall control and the memory BIST wrapper circuits 49 and 55 can be minimized.

  In the result storage register 2-3 of the memory BIST control circuit 200, 1 bit is assigned to each memory, and when the test end signal from the wrapper circuit is asserted, the test result signal from the wrapper circuit is sent to the result storage register 2 -3 may be written to the corresponding 1 bit. Further, regarding various data reading at the time of failure analysis, information related to data to be read may be transmitted to the wrapper circuit according to the value of the control register in the memory BIST control circuit 200. In this case, the wrapper circuit recognizes the failure analysis mode and the read data to be analyzed, and sends the read data obtained by performing a desired test operation back to the memory BIST control circuit 200.

  Hereinafter, a method for confirming by a program using the memory BIST circuit that the memory operates normally when the voltage changes will be described.

  When the internal power supply voltage is lowered, the delay value of each logic element constituting the circuit of the semiconductor device increases, and in particular, a memory having a sense amplifier or the like is greatly affected. As a result, the normal operation of the memory may not be ensured (for example, the access time cannot satisfy the request). After such voltage control, there is a limit in ensuring the operation of the memory only by memory access by a program instruction. Therefore, it is desirable to confirm that there is no problem in the operation of the memory by using a memory BIST circuit dedicated to the memory test. In the memory test based on the conventional scanning method, it was impossible to perform the memory test using the BIST circuit by the program control from the CPU. However, the memory BIST circuit according to the present invention can be controlled by the program, except for the shipping test. Can also be used effectively.

  FIG. 12 is a flowchart showing a memory operation checking method when the voltage changes.

  First, in step S1, a transition is made to the voltage control mode. Next, in step S2, the contents of the register are saved. That is, in preparation for the case where the CPU core program execution itself stops when the voltage is lowered, various data such as internal registers are saved in advance in an external SDRAM or a nonvolatile memory.

  In step S3, voltage control is performed. For example, the voltage is lowered. In the above description, the problem at the time of voltage drop has been mainly described. However, for example, if it is necessary to check the memory operation when the voltage is raised, the voltage may be raised at step S3. For this voltage control, a power supply control unit that can be controlled by a program command is provided in the semiconductor device, and the variable voltage generation source may be controlled according to the setting of the power supply control unit.

  In step S4, it is determined whether or not a timeout has occurred. In other words, a hang-up is detected by detecting a timeout by a watchdog timer or the like provided in the voltage control unit or the like. If timed out, the timer is reset in step S8. As a result, an internal reset is automatically performed, and a flag indicating that a timeout has occurred in a voltage control related register is recognized in the boot processing routine. In step S9, the standby state of the external memory (for example, the SDRAM self-refresh mode) is canceled, and various data are returned to the register. Thereafter, the process returns to step S3, and voltage control is executed again under loose conditions as necessary.

  If no time-out occurs in step S4, a memory BIST test is executed in step S5. In step S6, it is determined whether or not the memory is defective as a result of the memory test. If a defect is found in the memory, the process returns to step S3, and voltage control is executed again under loose conditions as necessary.

  If no defect is found in the memory, normal operation is restored in step S7. That is, the operation of the application or the like is resumed under conditions where the voltage setting, the clock frequency setting, and the like are stable.

  Note that when controlling the voltage, a cache-off state in which the instruction cache and data cache inside the CPU core are not used is set in advance. As a result of the memory BIST test after switching the voltage, if it is found that the memory operates normally, it can be confirmed that the memory operates normally with the internal voltage, so the CPU instruction cache, data cache, etc. are turned on. Resume normal operation.

  It is also possible to execute a data retention test using the memory BIST circuit of the present invention. In order to realize this, the BIST operation may be stopped at a set location during the operation of the memory BIST circuit, and the BIST operation may be restarted from the stopped state later by a program command or the like.

  For example, in the case of a RAM operation test, a specific sequence is as follows.

  First, the operation of the memory BIST circuit is temporarily stopped during the RAM-BIST test. For example, the operation of the memory BIST circuit is stopped when the data writing operation of the march or checkerboard test is completed. As a result, data is written in the RAM.

  Next, the voltage is varied by program control or the like as it is. After a certain period of time has elapsed, the voltage is returned to the original voltage value by program control or the like, and the temporarily stopped operation of the RAM-BIST is resumed. It is tested whether the written data can be read normally by the restarted test operation. Thereby, a data retention test is realized.

  As described above, the memory operation check method at the time of voltage change according to the present invention allows the memory operation test at the time of internal power supply voltage control to be confirmed by a program using the memory BIST circuit. Is executed for each set voltage value, and the operation of the semiconductor device when the power supply voltage is controlled can be reliably ensured. Such a memory operation checking method is useful for reducing power consumption in a large-scale integrated circuit.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1) CPU core circuit;
A bus connected to the CPU core circuit;
A semiconductor device comprising a memory BIST circuit for executing a memory test in response to an instruction supplied from the CPU core circuit via the bus.
(Appendix 2) CPU core circuit;
A semiconductor device including a memory BIST circuit connected to a bus inside the CPU core circuit and executing a memory test in response to an instruction supplied via the bus.
(Supplementary Note 3) The memory BIST circuit
A register accessible via the bus from the CPU core circuit;
The semiconductor device according to appendix 1 or 2, further comprising a control circuit that controls the operation of the memory test according to the contents of the register.
(Supplementary Note 4) The memory BIST circuit
An address generation circuit for generating an address signal under the control of the control circuit;
A pattern generation circuit that generates a data signal under the control of the control circuit;
4. The semiconductor device according to appendix 3, further comprising a signal analysis circuit that compares read data from the memory with an expected value and stores a comparison result in the register.
(Supplementary Note 5) a first signal line for supplying the address signal from the memory BIST circuit to the memory;
A second signal line for supplying the data signal from the memory BIST circuit to the memory;
A third signal line for supplying the read data from the memory to the memory BIST circuit;
The semiconductor device according to appendix 4, wherein the first to third signal lines are provided separately from the bus.
(Supplementary note 6) The semiconductor device according to supplementary note 5, further comprising a pipeline register provided on a path of the first to third signal lines.
(Appendix 7) The signal analysis circuit is:
A comparison circuit for comparing the read data with the expected value;
The semiconductor device according to claim 6, further comprising a timing adjustment circuit that adjusts the timing of the expected value supplied to the comparison circuit in accordance with the number of stages of the pipeline register.
(Supplementary note 8) The semiconductor according to Supplementary note 4, wherein the memory BIST circuit supplies the address signal and the data signal to the memory via the bus and receives the read data from the memory via the bus. apparatus.
(Appendix 9) The memory BIST circuit asserts a busy signal when executing the memory test, and the CPU core circuit stops an instruction execution operation in response to the assertion of the busy signal. Semiconductor device.
(Supplementary Note 10) The address generation circuit and the pattern generation circuit are provided for each of a plurality of memories, and further include a serial interface for transmitting a control signal from the control circuit to the plurality of address generation circuits and the pattern generation circuit. The semiconductor device according to appendix 4, which is included.
(Supplementary note 11) The semiconductor device according to supplementary note 4, wherein the signal analysis circuit is provided for each of the plurality of memories, and further includes a serial interface for transmitting data from the plurality of signal analysis circuits to the register. .
(Supplementary note 12) The semiconductor device according to supplementary note 4, wherein the signal analysis circuit further includes a mask circuit for masking the read data and the expected value.
(Supplementary note 13) The semiconductor device according to supplementary note 4, wherein the signal analysis circuit further includes a failure setting circuit for setting a failure value to the read data or the expected value.
(Supplementary Note 14) When the read data does not match the expected value, the signal analysis circuit immediately asserts a stop signal, and the control circuit, the address generation circuit, and the pattern generation circuit assert the stop signal. 6. The semiconductor device according to appendix 4, wherein the operation is stopped while the internal operation state is maintained in response.
(Supplementary note 15) The semiconductor device according to Supplementary note 14, wherein the CPU core circuit can read the internal operation state via the register.
(Supplementary note 16) The semiconductor device according to supplementary note 14, wherein the memory BIST circuit can restart the operation from a state in which the operation is stopped while the internal operation state is maintained.
(Supplementary Note 17) In a semiconductor device including a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit that executes a memory test according to an instruction supplied from the CPU core circuit via the bus ,
Transition to voltage control mode,
After changing to the voltage control mode, change the voltage of the internal power supply voltage,
After the internal power supply voltage is changed, the memory BIST circuit determines whether or not the memory operation is normal at the internal power supply voltage after the change,
If the memory operation is not normal as a result of the determination, the internal power supply voltage is changed and the determination is performed again.
A voltage control method comprising the steps of returning from the voltage control mode to a normal operation when the memory operation is normal as a result of the determination.
(Supplementary Note 18) Before changing the internal power supply voltage, the contents of the register are saved,
Detecting whether or not it hangs up after changing the internal power supply voltage,
Item 18. The voltage control method according to Item 17, further comprising the steps of restoring the contents of the register when the hang-up is detected.

It is a figure which shows the structure of the 1st Example of the semiconductor device incorporating the memory BIST circuit by this invention. It is a figure which shows an example of the address pattern which an address generation circuit produces | generates. It is a figure which shows another example of the address pattern which an address generation circuit produces | generates. It is a circuit diagram which shows an example of a structure of the signal analysis circuit provided with the mask processing function. It is a figure which shows an example of a structure of the 2nd Example of the semiconductor device containing the memory BIST circuit by this invention. It is a figure which shows an example of a structure of the 3rd Example of the semiconductor device containing the memory BIST circuit by this invention. It is a figure which shows an example of a structure of the signal analysis circuit in the case of a 3rd Example. It is a figure which shows an example of a structure of the signal analysis circuit suitable for the defect analysis of the memory which is operate | moving with a high-speed operating frequency. It is a figure which shows an example of a structure of the signal analysis circuit provided with the function which detects the defect of an expected value comparator. It is a figure which shows another example of a structure of the signal analysis circuit provided with the function which detects the defect of an expected value comparator. It is a figure which shows an example of a structure of the 4th Example of the semiconductor memory device carrying the memory BIST circuit by this invention. It is a flowchart which shows the memory operation confirmation method at the time of a voltage change.

Explanation of symbols

1 memory BIST circuit 2 register set 6 control circuit 7 address generation circuit 8 pattern generation circuit 9 signal analysis circuit 10 CPU core 13 module 16 bus bridge 17 on-chip bus 18 internal peripheral bus 19 module 20 module 21 control signal line 22 write data signal Lines 23 to 26 Read data signal line

Claims (3)

  1. A CPU core circuit;
    A bus connected to the CPU core circuit;
    A memory BIST circuit that executes a memory test in response to an instruction supplied from the CPU core circuit via the bus;
    A first signal line for supplying an address signal from the memory BIST circuit to the memory;
    A second signal line for supplying a data signal from the memory BIST circuit to the memory;
    A third signal line for supplying read data from the memory to the memory BIST circuit;
    A pipeline register provided on a path of the first to third signal lines; the first to third signal lines are provided separately from the bus; and the memory BIST circuit includes:
    A register accessible via the bus from the CPU core circuit;
    A control circuit for controlling the operation of the memory test according to the contents of the register;
    An address generation circuit for generating the address signal under the control of the control circuit;
    A pattern generation circuit for generating the data signal under the control of the control circuit;
    A signal analysis circuit that compares the read data from the memory with an expected value and stores a comparison result in the register; the signal analysis circuit includes a plurality of buffers for the expected value supplied from the pattern generation circuit; delaying timing and clock synchronization by the register, the signal analysis circuit, for a series of the read data and a set of the expected value, when there is a mismatch when there is disagreement even once for any bit position Immediately assert a stop signal, the control circuit, the address generation circuit, and the pattern generation circuit stop the operation while maintaining the internal operation state in response to the assertion of the stop signal, and from the circuit that stopped the operation Information indicating the memory subject to the memory test, the address address when the inconsistency occurs, and the currently executing memory Information indicating the content of Li test, a semiconductor device wherein the CPU core circuit, characterized in that the reading construed said register.
  2.   The address generation circuit and the pattern generation circuit are provided for each of a plurality of memories, and further include a serial interface that transmits a control signal from the control circuit to the plurality of address generation circuits and the pattern generation circuit. The semiconductor device according to claim 1.
  3.   2. The semiconductor device according to claim 1, wherein the signal analysis circuit further includes a failure setting circuit for setting a failure value to the read data or the expected value.
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