TW200901415A - Semiconductor package using copper wires and wire bonding method for the same - Google Patents

Semiconductor package using copper wires and wire bonding method for the same Download PDF

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Publication number
TW200901415A
TW200901415A TW096123660A TW96123660A TW200901415A TW 200901415 A TW200901415 A TW 200901415A TW 096123660 A TW096123660 A TW 096123660A TW 96123660 A TW96123660 A TW 96123660A TW 200901415 A TW200901415 A TW 200901415A
Authority
TW
Taiwan
Prior art keywords
carrier
wire
semiconductor package
copper
chip
Prior art date
Application number
TW096123660A
Other languages
Chinese (zh)
Inventor
Han-Lung Tsai
Chih-Ming Huang
Cheng-Hsu Hsiao
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW096123660A priority Critical patent/TW200901415A/en
Priority to US12/215,543 priority patent/US20080265385A1/en
Publication of TW200901415A publication Critical patent/TW200901415A/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

This invention provides a semiconductor package using copper wires and a wire bonding method for the same. The semiconductor package includes a carrier having a plurality of bonding contacts, and a chip mounted on the carrier. The wire bonding method includes: forming a plurality of bond pads on the chip; implanting stud bumps on the bonding contacts of the carrier; connecting electrically the chip and carrier by a plurality of copper wires configured for end-to-end connection of the stud bumps on the carrier and the bond pads on the chip; and forming encapsulant on the carrier to encapsulate the chip, copper wires, and stud bumps. The stud bumps implanted on the bonding contacts of the carrier improve bondability of the copper wires with the bonding contacts of the carrier, thus preventing stitch lift. With satisfactory eutectic bonding, residues of copper wires left behind after a soldering process have even tail surfaces and uniform tail length, thus enabling fabrication of free air balls (FAB) of uniform size. The method dispenses with a conventional step of implanting bumps on the bond pads of a chip, but improves eutectic bonding between the stud bumps and bond pads and thereby prevents ball lift which might otherwise arise from poor eutectic bonding of the bond pads of the chip.

Description

200901415 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種具銅線之半導體封裝件及其打線方 法’尤指一種以銅線電性連接承載件及接置於該承載件上 之晶片的半導體封裝件及用於該半導體封裝件之打線方 法。 【先前技術】 習知半導體封裝件’通常係使用金線（Au wire)將晶片 電性連接至如導線架或基板之晶片承載件，此乃因金線與 導線架銲結點（Finger)上之鍍銀層或基板銲結點上之鍍鎳 /金（Ni/Au)層可產生良好的共晶’而得確保金線與相對銲 結點之銲接品質；但金質材質之銲線有價格昂貴的缺點， 因此在銲線材質使用上，遂有以銅（Cu)質材質取代金（Au) 質材質的趨勢’但銅線（Cu wire)與導線架銲結點上之鍍銀 層或基板録結點上之鑛錄/金（Ni/All)層間並無法產生良好 的共晶，遂會使銅線焊接至鲜結點之縫接端（stitch end)發 生短尾（short tail)現象，而造成銲接後殘留在銲嘴外的銅 線之線尾端（Tail end)不平整及其線尾長度不一之問題，致 而影響到進行次一打線（wire bonding)前銅線之線尾端經 繞球成型之銲球（Free Air Ball，FAB)，使所成型之銲球的 大小無法均一。當鲜球的大小無法均一時，即易造成銲球 與晶片上之銲墊（Bond pad)銲接之共晶性不良而產生銲球 脫落（ball lift)的問題。 換言之’如第3 A圖所示’傳統之金線（Au wire)30之 5 110187 200901415 缝接端300與基板3】之銲沾 太丄ώ 點310上之鍍鎳/金（Ni/AU) 層可產生良好的共晶，故奋始。Λ ^ ^ . ’良〇與銲結點310間不致發生 缝點脫洛（stitch lift)之問n α χ 叩之問4，且於打線 3〇〇亦不會產生短尾現象 ^後顧接知 ^ ^ ^ ^ P . 便殘邊在知鳴Μ上的金線30 具有千整之線尾端301，而八綠g㈣〇Λι ^ h > ^ ^ % ^ ^ 線尾糕301具有均一線尾長 度ϋ ’故於進仃後續之打線竹豐乂 .,+/ι λΑ,θ玎深作業則之燒球時，均能成型出 大J較為均一的~球3〇2，而能#彳&八$ 向此確保金線與銲結點間之銲 接口口貝。而在使用銅線時， 弟川圖所不，由於銅線30, 與基板31’之銲結點31〇，上 上之銀鎳/金（Ni/Au)層間不呈良 好的共晶性’銅線30’之缝接端着於銲接至該群結點训， 後，該缝接端300’易形成短尾現象，而造成銲接後殘留在 銲嘴M，外之銅線3〇,的線尾端3()1，會產生不平整之狀況及 線尾長度h’不一的問題，遂使進行後續打線作業前之 時，產生的銲球302,之大小盔沐的 ^ 人小無法均一，而易造成銲接至晶 片33’之銲墊330,上的銲球3〇2,脫落（ball Hft)。 為了解決上述問題，如第4圖所示，美國專利公 20040072396號案揭示於晶片42之銲墊42〗上植設—金質 凸塊43(Au Stud Bump) ’以供銅線40之銲球4〇2得以銲二 於金質凸塊43上’由於該兩者能產生良好的共晶，故得提 升銅線40與銲墊421之銲結信賴性，有效改善銲球4〇2 脫落（ball lift)問題。惟，如前所述，銅線4〇與導線架戋美 板41之銲結點411上之鍍銀層或鍍鎳/金（Ni/A…層，仍無 法產生良好的共晶，故銅線之縫接端4〇〇銲接至鮮結點4ιι 上後仍存在有縫接點脫落（stitch lift)問題或短尾現象，亦 110187 6 200901415 .t影響貌續銲球形叙尺寸均—性（已詳述於前，故不另 贅言）。 力 因此’如何提出一種半導體封裝件及其打線方法，以 =銅線於as >{之銲塾上的銲球脫落⑽1闹問題，及於 架或基板上銲結點的缝點脫落（Stitch lift)問題，提升 ，：之銲結信賴性，確為此相關領域所迫切待解之課題。 【發明内容】 4柯 及其：目的在於提供一種具銅線之半導體封裝件 凸塊，提升銅’由f設與承載件之銲結點共晶良好的金質 ^ ·5、，、於銲結點的銲著性（bondability)，藉以解決 銲結點的縫點脫落⑽chnft)之問題。 错场决 本發明之另一目的在於接徂 _ 件及1^在於鍉供一種具銅線之半導體封裝 質^ 由植設與承載件之銲結點共晶良好的金 之問題。猎4決銅線於晶片之鲜塾的鮮球脫落⑽1肋） 件及種Γ線之半導體封裝 質凸塊’使銲接後殘留在銲嘴外:1點=良好的金 及均-的線尾長度，俾於進行次線之，尾端’ ，之銲球得大小均—，而毋需經 Λ # , 片之鲜墊形成良好的共晶。 為達刚述及其他目的’本發 = :::具有多數録结點的承二：:； Ί或基板；植設於該承載件之銲結點上之凸塊(stud 110187 7 200901415 • Bump)，該凸塊之材質係為包含金（Au)的材質，·接置於該 承載件上之晶片，於該晶片之作用表面上係具有多數銲 墊’·多數銅線，使各該銅線之兩端部分別銲接至晶片上之 鲜墊與承載件上之凸塊，俾藉由該銅線電性連接該晶片與 承載件；以及形成於該承載件上以包覆該晶片、銅線及凸 塊之封裝膠體。 本發明並提供一種用於前揭半導體封裝件之打線方 法，其步驟係包括··提供承载有晶片之承載件，而該承載 導線架或基板’且該承載件上具有多數銲結點，而 銲結點上植設凸塊，以及分別將多數銅線之一端 ^干：至-接置於該承载件上之一晶片上所形成的多數鋒 2將銅線之另-端部銲接至該銲結點上的凸塊， 由該銅線將晶片電性連接至承載件。 ^此，《明所揭示之具銅線之半導體封裝件及其打 線方去，乃猎植設於承載件之銲結 成良好的共晶，而 /貝凸塊與銅線形 rhn ^ 权升銅線於銲結點的銲著性 dab山ty)’俾解決銅線於承載 ㈣ch lift)問題，且銲接？點上之縫點脫洛 具平整之線尾端及均一的:尾㈣ 之線尾端經燒球成型的鮮球得大進仃；;一打線前銅線 片之銲墊上植設金質凸塊，二均―，因此毋需再於晶 法均一，而迭成白曰併解決因鲜球的大小無 而仏成〜球自晶片之銲 ，丄故可顯著提升銅線之銲結信賴性。 ）的問 【貫施方式】 110187 8 200901415 • 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技蟄之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其^不5 的具體實施例加以施行或應用，本說明書中的各項細== 可基於不同觀點與應用，在不悖離本發明之精神下夂 種修飾與變更。 τ谷 ▲以y之實施例係進—步詳細說明本發明之特徵及 效，但並非用以限制本發明之可實施範_。 本發明所提供之具銅線之半導體封裝件，係示於 :二圖導體封裝件，包括基板11、接置於該 土板上之日日片12、植設於該基板η上之全質 = 多數用以電性連接該基板‘2= 以及形成於該基板u上以包覆該晶片 二 凸塊13與銅線14之封裝膠體15。 ·，貝 該基板11上形成有多數鋒結點⑴，以讓金 杯設於該銲結點⑴上，俾供各 端 以縫接銲接之方式鱼 之知邛142 用之環氧樹炉其也鬼銲接。該基板11得為習 故該銲結點二胺基板、玻璃基板或陶莞基板， 之承載件者並不限於述。同時，作為晶片12 導線架承載晶片12。u ?所使用之基板1卜亦可使用 。亥日日片12上形成有多數 另一端部所燒球成型的銲球ui^121 ’仏各該銅線14之 分別端接至該基板u之, 鲜接其上，俾在該銅線14 之鲜結點1Π及晶片12之銲墊121 110187 9 200901415 .後，晶片12能藉該銅線14而與基板電性連接。 由於形成該封裝膠體15之模壓作業(Molding Pr〇cess) 及晶片12與基板11之黏接作業（Die Bond)均為習知，故 在此不另為文贅述。 一該半導體封裝件i之功效將於本發明之打線方法中予 以詳述。 如第2A至2B圖所示’本發明之打線方法能應用於以 批-人（Batch)或單數（Piece by piece)方式形成半導體封裝件 之製程中。 如第2A圖所示，該方法係先於形成於基板丨1上之多 數銲結點m上植設多數金質凸塊13，然後，如第圖 所不，以打線機將-銅線14之端部燒球成型為鲜球斤以 Απ Ball, FAB)141，再將鲜们4i以超音波熱壓或超音波 2合之方式銲，至該晶片12上之銲墊121，接著，將打線 圖不）之鋅嘴Μ上移—預定高度後，下引銲嘴M朝基 、板11之銲結點111移動，以形成銅線14之線弧（Wire Loop)，攻该銲嘴M移至銲結點m處時，即下壓該銲嘴 M以將銅線14缝點銲接至該銲結·點111上之金質凸塊 13 ’俾使該銅線14形成與金質凸塊13良好共晶且呈半月 ^之縫接端142，而完成銅線14與晶片12之鮮墊121及 基板11之銲結點111之銲接。200901415 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package having a copper wire and a wire bonding method thereof, and more particularly to a copper wire electrically connecting a carrier and being attached to the carrier A semiconductor package of a wafer and a wire bonding method for the same. [Prior Art] A conventional semiconductor package 'usually uses a gold wire to electrically connect the wafer to a wafer carrier such as a lead frame or a substrate, because the gold wire and the lead frame are soldered to the fuser. The nickel-plated/gold (Ni/Au) layer on the silver plating layer or the substrate solder joint can produce good eutectic' to ensure the soldering quality of the gold wire and the opposite solder joint; however, the gold material has a bonding wire The disadvantage of being expensive, therefore, in the use of the wire material, there is a tendency to replace the gold (Au) material with a copper (Cu) material, but the copper wire on the Cu wire and the lead frame is welded. Or the eutectic/gold (Ni/All) layer on the substrate recording point does not produce good eutectic, and the copper wire is soldered to the seam end of the fresh joint to have a short tail. Phenomenon, which causes the unevenness of the Tail end of the copper wire remaining outside the tip after soldering and the length of the tail end of the wire, which affects the copper wire before the second wire bonding The ball at the end of the wire is formed by a ball (Free Air Ball, FAB), so that the size of the formed solder ball is not uniform. . When the size of the fresh ball is not uniform, the eutecticity of soldering the solder ball to the bond pad on the wafer is liable to cause a problem of ball lift. In other words, 'as shown in Figure 3A', the conventional gold wire (Au wire) 30 5 110187 200901415 the seam end 300 and the substrate 3 are soldered to the surface. The nickel/gold (Ni/AU) on the point 310 The layer can produce good eutectic, so it starts. Λ ^ ^ . 'The problem of the stitch lift of the tie lift 焊 4 4 n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n ^ ^ ^ ^ P . The gold line 30 on the Zhiming 具有 has a thousand ends 301, and the eight green g(four) 〇Λι ^ h > ^ ^ % ^ ^ line cake 301 has a uniform tail Length ϋ 'So in the follow-up line of Zhu Feng 乂., + / ι λ Α, θ 玎 deep work, when burning the ball, can form a larger J more uniform ~ ball 3 〇 2, and can #彳 &amp ; eight $ to ensure the welding mouth between the gold wire and the welding node. When the copper wire is used, the Tachikawa figure does not. Because of the copper wire 30, the solder joint 31〇 with the substrate 31', the upper silver-nickel/gold (Ni/Au) layer does not have good eutecticity. The seam of the copper wire 30' is welded to the group of joints, and the seamed end 300' is easy to form a short tail phenomenon, which causes the welding wire M to remain after the welding, and the copper wire outside is 3 〇. At the end of the line 3 () 1, there will be a problem of unevenness and the length h' of the end of the line, so that when the subsequent wire-laying operation is performed, the generated solder ball 302 is the size of the helmet. Uniform, and easy to solder to the pad 330 of the wafer 33', the solder ball 3 〇 2, ball hft. In order to solve the above problem, as shown in FIG. 4, U.S. Patent No. 20040072396 discloses the implantation of a gold bump 43 (Au Stud Bump) on the pad 42 of the wafer 42 for the solder ball of the copper wire 40. 4〇2 can be soldered on the gold bumps 43. Since the two can produce good eutectic, the solder joint reliability of the copper wire 40 and the solder pad 421 can be improved, and the solder ball 4〇2 falling off can be effectively improved ( Ball lift) problem. However, as described above, the copper wire 4〇 and the lead frame 411 of the lead frame 411 of the silver plated layer or nickel/gold plating (Ni/A... layer still cannot produce good eutectic, so copper There is still a stitch lift problem or a short tail phenomenon after the seam of the wire is welded to the fresh joint 4 ι 4, and 110187 6 200901415 .t influences the shape of the spheroidal dimension. It has been described in detail before, so there is no further rumor.) The force therefore 'how to propose a semiconductor package and its wire-bonding method to = copper wire on the solder ball on the soldering as (10) 1 problem, and the frame Or the Stitch lift problem of the solder joints on the substrate, the improvement, and the reliability of the solder joints are indeed urgent issues to be solved in the related field. [Invention] 4 Ke and its purpose: to provide a Copper-clad semiconductor package bumps, which enhance the copper's eutectic bond quality with the solder joints of the carrier, and the bondability at the solder joints, thereby solving the soldering The problem of the seam point of the joint falling off (10) chnft). Wrong field decision Another object of the present invention is to provide a problem in that the semiconductor package of a copper wire is eutectic with a solder joint of the implant and the carrier. Hunting 4 copper wire on the wafer fresh squid off the ball (10) 1 rib) and the semiconductor package bump of the seed line 'to make the weld residue outside the tip: 1 point = good gold and even - tail The length, 俾 进行 进行 进行 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , For the purpose of Dagang and other purposes 'this hair = ::: with a majority of the record points::; Ί or substrate; bumps implanted on the solder joints of the carrier (stud 110187 7 200901415 • Bump The material of the bump is a material containing gold (Au), and the wafer attached to the carrier has a plurality of pads on the active surface of the wafer, and a plurality of copper wires are used to make each of the copper. The two ends of the wire are respectively soldered to the fresh pad on the wafer and the bump on the carrier, and the wafer and the carrier are electrically connected by the copper wire; and formed on the carrier to cover the wafer and copper The encapsulant of the wire and the bump. The present invention also provides a wire bonding method for a front-end semiconductor package, the steps of which include: providing a carrier carrying a wafer, and carrying the lead frame or substrate 'and having a plurality of solder joints on the carrier A bump is implanted on the solder joint, and one of the plurality of copper wires is respectively dried: a majority of the front end 2 formed on one of the wafers on the carrier is soldered to the other end of the copper wire A bump on the solder joint, the wafer is electrically connected to the carrier by the copper wire. ^This, "The semiconductor package with copper wire revealed by Ming and its wire-cutting side is welded to the carrier to form a good eutectic, and / bump and copper linear rhn ^ weight copper wire The solder joints of the solder joints dab mountain ty) '俾 solve the copper wire on the load (four) ch lift), and welding? The point on the point is the end of the line and the uniform: the tail of the tail (4) is made of a new ball formed by the burning ball; the gold piece is placed on the pad of the copper wire before the line Block, two--, so it is no longer necessary to be uniform in the crystal method, and it is stacked into a white enamel and solved because the size of the fresh ball is not formed and the ball is soldered from the wafer, so that the solder joint reliability of the copper wire can be significantly improved. . The method of the present invention is explained by the specific embodiments of the present invention. Those skilled in the art can easily understand other advantages of the present invention from the contents disclosed in the present specification. efficacy. The present invention can also be implemented or applied by the specific embodiment of the present invention. The details of the present invention can be modified and changed without departing from the spirit and scope of the invention. τ谷 ▲ In the embodiment of y, the features and effects of the present invention are described in detail, but are not intended to limit the implementation of the present invention. The semiconductor package with a copper wire provided by the present invention is shown in: a conductor package of the second figure, comprising a substrate 11, a sun piece 12 attached to the earth plate, and a whole body implanted on the substrate η A plurality of the encapsulants 15 for electrically connecting the substrate '2= and the substrate u to cover the wafer bumps 13 and the copper wires 14. · The base plate 11 is formed with a plurality of front nodes (1) so that the gold cups are disposed on the solder joints (1), and the ends are provided by seam welding, and the fish is known as the 142. Ghost welding. The substrate 11 is conventionally a solder joint of a diamine substrate, a glass substrate or a ceramic substrate, and the carrier is not limited to the above. At the same time, the wafer 12 is carried as a wafer 12 lead frame. u ? The substrate 1 used can also be used. On the celestial sheet 12, a solder ball ui^121 formed by a plurality of balls burned at the other end is formed, and each of the copper wires 14 is terminated to the substrate u, and is directly connected thereto, and the copper wire 14 is placed thereon. The chip 12 and the pad 12 of the wafer 12 are 110 110187 9 200901415. Thereafter, the wafer 12 can be electrically connected to the substrate by the copper wire 14. Since the molding operation for forming the encapsulant 15 and the bonding operation of the wafer 12 and the substrate 11 are well known, they are not described herein. The efficacy of the semiconductor package i will be described in detail in the wire bonding method of the present invention. As shown in Figs. 2A to 2B, the wire bonding method of the present invention can be applied to a process of forming a semiconductor package in a batch or a tablet (Piece by piece) manner. As shown in FIG. 2A, the method is to implant a plurality of gold bumps 13 on a plurality of solder joints m formed on the substrate ,1, and then, as shown in the figure, a wire bonding machine-copper wire 14 The end of the ball is formed into a fresh ball, Α π Ball, FAB) 141, and then the fresh 4i is welded by ultrasonic hot pressing or ultrasonic wave bonding to the pad 121 on the wafer 12, and then, After the predetermined height is reached, the lower lead tip M moves toward the base node 11 and the solder joint point 111 of the board 11 to form a wire loop of the copper wire 14 to attack the tip M of the wire. When the solder joint M is pressed, the soldering iron M is pressed down to weld the copper wire 14 to the gold bump 13 ' on the solder joint 111, so that the copper wire 14 is formed with the gold bump 13 is well eutectic and is half-mooned to the end 142, and the copper wire 14 is soldered to the fresh pad 121 of the wafer 12 and the solder joint 111 of the substrate 11.

山由於該銲結點111上之金質凸塊13能與銅線14之縫 接端142良好地共晶，故該縫接㈣142 +會發生短尾現象， 也不致產生因短尾現象而導致縫接端142自金質凸塊U 110187 30 200901415 .上脫洛之問題’且因銅線14於缝點鮮接後，不會有短尾 象之發生，令外露出該銲嘴Μ之線尾端143不致產生 ，而使進行次一打線作業時所燒球成 出之㈣141白勺大小能均一；由於該銲球ΐ4ι之 能大小均-，故在鮮接至晶片12上之另一鲜塾ΐ2ι後成句 3i::=(BallUft)的狀況。因而’本發明之具銅線 曰、-、十衣件及其打線方法，能顯著提升銅線與晶片及 曰曰片承載件間之銲著性，進而確保半導體封裝件之信賴性。 上述實施例僅為例示性說明本發明之原理及其功效， ，非用於限制本發明。任何熟習此技藝之人士均可在不違 背本發明之精神及範訂，對上述實施例進行修飾與變 2。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。 【圖式簡單說明】 第1圖係本發明所揭示之半導體封裝件的剖視圖； \ 第2 A及2B圖係本發明之打線方法的流程示意圖； 第3A圖係習知之使用金線（Au wire)之半導體封 的剖視圖； & 第3B圖係習知之使用銅線（Cu wire)之半導體封裝件 的剖視圖； & 第4圖係美國專利公開第2〇〇4〇〇72396號之半導體封 裝件的剖視圖； 、 11 承載件 【主要元件符號說明 1 半導體封裝件 110187 11 200901415 111 銲結點 12 晶片 121 鲜墊 13 凸塊 14 銅線 141 録球 142 缝接端 143 線尾端 15 封裝膠體 30 金線 300 缝接端 301 線尾端 302 鮮球 31 承載件 310 焊結點 30, 銅線 3005 缝接端 301， 線尾端 302, 鲜球 31， 承載件 310’ 銲結點 33? 晶片 33CT 銲墊 40 銅線 400 縫接端 402 鲜球 41 承載件 411 銲結點 42 晶片 421 銲墊 43 凸塊 12 110187Because the gold bumps 13 on the solder joints 111 can be well eutectic with the seam ends 142 of the copper wires 14, the stitching (four) 142+ will have a short tail phenomenon, and no short tail phenomenon will occur. The seam end 142 is from the gold bump U 110187 30 200901415 . The problem of the upper detachment ' and the copper wire 14 is freshly connected at the seam point, there will be no short tail image, so that the wire of the tip is exposed The tail end 143 is not generated, and the size of the ball that is burned by the ball in the next one-line operation is uniform. The size of the ball is uniform. Since the size of the ball 均4 ι is -, another fresh spot on the wafer 12 is freshly connected.塾ΐ2ι After the sentence 3i::=(BallUft). Therefore, the copper wire 曰, -, ten pieces of the present invention and the wire bonding method thereof can significantly improve the solderability between the copper wire and the wafer and the die carrier, thereby ensuring the reliability of the semiconductor package. The above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Modifications and variations of the above embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a semiconductor package disclosed in the present invention; \2A and 2B are schematic flowcharts of a wire bonding method of the present invention; FIG. 3A is a conventional use of a gold wire (Au wire) A cross-sectional view of a semiconductor package; & 3B is a cross-sectional view of a conventional semiconductor package using a Cu wire; & 4 is a semiconductor package of U.S. Patent Publication No. 2,742,396 Sectional view of the piece; 11 Carrier [Main component symbol description 1 Semiconductor package 110187 11 200901415 111 Solder joint 12 Chip 121 Fresh pad 13 Bump 14 Copper wire 141 Recording ball 142 Splicing end 143 Wire end 15 Package colloid 30 Gold wire 300 seam end 301 wire end 302 fresh ball 31 carrier 310 solder joint 30, copper wire 3005 seam end 301, wire end 302, fresh ball 31, carrier 310' solder joint 33? wafer 33CT Pad 40 Copper wire 400 Slotted end 402 Fresh ball 41 Carrier 411 Solder joint 42 Wafer 421 Pad 43 Bump 12 110187

Claims (1)

200901415 十、申請專利範圍： 1. 一種具銅線之半導體封裝件，係包括· 具有多數銲結點之承载件； 接置於該承載件上， 夕如# 形成有多數銲墊之晶片； 夕數植设於該承載件 夕献加a 碎、，'D點上之凸塊； 夕數銅線，用以分別端接 上之銲執，彳接該承載件上之凸塊及晶片 上之知墊’俾错錢線電 形成於該承載件上之封壯^日曰片與承載件；以及 線及凸塊。之封褒膠體，以包覆該晶片、銅 其 2.如申請專利範圍第1 貞之具銅、線之半導體封裝件 中該凸塊係以金(Au)為材質而製成者。 3'Γ=Γ_1項之關狀半㈣封裝件，其 二：另二端部係形成鲜球以銲接至該晶片上之辉 翊邛則以缝接銲接（stitch Bon 至該承載件上之凸塊。 万式知接 4. :申：:：範圍第1項之具銅線之半導體封裝件，其 中該承载件係為導線架。 5. ^申％專利範㈣〗項之具銅線之半導體封裝件，其 中，該承载件係為基板。 一 種用於具銅線之半導體封裝件之打線方 列步驟： 你已祜下 於形成在-承载件上之多數銲結點上方植設多 凸塊（StndBUmp);以及 之 將多數銅線之一端銲接至一接置於該承载件上 110187 13 200901415 晶片所具有之多數銲墊，而另一 之凸塊’俾藉該多數銅線電性:：：：：载件上 金為材質而製成者。、^方法’其中，該凸塊係以 .如申凊專利範圍第6項之打 :部係形成銲球以銲接至該晶片1之銲 =縫接銲接（S祕BGnd)之方式銲接至該承二= 如申凊專利範圍第6項之打缓 為導線架。 ㈣方法，其中，該承載件係 如申4專利範圍第6項之打缘 為基板。 貞之打線方法’其中’該承載件係 110187 14200901415 X. Patent application scope: 1. A semiconductor package with copper wire, comprising: a carrier having a plurality of solder joints; being placed on the carrier, Xiru # forming a wafer with a plurality of pads; The number is implanted on the carrier, and a bump is formed on the carrier, and the bump is on the 'D point; the copper wire is used to terminate the soldering on the carrier, and the bump on the carrier and the wafer are attached. Knowing the pad's wrong money line is formed on the carrier to seal the 曰 曰 与 与 and the carrier; and the line and the bump. The sealing gel is used to coat the wafer and the copper. 2. The copper-and-wire semiconductor package of the first application of the patent application is made of gold (Au). 3' Γ = Γ 项 项 项 半 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ块式知接4. :申::: The semiconductor package of the copper wire of the first item of the range, wherein the carrier is a lead frame. 5. ^申%专利范(四)〗 a semiconductor package, wherein the carrier is a substrate. A step of wire bonding for a semiconductor package having a copper wire: You have planted a multi-convex over a plurality of solder joints formed on the carrier Block (StndBUmp); and soldering one end of the majority of the copper wire to a plurality of pads on the carrier 110187 13 200901415, and the other bumps 'by the majority of the copper wires: :::: The carrier is made of gold as the material. ^ Method ' Among them, the bump is made. For example, in the scope of claim 6: the part is formed with solder balls to be soldered to the wafer 1 Welding = seam welding (S secret BGnd) way to the bearing 2 = as claimed in the sixth paragraph of the patent scope (4) The method, wherein the carrier is a substrate of the sixth aspect of the patent scope of claim 4, the method of wire bonding, wherein the carrier is 110187 14
TW096123660A 2007-04-11 2007-06-29 Semiconductor package using copper wires and wire bonding method for the same TW200901415A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI452640B (en) * 2009-02-09 2014-09-11 Advanced Semiconductor Eng Semiconductor package and method for packaging the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI452640B (en) * 2009-02-09 2014-09-11 Advanced Semiconductor Eng Semiconductor package and method for packaging the same

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