TW200849627A - Photovoltaic cell with shallow emitter - Google Patents

Abstract

A photovoltaic semiconductor apparatus for use in forming a solar cell with shallow emitter is disclosed. The apparatus includes first and second adjacent oppositely doped volumes of semiconductor material forming a semiconductor heterojunction. The apparatus also includes a first passivation layer of material on the front side, the first passivation layer having a first outer surface and a plurality of openings therethrough defining corresponding unpassivated areas of the front side that are unpassivated by the first passivation layer. The apparatus further includes a first conductive anti-reflective coating on the first outer surface of the passivation layer and on the corresponding unpassivated areas of the front side. The apparatus may further include dielectric antireflective coating on an outer surface of the first passivation layer. A conductive anti-reflective coating may be provided on the outer surface of dielectric antireflective coating layer and on the corresponding unpassivated areas of the front side. A back side surface of the apparatus may be finished in various ways including forming a passivation layer with openings as on the front side, forming a third doped volume adjacent the second doped volume, or forming a layer of aluminum with laser-fired contacts on a passivation layer on the back side surface. The apparatus may further include second conductive coating on the back side surface. The apparatus further includes first and second electrodes for collecting electric current correspondingly from front and back sides of photovoltaic apparatus.

Description

200849627 IX. INSTRUCTIONS: t TECHNICAL FIELD RELATED APPLICATIONS The US title of this application is a continuation-in-part application of 5 US Application No. 11/751,524, filed on May 21, 2007. FIELD OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to high efficiency photovoltaic (PV) cells having shallow emitters. [Previous 3 10 BACKGROUND OF THE INVENTION Crystalline germanium photovoltaic (PV) cells are generally constructed of a germanium substrate doped with impurities to produce a p/n heterojunction. The p/n heterojunction can typically form a fixed charge at the heterojunction by diffusion of phosphorus or boron into the front side of the p-type or n-type semiconductor substrate, and a permanent dipole having a voltage p 15 due to boron and phosphorus atoms. Charge layer. One part of the pv battery, between the front side and the p/n junction, is considered an emitter. When the pv battery is illuminated by light, the photon of the photon is generated by the photon. The high electric field of the /11 heterojunction provides charge separation. This displacement of the free charge results in a voltage difference between the 1) and 11 regions of the substrate. When the p&n region is connected to a circuit, current flows. This electrical 20 flow is collected from the PV cells by the front and rear metal contacts. The front and back side metal contacts are typically provided on the substrate via the use of screen printing techniques, wherein a portion of the conductive paste, which typically comprises silver and/or is screen printed on the front and back surfaces of the substrate via a mask on. As far as the front side of the substrate is concerned, the reticle typically has an opening, and the conductive paste contacts the surface of the substrate by the opening via 200849627. The front side reticle is typically configured to form a plurality of thin parallel line contacts connected to two or more thicker wires that are connected thereto and generally extend perpendicularly to the parallel line contacts. After the conductive paste is spread on the reticle, the reticle is removed and the wafer supporting the portion of the conductive paste is heated to dry the conductive paste. The wafer is then "fired" in an oven and the conductive paste enters a metal phase, at least one of which partially diffuses through the front surface of the substrate and into the substrate structure while leaving a portion of the surface solidified on the front surface. The complex thin parallel lines constitute a thin parallel linear current collection region that is considered to be a "finger", which is a thick vertical line that is considered to be a "bus bar". The finger 10 collects current from the front side of the substrate and transfers it to the power pole. The power pole can be connected to a circuit. Typically, each finger has a width and height of about 12 microns and 1 micron, respectively. Although the fingers are sufficient to collect a small current from the substrate, the poles need to collect a larger current from the fingers of the plurality, and accordingly have a larger cross section 15 and width. On the back surface of the substrate, a portion of the conductive paste containing the components of silver and aluminum is screen printed and dried in a region where it is used as an electrical contact. The partially conductive lean portion comprising aluminum is then spread over the entire back surface of the substrate and partially overlaps the edges of the contacts. This conduction is then dried by heating. The substrate is then subjected to "burning" in an oven and partially diffused into the back surface of the substrate. This produces a highly doped P+ layer, or back surface field (BSF), at the back surface of the substrate. Aluminum also alloys with the silver/aluminum joints in such areas where it overlaps the contacts. Between the back side fields of aluminum diffusing into the back surface of the substrate, the silver/aluminum contacts thus appear as a silver/yel solder pad in 200849627. The silver/aluminum contacts collect current from the back side of the substrate and serve as an electrical termination for the back side of the substrate. The area occupied by the finger and the power rod on the front side of the substrate is a well-known shading area (sha (jing area), because the non-transparent conductive paste constituting the hand 5 fingers and the power rod in this area) Preventing solar radiation from reaching the surface of the substrate. This shaded area reduces the current generation capacity of the device. Modern solar cell substrate pockets occupy 6_1% of the available active surface area.

/ The presence of metal contacts on the back side and the presence of silver/aluminum pads on the back side also cause a reduction in the voltage generated by the substrate, proportional to the metallized area, since the 10 junctions are diffused into the substrate before the side surface is charged Recombination has an adverse effect. Due to the different coefficients of thermal expansion between tantalum and silver/aluminum paste, conventional metallization techniques can also cause the substrate to bow. This is a problem with thin solar cells that use substrates that are less than 180 microns thick, rendering the cells fragile and thus reducing throughput. 15 20 In addition, traditional metallization techniques result in substantial damage in the emitter region. "This is to increase the conversion efficiency of solar power using conventional screen printing metallization techniques." The emitter design parameters are usually incorporated in the light illumination region. The best level of impurity concentration is as low as possible and the emitter is extremely thin. This is provided to improve photon collection, especially in the blue spectral region. Doping concentration in the area below the fingertip And the thickness of the emitter is on the & Ν $ series for the low electricity and % contact between the substrate and the finger and the power pole, but does not let ρ / show the media Emperor 4th /, Bay joint knife flow. It is easy to say, Need to make solar energy with the same emitter: radiant: its package, with different dopant concentrations and not ' 偟 使用 使用 使用 使用 使用 使用 使用 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Complicated. The field was awarded to Ruby et al. entitled "Self-Aligned? Selective-Emitter9Plasma.Etchback Process" by the title "Self-Aligned, Selective-Emitter9Plasma.Etchback Process" Patent No. 5,871,591 Out of a process for forming a selective emitter and passivated. The process uses a heavily doped emitter of plasma to improve its performance. Screen printing metal pattern, the so-called thumb of the solar cell, is used to shield the plasma residue so that only the emitter 10 is etched in the region 10 between the thumb poles, while the region below the gate maintains re-doping Miscellaneous to provide low contact resistance between the substrate and the screen printed metal gate. This process is potentially cost effective because it does not require precise alignment between the heavily doped regions and the screen printed pattern. After the emitter is etched, tantalum nitride is deposited by plasma enhanced chemical vapor deposition to produce an antireflective coating. The solar 15 energy cell is then annealed in a forming gas. Although this method allows for the formation of a selective emitter and increases solar cell efficiency, it has the disadvantage that selective emitter formation occurs only after the screen printed metal pattern has been formed on the solar cell b cell, and thus depends on the conventional Screen printing metallization technology. 20 awarded to Ruby et al. entitled “Self-Aligned by a self-aligned, selective emitter, plasma etchback process” (Self-Aligned,

A photovoltaic cell and a method of fabricating the same are described in U.S. Patent No. 6,091,021, the entire disclosure of which is incorporated herein by reference. Selective etching of the 200849627 polar region. This self-aligned selective etch provides an enhanced blue light response compared to a cell with a uniformly heavily doped emitter while maintaining a heavier push in the region below the gate line for low contact resistance. This can be used in place of the expensive and difficult alignment method for selectively etching the emitter and can be easily integrated with existing plasma processing methods and techniques. However, the proposed method requires selective emitter formation to be performed only after screen printing metallization has been applied to the solar cell, such that the process is dependent on conventional screen printing metallization techniques. 10 15 awarded to H〇rzel et al. entitled “Semiconductor devices with selective diffusion regions (Semiconductor Device whh sdectiveiy with ornaments (10) (10) (4)”, patents 6, 552, 414 and M25, with a description of the selective diffusion region A neon (pv) battery having a different degree of heterogeneity. The first screen printing process is for depositing a conductive paste of a cerium 3 dopant on a diffusion region of a substrate for generating a ytterbium-doped shot. The polar region. The metallized pattern of the screen-deposited deposition of your sample ^ her heart ~ the system is precisely aligned to ensure that the structure is connected to the highly doped emitter region. Furthermore, ^ _ and screen printing metallization technology. SUMMARY OF THE INVENTION According to one aspect of the present invention, m ” is used to form a solar cell, and the first and second phases of a semiconductor heterojunction are formed. The adjacent opposite half-and-sun 祛...6 doped volume of the material. The first-doped valley system is used as an emitter, and the device also includes a front side on the front side for receiving light. With a - outer surface and a passivation material layer, the opening of the first blunt number, through which the unenpassed regions of the corresponding front side are not passivated by the first passivation layer. The device further comprises a first layer located in the passivation layer a first conductive anti-reflective coating on the outer surface and the corresponding unpassivated region on the front side. The semiconductor heterojunction may be at least one of an ion implanted heterojunction and a thermally diffused 5 heterojunction. The first doped volume may have a sheet resistivity of from about 60 ohms per square to about 150 ohms per square, and desirably has a sheet resistivity of from about 80 ohms per square to about 150 ohms per square. The layer may be comprised of at least one of SiO 2 , SiN 4 and SiC 10. The first passivation layer may have a thickness of from about 10 nm to about 500 nm, and preferably from about 10 nm to about 50 nm. The thickness of the openings is from about 50 microns to about 200 microns. The openings in the first passivation layer are arranged in a parallel line to cover the 15th outer surface. Between the parallel lines of the openings in the second passivation layer Distance From 500 microns to about 5000 microns, the parallel lines can be joined by intersecting parallel lines to form a gate configuration. 20 The gate configuration has a mesh of from about 500 square microns to about 5000 square microns. The first conductive anti-reflective coating can be continuous. The first conductive anti-reflective coating can have a thickness of from about 70 nanometers to about 280 nanometers. 10 200849627 The first conductive anti-reflective coating can comprise InOx, SnOx, At least one of InSnOx, TiOx, and Ζn. The first conductive anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. 5 the device may include a second passivation layer on the backside surface, the second passivation layer having a second outer surface having a second plurality of openings through which the passivation is not passivated by the second passivation layer Corresponding front side unpassivated areas. The device also includes a second conductive anti-reflective coating on the second outer surface of the second passivation layer and the corresponding unpassivated region of the second outer surface. The second passivation layer may be composed of at least one of Si〇2, SiN4, and SiC. The second passivation layer can have a thickness of from about 10 nanometers to about 5 nanometers, and 15 preferably has a thickness of from about 10 nanometers to about 50 nanometers. The width of the openings in the second passivation layer is from about 50 microns to about 200 microns. The openings in the second passivation layer are arranged in a parallel line to cover the second outer surface. 20 The parallel lines may be spaced apart from about 500 microns to about 5000 microns. The parallel lines can be connected by a parallel parallel line to form a thumb-shaped configuration. The germanium gate configuration has a mesh of from about 5 square microns to about 5 square meters. 11 200849627 The second conductive anti-reflective coating can be continuous. The second conductive anti-reflective coating has a thickness of at least about the thickness of the first conductive anti-reflective coating. The second conductive anti-reflective coating has a thickness of from about 70 nanometers to about 500 nanometers. 5 The second conductive anti-reflective coating may comprise InOx, SnOx, InSnOx,

At least one of TiOx and ZnOx. The second conductive anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. In order to use a photovoltaic semiconductor device in a solar cell, the first and the 10 second electrodes are connected to the front side and the back side of the device. The first electrode includes a first light transmissive electrically insulating film having first and second opposing sides. The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating. The first electrode further includes a first plurality of conductors in the first adhesive coating such that a portion of the first plurality of conductors protrude from the first adhesive. The portions are soldered to the first conductive anti-reflective coating by an alloy coating on the portions for the first conductive anti-reflective coating and a portion of the first plurality of conductors The ohmic connection is formed such that electrons can pass between the unpassivated region on the front side and the first plurality of conductors, allowing the current 20 generated by the photovoltaic semiconductor device to be conducted by the first plurality of conductors. The second electrode includes a second electrically insulating film having first and second opposing sides. The first side of the second film has a second adhesive for bonding the second film to the second conductive anti-reflective coating. The second electrode further includes a second plurality of 12 200849627 conductors embedded in the second adhesive coating, such that a portion of the second conductor of the conductor adheres to the second plurality of conductors of the second portion One of the eight coatings on the parts is welded to the second material anti-reflection _, the heart (four) is divided into a plurality of conductors and the second material anti-reverse layer constitutes ohms: connection, resulting in electrons (four) money The second outer surface is fused by the second plurality of conductors to allow conduction through the second plurality of conductors by the flow generated by the photovoltaic semiconductor device. ^ In place of the second passivation layer and the second conductive anti-reflective coating, the apparatus may include opposite the semiconductor heterojunction and the second exchange volume: 10 adjacent to the second doping volume on the side a third doping volume. The third doped volume has the same polarity as the second doped volume to form an isotype junction with the second doped volume. The third doping volume also has a doping concentration greater than one of the second doping volumes, and the third doping volume has a backside surface. The device further includes a conductive anti-reflective coating on the backside surface of the third doped volume. The second conductive anti-reflective coating can be continuous and uniform, and have a thickness that is about the same as, or greater than, one of the first conductive anti-reflective coatings. The second conductive anti-reflective coating can have a thickness of from about 70 to about 500 nanometers. The second conductive anti-reflective coating layer may include at least one of In〇x, SnOx, InSnOx, TiOx, and ZnOx. The second conductive anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per 13 200849627 square. A solar cell using the device having the third doping volume is constructed by connecting the first and second electrodes to the front and back surfaces of the device. The first electrode includes a first light-transmissive electrically insulating film having 5 first and second opposing sides. The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating. The first electrode further includes a first plurality of conductors intended to be in the first adhesive coating such that a portion of the first plurality of conductors emerge from the first adhesive coating. The portions are soldered to the first 10 conductive anti-reflective coating by an alloy coating thereon for between the first conductive anti-reflective coating and a portion of the first plurality of conductors An ohmic connection is formed such that electrons can pass between the unpassivated region on the front side and the first plurality of conductors, allowing current generated by the photovoltaic semiconductor device to be conducted by the first plurality of conductors. The second electrode includes a second electrically insulating film having first and second opposite sides. The first side of the second film has a second adhesive for bonding the second film to the second conductive anti-reflective coating. The second electrode further includes a second plurality of conductors embedded in the second adhesive such that a portion of the second plurality of conductors protrude from the second adhesive coating. The second plurality of guiding systems of the portions are soldered to the second conductive anti-reflective coating by an alloy coating on the portions for use in a portion of the second plurality of conductors and the second An ohmic connection is formed between the conductive anti-reflective coatings, such that electrons can pass between the backside surface of the third volume and the second plurality of conductors, allowing current generated by the photovoltaic semiconductor device to be passed by the second plurality of conductors Conduction. 14 200849627 In another embodiment, the second doping volume may have a backside surface and may include a second purification layer on the backside surface, and may further include an aluminum layer on the second passivation layer . The aluminum layer has a plurality of laser-sintered current collecting contacts extending through the second passivation layer to the second dopant. A solar cell using a device having an aluminum layer includes first and second electrodes connected to the front and back surfaces of the device, respectively. The first electrode includes a first light transmissive electrically insulating film having first and second opposing sides. The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating. The first electrode further includes a first plurality of conductors embedded in the first adhesive such that a portion of the first plurality of conductors protrude from the first adhesive coating. The portions are soldered to the first conductive anti-reflective coating by an alloy coating thereon for forming an ohmic 15 between the conductive anti-reflective coating and a portion of the first plurality of conductors The connection is such that electrons can pass between the unpassivated region of the front side and the first plurality of conductors, allowing current generated by the photovoltaic semiconductor device to be conducted by the first plurality of conductors. The second electrode includes a second electrically insulating film having first and second opposing sides. The first side of the second film has a second adhesive 20 for bonding the second film to the aluminum layer. The second electrode further includes a second plurality of conductors embedded in the second adhesive such that a portion of the second plurality of conductors protrude from the second adhesive coating. The second plurality of guiding systems of the portions are soldered to the aluminum layer by an alloy coating on the portions to form an ohmic connection between a portion of the second plurality of conductors and the aluminum layer, 15 200849627 2 The current generated by the photovoltaic semiconductor device is transmitted from the second plurality of conductors to the second doped volume through the layer 1 and the laser sintered junction. According to another aspect of the present invention, a method of fabricating a photovoltaic semiconductor device for constituting a solar cell is provided. The method includes forming a first plurality of openings in a first passivation 5 layer, the first passivation layer The opening of the first plurality of openings on the front side of the first doping volume of the semiconductor material of the semiconductor wafer having the doped shells of the first and second adjacent opposing semiconductor materials constituting the heterobe junction a corresponding unpassivated region of the uranium side that is not passivated by the first passivation layer. The method is also included on the first outer surface of one of the first 10 purification layers and the corresponding ones on the front side Forming a first conductive anti-reflective coating on the passivation region. The first plurality of openings are configured to cause each of the openings of the first plurality of openings to have a width of from about 5 Å to about 2 Å. The operation of forming the first plurality of openings in the passivation layer comprises arranging the first plurality of openings in a flat 15 line manner to cover the first outer surface. The distance between the parallel lines of the openings in the first passivation layer may be about 500 microns. Up to about 5 μm. The operation of forming the first plurality of openings in the first passivation layer includes arranging the first plurality of openings in parallel lines by cross-parallel connection to form a gate configuration. The gate configuration has a mesh of from about 500 square microns to about 5 square microns. The first conductive anti-reflective coating operation can be included on the first outer surface and on the front side surface A first conductive anti-reflective coating is formed on the unpassivated region. The first conductive anti-reflective coating operation may comprise causing the first conductive anti-reflective coating to have from about 70 nm to about 280 nm. a thickness of the meter. The first conductive anti-reflective coating layer on the first outer surface and the non-passivated regions 5 of the front side surface may comprise a material comprising InOx; SnOx; InSnOx At least one of TiOx and ZnOx. The operation of the first conductive anti-reflective coating may comprise causing the first conductive anti-reflective coating to have a thickness of about 10 ohms per square to about 30 ohms per square. a thin layer of electricity The method may comprise forming the heterojunction by at least one of ion implantation and thermal diffusion. The method may comprise constituting the first doping volume having about 60 ohms per square to about 150 per square. An ohmic sheet resistivity, desirably having a sheet resistivity of from about 80 ohms per square to about 150 ohms per square. The method includes forming the first purification layer. The operation of forming the first passivation layer can be included in the Forming a layer on at least one of SiO 2 , SiN 4 , and SiC on the front side. constituting the first passivation layer includes causing the first passivation layer to have a thickness of from about 20 10 nm to about 500 nm, and desirably about 1 〇 nanometer to about 50 nm. The method comprises forming a second plurality of openings in a second passivation layer, the second passivation layer being tied to a back side surface of the second doping volume of the semiconductor material Upper, the second plurality of open boundaries are positioned on the backside surface corresponding to the unpassivated regions of 17 200849627. The method also includes forming a second conductive anti-reflective coating on the outer surface of the second purification layer and on the unpurified regions of the second backside surface. The second plurality of openings are configured to cause each opening in the second plurality of openings 5 to have a width of from about 50 microns to about 200 microns. The operation of forming the opening of the second plurality in the second passivation layer comprises arranging the second plurality of openings in a parallel line to cover the backside surface. The distance between the parallel lines in the second passivation layer can be from about 5 Å to about 5,000 microns. The operation of forming the second plurality of openings in the second passivation layer includes arranging the second plurality of openings in parallel lines by the parent-fork parallel line connection to form a gate configuration. The grid configuration has a mesh of from about 500 square microns to about 5 square microns. The second conductive anti-reflective coating operation may comprise forming a second continuous conductive anti-reflective coating on the outer surface of the second passivation layer and on the unpassivated regions of the backside surface. The constituting the second conductive anti-reflective coating operation can comprise causing the coating to have a thickness of from about 70 nanometers to about 500 nanometers. The second conductive anti-reflective coating operation comprises coating the outer surface of the second passivation layer and the unpassivated regions of the backside surface with a material comprising InOx; SnOx; InSnOx; TiOx And at least one of ZnOx. The constituting the second conductive anti-reflective coating operation can comprise causing the second 18 200849627 conductive anti-reflective coating to have a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. The method includes forming the second passivation layer. The constituting the second passivation layer may include a layer constituting at least one of 5SiO2, SiN4, and SiC on the outer surface. The constituting the second passivation layer comprises causing the second passivation layer to have a thickness of from about 10 nm to about 500 nm, and desirably from about 10 nm to about 50 nm. The method can include adhering an adhesive 10 on a light-transmissive electrically insulating film to the first conductive anti-reflective coating such that the bit is embedded in a corresponding portion of the first plurality of conductors in the adhesive. A portion of the alloy coating is disposed on the first conductive anti-reflective coating. The method can also include heating the alloy coating while pressing the exposed portions against the first conductive anti-reflective coating such that the alloy coating welds the exposed portions of the first plurality of conductors to the A first conductive anti-reflective coating is used to create an ohmic connection between the first plurality of conductors and the first conductive anti-reflective coating. The method can include bonding a second adhesive on a second electrically insulating film to the second conductive anti-reflective coating such that the second plurality of conductors are embedded in the second adhesive A second second alloy coating layer corresponding to the portion on the exposed portion is disposed on the second conductive anti-reflective coating. The method can further include heating the second alloy coating while pressing the exposed portion of the second plurality of conductors against the second conductive anti-reflective coating such that the second alloy coating will be the second plurality of conductors The exposed portion is soldered to the second conductive anti-reflective coating for creating an ohmic connection between the second plurality of conductors and the second conductivity 19 200849627 anti-reflective k layer. The square-shaped anti-reflective coating may be formed on the back side surface of the third doping volume on the second doping capacity opposite to the semiconductor bonding, the third doping The volume has the same doping polarity as the second volume 5, thereby forming a homojunction (4), and wherein the third doping volume also has a doping concentration greater than a doping concentration of the second volume . The first conductive anti-reflective coating forming operation may comprise forming a second continuous conductive anti-reflective coating on the backside surface of the third alternating volume. The second conductive anti-reflective coating composition can comprise causing the second conductive anti-reflective coating to have a thickness of from about 70 nanometers to about 5 nanometers. The constituting the second conductive anti-reflective coating operation may include coating the backside surface of the third doping volume with a material comprising at least one of ΐηθχ; Sn0x; InSnOx; TiOx and ZnOx. 15 The second conductive anti-reflective coating operation can comprise causing the second conductive anti-reflective coating to have a sheet resistivity of from about 1 ohm per square to about 3 ohms per square. The method can include bonding an adhesive on a light-transmissive electrically insulating film to the first conductive anti-reflective coating to cause a position on the corresponding exposed portion of the first plurality of conductors embedded in the adhesive 20 A portion of the alloy coating is disposed on the first conductive anti-reflective coating. The method can further include heating the alloy coating while pressing the exposed portions against the first conductive anti-reflective coating such that the alloy coating welds the exposed portions of the first plurality of conductors to the conductive resistance A reflective coating is used to create an ohmic connection between the first plurality of conductors and the first conductive anti-reflective coating of 20 200849627. The method can include bonding a second adhesive on a second electrically insulating film to the second conductive anti-reflective coating such that the second plurality of conductors are embedded in the second adhesive A second alloy coating layer corresponding to the portion on the exposed portion is disposed on the second conductive anti-reflective coating. The method can further include heating the second alloy coating while pressing the exposed portion of the second plurality of conductors against the second conductive anti-reflective coating such that the second alloy coating will be the second plurality of conductors The exposed portion is soldered to the second conductive anti-reflective coating for creating an ohmic connection between the second plurality of conductors and the second conductive anti-reflective coating. The method can include forming a second passivation layer on a back side surface of one of the second volumes. The constituting the second passivation layer may include a layer constituting at least one of SiO 2 , SiN 4 and SiC on the outer surface. The constituting the second passivation layer operation comprises causing the second passivation layer to have a thickness of from about -10 nm to about 500 nm, and desirably from about 10 nm to about 50 nm. The method can include forming an aluminum layer on the second passivation layer. The structuring of the aluminum layer may comprise forming the aluminum layer by at least one of vapor deposition and sputtering. The structuring of the aluminum layer can comprise forming the aluminum layer such that the aluminum layer has a thickness of from about 1 micron to about 20 microns, and desirably from about 2 microns to about 10 microns. The method can include forming a plurality of laser sintered joints in the aluminum layer. The method may include adhering an adhesive 21 200849627 on a light-transmissive electrically insulating film to the first conductive anti-reflective coating such that a corresponding exposed portion of the first plurality of conductors embedded in the adhesive is present. The upper portion of the alloy coating is disposed on the front side. The method may further comprise heating the alloy coating while pressing the exposed portions against the first conductive anti-reflective coating on the unpassivated regions 5 such that the alloy coating will be the first plurality An exposed portion of the conductor is soldered to the conductive anti-reflective coating for creating an ohmic connection between the first plurality of conductors and the first conductive anti-reflective coating. The method can include bonding a second adhesive 10 on a second electrically insulating film to the aluminum layer such that the bit is embedded in a corresponding portion of the second plurality of conductors in the second adhesive A second alloy coating is disposed on the I layer. The method can further include heating the second alloy coating while pressing the exposed portion of the second plurality of conductors against the aluminum layer such that the second alloy coating welds the exposed portions of the second plurality of conductors to the The aluminum layer 15 is used to create an ohmic connection between the second plurality of conductors and the aluminum layer for allowing current to flow between the second plurality of conductors and the second doped volume through the laser sintered junctions and The aluminum layer. According to another aspect of the present invention, a photovoltaic semiconductor device for forming a solar cell is provided. The apparatus includes a doped volume of first and second adjacent opposing semiconductor materials constituting a semiconductor heterojunction 20, the first doped volume being used as an emitter having a front side for receiving light. The device also includes a first passivation material layer on the front side, the first passivation layer having a first outer surface and a plurality of openings through which the corresponding openings not passivated by the first passivation layer are defined The unpassivated 22 200849627 region or "well device further comprises a layer on the first outer surface of the passivation layer; the anti-reflective coating causes the openings in the passivation layer to be No far dielectric anti-reflective coating. The device also includes a first conductive anti-reflective coating on the first dielectric anti-reflective coating and on the corresponding unpurified regions on the "Hill side. The semiconductor heterojunction may include at least one of an ion implanted heterojunction and a thermally expanded heterojunction. The first doped volume can comprise a sheet resistivity of from about 6 ohms per square to about 150 ohms per square. The first doped volume may comprise a sheet resistivity of from about 80 ohms per square to about 150 ohms per square. The first passivation layer may comprise at least one of Si 〇 2, SiN 4 and SiC. The first passivation layer can have a thickness of from about 10 nanometers to about 200 nanometers. 15 The first passivation layer can have a thickness of from about 10 nanometers to about 50 nanometers. The width of the openings in the first passivation layer is from about 50 microns to about 200 microns. The openings in the first passivation layer may have an elongated shape having a length between about 〇5 mm and about 4 mm and a width 20 of about ο1 mm. About 1 mm. The openings may be spaced apart by from about 1 mm to about 6 mm. The openings in the first passivation layer are disposed in a parallel line to cover the first outer surface. The parallel lines are spaced apart from about 500 microns to about 5000 microns. 23 200849627 The parallel lines can be connected by crossed parallel lines to form a gate configuration. The grid configuration has a mesh of from about 500 square microns to about 5,000 square microns. 5 The dielectric anti-reflective coating can have a thickness of from about 70 nanometers to about 100 nanometers. The dielectric anti-reflective coating can comprise nitride rock. The dielectric anti-reflective coating can have a refractive index between about 2.0 and about 2.5. The first conductive anti-reflective coating layer may include an oxide of at least one of indium, tin, titanium, and zinc. The first conductive anti-reflective coating can include an oxide of at least one of indium and tin doped with fluoride. The first conductive anti-reflective coating may have a thickness between about 70 nanometers and about 100 nanometers. 15 The first conductive anti-reflective coating can have a refractive index between about 1.7 and about 1.9. The dielectric anti-reflective coating can have a refractive index between about 2.0 and about 2.5 and the first conductive anti-reflective coating can have a refractive index between about 1.7 and about 1.9. According to another aspect of the present invention, a method of forming a photovoltaic semiconductor device for forming a solar cell is provided. The method includes forming a plurality of openings in a dielectric anti-reflective coating, and a first passivation layer is tied to one of the doping volumes of the first and second adjacent opposing semiconductor materials constituting a heterojunction The first doping volume of the semiconductor material of the semiconductor wafer is 24 200849627 on the uranium side, on the front side, ^ ^ ^ ^ ^ ^ ^ ^ ^ 幻幻1 in the middle of the 5 Haidi - doping volume of the X-lead', A passivated dielectric coated region is formed on the blast portion. The method also includes forming a [first-reflective coating" on the passivated dielectric coating region and the front side surface region. 5 forming a plurality of opening operations may include a system-first material removal process for removing portions of the dielectric anti-reflective coating that expose the surface of the first purification layer, and using a second process for The portions of a passivation layer produce the specialized exposed area of the front side of the human beta side. . The Haidi-process may include at least 10 of the laser stripping and selective plasma remnant operations, and the second process may include a wet chemical residue. Wet chemical etching can include wet chemical etching using fluoric acid. The method can include performing a wet chemical etch until the dielectric anti-reflective coating has a thickness of between about 70 nanometers and about 1 nanometer. The following is a description of the specific embodiments of the present invention in conjunction with the accompanying drawings, which will be apparent to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS The following drawings illustrate specific embodiments of the invention, and FIG. 1 is a cross-sectional view of a photovoltaic semiconductor device 20 in accordance with a first embodiment of the present invention. Figure 2 is a cross-sectional view of the apparatus of Figure 1 in the first stage of the machining operation. Figure 3 is a cross-sectional view of the apparatus of Figure 1 in a second stage of the machining operation. 25 200849627 Figure 4 is a cross-sectional view of the third stage of the processing of the apparatus of Figure 1. Figure 5 is a cross-sectional view of the apparatus of Figure 1 in the fourth stage of the machining operation. 5 Fig. 6 is a plan view of the apparatus of Fig. 1, showing that the openings in a passivation layer on a front surface of the apparatus of Fig. 1 are arranged in parallel lines. Figure 7 is a plan view of a device of a specific embodiment, wherein the opening system 10 in a passivation layer on a front surface of the device of Figure 1 is shown as a parallel line and a parallel and parallel line manner. The configuration is used to form a gate configuration. Figure 8 is a cross-sectional view of the fifth stage of the apparatus of Figure 1 in a processing operation. Figure 9 is a cross-sectional view of a device according to a second embodiment of the present invention, wherein a dielectric anti-reflective coating is applied to a passivation layer. Figure 10 is a cross-sectional view of the device of Figure 9 showing the removed portion of the dielectric anti-reflective coating. Figure 11 is a cross-sectional view of the apparatus of Figure 10 showing the removed portion of the dielectric anti-reflective coating and the first passivation layer. Figure 12 is a cross-sectional view of the device of Figure 11, showing a portion of the dielectric anti-reflective coating and the exposed portion of the outer surface of the first volume of the semiconductor wafer covered with a conductivity Anti-reflective coating. Figure 13 is a cross-sectional view of the device of Figure 8, wherein the back side surface is finally added in a manner similar to its front side surface. The 15th diagram and the second electrode system shown in the manufacturing operation phase are connected to the front and back side surfaces. . . . ^. ^ ^ A cross-sectional view of the apparatus, wherein the backside surface is finished with a second product and a conductive coating for final processing. Enlarged cross-section _ 5 towel material "(4) - one-segment segment # 10 Figure 16 is the s-side system with a cross-sectional view of the device, where the vest junction is an aluminum The layer is finally processed. [Implementation of cold:! DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 1, a photovoltaic semiconductor device constituting a solar cell is generally indicated by the symbol α. The device 10 includes doped 5 confluences 12 and 14 of a first and second adjacent opposing semiconductor material constituting a semiconductor-baffle junction 16 using the _doped volume as an emitter. For example, the

The equal volumes 12, 14 can be disposed in a semiconductor wafer according to conventional thermal diffusion or ion implantation techniques. The first doped volume 12 has a front side surface 18. A first passivation layer 20 is disposed on the front side surface 18. The first passivation layer 20 has a first outer surface 22 and a plurality of openings. Only five 20 openings 24, 26, 28, 30 and 32 are shown in the drawing, defining a front side surface that is not passivated by the first passivation layer 20. Corresponding unpassivated regions 34, 36, 38, 40 and 42 of 18. Although only five openings are shown for purposes of illustration, it is practical to have a greater number of openings. A first conductive anti-reflective coating 44 is disposed on the first outer surface 22 of the passivation layer and the unpassivated 27 200849627 regions 34, 36, 38, 40 and 42 of the front side surface 18. Referring to Figures 2 and 3, in order to form the apparatus shown in Figure 1, a crystalline lithographic wafer 15 is substituted with a suitable doping element of opposite polarity for generating the first and second volumes therebetween. 12 and 14 and the heterojunction 16. Typically a pre-doped p or n-type crystalline germanium wafer 15 is first etched using wet plasma etching techniques to remove saw damage from the germanium wafer. The front surface of the wafer is then textured using wet techniques to reduce the amount of solar radiation reflected from the front surface when in use. The rice doping film 15 is pre-doped to become a p-type semiconductor 1 〇 material, and the first doping volume 12 is usually doped with a phosphorus-containing substance: the circle-front The side is constructed, and if the 9 wafer is initially η =, the other side is usually doped with a stone. Doping can be accomplished by ion implantation techniques that aid in the removal or penetration of phosphorus ions into the pre-doped semiconductor material, 15 shallow emitters. The Μ Μ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In defining the Shi Xijing [the enamel junction 16 is one of the. The preferred ρ / η bonding properties can optionally be removed. Continuous annealing operation

The conventional formula described above contains a butterfly-like dopant and a subsequent annealing process having a heat of about 80 to about 80 to: after the initial doping of the semi-conducting operation, the heat of the gas by the atom of the agent

The conductor material can be further doped by successive sintering diffusion and retraction by applying a solid state dish or a rotten doping 28 200849627 source to the semiconductor material. However, ion implantation techniques generally consume less energy than conventional thermal diffusion processes and are therefore superior to thermal diffusion techniques. Referring to FIG. 4, in order to form a first passivation material layer on the front side surface 18, a low pressure chemical vapor deposition technique, a plasma enhanced chemical vapor deposition 5 technique or other suitable method for cerium oxide (SiO 2 ), nitrogen is used. Deuterium (SiN4) or tantalum carbide (SiC) deposits. Desirably, the first passivation layer 2 has a thickness of from about 1 nanometer to about 500 nanometers, and more preferably, a thickness of from about 1 nanometer to about nanometer. Referring to FIG. 5, for example, openings 24, 26, 28, 30, and 32 are formed by laser ablation 10 or selective plasma of the first passivation layer 2 to define the respective openings The unpassivated regions 34, 36, 38, 40, and 42 are equal. The openings in the first passivation layer can be disposed across the spaced apart parallel lines 54, 56, 58 and 60 of the first outer surface 22, with reference to Fig. 6. For example, the lines may have a width between about 50 microns and about 2 microns, and 15 such parallel lines may range from about 500 microns to about 5000 microns. Referring to FIG. 7, in an optional embodiment, the parallel lines 54, 56, 58 and 60 are connected by intersecting parallel lines 62, 64, 66 and 68 to form a gate configuration. . The grid configuration has a mesh 69 of from about 5 square microns to about 5000 square microns. Referring to FIG. 8, after the plurality of openings are formed in the first passivation layer 20, at least one of InOx, SnOx, InSnOx, TiOx or ZnOx is applied by chemical vapor deposition, sputtering or other conventional methods. The first conductive anti-reflective coating 44. Desirably, the first conductive anti-reflective coating 44 is formed to encompass the surface defined by the first outer surface 22 of the passivation layer and the unpassivated regions 34, 36, 38, 40, and 42 such as 29 200849627 Providing a continuous coating covering the entire top of the wafer. By continuous is meant that the first conductive anti-reflective coating 44 covering the entire surface is free of cracks, even though the first conductive anti-reflective coating cross-section has a slightly curved shape. Desirably, depending on the desired emitter thin layer conductivity and spectral sensitivity of the semiconductor device, the first conductive anti-reflective coating 44 has a thickness between about 70 nm and about 280 nm. . Also, desirably, the first anti-reflective coating has a sheet resistivity between about 1 ohm per square and about 3 ohms per square. 10 After completing the third step shown in Fig. 8, the front side of the device 1 is thus completed and ready to receive an electrode as will be explained below. In an optional embodiment, referring to Figures 4 and 9, a dielectric anti-reflective layer or coating is deposited on the outer surface 22 of the opening layer 20 as described above. Layer 50. Desirably, the dielectric anti-reflective coating 15 50 has an initial thickness of between about 1 nanometer and about 150 nanometers. The refractive index of the dielectric anti-reflective coating 50 should preferably be in the range of 2 Å to 2.5, and the dielectric anti-reflective coating 50 must be able to withstand exposure to about? The temperature of ^^ lasts for at least 10 minutes without causing its integrity and IV of the refractive index. A suitable dielectric anti-reflective coating 50 having such characteristics can be produced using a nitrite spray, a nitrite reactive splatter, a plasma enhanced chemical vapor deposition, or other suitable method. The use of a nitride-on-silicon dielectric anti-reflective coating 50 is desirable because it can be stripped of the surname by laser or by the use of a murine acid to remove the nitride film. When the button is engraved, the speed of the engraving work under the same conditions should preferably be about 1 time slower than the speed of the surnamed dioxide film. 30 200849627 >考第1Gg] 'With the - material removal process, such as laser stripping 2 or selective plasma etching or other suitable method to remove the special area of the dielectric anti-reflective coating do The dielectric anti-reflective coating pair constitutes openings 5 10 15 - 6 58 and 6G. Desirably, the dielectric anti-reflective coating 5 〇 terminates the laser or selective process, such that the residual portion of the dielectric anti-reflective coating continues to exist and the first passivation layer 20 is nearly exposed The areas 72, 74, 76, 78 and 8 are shown. The device of the /10 diagram is then followed by a second material removal process, such as using hydrofluoric acid wet _ until the residual portion of the dielectric anti-reflective coating is (4) the first-purified layer filament, as shown in FIG. Corresponding regions 72, 74, %, 78, and 8 of the front side surface 18 of the βHad doped grain product 12 are exposed and not passivated. It should be appreciated that the dielectric anti-reflective coating 50 becomes thinner during the process utilizing the wet chemical etching process of the hydrofluoric acid. After this portion, the final thickness 82 of the dielectric anti-reflective coating 50 should be between about 70 and about 1 nanometer. Subsequent to 72, 74, 76, 78 and 80, a conductive anti-reflective coating 52 comprising indium, or tin, or a combination of titanium or a combination of such materials is applied to the device such that the conductivity An anti-reflective coating is formed on top of the dielectric anti-reflective coating 5q and at the exposed areas of the front side surface 18 of the first doped volume 12 as shown in FIG. Preferably, 20 indium, tin, titanium or a mixed gas oxide of a mixture of indium and tin is used as the conductive anti-reflective coating 52. The conductive anti-reflective coating has a thickness of from about 70 to about 100 nanometers and should have a refractive index of from about 丨 to about I. 31 200849627 The dielectric anti-reflective coating 50 shields the first passivation layer 20 from wet etching of the hydrofluoric acid, and the dielectric anti-reflective coating and the conductive anti-reflective coating will be from the front side surface 18 of the photovoltaic device The reflection of incident solar radiation is reduced to a minimum of 0 5 It is well known that light reflection from any material is by equation: the condition is that the thickness of each material layer is greater than a quarter or greater than the wavelength 8 〇 nanometer, determined by the difference in refractive index between two adjacent materials. If the refractive index of the crucible is about 4·〇 and the refractive index of the conductive anti-reflective coating is about 17, the conductive anti-reflective coating 10 is directly in the front side of the first doping volume. At these regions of the exposed areas of surface 18, the total reflection is about 16%. The front side surface 18 is coated with the dielectric anti-reflective coating 5 and the dielectric anti-reflective coating has a refractive index of about 2.2, which becomes substantially less than 8%. At the regions where the conductive anti-reflective coating 52 (refractive index 1.7) is located at the dielectric anti-reflective coating 15 (refractive index 2_2), the total reflection is reduced to 丨.6%. Therefore, more light is allowed to enter the front side surface, resulting in a corresponding increase in the conversion efficiency of the photovoltaic device. It is also important to note that since the first change volume 12 is substantially a shallow emitter, there is a risk that having a plurality of holes 20 will cause negative shunting. In the particular embodiment shown, the dielectric anti-reflective coating 50 places the conductive anti-reflective coating 52 in the regions adjacent to the openings 72, 74, 76, 78, and 80. The first doping volume 12 (emitter) isolation is not in direct contact, reducing the potential shunted through the emitter 0 32 200849627; the configuration shown in Fig. 12 is suitable for the first: two. When the first volume is in the shape of the first volume, the second conductivity is equal to the coffee pot, and the (10) material is advantageously the first volume 12 is n-type, the first conductive anti-reflective coating 52 T indium The mono-oxide composition, for example, because the material advantageously interacts with the reading material. ,

Presenting: Test Figure 13 The second doping volume η has a back side surface 1〇4, which can be processed in a different manner in a plurality of ways. For example, as shown in Fig. 13A, the back side surface 1〇4 can be treated similarly to the front side surface 18 by a second passivation layer having an opening and a second conductive anti-reflective coating. Optionally, as shown in FIG. 15, the back side table, the two doping volumes adjacent to each other form a third doping volume, and a one on the outer surface of the first first product is formed The conductive anti-reflective coating is used as a final addition or the backside surface may be covered with a second passivation layer and an aluminum layer, and a plurality of laser sintered joints may be formed therein. Each of the alternative methods for final processing of the 4 old side surfaces will be described below. Referring to Fig. 13, in a specific embodiment, the back side surface 104 of the second doping volume 14 can be configured in a manner similar to the front side shown in Fig. 1. In particular, the apparatus shown in Fig. 8 accepts a further work in which a second passivation layer 1〇6 is provided on the backside surface 104. For example, the passivation layer 1〇6 may comprise Si〇2, SiN4 or SiC, and may be formed to have a thickness of from about 10 nm to about 500 nm, desirably from about 10 nm to about 5 nm. Meter. The second passivation layer 106 has a second outer surface 1 〇 8 and a second plurality of openings through the surface of 33 200849627, which are generally indicated by representative symbols 110, 112, 114, 116 and 118. The openings 110, 112, 114, 116, and 118 define respective unpassivated regions 120, 122, 124, 126, and 128 of the backside surface 1〇4 that are not passivated by the second passivation layer 106. For example, 5 the openings in the second passivation layer 106 are arranged in spaced apart parallel lines as shown in FIG. For example, the width of the lines can be between about 50 microns and about 200 microns, and the distance between the parallel lines can be between about 500 microns and about 5000 microns. After the plurality of openings are formed in the second passivation layer 106, the second conduction including at least one of InOx, SnOx, InSnOx, TiOx or ZnOx is applied by chemical vapor deposition, sputtering or other methods. Anti-reflective coating 130. Desirably, the second conductive anti-reflective coating 130 comprises an oxide of indium, wherein the second volume 14 of the semiconductor material comprises an n-type material and the second conductive anti-reflective coating 130 comprises a tin. The oxide of the semiconductor material of the 15th semiconductor material comprises a p-type material. Also desirably, the second conductive anti-reflective coating 130 is comprised of the surface defined by the second outer surface 108 of the passivation layer and the unpurified regions 120, 122, 124, 126, and 128. To provide a continuous coating covering the back side of the wafer. By continuous is meant that there is no break in the second conductive antireflective coating 13 that covers the entire surface, even though the second conductive antireflective coating cross-section has a slightly curved shape. Desirably, the second conductive anti-reflective coating 130 has a thickness approximately equal to or greater than the thickness of the first conductive anti-reflective coating 44. As such, the second conductive anti-reflective coating 130 can have a thickness of from about 70 nanometers to about 500 nanometers. Desirably, the 34 200849627 t anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. In order to prepare the front side and the back side of the apparatus as described above, the apparatus is prepared to receive the first and second electrodes separately. Referring to the first, generally, the 5th symbol 8G and the 14G standard (4) H electrode age are applied to the front side and the back side of the device. The first pole_ includes a first light-transmitting electrically insulating film 82 having first and second opposite side edges 84 and 86, respectively. The first light-transmissive electrically insulating layer 82, for example, may comprise a poly(tetra) film and may have a thickness of from about 6 microns to about just microns. The first side 84 has a -H)-adhesive coating to bond the first light-insulating film 82 to the first conductive anti-reflective coating 44 on the semiconductor device. Desirably, the adhesive coating has thermoplastic properties and is subject to a service of about 6 Torr < t to about 14 〇 C, or more desirably, when the bearing is at about 8 Torr and about 13 Torr. The temperature in the temperature range between turns becomes a fluid. (d) The adhesive 15 may have a thickness of from about 15 microns to about 130 microns. A plurality of conductors, one of which is indicated by the reference numeral 9A, is embedded in the first adhesive coating 88 such that the portion 92 protrudes from the first adhesive coating 88. Portions 92 of the conductors 90 are soldered to the first conductive anti-reflective coating 44 by heating and pressing an alloy configured to pre-form a coating 20 on the exposed portions 90 of the conductors 90. . The alloy may include a composition comprising silver (Ag), bismuth (Bi), cadmium (Cd), gallium (Ga), indium (In), lead (Pb), antimony (Sb), tin (Sn), and zinc. At least two of (Zn). For example, the alloy may comprise a composition comprising indium (In), tin (Sn), silver (Ag), a ratio of about 47% indium (In), about 51% tin (Sn), and about 2% Silver (Ag). 35 200849627 Optionally, the alloy may comprise indium (In) and tin (Sn) in a ratio of about 48 Å/Å to 1 (In) and about 52% to Tin (Sn). The alloy may have a thickness of from about 丨 microns to about 5 microns and has a melting temperature of from about 30 ° C to about 200 ° C. More specifically, the alloy may have a melting temperature of between about 60 ° C and about 150. (5 of 5. The portion 92 is soldered to the first conductive anti-reflective coating 44 to form an ohmic connection between the portion 92 of the conductor and the first conductive anti-reflective coating 44 to enable electrons to be And other unpassivated regions 34, 36, 38, 4 and 42 and the first conductive anti-reflective coating 44 and the portions of the conductors embedded in the adhesive on the first electrode 8 Passed between 92 to allow current generated by the photovoltaic semiconductor device 1 to be conducted by the conductors 9. The conductors 90 are connected to a power rod 94 used as a first terminal, collected from the conductor The current and the photovoltaic cell are capable of being connected to a circuit. Further details of the general and optional structure of the first electrode are obtained from the patent applicant's International Patent Application No. WO 2004/021455 A1, The second electrode is generally indicated by the representative symbol 14〇 and is applied to the second conductive anti-reflective coating 13〇. The second electrode 14 is connected to the first electrode. An electrode 80 is similar and includes a second electrical insulation The film 142 has a 20th first and second opposite sides 144 and 146. The second insulating film does not need to be transparent. The first side 144 of the second film 142 has a second adhesive coating 148. For bonding the second film to the second conductive anti-reflective coating 130. The conductor 1 of the first number is embedded in the second adhesive coating 148, so that the portion 152 is adhered to the second adhesive The coating is protruded and soldered to the second conductive anti-reflective coating 130 by heating at 36 200849627 and pressed thereon by an alloy coating, as described above, for the portion of the conductor 150 and the first An ohmic connection is formed between the two conductive anti-reflective coatings 130. The electrons are thus capable of being on the conductor 150, the second conductive anti-reflective coating, and the 5 un-passivated regions on the backside surface 1〇4 Passed between the figures in Figure 14 to allow current generated by the photovoltaic device 10 to be supplied to a circuit. A second capsule 154 is coupled to the conductors for providing a second terminal for The photovoltaic cell is connected to a circuit. Thus, in this particular embodiment, Figure 14 The illustrated power poles 94 and 154 are used as the positive and negative terminals of the solar cell, respectively. Referring to Figures 15 and 15A, optionally, the back side surface 1〇4 of the device 1 can be A third doping volume 160 adjacent to the second doping volume 14 on the side of one of the second doping volumes opposite the semiconductor heterojunction 16 is surface treated plus 1. The third doping The volume (10) has the same doping polarity as the second alternating volume 14 to form a homojunction 162. The second doping volume 16G has a -doping concentration greater than the second doping volume, the doping concentration, And having a backside surface 164. For example, the doping operation to form the third doping volume 160 can be accomplished by ion implantation or diffusion from an I-body environment containing a suitable doping element 2q. The second conductive anti-reflective coating 166 is disposed on the back side surface 164 of the third doped volume 160. Desirably, the second conductive anti-reflective coating 166 is continuous and has the same wetness, force, or greater than the thickness of the first anti-reflective coating 44. As such, the second conductive anti-reflective coating 166 has a thickness between about 7 nanometers and about a mid-saternity of 37 200849627 degrees. The first conductive anti-reflective coating 1 66 may include at least one of In〇X, Sn〇X, InSnOx, TiOx, and ZnOx. Desirably, the second conductive anti-reflective coating has a sheet resistivity of between about 1 ohm per square to about 30 ohms per square. The first and second electrodes 80 and 140 are respectively secured to the front side of the device and the second conductive anti-reflective coating 166 of the third doping volume 16 , in a manner related to the above In the same manner as in FIG. 10, the portions of the conductors 9 of the first electrode 80 are soldered to the first conduction by heating and pressing an alloy coating on the portions 92. An anti-reflective coating 44 for forming an ohmic connection between the first conductive anti-reflective coating 44 and the portions 92 of the first plurality of conductors 90 such that electrons can be on the front side surface 18 The unpassivated regions 34, 36, 38, 40 and 42 pass between the first plurality of conductors 90 to allow current generated by the photovoltaic semiconductor device to be conducted by the first plurality of conductors 90. In addition, the portions 152 of the second plurality of conductors 150 of the second electrode 140 are soldered to the second conductive anti-reflective coating by heating and pressing an alloy coating on the portions 152. a layer 166 for forming an ohmic connection between the portions 152 of the second plurality of conductors 150 and the second conductive anti-reflective coating 166, such that electrons can be in the second plurality of conductors 150 and the third dopant The back side surface 164 of the volume 160 passes between to allow current generated by the photovoltaic semiconductor device to be conducted by the second plurality of conductors 150. Referring to Figure 16, in another optional embodiment, the backside surface 1 〇4 of the device 10 is deposited to deposit an aluminum layer 170 on the second passivation layer 74, and The aluminum layer 170 and the second doping volume 14 pass through a laser sintered joint formed by the first purification layer of 38 200849627 for final processing. A second continuous purification layer 174 is first formed on the backside surface 104 of the second doped volume 14. The second passivation layer 174, for example, can be formed on the backside surface 104 of the second doped volume 14 by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition of SiO 2 , SiN 4 or SiC. The second passivation layer 174 can be formed to have a thickness of from about 1 nanometer to about 5 nanometers, and more desirably, a thickness of from about 10 nanometers to about 50 nanometers. The aluminum layer 170 is then formed on the surface of the second passivation layer 174 using vacuum evaporation or sputtering techniques. The aluminum layer 170 can be formed to have a thickness of from about 1 micrometer to about 2 nanometers, and more desirably, a thickness of from about 2 micrometers to about 1 micrometer. The laser sintered joint 172 is laser sintered into the aluminum layer using a conventional technique, such that a portion of the aluminum layer 17 is burned through the second passivation layer 174 and forms an alloy with the second doped volume 14. This produces a back surface field and an electrical 15 flow collection contact. To form a solar cell using the semiconductor device shown in FIG. 16, first and second electrodes 8A and 14 such as shown in FIG. 14 are connected to the first conductive anti-reflective coating 44 and An aluminum layer for allowing current to be supplied by the semiconductor device to an external circuit. For the first electrode 8 , 20, the portions 92 of the exposed conductor are soldered to the first conductive anti-reflective coating 44 by heating and pressing the alloy coating on the exposed portions. An ohmic connection is formed between the first conductive anti-reflective coating 44 and the portions 92 of the first plurality of conductors 9A, such that electrons can be applied to the unpassivated regions 34, 36, 38, 40 of the front side. And 42 and the first plurality of conductors 9 39 39 200849627 pass, the current generated by the photovoltaic device for the valley is conducted by the first plurality of conductors 90. For the second electrode 14 该, the exposed portions 152 of the second plurality of conductors 150 are soldered to the aluminum layer 17 by heating and pressing an alloy coating on the portions 152 for The portions 152 of the second plurality of conductors 5丨50 and the second doping volume 14 form an ohmic connection through the laser sintered contacts 172, allowing the current generated by the photovoltaic semiconductor device to be conducted by the second plurality of conductors 150 conduction. SUMMARY OF THE INVENTION The present invention provides a photovoltaic cell having a shallow emitter having a generally uniform thickness and a uniform uniformity, thereby eliminating the need to selectively form emitter regions of different thicknesses. Moreover, since the emitter is shallow, the device is more sensitive to blue light than devices having non-uniform thickness emitters, making the overall device more efficient at converting light energy into electrical energy. In addition, the methods and apparatus described herein do not require screen printing techniques, which eliminates a number of time consuming and energy consuming manufacturing steps and reduces the use of conductive paste on the front and back surfaces of the battery. Bow-like sensitivity. In addition, there is no need for screen printing technology to allow solar cells to be manufactured faster and at lower cost. In addition to avoiding the use of screen printing techniques, it is permissible to create a substantially more 射 emitter without the risk of emitter shunting. In addition to the combination provided by the passivation layer with openings and the conductive anti-reflective coating, it is possible to provide efficient surface current isolation while providing semiconductor surface passivation. In addition, the methods and apparatus described herein allow alternative methods for heterogeneous and homogenous 40 200849627 to form a _ sub-form as a thermal diffusion, thereby reducing energy consumption and manufacturing costs of manufacturing operations. Finally, V is used on the front side surface of the a-hai solar cell, and the first and second are respectively transferred to the first and second conductive anti-5 reflective coatings and the back side surface The electrodes are capable of eliminating the need to accurately align the conductors on the electrodes having pre-printed contacts. The electrodes are precisely aligned such that the conductors on the electrodes do not need to be aligned with pre-formed contacts on the front and back side surfaces, enabling manufacturing tolerances to be relaxed in solar cell manufacturing operations, further reducing Production 10 costs. While the invention has been shown and described with respect to the specific embodiments of the present invention BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a photovoltaic semiconductor device according to a first embodiment of the present invention. Figure 2 is a cross-sectional view of the apparatus of Figure 1 in the first stage of the machining operation. Figure 3 is a cross-sectional view of the second stage of the apparatus of Figure 1 in a second stage of the machining operation. Figure 4 is a cross-sectional view of the apparatus of Figure 1 in the third stage of the machining operation. Figure 5 is a cross-sectional view of the apparatus of Figure 1 in the fourth stage of the machining operation. 200849627 The sixth picture is the first! A plan view of the apparatus of the figure showing the openings in a passivation layer on a front surface of the apparatus of Fig. i arranged in a parallel line. Figure 7 is a plan view of a device of a second embodiment in which the opening in a passivation layer on a front surface of the device of Figure 1 is shown as a parallel line and a cross-parallel line. The configuration is used to form a gate configuration. Figure 8 is a cross-sectional view of the fifth stage of the apparatus of Figure 1 in a processing operation. Figure 9 is a fragmentary cross-sectional view of a device in accordance with a second embodiment of the present invention, wherein a dielectric anti-reflective coating is applied to a passivation layer. Figure 10 is a cross-sectional view of the device of Figure 9 showing the removed portion of the dielectric anti-reflective coating. Figure 11 is a cross-sectional view of the apparatus of Figure 10 showing the portion of the dielectric anti-reflective coating and the first passivation layer. Figure 12 is a cross-sectional view of the device of Figure 11, showing a portion of the dielectric anti-reflective coating and the exposed portion of the outer surface of the first volume of the semiconductor wafer coated with a conductive resistance Reflective coating. Figure 13 is a cross-sectional view of the apparatus of Figure 8, wherein the backside surface is finalized in a manner similar to its front side surface. Figure 14 is a perspective view of the apparatus of Figure 13 shown in a manufacturing stage in which the first and second electrodes are attached to the front and back side surfaces. Figure 15 is a cross-sectional view of the apparatus of Figure 8, wherein the back side 42 200849627 surface is finished with a third doped volume and a conductive coating. Figure 15A is a fragmentary enlarged cross-sectional view of a portion of the device shown in Figure 15. Figure 16 is a cross-sectional view of the apparatus of Figure 8, wherein the back side is finished with an aluminum layer having laser sintered joints for final processing.

i [Major component symbol description 10... Photovoltaic semiconductor device 12.14.. The doping volume of semiconductor material 15. Crystallized wafer 16... Semiconductor heterojunction 18... Front side surface 20... First passivation layer 22.. The first outer surface is 24.26.28.30.32... opening 34.36.38.40.42.. unpassivated area 44... first conductive anti-reflective coating 50.. dielectric anti-reflective coating 52.. opening / Conductive anti-reflective coating 54.56.58.60.. parallel lines / openings 62, 64, 66, 68... cross-parallel lines 69.. mesh 72, 74, 76, 78, 80 · · area 80... An electrode 82.. The final thickness of the first light-transmissive electrically insulating film/dielectric anti-reflective coating 84...the first side 86...the second side 88..the first adhesive coating 90..the conductor 92 The part of the conductor 94... the power pole 104.. the back side surface 106...the second passivation layer 108...the second outer surface 110,112,114,116,118...the opening 120,122,124,126 128.··Unpassivated region 130...second conductive anti-reflective coating 140...second electrode 142..second electrically insulating film 144...first side 146...second side 43 200849627 148.. . Second adhesive coating 150... Two-conductor conductor 152...part 154... second busbar 160... third doping volume 162.. homojunction 164... backside surface 166.. second conductive anti-reflective coating 170. .. Ming layer 172.. laser sintered joint 174... second passivation layer 44

Claims (1)

200849627 X. Patent application scope: 1·= species a--the solar (four) pool-photovoltaic semiconductor device, the package-constituting-the heterojunction of the semiconductor heterojunction (the heterojunction) and the doping volume of the opposite phase semiconductor material The first doped volume is used as an emitter having a front side for receiving light; and a first passivation material layer on the front side, the first passivation layer having a first outer surface And a plurality of openings through which the corresponding un-blunted regions of the front side that are not passivated by the first passivation layer are passed; and a conductive anti-reflective coating that is in the passivation layer On the first outer surface and the corresponding unpassivated regions of the front side. 2. The device of claim 3, wherein the semiconductor heterojunction is at least one of an ion implanted heterojunction and a thermally diffused heterojunction. 3. The device of claim 1, wherein the first doping volume has a sheet resistivity of from about 60 ohms per square to about 150 ohms per square. 4. The device of claim 1, wherein the first doping volume 20 has a sheet resistivity of from about 80 ohms per square to about 150 ohms per square. 5. The device of claim 3, wherein the first passivation layer is composed of at least one of Si〇2, SiN4, and SiC. 6. The device of claim 1, wherein the first passivation layer has a thickness of from 45 200849627 to about 10 nanometers to about 500 nanometers. 7. The device of claim 6, wherein the first passivation layer has a thickness of from about 10 nanometers to about 50 nanometers. 8. The device of claim 1, wherein the openings have a width of from about 50 microns to about 200 microns. 9. The device of claim 1, wherein the openings in the first passivation layer are arranged in a parallel line to cover the first outer surface. 10. The device of claim 9, wherein the parallel lines are spaced apart from about 500 microns to about 5000 microns. 10. The device of claim 8 wherein the parallel lines are connected by crossed parallel lines to form a grid configuration. 12. The device of claim 11 wherein the grid configuration has a mesh of from about 500 square microns to about 5000 square microns. 13- The device of claim 1, wherein the first conductive anti-reflective coating is continuous. 14. The device of claim 1, wherein the first conductive anti-reflective coating has a thickness of from about 70 nanometers to about 280 nanometers. 15. The device of claim 1, wherein the first conductive anti-reflective coating comprises at least one of InOx, SnOx, InSnOx, TiOx, and ZnOx. 16. The device of claim 1, wherein the first conductive anti-reflective coating has a sheet resistivity of between about 1 ohm per square and about 30 ohms per square. 17. The device of claim 1, further comprising: 46 200849627 a second passivation layer on the backside surface, the second passivation layer having a second outer surface having a second plurality An opening through which the unpassivated regions of the corresponding second outer surface not passivated by the second passivation layer are defined; and a second conductive anti-reflective coating that is tied to the second passivation The second outer surface of the layer and the corresponding unpassivated region of the second outer surface. 18. The device of claim 17, wherein the second passivation layer comprises at least one of SiO 2 , SiN 4 , and SiC. 10. The device of claim 17, wherein the second passivation layer can have a thickness of from about 10 nanometers to about 500 nanometers. 20. The device of claim 17, wherein the second passivation layer has a thickness of from about 10 nanometers to about 50 nanometers. 21. The device of claim 17, wherein the openings in the second passivation layer 15 have a width of from about 50 microns to about 200 microns. 22. The device of claim 17, wherein the openings in the second passivation layer are arranged in a parallel line to cover the second outer surface. 23. The device of claim 22, wherein the parallel lines are spaced apart from about 500 microns to about 5000 microns. 20. 24. The device of claim 23, wherein the parallel lines are connected by intersecting parallel lines to form a grid configuration. 25. The device of claim 24, wherein the grid configuration has a mesh of from about 500 square microns to about 5000 square microns. 26. The device of claim 17, wherein the second conductive anti-reverse 47 200849627 is continuous. 27. The device of claim 17, wherein the second conductive anti-reflective coating has a thickness of at least about the thickness of the first conductive anti-reflective coating. 28. The device of claim 17, wherein the second conductive anti-reflective coating has a thickness of between about 70 nanometers and about 500 nanometers. 29. The device of claim 17, wherein the second conductive anti-reflective coating layer comprises at least one of InOx, SnOx, InSnOx, TiOx, and ZnOx. 30. The device of claim 17, wherein the second conductive anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. 31. A solar cell device comprising the device of claim 17 and further comprising a first electrode, comprising: a first light transmissive electrically insulating film having first and second opposite sides 15; The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating; the first plurality of conductors are embedded in the first adhesive, causing a portion The first plurality of conductors protrude from the first adhesive; 20 the portions are soldered to the first conductive anti-reflective coating by an alloy coating on the portions for An electrically conductive anti-reflective coating forms an ohmic connection with the first plurality of conductors of the portions such that electrons can pass between the unpassivated regions of the front side and the first plurality of conductors to allow The current generated by the photovoltaic semiconductor device 48 200849627 is conducted by the conductor of the plurality of conductors. 32. A solar cell device comprising the device of claim 31 and further comprising a second electrode, comprising: a second electrically insulating film having first and second opposite sides; The first side of the second film has a second adhesive for bonding the second film to the second conductive anti-reflective coating; the second plurality of conductors are embedded in the second adhesive Causing a portion of the second plurality of conductors to protrude from the second adhesive; the second plurality of conductive systems of the portions are soldered to the second conductive resistance by an alloy coating on the portions 10 a reflective coating for forming an ohmic connection between the second plurality of conductors of the portions and the second conductive anti-reflective coating, such that electrons can be present in the unpassivated regions of the second outer surface The second plurality of conductors pass between each other to allow current generated by the photovoltaic semiconductor device to be conducted by the 15th and second plurality of conductors. 33. The device of claim 1, further comprising a third doping volume adjacent to the semiconductor heterojunction and adjacent to the second doping volume on one side of the second doping volume The third doping volume has the same doping polarity as the second doping volume, thereby forming an isotype junction with the second doping 20 volume, wherein the third doping volume also has a doping The concentration is greater than a doping concentration of the second doping volume, and wherein the third doping volume has a backside surface. 34. The device of claim 33, further comprising a second layer of conductive anti-reflective coating 49 200849627 positioned on the backside surface of the third doped volume. 35. The device of claim 34, wherein the second conductive anti-reflective coating has a thickness that is about the same as or greater than a thickness of one of the first conductive anti-reflective coatings. The apparatus of claim 34, wherein the second conductive anti-reflective coating has a thickness of from about 70 to about 500 nanometers. 37. The device of claim 34, wherein the second conductive anti-reflective coating comprises at least one of InOx, SnOx, InSnOx, TiOx, and ZnOx. The device of claim 34, wherein the second conductive anti-reflective coating has a sheet resistivity of from about 1 ohm per square to about 30 ohms per square. 39. A solar cell device comprising the device of claim 34 and further comprising a first electrode, comprising: a first light transmissive electrically insulating film having first and second opposing sides; The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating; the first plurality of conductors embedded in the first adhesive to cause the portion 20 The first plurality of conductors protrude from the first adhesive; the portions are soldered to the first conductive anti-reflective coating by an alloy coating on the portions for the first conduction An ohmic connection between the anti-reflective coating and the first plurality of conductors of the portions, such that electrons can pass between the unpassivated regions of the front side and the conductors of the plurality of 2008 20082727 to allow The current generated by the photovoltaic semiconductor device is conducted by the first plurality of conductors. 40. A solar cell device comprising the device of claim 39 and further comprising a first electrode, comprising: a second electrically insulating film having first and second opposing sides; the second The first side of the film has a second adhesive for bonding the second film to the second conductive anti-reflective coating; the second plurality of conductors are embedded in the second adhesive to cause a portion The second plurality of conductors protrude from the second adhesive; the second plurality of conductive systems of the portions are soldered to the second conductive anti-reflective coating by an alloy coating on the portions Forming an ohmic connection between the second plurality of conductors of the portions and the second conductive anti-reflective coating such that electrons can be on the back side surface of the third volume and the second plurality of conductors Passing through to allow current generated by the photovoltaic semiconductor device to be conducted by the second plurality of conductors. 41. The device of claim 2, wherein the second doped volume has a backside surface and further comprising: a second passivation layer that is tied to the backside surface; and an aluminum layer The base layer is on the second passivation layer, the aluminum layer having a plurality of laser sintering current collecting contacts extending from the aluminum layer through the second passivation layer to the second doping volume. 42. A solar cell device comprising the device of claim 41 and further comprising a first electrode, comprising: 51 200849627 a first light transmissive electrically insulating film having first and second opposite sides; The first side has a first adhesive for bonding the first film to the first conductive anti-reflective coating; 5 a first plurality of conductors embedded in the first adhesive to cause a portion The first plurality of conductors protrude from the first adhesive; the portions are soldered to the first conductive anti-reflective coating by an alloy coating on the portions for the conductive resistance Between the reflective coating and the first plurality of conductors of the portions, an ohmic junction is formed such that electrons can pass between the unpassivated regions of the front side and the first plurality of conductors to allow The current generated by the photovoltaic semiconductor device is conducted by the first plurality of conductors. 43. A solar cell device comprising the device of claim 42 and further comprising a second electrode, comprising: 15 - a second electrically insulating film having first and second opposing sides; The first side of the second film has a second adhesive for bonding the second film to the aluminum layer; the second plurality of conductors are embedded in the second adhesive to cause the second plurality of portions The conductor protrudes from the second adhesive; 20 the second plurality of conductive systems of the portions are soldered to the layer by an alloy coating on the portions for use in the portion An ohmic connection is formed between the two plurality of conductors and the outer surface of the second doped volume through the laser sintered junction to allow current generated by the photovoltaic semiconductor device to be conducted by the second plurality of conductors. 52 200849627 44. A method for fabricating a photovoltaic device of a solar cell, the method comprising: forming a first plurality of openings in a first passivation layer, the first passivation layer being tied to form a heterogeneity On a front side of the first doping volume of the semiconductor material of a semiconductor wafer having a doping volume of the first and second adjacent phases of the semiconductor material, the first plurality of openings are not defined by the a corresponding unpurified region of the first front side of the first passivation layer passivation, and a first conduction on the first outer surface of the first passivation layer and the corresponding unpassivated regions of the front side 10 Anti-reflective coating. 45. The method of claim 44, wherein the opening of the first plurality of openings comprises causing each of the openings of the first plurality of openings to have a width of from about 50 microns to about 200 microns. The method of claim 44, wherein the constituting the first plurality of openings in the first passivation layer comprises disposing the first plurality of openings in a parallel line to cover the first outer surface. 47. The method of claim 46, wherein the forming of the first plurality of openings comprises causing the parallel lines to be spaced apart from about 500 microns to about 20 microns. 48. The method of claim 44, wherein the constituting the first plurality of openings in the first passivation layer comprises arranging the first plurality of openings in parallel lines by a cross-parallel connection to form A gate configuration. 53 200849627 The method of claim 48, wherein the grid configuration has a mesh of from about 500 square microns to about 5,000 square microns. 50. The method of claim 44, wherein the first conductive anti-reflective coating operation comprises forming a first continuous conduction on the first outer surface and on the unpassivated regions of the front side surface Anti-reflective coating. The method of claim 44, wherein the constructing the first conductive anti-reflective coating comprises causing the first conductive anti-reflective coating to have a thickness of from about 70 nanometers to about 280 nanometers. The method of claim 44, wherein the constructing the first conductive anti-reflective coating on the first outer surface and on the unpassivated regions of the front side surface may comprise applying In〇X ; Sn〇X ; InSnOx ; a material of at least one of TiOx and ZnOx to the first outer surface and the unpassivated regions of the front side surface. The method of claim 44, wherein the constructing the first conductive anti-reflective coating comprises causing the first conductive anti-reflective coating to have an electrical conductivity of from about 1 ohm to about 3 ohms per square. A thin layer of resistivity. 54. The method of claim 44, further comprising forming the heterojunction by at least one of ion implantation and thermal diffusion. 55. The method of claim 44, further comprising causing the first doped volume to have a sheet resistivity of from 60 ohms per square to 150 ohms per square. 56. The method of claim 44, further comprising causing the 54 200849627 a doping volume to have a sheet resistivity of from 80 ohms per square to 150 ohms per square. 57. The method of claim 44, further comprising forming the first passivation layer. The method of claim 57, wherein the constituting the first passivation layer comprises a layer constituting at least one of SiO 2 , SiN 4 and SiC on the front side. 59. The method of claim 57, wherein the forming the first passivation layer comprises causing the first passivation layer to have a thickness of from about 10 nanometers to about 500 nanometers. 60. The method of claim 57, wherein the forming the first passivation layer comprises causing the first passivation layer to have a thickness of from about 10 nanometers to about 50 nanometers. 61. The method of claim 44, further comprising: 15 forming a second plurality of openings in a second passivation layer, the second passivation layer being tied to the second doped volume of the semiconductor material On a back side surface, the second plurality of open boundaries are positioned on corresponding unpurified regions on the back side surface; and on an outer surface of the second passivation layer and on the surface of the second back side 20 A second conductive anti-reflective coating is formed on the unpassivated area. 62. The method of claim 61, wherein the forming of the second plurality of openings comprises causing each of the openings of the second plurality of openings to have a width of from about 50 microns to about 200 microns. The method of claim 61, wherein the constituting the second plurality of openings in the second passivation layer comprises disposing the second plurality of openings in a parallel line to cover the back side surface. 64. The method of claim 63, wherein the arranging the openings of the second plurality in parallel lines comprises causing the parallel lines to be spaced apart from about 500 microns to about 5000 microns. 65. The method of claim 61, wherein the constituting the second plurality of openings in the second passivation layer comprises arranging the second plurality of openings in parallel lines by means of cross-parallel connections for forming A gate 10 pole configuration. 66. The method of claim 65, wherein the arranging the second plurality of openings in parallel lines by a cross-parallel connection to form a gate configuration comprises causing the gate configuration to have about 500 Mesh from square microns to about 5,000 square microns. The method of claim 61, wherein the second conductive anti-reflective coating operation is included on the outer surface of the second passivation layer and on the unpassivated regions of the backside surface A second continuous conductive anti-reflective coating is formed. 68. The method of claim 67, wherein the constructing the second conductive 20 antireflective coating comprises causing the coating to have a thickness of from about 70 nanometers to about 500 nanometers. 69. The method of claim 61, wherein the second conductive anti-reflective coating operation comprises coating the outer surface of the second passivation layer with a material and the unpassivated regions of the backside surface The material includes 56 200849627 InOx; SnOx; InSnOx; at least one of TiOx and ZnOx. The method of claim 61, wherein the constructing the second conductive anti-reflective coating comprises causing the second conductive anti-reflective coating to have an electrical conductivity of from about 1 ohm per square to about 30 ohms per square. A thin layer of resistance 5 rate. 71. The method of claim 61, further comprising constituting the second purification layer. The method of claim 69, wherein the constituting the second passivation layer comprises a layer constituting at least one of SiO 2 , SiN 4 and SiC on the back side surface. 73. The method of claim 69, wherein the forming the second passivation layer comprises causing the second passivation layer to have a thickness of from about 1 nanometer to about 500 nanometers. 74. The method of claim 69, wherein the constructing the second passivation layer 15 comprises causing the second passivation layer to have a thickness of from about 10 nanometers to about 50 nanometers. 75. The method of claim 61, further comprising: bonding an adhesive on a light-transmissive electrically insulating film to the first conductive anti-reflective coating such that the in-line is embedded in the adhesive An alloy coating layer on a portion of the corresponding exposed portion of the conductor of the 20th complex is disposed on the first conductive anti-reflective coating; and heating the alloy coating while pressing the exposed portions against the first a conductive anti-reflective coating such that the alloy coating welds the exposed portions of the first plurality of conductors to the first conductive anti-reflective coating 57 200849627 layer for the first plurality of conductors and the first An ohmic connection is created between a conductive anti-reflective coating. 76. The method of claim 75, further comprising: bonding a second adhesive on a second electrically insulating film to the second conductive anti-reflective coating to cause in-position a second alloy coating layer on a portion of the second plurality of conductors corresponding to the exposed portions of the second adhesive is disposed on the second conductive anti-reflective coating; and heating the second alloy coating while The exposed portions of the second plurality of conductors are pressed against the second conductive anti-reflective coating such that the second alloy coating welds the exposed portions of the second plurality of conductors to the second conductive An anti-reflective coating is used to create an ohmic connection between the second plurality of conductors and the second conductive anti-reflective coating. 77. The method of claim 44, further comprising: forming a back surface on a back side surface of a third doping volume on a side 15 side of the second doping volume opposite the semiconductor junction a second conductive anti-reflective coating having a same doping polarity as the second volume to form an isotype junction and wherein the third doping volume has a doping concentration greater than One of the second volumes is doped. The method of claim 77, wherein the second conductive anti-reflective coating comprises a second continuous conductive anti-reflective coating on the backside surface of the third doped volume. Floor. 79. The method of claim 77, wherein the second conductive anti-reflective coating comprises an operation comprising causing the second conductive anti-reflective coating 58 200849627 to have a temperature of from about 70 nm to about 500 nm. thickness. 80. The method of claim 77, wherein the second conductive anti-reflective coating operation comprises coating the backside surface of the third doping volume with a material comprising InOx; SnOx; InSnOx ; at least one of TiOx 5 and ZnOx. 81. The method of claim 77, wherein the constructing the second conductive anti-reflective coating comprises causing the second conductive anti-reflective coating to have a level of from about 1 ohm per square to about 30 ohms per square. Sheet resistivity. The method of claim 44, further comprising: bonding an adhesive on a light-transmissive electrically insulating film to the first conductive anti-reflective coating, such that the position is embedded in the adhesive An alloy coating of a portion of the first plurality of conductors on the corresponding exposed portion of the agent is disposed on the first conductive anti-reflective coating; and 15 heating the alloy coating while pressing the exposed portions against the position The first conductive anti-reflective coating on the unpassivated regions, causing the alloy coating to solder the exposed portions of the first plurality of conductors to the conductive anti-reflective coating for use in the first An electrical connection is made between the plurality of conductors and the first conductive anti-reflective coating. The method of claim 82, further comprising: bonding a second adhesive on a second electrically insulating film to the second conductive anti-reflective coating, causing the position to be embedded a second alloy coating layer on a portion of the second plurality of conductors corresponding to the exposed portion of the second adhesive is disposed on the second conductive anti-reflective coating; and 59 200849627 heating the second alloy coating simultaneously Pressing the exposed portions of the second plurality of conductors against the second conductive anti-reflective coating such that the second alloy coating welds the exposed portions of the second plurality of conductors to the second A conductive anti-reflective coating is used to create an ohmic connection between the second plurality of conductors and the second conductive anti-reflective coating. 84. The method of claim 44, further comprising forming a second passivation layer on a backside surface of one of the second volumes. 85. The method of claim 84, further comprising forming a layer on the second purification layer. The method of claim 84, further comprising forming a plurality of laser sintered joints in the aluminum layer. 87. The method of claim 86, further comprising: bonding an adhesive on a light-transmissive electrically insulating film to the first conductive anti-reflective coating, such that the position is embedded in the adhesive An alloy coating of a portion of the corresponding exposed portion of the conductor of the fifteenth complex is disposed on the front side; and heating the alloy coating while pressing the exposed portions against the unpassivated region The first conductive anti-reflective coating thereon, such that the alloy coating welds the exposed portions of the first plurality of conductors 20 to the conductive anti-reflective coating for the first plurality of conductors An ohmic connection is created between the first conductive anti-reflective coatings. 88. The method of claim 87, further comprising: bonding a second adhesive on a second electrically insulating film to the aluminum layer such that the position is embedded in the second adhesive a second plurality 60 200849627 A second alloy coating on the corresponding exposed portion of the conductor is disposed on the aluminum layer; and heating the second alloy coating while pressing the exposed portions of the second plurality of conductors Abutting the aluminum layer, causing the second alloy coating to weld the exposed portions of the second plurality of conductors to the aluminum layer for creating an ohmic connection between the second plurality of conductors and the aluminum layer, An allowable current flows between the second plurality of conductors and the second doped volume through the laser sintered joints and the aluminum layer. 89. A photovoltaic semiconductor device for forming a solar cell, the package 10 comprising: a doping volume of first and second adjacent opposing semiconductor materials constituting a semiconductor heterojunction, the first doping volume Used as an emitter having a front side for receiving light; a first layer of passivation material on the front side, the first blunt layer having a first outer surface and a plurality of openings via The openings define a corresponding unpassivated region of the front side that is not passivated by the first passivation layer, a dielectric anti-reflective coating that is tied to the first outer surface of the passivation layer, the openings No such dielectric anti-reflective coating; and 20 a first conductive anti-reflective coating on the dielectric anti-reflective coating and the corresponding unpassivated regions on the front side. 90. The device of claim 89, wherein the semiconductor heterojunction is at least one of an ion implanted heterojunction and a thermally diffused heterojunction. The apparatus of claim 89, wherein the first doping volume has a sheet resistivity of from about 60 ohms per square to about 150 ohms per square. 92. The device of claim 89, wherein the first doping volume 5 has a sheet resistivity of from about 80 ohms per square to about 150 ohms per square. 93. The device of claim 89, wherein the first passivation layer is comprised of at least one of SiO 2 , SiN 4 , and SiC. 94. The device of claim 89, wherein the first passivation layer has a thickness of from about 10 nanometers to about 200 nanometers. 95. The device of claim 94, wherein the first passivation layer has a thickness of from about 10 nanometers to about 50 nanometers. 96. The device of claim 89, wherein one of the openings in the first passivation layer is between about 50 microns and about 200 microns wide. The apparatus of claim 89, wherein the openings in the first passivation layer have an elongated shape having a length between about 0.5 mm and about 4 mm and The width is between about 0.1 mm and about 1 mm. 98. The device of claim 97, wherein the openings are spaced apart by about 20 1 mm to about 6 mm. 99. The device of claim 89, wherein the openings in the first passivation layer are arranged in a parallel line to cover the first outer surface. 100. The device of claim 99, wherein the parallel lines are spaced apart from about 500 microns to about 5000 microns. The apparatus of claim 99, wherein the parallel lines are connected by crossed parallel lines to form a grid configuration. 102. The device of claim 101, wherein the grid configuration has a mesh of from about 500 square microns to about 5000 square microns. The apparatus of claim 89, wherein the dielectric anti-reflective coating has a thickness of from about 70 nm to about 100 nm. 104. The device of claim 89, wherein the dielectric anti-reflective coating comprises tantalum nitride. 105. The device of claim 89, wherein the dielectric anti-reflective coating 10 has a refractive index between about 2.0 and about 2.5. 106. The device of claim 89, wherein the first conductive anti-reflective coating comprises a conductive oxide of at least one of indium, tin, titanium, and zinc. 107. The device of claim 89, wherein the first conductive anti-reflective coating comprises an oxide of at least one of indium and tin doped with fluoride. 108. The device of claim 89, wherein the first conductive anti-reflective coating has a thickness of between about 70 nanometers and about 100 nanometers. 109. The device of claim 89, wherein the first conductive anti-reflective coating has a refractive index between about 1.7 and about 1.9. 110. The device of claim 89, wherein the dielectric anti-reflective coating has a refractive index between about 2.0 and about 2.5 and the first conductive anti-reflective coating can have a refractive index between Between about 1.7 and about 1.9. 111. A method for fabricating a photovoltaic device for forming a solar cell. The method of manufacturing a semiconductor device comprises: forming a plurality of openings in a dielectric anti-reflective coating and a first passivation layer, the moieties having Forming a doped volume of the first and second adjacent opposing semiconductor materials of a heterojunction on a front side of a first doping volume of a semiconductor wafer of a semiconductor wafer for use on the front side Forming a passivated dielectric coating region on the exposed portion of the front side of the first doping volume; and forming a first on the passivated dielectric coating region and the exposed regions of the front side surface Conductive anti-reflective coating. The method of claim 111, wherein the opening of the plurality of openings comprises using a first material removal process for removing the area of the dielectric anti-reflective coating until the dielectric anti-reflective coating is left The remaining portion of the layer causes the portions of the surface of one of the first passivation layers to be nearly exposed, and a second process is used to remove the remaining portions and 15 to remove corresponding portions of the first purification layer, resulting in The exposed areas of the front side surface. 113. The method of claim 112, wherein the first process comprises at least one of a laser ablation and a selective plasma etch operation, and wherein the second process can comprise a wet chemical etch. The method of claim 113, wherein the wet chemical etching comprises wet chemical etching using a gas acid. 115. The method of claim 114, further comprising performing wet chemistry until the dielectric anti-reflective coating has a thickness of between about 70 nanometers and about 100 nanometers. 64