JP2008034609A - Solar battery element, solar battery module using same, and manufacturing methods of both - Google Patents

Solar battery element, solar battery module using same, and manufacturing methods of both Download PDF

Info

Publication number
JP2008034609A
JP2008034609A JP2006206107A JP2006206107A JP2008034609A JP 2008034609 A JP2008034609 A JP 2008034609A JP 2006206107 A JP2006206107 A JP 2006206107A JP 2006206107 A JP2006206107 A JP 2006206107A JP 2008034609 A JP2008034609 A JP 2008034609A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
solar cell
electrode
main surface
insulating material
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006206107A
Other languages
Japanese (ja)
Other versions
JP5025184B2 (en )
Inventor
Yuko Fukawa
Katsuhiko Shirasawa
祐子 府川
勝彦 白澤
Original Assignee
Kyocera Corp
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/02245Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/05Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H01L31/0516Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/54Material technologies
    • Y02E10/547Monocrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/52Manufacturing of products or systems for producing renewable energy
    • Y02P70/521Photovoltaic generators

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly efficient solar battery element having a simple constitution. <P>SOLUTION: The solar battery element 20 has a semiconductor substrate 1 as a first conductivity type, a first opposite-conductivity-type layer 2 formed on one principal surface of the semiconductor substrate 1, as the opposite-conductivity type to the conductivity type of the substrate 1; a plurality of through-holes 3 each of which ranges from the one principal surface of the semiconductor substrate 1 to the other principal surface thereof, and each of whose inner walls is coated with a second opposite-conductivity-type layer 6 or a first insulating-material layer 6; each first electrode 4 so formed as to range from the one-principal-surface side to the other-principal-surface side via each through-hole 3, and connected with the first opposite-conductivity-type layer 2; each second electrode 5 formed on the other principal surface and having the different polarity from the polarity of each first electrode 4; and each second insulating-material layer 7 interposed between the other-principal-surface side and each first electrode 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は太陽電池素子及びこれを用いた太陽電池モジュール、並びに、これらの製造方法に関するものである。 The present invention is a solar cell element and a solar cell module using the same, and to a method for their preparation.

現在主流の結晶型シリコン太陽電池を高効率化する方法の一つとして、図15に示すスルーホール型太陽電池に代表されるように、太陽電池素子の受光面側に形成された電極の面積を減らして受光面積を大きくするという方法が検討されている。 The current mainstream crystalline silicon solar cell as a way of high efficiency, as represented by a through-hole type solar cell shown in FIG. 15, the area of ​​the electrode formed on the light receiving surface of the solar cell element method of increasing the light receiving area is reduced has been examined.

スルーホール型太陽電池素子とは、受光面側から裏面側への貫通パスを設けることで、従来太陽電池素子の受光面側に存在していた電極をなくす、もしくは減らすことによって太陽電池素子の受光面積を向上させ、高効率化を図るというものである。 The through-hole type solar cell element, by providing the through path to the back surface side from the light receiving surface side, eliminating the electrodes was present on the light-receiving surface of the conventional solar cell element, or the light receiving solar cell element by reducing improve the area, it is that achieve high efficiency. 例えば、第一導電型の結晶基板表面上に順次第一導電型の化合物半導体層、第二導電型の化合物半導体層を順次積層し、スルーホールを介して受光面側電極を裏面側に回すという構造が開示されている(例えば、特許文献1参照)。 For example, the compound semiconductor layer sequentially first conductivity type to the first conductivity type of the crystal substrate surface, that a compound semiconductor layer of the second conductivity type are sequentially laminated, through the through hole turn the light-receiving surface-side electrode on the back side structure is disclosed (for example, see Patent Document 1).

また、スルーホールの裏面側周辺に逆導電型層を広げた構造を有する太陽電池素子も示されている(例えば、特許文献2参照)。 Also shown solar cell elements having a structure in which spread opposite conductivity type layer on the back surface side periphery of the through hole (e.g., see Patent Document 2). 図15(a)はその構造を示す断面図、図15(b)は正面図(受光面側)、図15(c)は背面図(裏面構造)を示したものである。 FIG. 15 (a) sectional view showing the structure, FIG. 15 (b) front view (light receiving surface side), and FIG. 15 (c) shows a rear view (back side structure).

この太陽電池素子の製造方法としては、まず一導電型(例えばP型)を示す半導体基板1に機械的ドリルなどにより多数の貫通孔3を設けた後、貫通孔3の内壁を含む半導体基板1の両面に逆導電型(例えばN型)拡散層2(一主面側逆導電型層42a、貫通孔逆導電型層42b、他主面側逆導電型層42c)が形成される。 The manufacturing method of the solar cell element, after providing a large number of through-holes 3 or the like mechanical drill semiconductor substrate 1 is first shown one conductivity type (e.g. P-type), the semiconductor substrate 1 including the inner walls of the through-hole 3 of the opposite conductivity type on both sides (for example, N-type) diffusion layer 2 (the main surface side opposite conductivity type layer 42a, the through hole opposite conductivity type layer 42b, the other principal surface side opposite conductivity type layer 42c) is formed. このとき裏面側には他主面側逆導電型層42cを形成しない領域が必要となる。 At this time the region does not form the other main surface opposite conductivity type layer 42c is needed on the back side. その後、裏面側の他主面側逆導電型層42c上および貫通孔3内に第一電極4(貫通孔電極44b、他主面側電極44c)を、他主面側逆導電型層42cを形成していない領域に第二電極45を形成し、一主面側電極44aを貫通孔電極44bと接続することで太陽電池素子が完成する。 Thereafter, the first electrode on the back side of the other principal surface side opposite conductivity type layer 42c and on the through-hole 3 4 (through hole electrode 44b, the other main surface side electrode 44c) and the other main surface opposite conductivity type layer 42c the second electrode 45 is formed on the formed non regions, the solar cell element is completed by connecting the through-hole electrode 44b one main surface side electrode 44a.

このような太陽電池素子は、例えば銅箔をはんだで被覆した配線材で接続することを繰り返すことで、太陽電池素子同士を接続することによって太陽電池モジュールを構成する。 Such solar cell element, for example, by repeating to connect the copper foil wiring member coated with solder, a solar cell module by connecting together the solar cell element.
特開昭63−211773号公報 JP-A-63-211773 JP 特表2002−500825号公報 JP-T 2002-500825 JP 特開2003−197940号公報 JP 2003-197940 JP 特開2001−118425号公報 JP 2001-118425 JP

しかしながら、上述した従来のスルーホール型太陽電池素子では、裏面側に存在するP型領域とN型領域との絶縁を確実なものにするため、電極同士を十分に離して形成すること、或いは、両電極間に所定の絶縁溝をレーザーやグルーブなどの機械的方法で形成したり、薬品やペーストなどを用いた化学処理などによって形成する必要がある。 However, in the conventional through-hole type solar cell element described above, for the insulation between the P-type region and the N-type region present on the back side in what ensures, be formed sufficiently away electrodes together, or, may be formed by a mechanical method such as laser or grooves a predetermined insulation groove between the electrodes, it is necessary to form the chemical treatment using chemicals, etc. or paste. それ故、発電に寄与しない領域を必要以上に広く取る必要があり、また、絶縁溝を形成することによって太陽電池素子の機械的強度の低下を招くといった問題があった。 Therefore, it is necessary to widen unnecessarily region that does not contribute to power generation, also, there is a problem lowering the mechanical strength of the solar cell element by forming an insulating groove.

本発明はこれらの問題点に鑑みてなされたものであり、簡易な構成で且つ高効率な太陽電池素子およびそれを用いた太陽電池モジュール、並びにそれらの製造方法を提供するものである。 The present invention has been made in view of these problems, and high efficiency solar cell element and a solar cell module using the same with a simple structure, and there is provided a process for their preparation.

本発明の太陽電池素子は、一導電型を示す半導体基板と、前記半導体基板の一主面に形成され、前記一導電型と逆の導電型を示す第一逆導電型層と、前記半導体基板の一主面から他主面に至り、内壁が第二逆導電型層或いは第一絶縁材料層で覆われた複数の貫通孔と、前記一主面側から前記貫通孔内を介して前記他主面側に至るように形成され、前記第一逆導電型層と接続された第一電極と、前記他主面上に形成され、前記第一電極と極性を異にする第二電極と、前記他主面と前記第一電極との間に介在された第二絶縁材料層とを有してなるものである。 Solar cell device of the present invention includes a semiconductor substrate illustrating one conductivity type, and said formed on one main surface of the semiconductor substrate, a first opposite conductivity type layer exhibiting the one conductivity type opposite conductivity type, said semiconductor substrate one reaches from the main surface to the other major surface, said through a plurality of through-holes the inner wall is covered with the second opposite conductivity type layer or the first insulating material layer, said through hole from said one main surface side other is formed so as to reach the main surface, a first electrode connected to the first opposite conductivity type layer, wherein formed on the other main surface, a second electrode having different the first electrode and the polarity, have been those made and a second insulating material layer disposed between the first electrode and the other main surface.

また、前記第二絶縁材料層は、酸素化合物或いは窒素化合物を主成分とすることを特徴とする。 Further, the second insulating material layer is characterized in that a main component oxygen compound or a nitrogen compound.

また、前記第二絶縁材料層は、水素を含有することを特徴とする。 Further, the second insulating material layer is characterized by containing hydrogen.

また、前記他主面上で、前記第一電極と前記第二電極との間に介在された第三絶縁材料層、をさらに有することを特徴とする。 Further, on the other main surface, a third insulating material layer interposed between the second electrode and the first electrode, characterized in that it further comprises a.

また、前記他主面と前記第二電極との間に、前記一導電型を示す高濃度ドープ層が存在することを特徴とする。 Further, between the second electrode and the other main surface, wherein the highly doped layer exhibiting the one conductivity type is present.

また、前記第二電極はアルミニウムを主成分とすることを特徴とする。 Further, the second electrode is characterized by mainly containing aluminum.

また、前記第一電極は、前記一主面上に廻り込むように存在することを特徴とする。 Further, the first electrode is characterized by the presence so as to go around on the one main surface.

また、前記一主面は、幅及び高さが2μm以下であり、且つ、アスペクト比が0.1〜2を満たす多数の凸部を有することを特徴とする。 Further, the one main surface, is not less 2μm or less width and height, and an aspect ratio and having a plurality of protrusions to meet the 0.1-2.

また、前記一主面のシート抵抗は60〜300Ω/□であることを特徴とする。 The sheet resistance of the one main surface is characterized by a 60~300Ω / □.

また本発明の太陽電池モジュールは、上述の太陽電池素子を複数接続して成るものであって、一の太陽電池素子及び他の太陽電池素子は、それらの他主面に接合された配線材を用いて互いに接続されるものである。 The solar cell module of the present invention, which formed by connecting a plurality of the above-mentioned solar cell element, a solar cell element and the other solar cell element, a wiring material that their joined to the other main surface it is intended to be connected to each other using.

さらに本発明の太陽電池素子の製造方法は、上述の太陽電池素子の製造方法であって、前記他主面に、少なくとも前記第二絶縁材料層となる絶縁材料層を形成する工程と、前記絶縁材料層が形成された前記半導体基板に、前記複数の貫通孔を形成する工程と、前記貫通孔が形成された前記半導体基板のうち、前記絶縁材料層が被覆されていない領域の少なくと一部を他の導電型に反転させる工程とを有するものである。 Method of manufacturing a solar cell device of the present invention is a manufacturing method of the above-described solar cell element, to the other major surface, forming an insulating material layer formed of at least the second insulating material layer, the insulation on the semiconductor substrate material layer is formed, and forming said plurality of through holes, the through holes of the semiconductor substrate which is formed, a portion with less of a region where the insulating material layer is not coated the and a step of reversing the other conductivity type.

またさらに本発明の太陽電池素子の製造方法は、上述の太陽電池素子の製造方法であって、前記半導体基板に前記複数の貫通孔を形成する工程と、前記貫通孔が形成された前記半導体基板のうち、所定領域を他の導電型に反転させる工程と、前記所定領域を除く領域の少なくとも一部を、少なくとも前記第二絶縁材料層となる絶縁材料層で被覆する工程とを有するものである。 Moreover, the method of manufacturing a solar cell device of the present invention also provides a method for producing the aforementioned solar cell elements, a step of forming a plurality of through-holes in the semiconductor substrate, the semiconductor substrate having the through-hole is formed of those with a step of reversing the predetermined region on the other conductivity type, at least part of the area except for the predetermined region, and a step of covering at least the the second insulating material layer insulating material layer .

さらにまた本発明の太陽電池モジュールの製造方法は、上述の太陽電池モジュールの製造方法であって、前記太陽電池素子の一主面側を下方に向けて所定の基体上に載置し、上方から配線材を接触させる工程を有するものである。 Furthermore the method for manufacturing the solar cell module of the present invention is a manufacturing method of the above-mentioned solar cell module was placed on a predetermined substrate toward the one main surface side of the solar cell element downwardly from above and it has a step of contacting the wiring member.

本発明の太陽電池素子は、一導電型を示す半導体基板と、前記半導体基板の一主面に形成され、前記一導電型と逆の導電型を示す第一逆導電型層と、前記半導体基板の一主面から他主面に至り、内壁が第二逆導電型層或いは第一絶縁材料層で覆われた複数の貫通孔と、前記一主面側から前記貫通孔内を介して前記他主面側に至るように形成され、前記第一逆導電型層と接続された第一電極と、前記他主面上に形成され、前記第一電極と極性を異にする第二電極と、前記他主面と前記第一電極との間に介在された第二絶縁材料層とを有してなることから、半導体基板の他主面に逆導電型層を設けることなく、半導体基板の一導電型領域と第一電極との間の絶縁を図ることができるため、第二電極の形成領域をより広くして太陽電池素子の特性向 Solar cell device of the present invention includes a semiconductor substrate illustrating one conductivity type, and said formed on one main surface of the semiconductor substrate, a first opposite conductivity type layer exhibiting the one conductivity type opposite conductivity type, said semiconductor substrate one reaches from the main surface to the other major surface, said through a plurality of through-holes the inner wall is covered with the second opposite conductivity type layer or the first insulating material layer, said through hole from said one main surface side other is formed so as to reach the main surface, a first electrode connected to the first opposite conductivity type layer, wherein formed on the other main surface, a second electrode having different the first electrode and the polarity, said other main surface from becoming and a second insulating material layer interposed between the first electrode without providing the opposite conductivity type layer on the other main surface of the semiconductor substrate, a semiconductor substrate one since it is possible to achieve conductivity type region and the insulation between the first electrode, especially propensity wider to the solar cell element formation region of the second electrode を図ることが可能となる。 It is possible to achieve. しかも、機械的方法や化学処理等によって絶縁溝を形成する必要がないため、太陽電池素子の機械的強度の低下を招くこともない。 Moreover, it is not necessary to form the insulation trenches by mechanical methods and chemical treatment and the like, nor causing a decrease in mechanical strength of the solar cell element.

また、前記第二絶縁材料層は、酸素化合物或いは窒素化合物を主成分とすることが好ましく、これによって、リーク電流の発生等を抑制することができるとともに、界面におけるパッシベーション効果によって半導体基板の他主面の表面再結合速度を低減させて、太陽電池素子の出力特性を向上させることが可能になる。 Further, the second insulating material layer is preferably composed mainly of oxygen compound or a nitrogen compound, whereby, it is possible to suppress the occurrence of leakage current, other main semiconductor substrate with a passivation effect at the interface by reducing the surface recombination velocity of the surface, it is possible to improve the output characteristics of the solar cell element.

また、前記第二絶縁材料層は水素を含有することが好ましく、これによって、半導体基板への水素供給が行われて半導体基板の粒界が効果的にパッシベートされ、上記出力特性をさらに向上させることができる。 Further, the second insulating material layer preferably contains hydrogen, whereby, it is made of hydrogen supply to the semiconductor substrate grain boundaries of the semiconductor substrate is effectively passivated, to further improve the output characteristics can.

また、前記他主面上で、前記第一電極と前記第二電極との間に介在された第三絶縁材料層をさらに有することが好ましく、これによって、両電極間でのリーク電流の発生を抑制することが可能となる。 Further, on the other main surface, more preferably has a third insulating material layer interposed between the second electrode and the first electrode, thereby, generation of a leakage current between the electrodes it is possible to suppress.

また、前記他主面と前記第二電極との間に、前記一導電型を示す高濃度ドープ層が存在することが好ましく、これによって、半導体基板の他主面表面近傍でのキャリア再結合による効率低下を防ぐことができ、半導体基板と第二電極の間にオーミックコンタクトを得ることができる。 Further, between the second electrode and the other main surface, it is preferable that the high-concentration doped layer exhibiting the one conductivity type is present, by which, due to carrier recombination at the other principal surface vicinity of the semiconductor substrate it is possible to prevent decrease in efficiency can be obtained an ohmic contact between the semiconductor substrate and the second electrode. 特に、前記第二電極はアルミニウムを主成分とすることが好ましく、これによって、第二電極を形成すると同時に、P型半導体基板に対して高濃度ドープ層を形成することができる。 In particular, the second electrode is preferably composed mainly of aluminum, whereby, at the same time to form a second electrode, it is possible to form a highly doped layer relative to the P-type semiconductor substrate.

また、前記第一電極は、前記一主面上に廻り込むように存在することが好ましく、これによって、半導体基板中で生成されたキャリアを第一逆導電型層を通じて効率よく集電することができ、貫通孔内を介して他主面側から上記キャリアを取り出すことができる。 Further, the first electrode is preferably present so as to go around on the one main surface, thereby, be efficiently collector through the carriers generated in the semiconductor substrate a first opposite conductivity type layer it can, can be taken out the carrier from the other main surface via a through hole.

また、前記一主面は、幅及び高さが2μm以下であり、且つ、アスペクト比が0.1〜2を満たす多数の凸部を有することが好ましく、これによって、反射率が低減し太陽光が半導体基板内へ多く吸収されるため太陽電池素子の特性を向上させることができる。 Further, the one main surface, is not less 2μm or less width and height, and preferably has a plurality of protrusions having an aspect ratio satisfies 0.1 to 2, whereby the reflectance is reduced sunlight There can be improved characteristics of the solar cell element is absorbed much into the semiconductor substrate.

また、前記一主面のシート抵抗は60〜300Ω/□であることが好ましく、これによって、受光面での表面再結合の増大及び表面抵抗の増大を抑えることができ、特に、上記微細な突起と組み合わせることによって、太陽電池を形成したときの短絡電流を大幅に増大させることができる。 It is preferable that the sheet resistance of the main surface is 60~300Ω / □, which makes it possible to suppress an increase in increased surface recombination and surface resistance of the light receiving surface, in particular, the fine protrusions combined with, can significantly increase the short-circuit current when the formation of the solar cell.

また本発明の太陽電池モジュールは、上述の太陽電池素子を複数接続して成るものであって、一の太陽電池素子及び他の太陽電池素子は、それらの他主面に接合された配線材を用いて互いに接続されるものであることから、配線材を折り曲げて一主面側にもってくる必要もなく、簡素な構成で配線材の電極からの剥離を抑制することができる。 The solar cell module of the present invention, which formed by connecting a plurality of the above-mentioned solar cell element, a solar cell element and the other solar cell element, a wiring material that their joined to the other main surface since it is intended to be connected to each other by using, without the need to bring the one main surface side by bending a wire material, it is possible to suppress separation from the electrode of the wiring member with a simple configuration.

さらに本発明の太陽電池素子の製造方法は、上述の太陽電池素子の製造方法であって、前記他主面に、少なくとも前記第二絶縁材料層となる絶縁材料層を形成する工程と、前記絶縁材料層が形成された前記半導体基板に、前記複数の貫通孔を形成する工程と、前記貫通孔が形成された前記半導体基板のうち、前記絶縁材料層が被覆されていない領域の少なくと一部を他の導電型に反転させる工程とを有することから、絶縁材料層を導電型の反転を防止する層とすることで、極めて簡易に所望の部位のみを反転させることができる。 Method of manufacturing a solar cell device of the present invention is a manufacturing method of the above-described solar cell element, to the other major surface, forming an insulating material layer formed of at least the second insulating material layer, the insulation on the semiconductor substrate material layer is formed, and forming said plurality of through holes, the through holes of the semiconductor substrate which is formed, a portion with less of a region where the insulating material layer is not coated from it and a step of reversing the other conductivity type, an insulating material layer by a layer that prevents reversal of the conductivity types can be reversed only the desired site very easily. この場合に、絶縁材料層中に水素を含有していれば、導電型の反転工程中において半導体基板への水素供給が行われて半導体基板の粒界が効果的にパッシベートされ、上記出力特性をさらに向上させることができる。 In this case, if the contained hydrogen in the insulating material layer, the grain boundary of the hydrogen supply been conducted with the semiconductor substrate to the semiconductor substrate is effectively passivated in conductivity type in the inversion process, the output characteristic it can be further improved.

またさらに本発明の太陽電池素子の製造方法は、上述の太陽電池素子の製造方法であって、前記半導体基板に前記複数の貫通孔を形成する工程と、前記貫通孔が形成された前記半導体基板のうち、所定領域を他の導電型に反転させる工程と、前記所定領域を除く領域の少なくとも一部を、少なくとも前記第二絶縁材料層となる絶縁材料層で被覆する工程とを有することから、絶縁材料層の熱による劣化、並びに、拡散防止膜として要求特性を考慮することなく、所望の材料を用いて絶縁材料層を構成することができる。 Moreover, the method of manufacturing a solar cell device of the present invention also provides a method for producing the aforementioned solar cell elements, a step of forming a plurality of through-holes in the semiconductor substrate, the semiconductor substrate having the through-hole is formed among the steps of inverting the predetermined region on the other conductivity type, at least part of the area except for the predetermined region, since a step of coating with an insulating material layer formed of at least the second insulating material layer, thermal degradation of the insulating material layer, and, without taking into account the required characteristics as the diffusion preventing film, it is possible for the insulating material layer with a desired material.

さらにまた本発明の太陽電池モジュールの製造方法は、上述の太陽電池モジュールの製造方法であって、前記太陽電池素子の一主面側を下方に向けて所定の基体上に載置し、上方から配線材を接触させる工程を有することから、安定して配線材を接着させることができ、配線工程における太陽電池素子のクラックや割れ等を抑制することができ、他主面側に形成された電極上に配線材を設ければよいため、太陽電池素子の上下を引っくり返したりする必要がなく工程が煩雑になることを抑制することができる。 Furthermore the method for manufacturing the solar cell module of the present invention is a manufacturing method of the above-mentioned solar cell module was placed on a predetermined substrate toward the one main surface side of the solar cell element downwardly from above since it has the step of contacting the wiring member can be adhered stably and wiring member, it is possible to suppress the cracks or fractures of the solar cell element in the wiring step, formed on the other main surface side electrode since it is sufficient to provide a wiring material above process it is not necessary or turned over the upper and lower solar cell element can be prevented from becoming complicated.

以下、本発明の実施形態を添付図面に基づき詳細に説明する。 Hereinafter will be described an embodiment of the basis of the accompanying drawings of the present invention.

≪太陽電池素子≫ «Solar cell element»
図1は本発明の太陽電池素子の一実施形態を示す断面図である。 Figure 1 is a sectional view showing an embodiment of a solar cell element of the present invention.

以下、一導電型を示す半導体基板1として、P型のシリコン基板を使用する場合を例にとり説明する。 Hereinafter, the semiconductor substrate 1 shown one conductivity type, will be described taking as an example a case of using a P-type silicon substrate. なお、N型のシリコン基板を用いても良いのは言うまでもなく、その場合には電極の極性を逆にすればよい。 Incidentally, may be used N-type silicon substrate of course, it may be the polarity of the electrodes reversed in that case.

P型シリコン基板1には、その一主面(受光面)から他主面(裏面)に貫通する貫通孔3が複数設けられている。 The P-type silicon substrate 1, a through hole 3 is provided with a plurality of penetrating from one main surface thereof (light-receiving surface) to another major surface (back surface). 貫通孔3の内壁は、リンなどを拡散させることによってN型の逆導電型層、或いは酸化膜や窒化膜などからなる第一絶縁材料層が形成されている。 The inner wall of the through-hole 3, opposite conductivity type layer of N-type by diffusing phosphorus or the like, or the first insulating material layer made of oxide or nitride film is formed.

この半導体基板1の一主面は、リンなどを拡散させることによってN型の逆導電型層2が形成されている。 The one main surface of the semiconductor substrate 1, opposite conductivity type layer 2 of the N-type by diffusing phosphorus or the like is formed.

第一電極4は、一主面側から貫通孔内を介して他主面側に至るように形成され、逆導電型層2と接続される電極であり、図1に示すように、一主面側電極4a、貫通孔電極4bおよび他主面側電極4cで構成される。 The first electrode 4 is formed to extend through the through-hole from one principal surface to the other main surface side, an electrode to be connected to the opposite conductivity type layer 2, as shown in FIG. 1, one principal side electrode 4a, constituted by the through-hole electrode 4b and the other main surface side electrode 4c. 第一電極4は、銀などを主成分とした材料によって形成される。 The first electrode 4 is formed of a material mainly composed of silver.

ここで、第一電極4は、一主面上に廻り込むように存在することが好ましい。 Here, the first electrode 4 is preferably present so as to go around on one principal surface. 例えば、図2(a)に示されるように、さらに一主面上に線状の集電部を有することが好ましい。 For example, as shown in FIG. 2 (a), it may further include a linear collector portions on one main surface. つまり、一主面側電極4aは複数のラインにより構成されているとともに、このラインは貫通孔電極4bの少なくとも1つと接続される。 In other words, one main surface side electrode 4a together with is composed of a plurality of lines, the line is connected to at least one of the through-hole electrode 4b. これにより、半導体基板1中で生成されたキャリアを効率よく集電することができ、貫通孔電極4bを通して、裏面側の他主面側電極4cから取り出すことができる。 Thus, the carriers generated in the semiconductor substrate 1 can be efficiently collector, through the through-hole electrodes 4b, can be taken out from the back side of the other main surface side electrode 4c. また、図2(b)に示すように、一主面側電極4aは少なくとも貫通孔電極4b上に形成されたポイント状であってもよく、このようにポイント状にすることによって、半導体基板1に吸収される受光量を多くすることができる。 Further, as shown in FIG. 2 (b), by one principal surface electrode 4a may be a point-like formed on at least the through-hole electrodes 4b, to thus point-like, the semiconductor substrate 1 it is possible to increase the amount of received light that is absorbed by the.

なお、他主面側電極4cは、後述するように、例えば、酸化膜、窒化膜或いはそれらの混合膜等からなる第二絶縁材料層7を介して、半導体基板1の他主面上に形成される。 The other main surface side electrode 4c, as described later, for example, oxide film, through the second insulating material layer 7 made of a nitride film or a mixed film of them, formed on the other main surface of the semiconductor substrate 1 It is.

高濃度ドープ層9は、半導体基板1の他主面の貫通孔近傍以外の略全面に、ボロンやアルミニウムを高濃度に拡散してなるものであり、半導体基板1の他主面と後述の第二電極5との間に位置するように形成される。 Highly doped layer 9 on the other main surface through hole substantially the entire surface other than the vicinity of the semiconductor substrate 1, which is formed by diffusing boron or aluminum at a high concentration, the later with the other main surface of the semiconductor substrate 1 It is formed so as to be positioned between the second electrode 5. ここで、高濃度とは、半導体基板1における一導電型不純物の濃度よりも不純物濃度が大きいことを意味する。 Here, the high concentration, it means a greater impurity concentration than that of the one conductivity type impurity in the semiconductor substrate 1. この高濃度ドープ層9は、半導体基板1の他主面の全領域の70%以上90%以下に形成されることが好ましい。 The highly doped layer 9 is preferably formed in 70% to 90% of the total area of ​​the other main surface of the semiconductor substrate 1. 70%以上とすることで、太陽電池素子の出力特性を効果的に向上させることができ、90%以下とすることで、外部取出電極である他主面側電極4cの面積を確保して抵抗損失を低減することが可能となる。 By 70% or more, it is possible to effectively improve the output characteristics of the solar cell element, by 90% or less, to ensure the area of ​​the other main surface side electrode 4c is an external lead-out electrode resistance it is possible to reduce the loss.

第二電極5は、半導体基板の他主面上に位置し且つ第一電極4と極性を異にするものであり、アルミニウムや銀を主成分とする材料によって構成された集電電極5bと、該集電電極5bと接続され銀などを主成分とする出力取出電極5aとで構成される。 The second electrode 5 is for different in position by and first electrode 4 and the polarity on the other main surface of the semiconductor substrate, a collector electrode 5b made of a material mainly composed of aluminum or silver, configured to silver is connected to the current collector electrode 5b at the output extraction electrode 5a as a main component. なお、集電電極5bは、上述の高濃度ドープ層9上に形成することが好ましく、これによって半導体基板1中で生成されたキャリア(電子、正孔)を効率よく集電することができる。 Note that the collector electrode 5b is preferably formed on the high concentration doped layer 9 described above, whereby it is possible to efficiently collect the carriers generated in the semiconductor substrate 1 (electrons, holes). また、集電電極5bは、基板内で吸収されなかった光を再び基板内へ反射させて光電流を増加させる役割をも有し得る。 Further, the collector electrode 5b is the light not absorbed in the substrate is again reflected into the substrate may also have a role to increase the photocurrent. さらに、アルミニウムを用いることで、集電電極5bを形成する際に、高濃度ドープ層9を同時に形成することができる。 Further, by using the aluminum can when forming the collector electrode 5b, at the same time form a heavily doped layer 9.

また、高濃度ドープ層9が形成されていない半導体基板1の他主面の略全面を、少なくとも第二絶縁材料層7を含む絶縁材料層で覆うことにより、半導体基板1と第一電極4とが直接接触しないため、デッドレイヤーの形成を避けることができる。 Further, substantially the whole surface of the other main surface of the semiconductor substrate 1 to high-concentration doped layer 9 is not formed, by covering with an insulating material layer comprising at least a second insulating material layer 7, a semiconductor substrate 1 and the first electrode 4 because but not in direct contact, it is possible to avoid the formation of dead layer. しかも、第二絶縁材料層7として酸化膜や窒化膜を用いる場合には、パッシベーション効果によって半導体基板1の他主面の表面再結合速度を低減させて太陽電池素子の出力特性を向上させることが可能になる。 Moreover, in the case of using an oxide film or a nitride film as the second insulating material layer 7, the passivation effect by reducing the surface recombination velocity of the other main surface of the semiconductor substrate 1 to improve the output characteristics of the solar cell element possible to become. さらに、これらの絶縁材料層に水素を含有させればパッシベーション効果がさらに向上させることが可能になる。 Furthermore, it is possible to be contained hydrogen in these insulating material layer passivation effect is further improved. 水素含有の絶縁材料層として、例えば、他の導電型を示す水素化アモルファスシリコン膜を用いても構わない。 As the insulating material layer of the hydrogen-containing, for example, may be used hydrogenated amorphous silicon film showing the other conductivity type. また、半導体基板と他の導電型を示す水素化アモルファスシリコン膜の間にノンドープ型(i型)の水素化アモルファスシリコン膜を設けても構わない。 Further, it may be a hydrogenated amorphous silicon film of non-doped (i-type) is provided between the hydrogenated amorphous silicon film of the semiconductor substrate and the other conductive type.

また、隣接する第一電極4(他主面側電極4c)と第二電極5(集電電極5b)との距離は0.3mm以上5mm以下であることが好ましい。 Further, it is preferable that the distance between the adjacent first electrode 4 (the other main surface side electrode 4c) and the second electrode 5 (the collector electrode 5b) is 0.3mm or more 5mm or less. この範囲とすることで、リーク電流の発生を抑制しつつ、高濃度ドープ層9の領域を広くして太陽電池素子の特性向上を図ることが可能になる。 With this range, while suppressing the occurrence of leakage current, it is possible to improve the characteristics of the solar cell element to widen the area of ​​the heavily doped layer 9.

また、半導体基板1の他主面上で第一電極4(他主面側電極4c)と第二電極5(集電電極5b)との間に、第三絶縁材料層8が形成されていることが好ましく、これによってリーク電流の発生を抑制することができる。 Further, on the other main surface a first electrode 4 of the semiconductor substrate 1 between the (other main surface side electrode 4c) and the second electrode 5 (collector electrode 5b), a third insulating material layer 8 is formed it is preferred, whereby it is possible to suppress the occurrence of leakage current. 特に、第三絶縁材料層8に水素を含有させれば、パッシベーション効果をも得ることができる。 In particular, if hydrogen is contained in the third insulating material layer 8, it is possible to obtain also a passivation effect. 水素含有の絶縁材料層として、例えば、ノンドープ型(i型)の水素化アモルファスシリコン膜を用いても構わない。 As the insulating material layer of the hydrogen-containing, for example, may be used hydrogenated amorphous silicon film of non-doped (i-type).

なお、半導体基板1の一主面は、幅と高さが2μm以下であり、アスペクト比が0.1〜2の微細な凸部が多数形成されていることが好ましく、これによって、反射率が低減し太陽光が半導体基板内へ多く吸収されるため太陽電池素子の特性を向上させることができる。 Note that one main surface of the semiconductor substrate 1 is the 2μm or less width and height, it is preferable that minute projections having an aspect ratio of 0.1 to 2 are formed a large number, whereby the reflectance is reduced sunlight can improve the characteristics of the solar cell element is absorbed much into the semiconductor substrate. また、一主面のシート抵抗が60〜300Ω/□であることが好ましく、この範囲とすることで受光面での表面再結合の増大及び表面抵抗の増大を抑えることができ、特に、上記微細な突起と組み合わせることによって、太陽電池を形成したときの短絡電流を大幅に増大させることができる。 Further, it is possible to suppress preferably the sheet resistance of the main surface is 60~300Ω / □, increase and increased surface resistance of the surface recombination at the light-receiving surface by this range, in particular, the fine by combining the Do protrusion may significantly increase the short-circuit current when the formation of the solar cell. なお、シート抵抗の値は、四探針法により測定することができ、半導体基板の表面に一直線上に並んだ4本の金属針を加圧しながら接触させ、外側の2本の針に電流を流したときに、内側の2本の針の間に発生した電圧を測定し、この電圧と流した電流からオームの法則によって抵抗値が求められる。 The value of the sheet resistance may be measured by a four probe method, four metal needles arranged in a straight line on the surface of the semiconductor substrate is contacted under pressure, the current two needles of outer when flushed, to measure the voltage generated between the two needles of the inner resistance value by Ohm's law from the current supplied with this voltage is obtained.

≪太陽電池モジュール≫ «Solar cell module»
上述した本発明の太陽電池素子は、通常、複数接続されて太陽電池モジュールとして構成される。 Solar cell device of the present invention described above is generally configured as a solar cell module is connected.

太陽電池モジュールの代表的構造図を図4に示す。 Figure 4 shows the typical structural diagram of a solar cell module. 図4は、本発明の太陽電池モジュールの一実施形態を示す図であり、図4(a)は断面図、図4(b)は正面図である。 Figure 4 is a diagram showing an embodiment of a solar cell module of the present invention, FIG. 4 (a) is a cross-sectional view, FIG. 4 (b) is a front view.

図4(a)に示すように、ガラス等からなる透明部材22の上に、透明のエチレンビニルアセテート共重合体(EVA)等からなる表側充填材24と、配線材21によって接続された複数の太陽電池素子20と、EVA等からなる裏側充填材25と、ポリエチレンテレフタレート(PET)や金属箔をポリフッ化ビニル樹脂(PVF)で挟みこんだ裏面保護材23と、を順次積層して、ラミネータ装置の中で脱気・加熱して押圧することによって一体化させ、太陽電池モジュール30を完成することができる。 As shown in FIG. 4 (a), on a transparent member 22 made of glass or the like, the front side filler 24 made of transparent ethylene-vinyl acetate copolymer (EVA) or the like, a plurality of which are connected by a wiring member 21 the solar cell element 20, a back side filler 25 made of EVA or the like, is sandwiched by polyethylene terephthalate (PET) or metal foil polyvinyl fluoride resin (PVF) and the back surface protective member 23 are sequentially stacked, laminator was degassed and heating are integrated by pressing in, it is possible to complete the solar cell module 30.

配線材21としては、通常、厚さ0.1〜0.2mm程度、幅2mm程度の銅箔の全面を半田材料によって被覆したものを所定の長さに切断してなるものが好適に用いられ、これを太陽電池素子の電極上に半田付けして使用される。 As the wiring material 21, typically, a thickness of about 0.1 to 0.2 mm, is used preferably made by cutting a material obtained by coating the entire surface of a copper foil having a width of about 2mm by a solder material to a predetermined length They are used which are soldered onto the electrodes of the solar cell element. 本発明の太陽電池素子20は、他主面に第一電極及び第二電極を有することから、図4(a)に示されるように、配線材21は太陽電池素子20の他主面に設けられた電極と接続して設ければよく、配線材21を折り曲げて一主面側にもってくる必要もなく、配線材21の電極からの剥離を抑制することができる。 Solar cell element 20 of the present invention has a first electrode and a second electrode on the other principal surface, as shown in FIG. 4 (a), the wiring material 21 is provided on the other main surface of the solar cell element 20 was electrodes and may be provided to connect, it is not necessary to bring the one main surface side by bending a wire material 21, it is possible to suppress separation from the electrode of the wiring member 21.

また、配線材21を用いた太陽電池素子同士の接続パターンとしては、図5(a)に示すように、第一の太陽電池素子20aの第一電極4(他主面側電極4c)がこれと隣接する第二の太陽電池素子20bの第二電極5(出力取出電極5a)に接続されているとともに、第一の太陽電池素子20aの第二電極5(出力取出電極5a)は第三の太陽電池素子20cの第一電極4(他主面側電極4c)と接続することができる。 As the connection pattern of the solar cell elements with each other using a wiring member 21, as shown in FIG. 5 (a), the first electrode 4 of the first solar cell element 20a (the other main surface side electrode 4c) is this and together they are connected to the second electrode 5 (output extraction electrode 5a) of the second solar cell element 20b adjacent, second electrode 5 of the first solar cell element 20a (output extraction electrode 5a) a third it can be connected to the first electrode 4 (the other main surface side electrode 4c) of the solar cell element 20c.

また、図5(b)に示されるように、第一の太陽電池素子20aの第一電極4(他主面側電極4c)がこれと隣接する第三の太陽電池素子20cの第一電極4(他主面側電極4c)に接続されるとともに、第一の太陽電池素子20aの第二電極5(出力取出電極5a)は第二の太陽電池素子20bの第二電極5(出力取出電極5a)と接続しても良い。 Further, FIG. 5 as (b), the first electrode 4 of the third solar cell element 20c first electrode 4 of the first solar cell element 20a (the other main surface side electrode 4c) is adjacent thereto It is connected to (the other main surface side electrode 4c), the second electrode 5 of the first solar cell element 20a (output extraction electrode 5a) and the second electrode 5 (output extraction electrode 5a of the second solar cell element 20b ) and it may be connected.

なお、上述の太陽電池モジュール30の外周には、アルミニウムなどの枠28をはめ込むことができる。 Incidentally, on the outer circumference of the solar cell module 30 described above, it is possible to fit the frame 28, such as aluminum. さらに、直列接続された複数の太陽電池素子20のうち、最初の太陽電池素子及び最後の太陽電池素子の各電極の一端は、出力取出配線26によって出力取出部である端子ボックス27に接続される。 Furthermore, among the plurality of solar cell elements 20 connected in series, one end of each electrode of the first solar cell element and the end of the solar cell element is connected to a terminal box 27 which is an output extraction portion by output extraction wiring 26 .

≪太陽電池素子の製造方法(第一実施形態)≫ «The method of manufacturing a solar cell device (first embodiment)»
本発明の太陽電池素子の製造方法の第一実施形態について、図6を用いて説明する。 For the first embodiment of a method for manufacturing a solar battery cell of the present invention will be described with reference to FIG.

<半導体基板の準備工程> <Preparation process of the semiconductor substrate>
まず、一導電型を示す半導体基板1として、P型のシリコン基板を準備する(図6(a))。 First, as the semiconductor substrate 1 shown one conductivity type, to prepare a P-type silicon substrate (FIG. 6 (a)).

シリコン基板は、単結晶シリコン基板であれば、FZやCZ法など公知の製法で作製された単結晶シリコンインゴットから切り出すことで得られる。 Silicon substrate, if the single crystal silicon substrate is obtained by cutting a single crystal silicon ingot manufactured by a known method such as FZ or CZ method. また、多結晶シリコン基板であれば、キャスト法や鋳型内凝固法などの公知の製法で作製された多結晶シリコンインゴットから切り出すことで得られる。 Further, if the polycrystalline silicon substrate obtained by cutting a polycrystalline silicon ingot manufactured by a known method such as casting or mold in solidification process. また、リボン法等の引き上げ法で得られた板状シリコンを用いる場合は、この板状シリコンを所定の大きさにカットし、必要に応じて表面研磨処理等を施すことで所望のシリコン基板を得ることができる。 In the case of using a plate-like silicon obtained by pulling method ribbon method, to cut the plate-shaped silicon into a predetermined size, a desired silicon substrate by performing a surface polishing treatment or the like, if necessary it is possible to obtain.

シリコン基板の導電型の制御は、上記各シリコンインゴット製造方法において、ドーパント元素そのもの或いはドーパント元素がシリコン中に適量含まれたドーパント材を、適量、シリコン融液中に溶かすことで実現できる。 Conductivity type control of the silicon substrate, in each of the silicon ingot manufacturing method, the dopant material dopant element itself or dopant element is contained an appropriate amount in the silicon can be achieved by dissolving an appropriate amount, into the silicon melt.

以下、B(ボロン)あるいはGa(ガリウム)が、1E15〜1E17atoms/cm 程度ドープされたP型結晶シリコン基板を用いた場合について説明する。 Hereinafter, B (boron) or Ga (gallium) is, the case of using the P-type crystalline silicon substrate which is 1E15~1E17atoms / cm 3 about dope. ここで、Gaを用いれば、基板中のO(酸素)とBとが関係して生じる光劣化現象を回避できるので高効率化に好適である。 Here, the use of Ga, is suitable for high efficiency can be avoided the photodegradation phenomenon caused O in the substrate (oxygen) and B is involved. また、シリコン基板の厚みは、300μm以下にすることが好ましく、より好ましくは250μm以下、さらに好ましくは150μm以下にすればよい。 The thickness of the silicon substrate is preferably a 300μm or less, more preferably 250μm or less, and more preferably be in the 150μm or less.

なお、基板の切り出し(スライス)に伴う基板表層部の機械的ダメージ層や汚染層を除去するために、この基板の受光面側及び裏面側の表層部をNaOHやKOH、あるいはフッ酸と硝酸の混合液などでそれぞれ10〜20μm程度エッチングし、その後、純水などで洗浄する。 In order to remove the mechanical damage layer or contamination layer on the substrate surface layer portion due to the cutting out of the substrate (slice), the surface portion of NaOH or KOH of the light-receiving surface side and back surface side of the substrate or of hydrofluoric acid and nitric acid, mixture at such respectively 10~20μm etched by about, then washed with pure water or the like.

<貫通孔の形成工程> <Step of forming the through hole>
次に、半導体基板1の一主面から他主面に至るような貫通孔3を形成する(図6(b))。 Next, a through hole 3 as leading to another principal surface of one main surface of the semiconductor substrate 1 (Figure 6 (b)).

貫通孔3は、機械的ドリル、ウォータージェット或いはレーザー装置等を用いて、半導体基板1の裏面側から受光面側に向けて形成すればよい。 Through-hole 3, mechanical drilling, using a water jet or laser devices, etc., may be formed toward the light-receiving surface side from the back side of the semiconductor substrate 1. また、用いる装置や条件において穴加工による基板への損傷が少なければ、受光面側から裏面側に向けて貫通孔3を形成してもよい。 Also, the less damage to the substrate by drilling in the equipment and conditions employed, may be formed through-hole 3 toward the back side from the light receiving surface side. また、貫通孔3形成位置以外のところにレジストやマスクを形成し、化学エッチングによって貫通孔3を形成しても構わない。 Further, a resist or mask is formed at other than the through-hole 3 formed position, may be formed a through-hole 3 by chemical etching. なお、貫通孔3は、一定のピッチで複数形成されることが好ましい。 The through hole 3 is preferably formed with a plurality at a predetermined pitch.

<他主面への絶縁材料層の形成工程> <Step of forming the insulating material layer to the other main surface>
次に、半導体基板1の他主面に、第二絶縁材料層7及び第三絶縁材料層8となる絶縁材料層を形成する(図6(c))。 Next, the other main surface of the semiconductor substrate 1, an insulating material layer made of a second insulating material layer 7 and the third insulating material layer 8 (Figure 6 (c)).

具体的には、シリコン酸化膜(SiO 膜)、チタン酸化膜(TiO )やシリコン窒化膜(SiNx)などを、スパッタ法、蒸着法或いはCVD法などを用いて、厚さ10nm〜50μm程度で形成する。 Specifically, a silicon oxide film (SiO 2 film), or titanium oxide (TiO 2) or silicon nitride film (SiNx), a sputtering method, a vapor deposition method or a CVD method, a thickness of 10nm~50μm about in form. また、酸素雰囲気または大気雰囲気の熱酸化炉内で半導体基板1に熱処理を施したり、酸化膜材料をスピンコート法、スプレー法やスクリーン印刷法等の塗布法を用いて塗布・焼成することによって、酸化膜(絶縁材料層)を形成しても構わない。 Also, or subjected to a heat treatment to the semiconductor substrate 1 by a thermal oxidation furnace in an oxygen atmosphere or an air atmosphere, a spin coating method an oxide film material, by coating and baking using a coating method such as a spray method, a screen printing method, it may be formed an oxide film (insulating material layer). なお、絶縁材料層は単層膜であってもよいし、酸化シリコン膜と窒化シリコン膜の二層構造等からなる複数層であってもよい。 The insulating material layer may be a single layer film, or may be a multi-layer consisting of two layer structure of a silicon oxide film and a silicon nitride film.

また、プラズマCVD法を用いて形成したシリコン窒化膜は、水素(H )を含んでおり、成膜中及び成膜後の加熱により、半導体基板1内に水素(H )を拡散させ、半導体基板1中に存在するダングリングボンド(余った化学結合手)に水素(H )を結合させることにより、キャリアがダングリングボンドに捕まる確率を低減することができるため、パッシベーション効果を有することができる。 The silicon nitride film formed by plasma CVD includes a hydrogen (H 2), by heating during or after the deposition and the deposition, to diffuse hydrogen (H 2) in the semiconductor substrate 1, by binding the hydrogen (H 2) to the dangling bonds (excess chemical bonds) present in the semiconductor substrate 1, it is possible that the carrier to reduce the probability of getting caught dangling bonds, having a passivation effect can. よって、他主面の略全面にシリコン窒化膜を形成することにより、高効率な太陽電池素子を形成することが可能となる。 Therefore, by forming a silicon nitride film on substantially the entire surface of the other main surface, it is possible to form a highly efficient solar cell devices.

また、略全面に絶縁材料層を形成することで、後工程である逆導電型層(拡散層)の形成に際して、半導体基板1の裏面側に逆導電型層が形成されるのを防止することができる。 Further, substantially the entire surface to form an insulating material layer, when forming the opposite conductivity type layer is a post-process (diffusion layer), to prevent the opposite conductivity type layer is formed on the back surface side of the semiconductor substrate 1 can. 特に、CVD法や塗布法等を用いれば、絶縁材料層のみを半導体基板1の他主面側表面のみに形成することができるため好ましい。 In particular, the use of the CVD method or a coating method, or the like, preferably possible to form only the insulating material layer only on the other main surface side surface of the semiconductor substrate 1.

なお、本工程の変形例として、絶縁材料層7、8の形成は、第一電極4(他主面側電極4c)の形成までに行えば良く、例えば、反射防止膜10や高濃度ドープ層9、集電電極5bの形成の後に行っても構わない。 As a modification of this process, formation of the insulating material layers 7 and 8 may be performed before the formation of the first electrode 4 (the other main surface side electrode 4c), for example, the anti-reflection film 10 and the highly doped layer 9, may be performed after the formation of the collector electrode 5b.

<凹凸構造の形成工程> <Process of forming the convex-concave structure>
次に、半導体基板1の受光面側に、光反射率の低減を効果的に行うための微細な突起(凸部)をもつ凹凸構造1aを形成する(図6(d))。 Next, on the light-receiving surface side of the semiconductor substrate 1, to form an uneven structure 1a with minute projections (projecting portions) for performing reduction of light reflectance effectively (Fig. 6 (d)).

凹凸構造1aの形成方法としては、NaOHやKOHなどによるアルカリ液によるウェットエッチング法や、Siをエッチングする性質を有するエッチングガスを用いるドライエッチング法を用いることができる。 As a method for forming the irregular structure 1a, it can be used like or wet etching method using an alkaline solution with NaOH or KOH, a dry etching method using an etching gas having a property of etching Si.

前者は、先に述べた基板表層部のダメージ層を除去するプロセスに連続して行うことができ、特に基板裏面側をエッチング防止材でマスクしない限り、基板裏面側にも凹凸構造が形成されるため好ましい(不図示)。 The former can be performed continuously in the process of removing the damaged layer of the substrate surface layer portion described above, the uneven structure is formed also on unless masked, the substrate back side in particular the rear surface side of the substrate by etching prevention material desirable (not shown).

後者は、基本的に、処理した面(受光面側)にだけ微細な凹凸構造1aが形成される。 The latter is basically treated surface only (the light receiving surface side) fine uneven structure 1a is formed. ドライエッチング法には様々な手法があるが、特にRIE法(Reactive Ion Etching法)を用いると、広い波長域に渡って極めて低い光反射率に抑えられる微細な凹凸構造1aを広い面積に渡って短時間で形成することができるので、高効率化に極めて有効である(例えば、特許文献3参照)。 Although the dry etching has a variety of techniques, especially the use RIE method (Reactive Ion Etching method), over a fine uneven structure 1a to be suppressed to a very low reflectance over a wide wavelength range over a wide area can be formed in a short time, it is very effective in high efficiency (e.g., see Patent Document 3). また、結晶の面方位に大きく影響されないで凹凸構造1aを形成できる特徴があるので、結晶シリコン基板として多結晶シリコン基板を用いた場合でも、多結晶シリコン基板内の各結晶粒の面方位に依存しないで、基板全域に渡って低反射率を有する微細凹凸構造を一様に形成することができる。 Further, since there is a feature capable of forming an uneven structure 1a without being greatly affected by the surface orientation of the crystal, even when a polycrystalline silicon substrate as crystalline silicon substrate, depending on the plane orientation of each crystal grain in the polycrystalline silicon substrate not, it is possible to uniformly form a fine uneven structure having a low reflectance over the entire substrate. さらに、ドライエッチング法を用いれば、前工程で半導体基板1の受光面側にも絶縁材料層が形成された場合に、各種条件を調整することによって、予め受光面側の絶縁材料層を除去することなく凹凸構造1aを形成することが可能である。 Further, by using a dry etching method, when also the insulating material layer on the light-receiving surface side of the semiconductor substrate 1 is formed in the previous step, by adjusting various conditions, in advance remove the insulating material layer of the light-receiving surface side it is possible to form the uneven structure 1a without.

なお、上記各工程に関する変形例として、凹凸構造1aを形成した後に、貫通孔3の形成、および絶縁材料層7、8の形成を行っても構わない。 As a modified example of the above process, after forming the concave-convex structure 1a, formation of the through-hole 3, and may be performed to form the insulating material layers 7,8. 例えば、図7に示されるように、凹凸構造1aを形成した半導体基板1に、第二絶縁材料層7及び第三絶縁材料層8となる絶縁材料層を形成し(図7(a))、その後に、貫通孔3を形成しても構わない(図7(b))。 For example, as shown in FIG. 7, the semiconductor substrate 1 formed with the uneven structure 1a, to form a second insulating material layer 7 and the insulating material layer formed of a third insulating material layer 8 (FIG. 7 (a)), Thereafter, it is also possible to form the through-hole 3 (Fig. 7 (b)). このようにすることによって、貫通孔3内壁に絶縁材料層が形成されることもなく、工程を単純化することができる。 By doing so, without the insulating material layer in the through-hole 3 the inner wall is formed, it is possible to simplify the process.

<一主面への逆導電型層の形成工程> <Process of forming the opposite conductivity type layer to the main surface>
次に、一主面上(受光面上)に第一逆導電型層2(拡散層)を形成し、貫通孔3の内壁に逆導電型を成す第二逆導電型層6を形成する(図6(e))。 Then, the main surface on to form the first opposite conductivity type layer 2 (on the light-receiving surface) (diffusion layer), to form a second opposite conductivity type layer 6 forming the opposite conductivity type on the inner wall of the through hole 3 ( Figure 6 (e)).

逆導電型を形成するためのN型化ドーピング元素としてはP(リン)を用いることが好ましく、シート抵抗が60〜300Ω/□程度のN 型とする。 It is preferable to use P (phosphorus) as N-type doping element for forming the opposite conductivity type, the sheet resistance is to 60~300Ω / □ degree of N + -type. これによって上述のP型バルク領域との間にPN接合部が形成される。 This PN junction is formed between the above-described P-type bulk regions.

第一逆導電型層2及び第二逆導電型層6は、ペースト状態にしたP を半導体基板表面に塗布して熱拡散させる塗布熱拡散法、ガス状態にしたPOCl (オキシ塩化リン)を拡散源とした気相熱拡散法、及び、P イオンを直接拡散させるイオン打ち込み法などによって形成される。 The first opposite conductivity type layer 2 and the second opposite conductivity type layer 6, coating thermal diffusion method is thermally diffused by applying a P 2 O 5 with a paste state on the surface of a semiconductor substrate, POCl 3 (oxychloride was a gas state vapor thermal diffusion method with a diffusion source of phosphorus), and are formed by an ion implantation method of diffusing P + ions directly. この第一逆導電型層2及び第二逆導電型層6は、0.2〜0.5μm程度の深さに形成されることが好ましい。 The first opposite conductivity type layer 2 and the second opposite conductivity type layer 6 is preferably formed to a depth of about 0.2 to 0.5 [mu] m.

なお、処理対象面と反対側の面にも拡散領域が形成されるような条件下では、その部分に予め絶縁材料層7、8を形成することにより、部分的に拡散を防止することができ、また、絶縁材料層7、8を形成しない場合には、反対側の面に形成された部分を後からエッチングして除去してもよい。 In the conditions such as the diffusion region on the surface opposite to the processed surface is formed by forming a pre-layer of insulating material 7, 8 in that portion, it is possible to prevent the partial diffusion Further, in the case of not forming an insulating material layer 7 and 8, it may be removed by etching after the surface portion formed on the opposite side. 例えば、半導体基板1の受光面側にレジスト膜を塗布し、フッ酸又はフッ酸と硝酸の混合液を用いてエッチング除去した後、レジスト膜を除去することにより行う。 For example, a resist film is applied on the light-receiving surface side of the semiconductor substrate 1, after etching is removed using a mixed solution of hydrofluoric acid or hydrofluoric acid and nitric acid, carried out by removing the resist film. なお、後述するように、裏面の高濃度ドープ層9をアルミニウムペーストによって形成する場合は、P型ドープ剤であるアルミニウムを充分な濃度で充分な深さまで拡散させることができるので、既に拡散してあった浅い逆導電型層の影響は無視することができ、この高濃度ドープ層9形成位置に存在する逆導電型層は特に除去する必要がない。 As described later, when the back surface of the highly doped layer 9 is formed of aluminum paste, it is possible to diffuse to the aluminum a sufficient concentration sufficient depth of P-type dopant, already diffused effect of a shallow opposite conductivity type layer can be neglected, opposite conductivity type layer present on the highly doped layer 9 forming position need not be particularly removed.

なお、第一逆導電型層2及び第二逆導電型層6の形成方法は上記方法に限定されるものではなく、例えば薄膜技術及び条件を用いて、水素化アモルファスシリコン膜や、微結晶シリコン膜を含む結晶質シリコン膜などを形成してもよい。 In addition, the method of forming the first opposite conductivity type layer 2 and the second opposite conductivity type layer 6 is not limited to the above methods, for example using thin-film techniques and conditions, and hydrogenated amorphous silicon film, a microcrystalline silicon such as crystalline silicon film containing film may be formed. ここで水素化アモルファスシリコン膜を用いて第一逆導電型層2(或いは第二逆導電型層6)を形成する場合は、その厚さは50nm以下、好ましくは20nm以下とし、結晶質シリコン膜を用いて形成する場合はその厚さは500nm以下、好ましくは200nm以下とする。 If here forming a hydrogenated amorphous silicon film a first opposite conductivity type layer 2 by using (or the second opposite conductivity type layer 6), the thickness thereof is 50nm or less, preferably a 20nm or less, a crystalline silicon film when formed using its thickness is 500nm or less, preferably 200nm or less. さらに、半導体基板1と第一逆導電型層2(第二逆導電型層6)との間に、i型シリコン領域(不図示)を厚さ20nm以下で形成してもよい。 Furthermore, between the semiconductor substrate 1 and the first opposite conductivity type layer 2 (second opposite conductivity type layer 6), i-type silicon region (not shown) may be formed with a thickness of less than 20nm a.

ここで、貫通孔3の内壁には、上述の第二逆導電型層6に代えて、第二絶縁材料層7や第三絶縁材料層8と同様に、シリコン酸化膜(SiO 膜)、チタン酸化膜(TiO )やシリコン窒化膜(SiNx)等からなる第一絶縁材料層6を形成しても構わない。 Here, the inner wall of the through-hole 3, instead of the second opposite conductivity type layer 6 described above, similarly to the second insulating material layer 7 and the third insulating material layer 8, a silicon oxide film (SiO 2 film), it may be formed of the first insulating material layer 6 made of a titanium oxide film (TiO 2) or silicon nitride film (SiNx) or the like. この場合、第一絶縁材料層6は、第二絶縁材料層7及び第三絶縁材料層8と同時に形成すればよく、当該絶縁材料層の形成後に導電型の反転工程を行えば、一主面側のみに逆導電型層2を形成することができる。 In this case, the first insulating material layer 6 may be a second insulating material layer 7 and the third insulating material layer 8 formed at the same time, by performing inversion process of the conductivity type after forming of the insulating material layer, one main surface it is possible to form the opposite conductivity type layer 2 only on the side.

また、上記各工程に関する変形例として、図8に示すようにして上記構成を形成しても良い。 Further, as a modified example of the above steps, it may be formed above configuration as shown in FIG. すなわち、凹凸構造1aを形成した半導体基板1に、複数の貫通孔3を設け(図8(a))、拡散工程より一主面上及び貫通孔3内部に第一逆導電型層(拡散層)2及び第二逆導電型層6を形成する(図8(b))。 That is, the semiconductor substrate 1 formed with the uneven structure 1a, a plurality of through-holes 3 provided (FIG. 8 (a)), on one main surface than the diffusion step and the through hole 3 inside the first opposite conductivity type layer (diffusion layer ) to form a 2 and a second opposite conductivity type layer 6 (Figure 8 (b)). なお、逆導電型層が他主面上にも形成された場合には、エッチングして他主面上の逆導電型層を除去すれば良い。 In the case where the opposite conductivity type layer was also formed on the other main surface may be etched and removed opposite conductivity type layer on the other main surface. その後、他主面上の少なくとも一部に第二絶縁材料層及び前記第三絶縁材料層の少なくともいずれか一方となる絶縁材料層を被覆してもよい(図8c))。 Thereafter, it may be coated at least one to become an insulating material layer of the at least part of the other main surface second insulating material layer and the third insulating material layer (Fig. 8c)).

<反射防止膜の形成工程> <Process of forming the antireflection film>
次に、第一逆導電型層2の上に、反射防止膜10を形成する事が好ましい(図6(f))。 Next, on the first opposite conductivity type layer 2, it is preferable to form an antireflection film 10 (FIG. 6 (f)).

反射防止膜10の材料としては、SiNx膜(Si 34ストイキオメトリを中心にして組成比(x)には幅がある)、TiO 2膜、SiO 膜、MgO膜、ITO膜、SnO 2膜やZnO膜などを用いることができる。 As the material of the antireflection film 10, SiNx film (Si 3 N 4 stoichiometry around the Cytometry composition ratio (x) is the width), TiO 2 film, SiO 2 film, MgO film, ITO film, SnO such as 2 film or ZnO film can be used. その屈折率及び厚みは、材料によって適宜選択されて適当な入射光に対して無反射条件を実現できるようにすればよく、例えば半導体基板1がシリコン基板である場合、屈折率は1.8〜2.3程度、厚み500〜1200Å程度にすればよい。 Its refractive index and thickness may be so can be realized nonreflective condition to be appropriately selected appropriate incident light material, for example, when the semiconductor substrate 1 is a silicon substrate, the refractive index 1.8 about 2.3, may be set to a thickness of about 500~1200Å.

反射防止膜10の形成方法としては、PECVD法、蒸着法やスパッタ法などを用いることができる。 The method of forming the antireflection film 10, PECVD method, or a vapor deposition method or a sputtering method.

なお、反射防止膜10は、一主面側電極4aを形成するために所定のパターンでパターニングしておいてもよい。 The reflection preventing film 10 may be previously patterned in a predetermined pattern to form the one main surface side electrode 4a. パターニング法としては、レジストなどマスクを用いたエッチング法(ウェットあるいはドライ)や、反射防止膜10形成時にマスクを予め形成しておき、反射防止膜10形成後にこれを除去する方法、を用いることができる。 The patterning method, a resist or etching method using a mask such as (wet or dry), formed in advance mask during preventing film 10 forming the reflection, a method of removing them after preventing film 10 formed reflection, the use of it can. なお、反射防止膜10の上に一主面側電極4aの導電性ペーストを直接塗布し焼き付けることによって一主面側電極4aと第一逆導電型層2を電気的に接触させる、いわゆるファイヤースルー法(例えば、特許文献4参照)を用いる場合は、上記パターニングの必要はない。 Incidentally, electrical contacting one main surface side electrode 4a and the first opposite conductivity type layer 2 by baking applying a conductive paste one main surface side electrode 4a directly on the antireflection film 10, a so-called fire-through law (for example, see Patent Document 4) the case of using, there is no need for the patterning.

<他主面への高濃度ドープ層の形成工程> <Step of forming the heavily doped layer to the other main surface>
次に、半導体基板1の他主面には、一導電型半導体不純物が高濃度に拡散された高濃度ドープ層9を形成することが好ましい(図6(g))。 Then, the other main surface of the semiconductor substrate 1, it is preferable to form the highly doped layer 9 one conductivity type semiconductor impurity is diffused in a high concentration (Fig. 6 (g)). この高濃度ドープ層9とは、半導体基板1よりも一導電型不純物の割合が多い層を意味し、半導体基板1の裏面近くでのキャリア再結合による効率低下を防ぐために内部電界を形成するものである。 What this a highly doped layer 9, which means the layer ratio of one conductivity type impurity is larger than the semiconductor substrate 1, to form an internal electric field in order to prevent the efficiency reduction due to carrier recombination near the back surface of the semiconductor substrate 1 it is.

不純物元素としてはB(ボロン)やAl(アルミニウム)を用いることができ、不純物元素濃度を1E18〜5E21 atoms/cm 程度の高濃度として、P 型とすることによって後述する集電電極5bとの間にオーミックコンタクトを得ることができる。 As the impurity element may be used as B (boron) and Al (aluminum), an impurity element concentration as high concentration of about 1E18~5E21 atoms / cm 3, and the collector electrode 5b to be described later by a P + -type it is possible to obtain an ohmic contact between.

高濃度ドープ層9は、その形成予定位置に存在する絶縁材料層7、8をエッチング除去した後、BBr (三臭化ボロン)を拡散源とした熱拡散法を用いて温度800〜1100℃程度で形成することができる。 Highly doped layer 9, its after an insulating material layer 7 and 8 present in the form predetermined position is removed by etching, BBr 3 (boron tribromide) by a thermal diffusion method using a diffusion source temperature 800 to 1100 ° C. it can be formed in degree. なお、当該工程を行うに際して、既に形成されている第一逆導電型層2に酸化膜などの拡散バリアを形成しておくことが望ましい。 Incidentally, when performing the process, it is desirable to form a diffusion barrier such as an oxide film on the first opposite conductivity type layer 2 which has already been formed.

また、不純物元素としてアルミニウムを用いる場合は、アルミニウム粉末と有機ビヒクル等からなるアルミニウムペーストを印刷法で塗布した後、温度700〜850℃程度で熱処理(焼成)してアルミニウムを半導体基板1に向けて拡散したりする方法を用いることができる。 In the case of using aluminum as an impurity element is formed by applying an aluminum paste comprising aluminum powder and an organic vehicle such as a printing method and a heat treatment at a temperature of about 700-850 ° C. (sintering) and toward the aluminum into the semiconductor substrate 1 how to or spread can be used. この場合、印刷面だけに所望の拡散領域を形成することができ、且つ、焼成されたアルミニウムは、除去せずにそのまま集電電極5bとして利用することもできる。 In this case, only it is possible to form a desired diffusion region printing surface, and, calcined aluminum can also be utilized as it is as the collector electrode 5b is not removed.

また、上記方法に限定されず、例えば薄膜技術を用いて水素化アモルファスシリコン膜や微結晶Si相を含む結晶質シリコン膜などを形成しても良い。 Further, not limited to the above methods, for example using thin-film technology may be formed such as crystalline silicon film containing hydrogenated amorphous silicon film or a microcrystalline Si phase. 特にpn接合部を、薄膜技術を用いて形成した場合は、高濃度ドープ層9の形成も薄膜技術を用いて行う。 In particular a pn junction, when formed using a thin film technology, carried out using a form also thin-film technology heavily doped layer 9. このとき膜厚は10〜200nm程度とする。 At this time, thickness of about 10~200nm. このとき、半導体基板1と高濃度ドープ層9との間にi型シリコン領域(不図示)を厚さ20nm以下で形成すると特性向上に有効である。 In this case, it is effective to improve characteristics by forming i-type silicon region (not shown) 20 nm or less thick between the semiconductor substrate 1 and the highly doped layer 9.

なお、本工程の変形例として、上述のように、高濃度ドープ層9の形成予定位置に存在する絶縁材料層7、8を予め除去することなく、ファイヤースルー法を用いることができる。 As a modification of this process, as described above, without prior removal of the insulating material layers 7 and 8 present in the formation planned location of the heavily doped layer 9, it is possible to use fire-through method. すなわち、図9(a)に示すように、絶縁材料層7、8の上にアルミニウムペーストを直接塗布した後、図9(b)に示すように、焼き付けることにより集電電極5bおよび高濃度ドープ層9を形成することができる。 That is, as shown in FIG. 9 (a), after applying the aluminum paste directly on the insulating material layer 7 and 8, as shown in FIG. 9 (b), the collector electrode 5b and highly doped by baking it is possible to form the layer 9.

<第一電極および第二電極の形成方法> <Method of forming the first electrode and the second electrode>
次に、半導体基板1に、一主面側電極4aと貫通孔電極4bを形成する(図6(h))。 Then, the semiconductor substrate 1, to form a the one principal surface side electrode 4a through hole electrode 4b (FIG. 6 (h)).

これらの電極は、半導体基板1の受光面に従来周知の塗布法を用いて導電性ペーストを塗布すればよく、例えば銀等からなる金属粉末、有機ビヒクル及びガラスフリットを、該金属100重量部に対してそれぞれ10〜30重量部、0.1〜5重量部を添加してペースト状にしてなる導電性ペーストを、図2(a)及び(b)に示すような所定の電極形状に塗布し、最高温度500〜850℃で数十秒〜数十分程度焼成することにより形成される。 These electrodes may be coated with a conductive paste using a conventionally known coating method on the light receiving surface of the semiconductor substrate 1, for example, a metal powder composed of silver or the like, an organic vehicle and glass frit, with the metal 100 parts by weight each 10-30 parts by weight for the conductive paste comprising a paste by adding 0.1-5 parts by weight, was applied to a predetermined electrode shape as shown in FIG. 2 (a) and (b) , it is formed by firing several tens of seconds to several tens of minutes at a maximum temperature of 500 to 850 ° C.. なお、塗布後、所定の温度で溶剤を蒸散させて乾燥させたほうが好ましい。 Incidentally, after coating, preferably better it was dried by evaporation of the solvent at a predetermined temperature. また、予め貫通孔電極4bの部分のみに導電性ペーストを塗布・乾燥し、再度一主面側電極4aの部分に導電性ペーストを塗布した後に焼成する等、一主面側電極4aと貫通孔電極4bとを別々に塗布・焼成して形成しても構わない。 Further, in advance through holes only in the conductive paste portions of the electrodes 4b and coating and drying, etc. of firing after applying a conductive paste to a portion of the back one principal surface electrode 4a, one main surface side electrode 4a and the through-hole it is also possible to form the electrode 4b are applied and fired separately.

なお、後述のように他主面側電極4cを形成する際、導電性ペーストを貫通孔3に充填して貫通孔電極4bを形成することができるため、一主面側電極4aを形成する際に貫通孔3に十分な導電性ペーストが充填できなくても構わない。 Note that when forming the other main surface side electrode 4c as described below, it is possible to form the through-hole electrode 4b is filled with a conductive paste into the through-hole 3, when forming the one main surface side electrode 4a sufficient conductive paste into the through-hole 3 is may be impossible to fill in.

次に、半導体基板1の他主面上に、集電電極5bを形成する(図6(i))。 Then, on another main surface of the semiconductor substrate 1 to form a collector electrode 5b (FIG. 6 (i)).

上述の塗布法を用いて、半導体基板1の裏面に導電性ペーストを塗布すればよく、例えばアルミニウムまたは銀等からなる金属粉末、有機ビヒクル及びガラスフリットを、該金属100重量部に対してそれぞれ10〜30重量部、0.1〜5重量部を添加してペースト状にしてなる導電性ペーストを、図3に示すような所定の電極形状に塗布し、最高温度500〜850℃で数十秒〜数十分程度焼成することにより集電電極5bを形成する。 Using the above coating method, may be applying a conductive paste on the back surface of the semiconductor substrate 1, for example, a metal powder made of aluminum or silver, or the like, an organic vehicle and glass frit, respectively the metal 100 parts by weight of 10 30 parts by weight, the conductive paste comprising a paste by adding 0.1-5 parts by weight, was applied to a predetermined electrode shape as shown in FIG. 3, several tens of seconds at a maximum temperature 500 to 850 ° C. forming a collector electrode 5b by firing about to several tens of minutes. なお、前述したように、アルミニウムペーストを用いる場合は、高濃度ドープ層9と集電電極5bとを同時に形成することができ、特に半導体基板1の他主面側の全領域の70%以上90%以下の範囲で形成することが好ましい。 As described above, when using the aluminum paste may be formed simultaneously with the highly doped layer 9 and the collector electrode 5b, in particular more than 70% of the total area of ​​the other main surface of the semiconductor substrate 1 90 % it is preferably formed in the range.

次に、半導体基板1の他主面に、他主面側電極4cと出力取出電極5aとを形成する(図6(j))。 Next, the other main surface of the semiconductor substrate 1 to form an output extracting electrode 5a and the other main surface side electrode 4c (FIG. 6 (j)).

上述の塗布法を用いて、半導体基板1の裏面に導電性ペーストを塗布すれば良く、例えば銀等からなる金属粉末、有機ビヒクル及びガラスフリットを、該金属100重量部に対してそれぞれ10〜30重量部、0.1〜5重量部を添加してペースト状にしてなる導電性ペーストを、例えば、図3に示すような所定の電極形状に塗布し、最高温度500〜850℃で数十秒〜数十分程度焼成することにより他主面側電極4cと出力取出電極5aとを形成する。 By using the coating methods described above, may be coated with a conductive paste on the back surface of the semiconductor substrate 1, for example, a metal powder composed of silver or the like, an organic vehicle and glass frit, respectively the metal 100 parts by weight of 10 to 30 parts, the conductive paste comprising a paste by adding 0.1-5 parts by weight, for example, is applied to a predetermined electrode shape as shown in FIG. 3, several tens of seconds at a maximum temperature 500 to 850 ° C. by firing order to several tens of minutes to form an output extracting electrode 5a and the other main surface side electrode 4c.

なお、他主面側電極4cと出力取出電極5aとを別々に形成したり、別の導電性ペーストを用いて形成しても構わない。 Incidentally, it may or forming the output extraction electrode 5a and the other main surface side electrode 4c separately be formed using other conductive paste. この場合、出力取出電極5aの形成位置に絶縁材料層が存在していても、出力取出電極5aはファイヤースルー法を用いることにより半導体基板1と接触させるとともに、他主面側電極4cについてはファイヤースルー法を用いることなく、絶縁材料層7の上に積層形成することが可能である。 In this case, even in the presence of the insulating material layer to form a position output extraction electrodes 5a, the output extraction electrode 5a along with contacting with the semiconductor substrate 1 by using the fire-through method, fire for other main surface side electrode 4c without using the through method, it is possible to laminate formed on the insulating material layer 7.

なお、集電電極5bを形成する場合には、出力取出電極5aの一部が集電電極5bの一部と重なるように構成されることが好ましい。 When forming a collector electrode 5b is preferably part of the output extraction electrode 5a is configured so as to overlap with part of the collector electrode 5b. この場合、出力取出電極5aは、半導体基板1と直接接している必要はなく、図10に示されるように、集電電極5bとのコンタクトが取れていれば、第四絶縁材料層11上に形成しても構わない。 In this case, the output-extracting electrode 5a need not in direct contact with the semiconductor substrate 1, as shown in FIG. 10, if 0.00 contact with the collector electrode 5b, on the fourth insulating material layer 11 formed may be.

なお、本工程の変形例として、上述のように、絶縁材料層の上からアルミニウムペーストを塗布・焼成して、絶縁材料層をファイヤースルーさせ、高濃度ドープ層9と集電電極5bを形成した後(図9)、ファイヤースルーすることのできない導電性ペーストまたは焼成条件を用いて、絶縁材料層上に第一電極4(他主面側電極4c)と第二電極5(出力取出電極5a)を形成しても構わない。 As a modification of this process, as described above, an aluminum paste is applied and baked over the insulating material layer, an insulating material layer is fire-through, to form a highly doped layer 9 and the collector electrode 5b after (9), by using a conductive paste or the firing conditions that can not be fire through the insulating material layer over the first electrode 4 (the other main surface side electrode 4c) and the second electrode 5 (output extraction electrode 5a) it may be formed. このように、第二電極5の下部に絶縁材料層を設けることによって、パッシベーション効果を得ることができる。 Thus, by providing the insulating material layer in the lower portion of the second electrode 5, it is possible to obtain the passivation effect. さらに、これらの絶縁材料層に水素を含有させればパッシベーション効果をさらに向上させることが可能になる。 Furthermore, it is possible to further improve the passivation effect be contained hydrogen in these insulating material layer. 水素含有の絶縁材料層として、例えば、ノンドープ型(i型)の水素化アモルファスシリコン膜を設けても構わない。 As the insulating material layer of the hydrogen-containing, for example, may be provided a hydrogenated amorphous silicon film of non-doped (i-type).

また、絶縁材料層の上に第一電極4(他主面側電極4c)が形成されることにより、半導体基板上に電極を形成する場合に比べて、電極中にガラスフリットを有することから電極強度を向上させることができる。 Further, by the first electrode 4 on the insulating material layer (the other main surface side electrode 4c) is formed, as compared with the case of forming an electrode on a semiconductor substrate, the electrode since it has a glass frit in the electrode it is possible to improve the strength.

以上のようにして、本発明の太陽電池素子が完成する。 As described above, the solar cell element of the present invention is completed.

なお、必要に応じて、半田ディップ処理によって裏面側に形成された第一電極4,第二電極5に半田領域を形成してもよい。 If necessary, the first electrode 4 formed on the back side by the solder dipping process, may be formed solder region to the second electrode 5.

≪太陽電池素子の製造方法(第二実施形態)≫ «The method of manufacturing a solar cell element (Second Embodiment)»
本発明の太陽電池素子の製造方法の第二実施形態について、図11を用いて説明する。 A second embodiment of a method for manufacturing a solar battery cell of the present invention will be described with reference to FIG. なお、上記第一実施形態と同様の工程について説明を省略するものとし、主として本実施形態の特徴部分について図11を用いて詳細に説明する。 Incidentally, shall not be described for the above first embodiment and the same step will be described in detail with reference to FIG. 11 will be mainly feature of this embodiment.

本実施形態の特徴は、概略、貫通孔の形成工程、逆導電型層の形成工程及び絶縁材料層の形成工程を、順次行う事にある。 This embodiment is characterized in general, the formation process of the through hole, the step of forming the opposite conductivity type layer forming step and the insulating material layer, in carrying out successively. このように、逆導電型層の形成工程の後に絶縁材料層の形成工程を設けることにより、絶縁材料層の熱による劣化、並びに、拡散防止膜として要求特性を満たす必要がなく、絶縁材料層の制約条件を緩めることができ、電極と半導体基板を絶縁できる程度の厚みを形成することが可能となる。 Thus, by providing the step of forming the insulating material layer after the step of forming the opposite conductivity type layer, thermal degradation of the insulating material layer, as well, it is not necessary to satisfy the required characteristics as the diffusion preventing film, the insulating material layer can loosen the constraints, the electrode and the semiconductor substrate can be formed thick enough to insulation.

具体的には以下の通りである。 More specifically, it is as follows.

<貫通孔の形成工程> <Step of forming the through hole>
まず、第一実施形態における半導体基板の準備工程及び凹凸構造の形成工程を順に行って形成された半導体基板1に対して、その一主面から他主面に至るような貫通孔3を形成する(図11(a))。 First, the process of forming the preparing step and the uneven structure of the semiconductor substrate in the first embodiment with respect to the semiconductor substrate 1 which is formed by performing in sequence, to form a through-hole 3 as leading to the other main surface of the one main surface (Figure 11 (a)). 貫通孔の形成工程についても、上記第一実施形態と同様に行えば良い。 For even step of forming the through-holes, it may be performed in the same manner as in the first embodiment.

<一主面への逆導電型層の形成工程> <Process of forming the opposite conductivity type layer to the main surface>
次に、一主面上(受光面上)に第一逆導電型層(拡散層)2を形成する(図11(b))。 Next, a first opposite conductivity type layer on one principal surface (on the light-receiving surface) to form the (diffusion layer) 2 (FIG. 11 (b)).

この際、貫通孔3の内壁および他主面上にも逆導電型層が形成された場合には、エッチングして貫通孔3の内壁および他主面上の逆導電型層を除去する。 At this time, if the opposite conductivity type layer to the inner wall and the other main surface of the through-hole 3 is formed, removing the opposite conductivity type layer on the inner wall and the other main surface of the through-hole 3 by etching. 例えば、半導体基板1の受光面側にレジスト膜を塗布し、フッ酸又はフッ酸と硝酸の混合液を用いてエッチング除去した後、レジスト膜を除去することにより行う。 For example, a resist film is applied on the light-receiving surface side of the semiconductor substrate 1, after etching is removed using a mixed solution of hydrofluoric acid or hydrofluoric acid and nitric acid, carried out by removing the resist film.

<他主面及び貫通孔内壁への絶縁材料層の形成工程> <Step of forming the insulating material layer to the other main surface and the inner wall of the through hole>
次に、貫通孔3の内壁に第一絶縁材料層6を形成し、半導体基板1の他主面に第二絶縁材料層7及び第三絶縁材料層8を含む絶縁材料層を形成する(図11(c))。 Next, the first insulating material layer 6 is formed on the inner wall of the through-hole 3, an insulating material layer containing a second insulating material layer 7 and the third insulating material layer 8 on the other main surface of the semiconductor substrate 1 (FIG. 11 (c)).

具体的には、シリコン酸化膜(SiO 膜)、チタン酸化膜(TiO )やシリコン窒化膜(SiNx)などを、厚さ10nm〜50μm程度で形成する。 Specifically, a silicon oxide film (SiO 2 film), or titanium oxide (TiO 2) or silicon nitride film (SiNx), is formed with a thickness of about 10Nm~50myuemu. また、あらかじめ受光面側にレジスト膜を塗布し、絶縁材料層形成後レジスト膜を除去することによって、半導体基板の一主面上への絶縁材料層の形成しないようにすることができる。 The resist film is applied on the pre-light-receiving surface side, by removing the insulating material layer after forming the resist film, it is possible not to form the insulating material layer on one main surface of the semiconductor substrate.

また、貫通孔3の内壁に形成される第一絶縁材料層6と、半導体基板1の他主面に形成される、第二絶縁材料層7および第三絶縁材料層8を含む絶縁材料層とは、それぞれ別工程によって形成されても構わないが、同時に形成することにより工程を単純化することができる。 Further, a first insulating material layer 6 formed on the inner wall of the through-hole 3, are formed on the other main surface of the semiconductor substrate 1, a second insulating material layer 7 and the insulating material layers comprising a third insulating material layer 8 is may be formed by separate steps, respectively, you can simplify the process by forming simultaneously.

≪太陽電池モジュールの製造方法≫ «Of the solar cell module manufacturing method»
次に、上述したような太陽電池素子を用いた太陽電池モジュールを形成する製造工程について説明する。 Next, description will be given of a manufacturing process of forming a solar cell module using the solar cell element as described above.

図4(a)に示すように、透明部材22の上に、透明のエチレンビニルアセテート共重合体(EVA)などからなる表側充填材24と、配線材21によって隣接太陽電池素子のマイナス電極とプラス電極とを交互に接続された複数の太陽電池素子20、または隣接太陽電池素子のマイナス電極とマイナス電極、プラス電極とプラス電極とを接続された複数の太陽電池素子20と、EVAなどからなる裏側充填材25と、例えばポリエチレンテレフタレート(PET)や金属箔をポリフッ化ビニル樹脂(PVF)で挟みこんだ裏面保護材23とを順次積層して、ラミネータの中で脱気、加熱して押圧することによって一体化させる。 As shown in FIG. 4 (a), on a transparent member 22, the front side filler 24 made of transparent ethylene-vinyl acetate copolymer (EVA), negative electrode and a positive adjacent solar cell elements by a wiring member 21 back a plurality of solar cell elements 20 connected to the electrodes are alternately or negative electrode and the negative electrode of the adjacent solar cell elements, and a plurality of solar cell elements 20 connected between the positive electrode and the positive electrode, and the like EVA and the filler 25, such as polyethylene terephthalate (PET) or metal foil and a back surface protective member 23 is sandwiched by the polyvinyl fluoride resin (PVF) are sequentially stacked, degassing, heating and pressing in a laminator It is integrated by.

なお、これらの太陽電池素子同士を接続する配線材21としては、通常、厚さ0.1〜0.2mm程度、幅2mm程度の銅箔の全面を半田材料によって被覆したものを、所定の長さに切断し、太陽電池素子の電極上に半田付けして用いる。 As the wiring member 21 for connecting these solar cell elements with each other, usually to a thickness of about 0.1 to 0.2 mm, a material obtained by coating the entire surface of a copper foil having a width of about 2mm by the solder material, a predetermined length It was cut and used in soldering on the electrodes of the solar cell element.

また、本発明の太陽電池素子を用いることによって、他主面側に第一電極4と第二電極5を設けているため、太陽電池素子の一主面側を下方に向けて載置し、上方から配線材21を接触させて、接続すればよく、配線材21を接続するために、太陽電池素子を引っくり返す等の作業を必要としないため、生産性を向上することができる。 Further, by using the solar cell element of the present invention, since the first electrode 4 and the second electrode 5 provided on the other main surface side, placed toward the one main surface side of the solar cell element downwardly, contacting the wiring member 21 from above, may be connected, in order to connect the wiring member 21, because it does not require a work such as turn over the solar cell element, it is possible to improve productivity.

次に、直列接続された複数の素子の最初の素子と最後の素子の電極の一端を、出力取出部である端子ボックス27に、出力取出配線26によって接続する。 Then, one end of the first element and the last element electrodes of a plurality of elements connected in series, the terminal box 27 which is an output extraction portion, connected by output extracting wiring 26. また、図4(b)に示すように、必要に応じてアルミニウムなどの枠28を周囲にはめ込む。 Further, as shown in FIG. 4 (b), fitted the frame 28 such as aluminum around as needed. 以上によって太陽電池モジュールを完成させる。 To complete the solar cell module by more.

なお、本発明は上記実施形態に限定されるものではなく、本発明の範囲内で多くの修正および変更を加えることが出来る。 The present invention is not limited to the above embodiment, it is possible to make numerous modifications and variations within the scope of the present invention.

たとえば、第一電極4(一主面側電極4a、貫通孔電極4b及び他主面側電極4c)、第二電極5(出力取出電極5a及び集電電極5b)の各種電極における塗布・焼成は、上述の実施形態で述べた順序で形成する必要はなく、これに代えて、例えば、各電極となる導電性ペーストを塗布した後に一括焼成を行ってすべての電極を形成したり、或いは、集電電極5b、出力取出電極5a、他主面側電極4c及び貫通孔電極4bを塗布・焼成して形成した後に、一主面側電極4aを塗布・焼成して形成してもよく、適宜、組み合わせて電極を形成すればよい。 For example, the first electrode 4 (first principal surface side electrode 4a, the through-hole electrode 4b and the other main surface side electrode 4c), coating and baking in the various electrodes of the second electrode 5 (output extraction electrodes 5a and collector electrode 5b) is need not be formed in the order described in the above embodiment, instead of this, for example, to form all of the electrodes by performing a co-firing after applying a conductive paste to be the respective electrodes, or current denden electrode 5b, the output extraction electrodes 5a, after forming by coating and firing the other main surface side electrode 4c and the through-hole electrodes 4b, may be formed by coating and baking the one principal surface side electrode 4a, as appropriate, it may be formed an electrode combination.

また、他主面側電極4cの電極形状は、図3に示されるような帯状に限定されるものではなく、これに代えて、例えば、図12(a)に示されるように、他主面側電極4cは、貫通孔電極4b上に形成されたポイント状に形成されてもよい。 The electrode shape of the other main surface side electrode 4c, is not limited to belt-shaped as shown in FIG. 3, instead of this, for example, as shown in FIG. 12 (a), the other main surface side electrode 4c may be formed in a point shape formed on the through-hole electrode 4b. この場合には、図12(b)に示されるように、各ポイント状他主面側電極4cの間には第五絶縁材料層12が形成されることが好ましく、パッシベーション効果を得て太陽電池素子の出力特性を向上させることができる。 In this case, as shown in FIG. 12 (b), it is preferable to fifth dielectric material layer 12 is formed between each point-like other main surface side electrode 4c, the solar cell to obtain a passivation effect it is possible to improve the output characteristics of the device.

さらに、絶縁材料層を形成した後に水素添加処理を行っても構わない。 Furthermore, it may be subjected to hydrogenation treatment after forming the insulating material layer. 水素添加処理により、シリコン基板の粒界に水素を拡散させて、基板の粒界においてパッシベーションを発揮させることができる。 By hydrogenation treatment, hydrogen is diffused into the grain boundary of the silicon substrate, it can exhibit passivation at the grain boundaries of the substrate. 水素添加処理としては、水素雰囲気内においてプラズマ処理すればよい。 The hydrogenation treatment may be a plasma treatment in a hydrogen atmosphere. また、水素雰囲気中にヘリウム、アルゴンなどの不活性ガスを混合してもよい。 Also, in the hydrogen atmosphere helium may be mixed with an inert gas such as argon. 水素プラズマを発生させるための電源の周波数は、ラジオ周波数(RF)やマイクロ波を使用すればよい。 Frequency of the power supply for generating hydrogen plasma, it is sufficient to use a radio frequency (RF) or microwave.

またさらに、上述の第二実施形態において、貫通孔3を形成した後、一主面上(受光面上)に第一逆導電型層(拡散層)2を形成したが、これに代えて、第一逆導電型層2を形成した後に、貫通孔3を形成しても良く、これによって貫通孔3の内壁に拡散層が形成されるのを抑制することができる。 Furthermore, in the second embodiment described above, after forming the through holes 3, one main surface on (on the light-receiving surface) to the first opposite conductivity type layer (diffusion layer) were formed 2, instead of this, after forming the first opposite conductivity type layer 2 may be formed through-hole 3, whereby it is possible to suppress the diffusion layer is formed on the inner wall of the through-hole 3.

さらにまた、上述の第二実施形態において、第一逆導電型層2を形成した後で絶縁材料層を形成するようにしたが、これに代えて、図13に示すように、第一逆導電型層2の形成に先立って、貫通孔3の内壁に第一絶縁材料層6および他主面上の少なくとも一部に第二絶縁材料層及び前記第三絶縁材料層の少なくともいずれか一方となる絶縁材料層を被覆するようにしても良い(図13(b))このようにすることで、後工程である逆導電型層(拡散層)の形成に際して、半導体基板1の貫通孔3の内壁3および裏面側に逆導電型層が形成されるのを防止することができる。 Furthermore, in the second embodiment described above, but so as to form an insulating material layer after forming the first opposite conductivity type layer 2, instead of this, as shown in FIG. 13, a first reverse-conducting prior to the formation of the mold layer 2, the at least one of at least a portion the second insulating material layer and the third insulating material layer of a first insulating material layer 6 and the other on the main surface on the inner wall of the through hole 3 upon formation of may be so as to cover the insulating material layer (FIG. 13 (b)) by doing so, opposite conductivity type layer is a post-process (diffusion layer), the inner wall of the through-hole 3 of the semiconductor substrate 1 it is possible to prevent the opposite conductivity type layer is formed on the 3 and the back side. 特に、CVD法や塗布法等を用いれば、絶縁材料層のみを、貫通孔3の内壁および半導体基板1の他主面側表面のみに形成することができるため好ましい。 In particular, the use of the CVD method or a coating method, or the like, only the insulating material layer, preferably possible to form only the inner wall and the other principal surface of the semiconductor substrate 1 of the through-hole 3.

さらにまた、他主面側には逆導電型領域を設けないことが望ましいが、図14に示されるように、貫通孔3の近傍に逆導電型領域(第3逆導電型領域)が形成されていてもよく、この場合、1つの貫通孔3の周囲に形成された第3逆導電型領域13の占める領域は第一電極4(他主面側電極4c)の占める領域よりも小さくなるよう形成すればよい。 Furthermore, the other main surface is desirably without the opposite conductivity type region, as shown in FIG. 14, opposite conductivity type region (third opposite conductivity type region) is formed in the vicinity of the through-hole 3 even well, in this case, one area occupied by the third opposite conductivity type region 13 formed around the through-hole 3 is to be smaller than the region occupied by the first electrode 4 (the other main surface side electrode 4c) it may be formed. 例えば、塗布法等用いて、一主面側および貫通孔3の内壁に、第一、第二逆導電型領域を形成した際に、他主面側の貫通孔3周囲にも第三逆導電型層13が形成された場合において、特に有効な構造形態となる。 For example, by using a coating method or the like, to the inner wall of the main surface side and the through-hole 3, first, when the formation of the second opposite conductivity type region, the third opposite conductivity to through-hole 3 around the other main surface in the case where the mold layer 13 is formed, a particularly effective structure forms. さらには、第二絶縁材料層7がガラスペースト等を塗布・焼成して形成することにより、第三逆導電型層のpn分離を同時に行ってもよく、そのままガラスから成る第二絶縁材料層7を残して、その上に第一電極4を形成すれば、工程を簡略化して形成することが可能となる。 Furthermore, the second insulating material layer 7 by forming by coating and baking a glass paste or the like, may be subjected to pn separation of the third opposite conductivity type layer at the same time, the second insulating material layer 7 as made of glass leaving, by forming the first electrode 4 thereon, it is possible to form a simplified process. さらには、高濃度ドープ層9を第三逆導電型層13の近傍まで設けた後に、ガラスペーストを高濃度ドープ層9と第三逆導電型層13との境界部分に塗布・焼成してpn分離を行ってもよい。 Further, after providing the highly doped layer 9 to the vicinity of the third opposite conductivity type layer 13, a glass paste is applied and baked as highly doped layer 9 at the boundary between the third opposite conductivity type layer 13 pn the separation may be carried out.

本発明の太陽電池素子の一実施形態を示す断面図である。 It is a cross-sectional view showing an embodiment of a solar cell element of the present invention. 本発明の太陽電池素子の一実施形態を示す正面図である。 Is a front view showing an embodiment of a solar cell element of the present invention. 本発明の太陽電池素子の一実施形態を示す背面図である。 Is a rear view showing an embodiment of a solar cell element of the present invention. 本発明の太陽電池モジュールの一実施形態を示す図であり、(a)は断面図、(b)は正面図である。 Is a diagram showing an embodiment of a solar cell module of the present invention, (a) is a sectional view, (b) is a front view. 本発明の太陽電池モジュールの他の実施形態を示す背面図であり、特に隣接する太陽電池素子同士の接続構造を示すものである。 It is a rear view showing another embodiment of a solar cell module of the present invention and, in particular, showing the connection structure between the solar cell element adjacent. 本発明の太陽電池モジュールの製造方法の一実施形態を示す断面図である。 It is a cross-sectional view illustrating an embodiment of a method for manufacturing a solar cell module of the present invention. 本発明の太陽電池素子の製造方法の変形例を示す断面図であり、特に絶縁材料層を形成した後で貫通孔を形成する工程を説明するものである。 Is a cross-sectional view showing a modified example of a method for manufacturing a solar cell device of the invention, it illustrates the step of forming the through hole, especially after forming the insulating material layer. 本発明の太陽電池素子の製造方法の変形例を示す断面図である。 A modification of the method of manufacturing the solar cell device of the present invention is a cross-sectional view illustrating. 本発明の太陽電池素子の製造方法の第一実施形態を示す断面図であり、特にファイアースルー法による高濃度ドープ層の形成工程を説明するものである。 Is a cross-sectional view showing a first embodiment of a method for manufacturing a solar battery cell of the present invention are those particularly illustrating the step of forming the heavily doped layer by fire-through method. 本発明の太陽電池素子の第一実施形態を示す断面図であり、特に出力取出電極を説明するものである。 It is a cross-sectional view showing a first embodiment of a solar cell element of the present invention and, in particular, illustrating the output extraction electrode. 本発明の太陽電池素子の製造方法の第二実施形態を示す断面図であり、特に(b)は、貫通孔が形成された(a)の半導体基板に第一逆導電型層を形成する工程を、(c)は、さらに少なくとも第二絶縁材料層となる絶縁材料層を形成する工程を説明するものである。 Is a cross-sectional view showing a second embodiment of a method for manufacturing a solar battery cell of the present invention, particularly (b) showing the step of forming a first opposite conductivity type layer on a semiconductor substrate of the through-holes are formed (a) the, (c) is a diagram for explaining a step of further forming at least a second insulating material layer to become an insulating material layer. 本発明の太陽電池素子の他の実施形態、特に第一電極の形状を説明する図であり、(a)は背面図、(b)は断面図である。 Other embodiments of the solar cell element of the present invention, is a view particularly illustrating the shape of the first electrode, (a) shows the rear view, (b) is a cross-sectional view. 本発明の太陽電池素子の製造方法の第二実施形態を示す断面図であり、特に貫通孔の内壁に第一絶縁材料層を形成する工程を説明するものである。 Is a cross-sectional view showing a second embodiment of a method for manufacturing a solar cell device of the invention, it illustrates the step of forming the first insulating material layer, especially on the inner wall of the through hole. 本発明の太陽電池素子のさらに他の実施形態を示す断面図である。 It is a sectional view showing still another embodiment of the solar cell element of the present invention. 従来のスルーホール型太陽電池素子を示す図であり、(a)は断面図、(b)は正面図、(c)は背面図である。 Is a diagram showing a conventional through-hole type solar cell element, (a) shows the cross sectional view, (b) is a front view, (c) is a rear view.

符号の説明 DESCRIPTION OF SYMBOLS

1 :半導体基板1a :凹凸構造2 :第一逆導電型層(拡散層) 1: semiconductor substrate 1a: uneven structure 2: first opposite conductivity type layer (diffusion layer)
3 :貫通孔4 :第一電極4a :一主面側電極4b :貫通孔電極4c :他主面側電極5 :第二電極5a :出力取出電極5b :集電電極6 :第一絶縁材料層(第二逆導電型層) 3: through-hole 4: the first electrode 4a: one principal surface electrode 4b: through-hole electrodes 4c: the other main surface side electrode 5: second electrode 5a: output extraction electrode 5b: collecting electrode 6: first insulating material layer (second opposite conductivity type layer)
7 :第二絶縁材料層8 :第三絶縁材料層9 :高濃度ドープ層10 :反射防止膜11 :第四絶縁材料層12 :第五絶縁材料層13 :第三逆導電型層20 :太陽電池素子21 :配線材22 :透明部材23 :裏面保護材24 :表側充填材25 :裏側充填材26 :出力取出配線27 :端子ボックス28 :枠30 :太陽電池モジュール31 :半導体基板31a:凹凸構造32 :逆導電型層34 :第一電極(一主面側電極) 7: the second insulating material layer 8: third insulating material layer 9: a highly doped layer 10: antireflective film 11: fourth insulating material layer 12: fifth dielectric material layer 13: third opposite conductivity type layer 20: Solar battery element 21: wiring member 22: transparent member 23: rear surface protective member 24: front side filler 25: back side filler 26: output extraction wiring 27: terminal box 28: frame 30: solar cell module 31: a semiconductor substrate 31a: irregular structure 32: the opposite conductivity type layer 34: first electrode (one principal surface electrode)
34a:出力取出電極34b:集電電極35 :第二電極(他主面側電極) 34a: output extraction electrode 34b: collector electrode 35: second electrode (the other main surface side electrode)
35a:出力取出電極35b:集電電極36 :高濃度ドープ層37 :反射防止膜41 :半導体基板42 :逆導電型層(拡散層) 35a: output extraction electrode 35b: collector electrode 36: a highly doped layer 37: antireflective film 41: Semiconductor substrate 42: the opposite conductivity type layer (diffusion layer)
42a:一主面側逆導電型層42b:貫通孔逆導電型層42c:他主面側逆導電型層43 :貫通孔44 :第一電極44a:一主面側電極(集電電極) 42a: one principal surface opposite conductivity type layer 42b: through hole opposite conductivity type layer 42c: the other principal surface side opposite conductivity type layer 43: through hole 44: first electrode 44a: one principal surface electrode (collector electrode)
44b:貫通孔電極44c:他主面側電極45 :第二電極 44b: through-hole electrode 44c: the other main surface side electrode 45: second electrode

Claims (13)

  1. 一導電型を示す半導体基板と、 A semiconductor substrate illustrating one conductivity type,
    前記半導体基板の一主面に形成され、前記一導電型と逆の導電型を示す第一逆導電型層と、 Said formed on one main surface of the semiconductor substrate, a first opposite conductivity type layer exhibiting the one conductivity type opposite conductivity type,
    前記半導体基板の一主面から他主面に至り、内壁が第二逆導電型層或いは第一絶縁材料層で覆われた複数の貫通孔と、 A plurality of through-hole through which the lead to the other main surface of one main surface of the semiconductor substrate, the inner wall is covered with the second opposite conductivity type layer or the first insulating material layer,
    前記一主面側から前記貫通孔内を介して前記他主面側に至るように形成され、前記第一逆導電型層と接続された第一電極と、 The formed from one principal surface so as to reach to the other main surface side through the through hole, a first electrode connected to the first opposite conductivity type layer,
    前記他主面上に形成され、前記第一電極と極性を異にする第二電極と、 Wherein formed on the other main surface, a second electrode having different the first electrode and the polarity,
    前記他主面と前記第一電極との間に介在された第二絶縁材料層と、を有してなる太陽電池素子。 The other main surface with a second insulating material layer, comprising a solar cell element which is interposed between the first electrode.
  2. 前記第二絶縁材料層は、酸素化合物或いは窒素化合物を主成分とすることを特徴とする請求項1に記載の太陽電池素子。 Said second insulating material layer, a solar cell element according to claim 1, characterized in that a main component oxygen compound or a nitrogen compound.
  3. 前記第二絶縁材料層は、水素を含有することを特徴とする請求項1又は2に記載の太陽電池素子。 Said second insulating material layer, a solar cell element according to claim 1 or 2, characterized in that it contains hydrogen.
  4. 前記他主面上で、前記第一電極と前記第二電極との間に介在された第三絶縁材料層、をさらに有することを特徴とする請求項1乃至3のいずれか一項に記載の太陽電池素子。 Wherein on the other main surface, according to any one of claims 1 to 3 third insulating material layer interposed, characterized in that it further comprises a to between the second electrode and the first electrode solar cell element.
  5. 前記他主面と前記第二電極との間に、前記一導電型を示す高濃度ドープ層が存在することを特徴とする請求項1乃至4のいずれか一項に記載の太陽電池素子。 It said other main surface and between the second electrode, the solar cell element according to any one of claims 1 to 4, characterized in that highly doped layer exhibiting the one conductivity type is present.
  6. 前記第二電極はアルミニウムを主成分とすることを特徴とする請求項5に載の太陽電池素子。 Said second electrode is a solar cell element mounting in claim 5, characterized in that the main component of aluminum.
  7. 前記第一電極は、前記一主面上に廻り込むように存在することを特徴とする請求項1乃至6に記載の太陽電池素子。 The first electrode, the solar cell element according to claims 1 to 6, characterized in that there so as to go around on the one main surface.
  8. 前記一主面は、幅及び高さが2μm以下であり、且つ、アスペクト比が0.1〜2を満たす多数の凸部を有することを特徴とする請求項1乃至7のいずれか一項に記載の太陽電池素子。 The one main surface, is not less 2μm or less width and height, and, in any one of claims 1 to 7 aspect ratio and having a plurality of protrusions to meet the 0.1-2 solar cell element described.
  9. 前記一主面のシート抵抗は60〜300Ω/□であることを特徴とする請求項1乃至8のいずれか一項に記載の太陽電池素子。 Solar cell element according to any one of claims 1 to 8, wherein the sheet resistance of the main surface is 60~300Ω / □.
  10. 請求項1乃至9のいずれか一項に記載の太陽電池素子を複数接続して成る太陽電池モジュールであって、 A solar cell module formed by connecting a plurality of solar cell elements according to any one of claims 1 to 9,
    一の太陽電池素子及び他の太陽電池素子は、それらの他主面に接合された配線材を用いて互いに接続されることを特徴とする太陽電池モジュール。 Solar cell module and being connected to each other using one the solar cell elements and other solar cell element, a wiring member that is joined to their other principal surface.
  11. 請求項1乃至9のいずれか一項に記載の太陽電池素子の製造方法であって、 A method of manufacturing a solar cell device according to any one of claims 1 to 9,
    前記他主面に、少なくとも前記第二絶縁材料層となる絶縁材料層を形成する工程と、 To the other main surface, and forming at least the the second insulating material layer insulating material layer,
    前記絶縁材料層が形成された前記半導体基板に、前記複数の貫通孔を形成する工程と、 The said semiconductor substrate having an insulating material layer is formed, and forming said plurality of through holes,
    前記貫通孔が形成された前記半導体基板のうち、前記絶縁材料層が被覆されていない領域の少なくとも一部を他の導電型に反転させる工程と、を有することを特徴とする太陽電池素子の製造方法。 The through hole of the semiconductor substrate which is formed, fabrication of the solar cell element in which the insulating material layer is characterized by having a, a step of inverting at least a portion to another conductivity type region which is not covered Method.
  12. 請求項1乃至9のいずれか一項に記載の太陽電池素子の製造方法であって、 A method of manufacturing a solar cell device according to any one of claims 1 to 9,
    前記半導体基板に前記複数の貫通孔を形成する工程と、 Forming a plurality of through-holes in the semiconductor substrate,
    前記貫通孔が形成された前記半導体基板のうち、所定領域を他の導電型に反転させる工程と、 Among the semiconductor substrate on which the through holes are formed, a step of inverting the predetermined region on the other conductivity type,
    前記所定領域を除く領域の少なくとも一部を、少なくとも前記第二絶縁材料層となる絶縁材料層で被覆する工程と、と有することを特徴とする太陽電池素子の製造方法。 Wherein at least a part of the area except for the predetermined region, at least the second a step of coating with an insulating material layer formed of an insulating material layer, and a manufacturing method of the solar cell element, characterized in that it comprises.
  13. 請求項10に記載の太陽電池モジュールの製造方法であって、 A method of manufacturing a solar cell module according to claim 10,
    前記太陽電池素子の一主面側を下方に向けて所定の基体上に載置し、上方から配線材を接触させる工程、を有することを特徴とする太陽電池モジュールの製造方法。 Wherein toward the one main surface side of the solar cell element downwardly and placed on a given substrate, a method for manufacturing a solar cell module characterized by having a step, of contacting the wiring member from above.
JP2006206107A 2006-07-28 2006-07-28 Solar cell element and a solar cell module using the same, and a method for their preparation Active JP5025184B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006206107A JP5025184B2 (en) 2006-07-28 2006-07-28 Solar cell element and a solar cell module using the same, and a method for their preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006206107A JP5025184B2 (en) 2006-07-28 2006-07-28 Solar cell element and a solar cell module using the same, and a method for their preparation

Publications (2)

Publication Number Publication Date
JP2008034609A true true JP2008034609A (en) 2008-02-14
JP5025184B2 JP5025184B2 (en) 2012-09-12

Family

ID=39123727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006206107A Active JP5025184B2 (en) 2006-07-28 2006-07-28 Solar cell element and a solar cell module using the same, and a method for their preparation

Country Status (1)

Country Link
JP (1) JP5025184B2 (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294080A (en) * 2007-05-22 2008-12-04 Sanyo Electric Co Ltd Solar cell and manufacturing method of same
JP2009177109A (en) * 2008-01-25 2009-08-06 Samsung Sdi Co Ltd Solar battery and method of manufacturing same
WO2009123149A1 (en) * 2008-03-31 2009-10-08 京セラ株式会社 Solar cell element and solar cell module
JP2009266848A (en) * 2008-04-21 2009-11-12 Sanyo Electric Co Ltd Solar cell module
JP2010010649A (en) * 2008-05-29 2010-01-14 Kyocera Corp Method of manufacturing solar cell module
EP2212920A2 (en) * 2008-08-01 2010-08-04 LG Electronics Inc. Solar cell, method of manufacturing the same, and solar cell module
JP2010171263A (en) * 2009-01-23 2010-08-05 Mitsubishi Electric Corp Method of manufacturing photovoltaic device
KR101032624B1 (en) 2009-06-22 2011-05-06 엘지전자 주식회사 Solar cell and mehtod for manufacturing the same
KR20110049669A (en) * 2009-11-03 2011-05-12 엘지전자 주식회사 Solar cell module
WO2011055946A3 (en) * 2009-11-03 2011-09-29 엘지이노텍주식회사 Solar cell and method for manufacturing same
JP2012070011A (en) * 2012-01-10 2012-04-05 Sharp Corp Solar cell module
JP2012070015A (en) * 2012-01-12 2012-04-05 Sanyo Electric Co Ltd Solar cell module
EP2443662A1 (en) * 2009-06-18 2012-04-25 LG Electronics Inc. Solar cell and method of manufacturing the same
WO2012053079A1 (en) * 2010-10-20 2012-04-26 三菱電機株式会社 Photovoltaic device and method for manufacturing same
JP2012094921A (en) * 2012-02-14 2012-05-17 Sanyo Electric Co Ltd Solar cell module
JP2012517112A (en) * 2009-02-18 2012-07-26 クアルコム,インコーポレイテッド Efficiency of the improved photovoltaic cells by using a through silicon via
WO2012156398A1 (en) 2011-05-17 2012-11-22 Schott Solar Ag Back-contact solar cell and method for producing such a back-contact solar cell
US8399760B2 (en) 2008-01-11 2013-03-19 Samsung Sdi Co., Ltd. Solar cell having improved electrode structure reducing shading loss
JP2013128095A (en) * 2011-12-16 2013-06-27 Lg Electronics Inc Solar cell and method for manufacturing the same
JP2013544037A (en) * 2011-05-27 2013-12-09 シーエスアイ セルズ カンパニー リミテッドCsi Cells Co., Ltd Method of manufacturing a back contact silicon solar cell
US8680392B2 (en) 2009-06-04 2014-03-25 Lg Electronics Inc. Solar cell and method of manufacturing the same
KR101437860B1 (en) * 2008-03-23 2014-09-12 주식회사 뉴파워 프라즈마 Solar cell device porous antireflection layer and method of manufacture
US9153713B2 (en) 2011-04-02 2015-10-06 Csi Cells Co., Ltd Solar cell modules and methods of manufacturing the same
US9209342B2 (en) 2011-05-27 2015-12-08 Csi Cells Co., Ltd Methods of manufacturing light to current converter devices
US9490375B2 (en) 2011-04-04 2016-11-08 Mitsubishi Electric Corporation Solar cell and method for manufacturing the same, and solar cell module
GB2551108A (en) * 2016-05-06 2017-12-13 Teledyne E2V (Uk) Ltd Image sensor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0251282A (en) * 1988-08-12 1990-02-21 Sharp Corp Photoelectric conversion device
JPH04107881A (en) * 1990-08-28 1992-04-09 Kyocera Corp Solar cell element
JPH04223378A (en) * 1990-12-25 1992-08-13 Sharp Corp Solar cell
JPH05299673A (en) * 1992-04-24 1993-11-12 Kyocera Corp Solar battery element
JP2001135834A (en) * 1999-11-08 2001-05-18 Sharp Corp Photoelectric conversion element and manufacturing method thereof
JP2003197940A (en) * 2001-12-25 2003-07-11 Kyocera Corp Method for roughing substrate for solar battery

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0251282A (en) * 1988-08-12 1990-02-21 Sharp Corp Photoelectric conversion device
JPH04107881A (en) * 1990-08-28 1992-04-09 Kyocera Corp Solar cell element
JPH04223378A (en) * 1990-12-25 1992-08-13 Sharp Corp Solar cell
JPH05299673A (en) * 1992-04-24 1993-11-12 Kyocera Corp Solar battery element
JP2001135834A (en) * 1999-11-08 2001-05-18 Sharp Corp Photoelectric conversion element and manufacturing method thereof
JP2003197940A (en) * 2001-12-25 2003-07-11 Kyocera Corp Method for roughing substrate for solar battery

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008294080A (en) * 2007-05-22 2008-12-04 Sanyo Electric Co Ltd Solar cell and manufacturing method of same
US8399760B2 (en) 2008-01-11 2013-03-19 Samsung Sdi Co., Ltd. Solar cell having improved electrode structure reducing shading loss
JP2009177109A (en) * 2008-01-25 2009-08-06 Samsung Sdi Co Ltd Solar battery and method of manufacturing same
KR101437860B1 (en) * 2008-03-23 2014-09-12 주식회사 뉴파워 프라즈마 Solar cell device porous antireflection layer and method of manufacture
WO2009123149A1 (en) * 2008-03-31 2009-10-08 京セラ株式会社 Solar cell element and solar cell module
JP5149376B2 (en) * 2008-03-31 2013-02-20 京セラ株式会社 Solar cell element and the solar cell module
US9209332B2 (en) 2008-03-31 2015-12-08 Kyocera Corporation Solar cell element and solar cell module
JP2013042185A (en) * 2008-03-31 2013-02-28 Kyocera Corp Solar cell element and solar cell module
JP2009266848A (en) * 2008-04-21 2009-11-12 Sanyo Electric Co Ltd Solar cell module
JP2010010649A (en) * 2008-05-29 2010-01-14 Kyocera Corp Method of manufacturing solar cell module
EP2212920A2 (en) * 2008-08-01 2010-08-04 LG Electronics Inc. Solar cell, method of manufacturing the same, and solar cell module
EP2212920A4 (en) * 2008-08-01 2013-09-18 Lg Electronics Inc Solar cell, method of manufacturing the same, and solar cell module
KR100997113B1 (en) * 2008-08-01 2010-11-30 엘지전자 주식회사 Solar Cell and Method for Manufacturing thereof
JP2010171263A (en) * 2009-01-23 2010-08-05 Mitsubishi Electric Corp Method of manufacturing photovoltaic device
JP2014082528A (en) * 2009-02-18 2014-05-08 Qualcomm Inc Photovoltaic cell efficiency improved using through silicon vias
JP2016026413A (en) * 2009-02-18 2016-02-12 クアルコム,インコーポレイテッド Photovoltaic cell and method of manufacturing the same
JP2012517112A (en) * 2009-02-18 2012-07-26 クアルコム,インコーポレイテッド Efficiency of the improved photovoltaic cells by using a through silicon via
US8680392B2 (en) 2009-06-04 2014-03-25 Lg Electronics Inc. Solar cell and method of manufacturing the same
EP2443662A1 (en) * 2009-06-18 2012-04-25 LG Electronics Inc. Solar cell and method of manufacturing the same
EP2443662A4 (en) * 2009-06-18 2013-01-02 Lg Electronics Inc Solar cell and method of manufacturing the same
US9306084B2 (en) 2009-06-18 2016-04-05 Lg Electronics Inc. Solar cell and method of manufacturing the same
US8507789B2 (en) 2009-06-22 2013-08-13 Lg Electronics Inc. Solar cell and method of manufacturing the same
US8481847B2 (en) 2009-06-22 2013-07-09 Lg Electronics Inc. Solar cell and method of manufacturing the same
KR101032624B1 (en) 2009-06-22 2011-05-06 엘지전자 주식회사 Solar cell and mehtod for manufacturing the same
US8203072B2 (en) 2009-06-22 2012-06-19 Lg Electronics Inc. Solar cell and method of manufacturing the same
WO2011055946A3 (en) * 2009-11-03 2011-09-29 엘지이노텍주식회사 Solar cell and method for manufacturing same
CN102598302A (en) * 2009-11-03 2012-07-18 Lg伊诺特有限公司 Solar cell and method for manufacturing same
KR20110049669A (en) * 2009-11-03 2011-05-12 엘지전자 주식회사 Solar cell module
KR101708243B1 (en) 2009-11-03 2017-02-20 엘지전자 주식회사 Solar cell module
WO2012053079A1 (en) * 2010-10-20 2012-04-26 三菱電機株式会社 Photovoltaic device and method for manufacturing same
US9153713B2 (en) 2011-04-02 2015-10-06 Csi Cells Co., Ltd Solar cell modules and methods of manufacturing the same
US9490375B2 (en) 2011-04-04 2016-11-08 Mitsubishi Electric Corporation Solar cell and method for manufacturing the same, and solar cell module
DE102011051511A1 (en) * 2011-05-17 2012-11-22 Schott Solar Ag Back-contact solar cell and method of manufacturing such a
WO2012156398A1 (en) 2011-05-17 2012-11-22 Schott Solar Ag Back-contact solar cell and method for producing such a back-contact solar cell
US9209342B2 (en) 2011-05-27 2015-12-08 Csi Cells Co., Ltd Methods of manufacturing light to current converter devices
JP2013544037A (en) * 2011-05-27 2013-12-09 シーエスアイ セルズ カンパニー リミテッドCsi Cells Co., Ltd Method of manufacturing a back contact silicon solar cell
US9281435B2 (en) 2011-05-27 2016-03-08 Csi Cells Co., Ltd Light to current converter devices and methods of manufacturing the same
US9634160B2 (en) 2011-12-16 2017-04-25 Lg Electronics Inc. Solar cell and method for manufacturing the same
JP2013128095A (en) * 2011-12-16 2013-06-27 Lg Electronics Inc Solar cell and method for manufacturing the same
JP2012070011A (en) * 2012-01-10 2012-04-05 Sharp Corp Solar cell module
JP2012070015A (en) * 2012-01-12 2012-04-05 Sanyo Electric Co Ltd Solar cell module
JP2012094921A (en) * 2012-02-14 2012-05-17 Sanyo Electric Co Ltd Solar cell module
GB2551108A (en) * 2016-05-06 2017-12-13 Teledyne E2V (Uk) Ltd Image sensor

Also Published As

Publication number Publication date Type
JP5025184B2 (en) 2012-09-12 grant

Similar Documents

Publication Publication Date Title
US20070209697A1 (en) Solar Cell And Manufacturing Method Therefor
US20100243040A1 (en) Solar cell and fabrication method thereof
US20070137692A1 (en) Back-Contact Photovoltaic Cells
US20060130891A1 (en) Back-contact photovoltaic cells
US20090139570A1 (en) Solar cell and a manufacturing method of the solar cell
WO2009096539A1 (en) Solar battery element and solar battery element manufacturing method
US20110139243A1 (en) Solar cell and method for manufacturing the same
US20070295399A1 (en) Back-Contact Photovoltaic Cells
US20110140226A1 (en) Semiconductor devices and methods for manufacturing the same
US20090272419A1 (en) Solar Cell Module
JP2005310830A (en) Solar cell and manufacturing method thereof
JP2005123447A (en) Solar battery and method for manufacturing the same
JP2007281044A (en) Solar battery
US20110100459A1 (en) Solar cell and method for manufacturing the same
JP2006120945A (en) Solar cell and solar cell module
JP2008529265A (en) Semiconductor device having a heterojunction and inter finger structure to
US20100275987A1 (en) Solar Cell and Solar Cell Manufacturing Method
JP2006073617A (en) Solar cell and manufacturing method thereof
JP2005038907A (en) Integrated photoelectric converter
JP2009295715A (en) Photoelectric conversion device and method of manufacturing the same
JP2009152222A (en) Manufacturing method of solar cell element
JP2004064028A (en) Solar cell and method of manufacturing the same
JP2008270743A (en) Solar cell module
JP2007281023A (en) Conductive paste for solar cell element and method of manufacturing solar cell element using the same
JP2010186900A (en) Solar cell and method of manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090120

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101124

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120110

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120302

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120522

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120619

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150629

Year of fee payment: 3

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150