200847360 九、發明說明： [發明所屬之技術領域】 本發明大致係有關於電路元件(circuit components)之封裝(package)， 特別是有關於一種適於自動化大量生產，具良好散熱性能並適於大功率用 途之無導接腳平片型封裝(Leadless Flat Package)。 [先前技術】 諸如二極體(diode> 電晶體(transistor》電阻(resistor)與電容(capacitor) ， 等的主動及被動式電路元件(active and passive circuit components)，乃是 廣泛應用於電子電路中之電路元件。不論是小信號(signal)或功率(power) 用途的，線性(linear)或數位(digital)性質的電路，皆需應用到此些不同性質 的離散式電路元件。除了整合於積體電路之中的二極體，電阻與電容之外， 離散元件(discrete component)形式的二極體，電阻與電容元件，是為使用 量極大的電子零件。 離散式電路元件有多種型式的包裝(packaging)，常見者諸如導線型包 裝(leaded package)。基於小型化的需求，表面黏著技術(SMT, surf ace-mount technology)型式之離散式兀件，已逐漸變成微型化電子裝 置所需採用的電路元件，故以低成本進行高速率的大量生產，乃是此類離 散式電路元件之製造所必須採行的方向。 不過，習知技術之SMT型式離散式電路元件之製作過程步驟繁複，且 元件結構相形不利於散熱，且無法製作小至0402以下之尺寸。例如，發明 專利1223580號案之「具有製程階段盲孔之電路元件及其製作方法」，其所 揭示之製程步驟包含了製作盲孔，暫時性地充填盲孔，其後再清除盲孔等 相對較為繁複的過程步驟。 此外，該離散式元件之整批製作過程完畢後，其個別元件切割分離的處 5 200847360 %· 理牽涉到貫通孔/盲孔的切割。此種對導電層的切割易於對元件的整體結構 形成不利的破壞性應力，其結果為整體製程良率的降低。並且，切割時之 應力亦會不利地影響元件晶粒之熱傳導散出之能力。 [發明内容] 因此，本發明之目的即在於提供一種離散式電路元件之結構及其相關製 作方法，其可以簡化製作過程，降低製造成本。 本發明之另一目的係在於提供一種離散式電路元件之結構及其相關製 作方法，其具有堅固構形，易於獲得高製程良率。 f 本發明之又一目的係在於提供一種離散式電路元件之結構及其相關製 作方法，其具有良好晶粒散熱能力。 本發明之再一目的係在於提供一種離散式電路元件之結構及其相關製 作方法，其可適合於極小尺寸之元件封裝。 為達前述目的，本發明提供一種離散式電路元件，其包含有一基板，其 第一表面上形成有電性互相獨立之一第一導電段及一第二導電段，且其第 二表面上形成有電性互相獨立之對應一第一導電段及一第二導電段。另有 一第一鍍覆貫通孔，將基板第一表面之第一導電段電性地與第二表面之對 應第一導電段電性連結，以及一第二鍍覆貫通孔，其將基板第一表面之第 ^ 二導電段電性地與第二表面之對應第二導電段電性連結。定置在該第一表 面第二導電段上之一元件晶粒，其一第一電極係直接電性地連結至基板第 一表面第二導電段，且其一第二電極則電性地連結至第一表面第一導電 段。電性絕緣物質水氣密地完全包覆基板第一表面上之元件晶粒及其第一 及第二導電線路。 [實施方式] 圖1顯示用於製作本發明無導接腳平片型封裝較佳實施例電路元件之 基板晶粒面之立體圖。如圖所示，用以承載整個矩陣排列的，典型多達數 6 200847360 百個離散式電路元件的基板ιοα其晶粒面u〇之表面上有多個離散式電路 元件之初始導電線路111A，112A，112B，···及116A，116B等，係排列於， 例如圖中所顯示的，一個二維正交的矩陣之中。基板100本身在此製程早 期階段，亦係被使用作為本發明整批製作，數量眾多的電路元件之基礎承 載片板用途。 相對於圖1之晶粒面的初始導電線路，基板10〇在其圖1的晶粒面110 之反對表面亦即元件之銲接面亦有一個由多個初始導電線路211 21之… 及214等，排列於一個對應的矩陣之中。圖2係為圖1基板之銲接面之立 體圖，其表面上亦有多個離散式電路元件之初始導電線路211A，211B， 212A，212B···與216A，216B排列於矩陣之中。圖2之基板銲接面210係 為圖1之基板晶粒面110水平翻轉所顯示之銲接面導電線路矩陣排列圖形 在每一個離散元件的初始導電線路之中(包含晶粒面及銲接面)，在大致 位於該組導電線路的兩端位置，各皆形成有一貫通孔，實質上垂直貫穿基 板100的整個厚度。例如，圖1及2中的導電線路111A，111B及對應的 211Λ 211B之中，貫穿有一組貫通孔131A，131B，在導電線路113A，113B 及對應的213A，213B之中則貫穿有一貫通孔133A，133B。 圖3顯示典型雙面電路基板鍍覆貫通孔之橫截面圖，其顯不基板1〇〇晶 粒面110及銲接面210上之對應初始導電線路112B，212B之構形細節，而 圖4則為圖1及2之基板之橫截面圖。圖1及2之中，每一個以虛線所圍 繞之大致矩形之區域，如同後面所將說明的，係代表一個離散電路元件之 實體範圍。例如圖1所示，虛線122所標示的範圍係為本發明一個完整離 散式電路元件的實體範圍，其中，於範圍122内大致中心之處，如虛線區 域152所標示的位置，係為元件晶粒所將定置之位置。 注意到如圖1之立體圖中所顯示的，導電線路在基板1〇〇晶粒面Π0上 沿長軸方向(圖中之大略水平方向)之對稱圖形。依據本發明離散式電路元件 7 200847360 之一較佳實施例，其導電線路於圖1中所顯示一個別元件之元件個體腳印 (component footprint)範圍 122 内，沿其短軸方向(圖中之大略垂直方向)， 導電線路112B實質上係呈現大致不對稱的圖形。導電線路Π2Α與112B 實質上係屬互相電性獨立之兩導電圖形。導電線路112A與112B兩者互不 接觸，保持電性互相獨立的開路狀態。 在圖1所顯示之實施例之中，左側之導電線路112B係為向元件中心152 延伸較多的導電線路。不過，如同習於本技藝者所可以理解的，若安排左 側的導電線路延伸到達元件中心，亦同樣是可行的作法。 圖4之橫截面圖顯示，各貫通孔係為鍍覆貫通孔(PTH, Plated Through-Hole)。貫通孔131A及132B係利用包含諸如濺鈹(sputtering), 電鍍(electroplating)等製作印刷電路基板的技術，在透通的孔壁上形成導電 金屬層。貫通孔壁上的此鍍覆金屬層便可以將基板100的晶粒面與相對反 面的銲接面上的導電線路互相電性地連接結起來。 圖1與2所顯示之基板，係作為本發明離散式電路元件之基礎。此基板 係為電性絕緣之板材，其可以是，例如玻璃纖維強化樹酯(FRP)，或者是利 用模鑄(molding)等技術，使用適當之絕緣性質材料製作成板材。其後可利 用諸如微影蝕刻技術(photolithography)而製作晶粒面及錫接面上之導電 線路。 貫通孔可利用數働卩工機具(NC tools)，在定位上鑽孔貫通。其後，如 同前述，可利用濺鍍與/或電鍍等製程而形成鈹覆貫通孔。鑪覆貫通孔形成 後，即可獲得圖1及2所顯示之基板1〇〇。 接著，如圖5所示，於一較佳實施例之中，鍍覆貫通孔132A，132B内 即可埋入塞孔之填充材料。鍍覆貫通孔中所填入者可以是具良好導電性質 的永久性材料。如同習於本技藝者所可以理解的，適用的材質包含有，例 如’導電膠，錫嘗或錫球等，此等填充材料經過製程處理之後可以完全而 8 200847360 * 緊密地塞滿整個PTH。之後，其鍍覆貫通孔132A，132B已被填滿之銲接 面導電線路212A及212B便可進行一次諸如電鍍的程序，以將原貫通孔的 開孔完全覆蓋。圖5所示之例中，晶粒面上110貫通孔132A，132B的開孔 亦完全被覆蓋。 或者，依另一較佳之作法，如圖6所示，貫通孔製作過程之中的内壁鍍 覆處理可以持續進行至整個貫通孔被鍍覆物質所填滿時為止。 圖5及6中所顯示的基板100,其鍍覆貫通孔内已填充有埋孔材料並已 被以導電性物質加以覆蓋。利用此基板，如圖7所示，接著便可以將離散 式電路元件之晶粒定置於定位上，如圖1所示之定位152。圖7之橫截面圖 顯示一離散式電路元件之晶粒712被定置於基板100之晶粒面110上。元 件晶粒712之一電極，並且與基板100上之晶粒面之導電線路112B電性地 連結。 晶粒712與導電線路112B之電性接合可以利用，例如，以電氣爐加熱， 使預先形成於晶粒712下表面或導電線路152位置上之銲錫熔化，冷卻後 將晶粒712銲著於導電線路112B之152定位上。 當電路元件晶粒712下表面之電極與晶粒面上之導電線路112B上達成 穩固電性接合之後，晶粒712另一端，亦即，頂端上之另一電極，便可以 % 利用諸如跳接線732而與基板100晶粒面110上的另一導電線路112A，透 過導線而電性地接合。 當完成圖7所顯示之構造倦各元件晶粒之電極便已電性地連結到其各 自基板範圍(圖中以虛線所標示出來之元件範圍)内的對應軟銲接觸端子 上。此時，電性結構已建構完成，但仍排列於矩陣中之各個離散式電路元 件，便可以進行水氣密封(hermetic seal)的處理。圖8之橫截面圖即顯示圖 7之離散式電路元件晶粒被水密性材料800包覆的情形。此種密封包覆可 以，例如，利用模鑄的方式進行。只需利用模具在基板100的晶粒面110 9 200847360 鋤 上方形成一個高度適恰之空間，便可以利用，例如，將熔融(軟化)之水氣密 封材質注入該空間内，而可以方便而容易地製成水氣密封裝8〇〇。此可將晶 粒712等保護於其中。注意到，水氣密絕緣材質800之選定，亦可為與基 板100本身所使用者完全相同之物質。 之後，圖9之橫截面圖顯示，圖8之基板構造可沿圖中箭頭指示位置進 行切割而被切成分離之離散式電路元件。圖9所顯示依據本發明之較佳實 施例，其兩電極皆可具有一個面積夠大，且高度顯著高於基板上之初始導 電線路厚度的一個導電接面，即導電接面212C及212D。在本發明各個離 散式電路元件於印刷電路板上進行軟銲時，此導電接面可以確保良好的軟 銲品質，並可於電路元件於印刷電路板上進行組裝的軟銲程序時，利用熔 融銲錫的表面張力而有助於元件的精確定位。 本發明離散式電路元件，雖然使用一片形成有貫通孔之基板作為建構整 個矩陣的多個元件之基礎，但在其製程的初期，此些貫通孔便被埋實。因 此，在每一個元件之指定形成範圍之中，由於不需要再預留後續鑽孔處理 的空間，因此，整個元件之範圍便可以充份運用來承載元件晶粒。換句話 說，元件在基板上所必須佔用的最小空間便可以盡可能地縮小。此種特點 極為適合於製作微小型的元件，諸如0603, 0402,甚至更小規格的元件。 相較之下，習知技術之中由於必須保留鑽孔的安全空間，故其元件尺寸便 無法如同本發明所揭示之離散式電路元件一樣地縮到最小。 此外，由於本發明離散式電路元件之整體構造容許晶粒至其承載基板的 導電端之間的最短路線，故其不但電阻低，其導熱性亦佳，可適用於功率 離散式電路元件之用途。若應用於小訊號元件之用途，則其良好電性亦可 適於高頻之需求。 雖然前面的說明文字已是本發明特定實施例的一個完整的說明，但其各 種的修改變化，變動的構造及等效者的應用仍是可能的。例如，雖然前述 實施例之詳細說明中只廣泛地以離散式電路元件來說明本發明，但如同習 200847360 於本技藝之士所可以理解者，SMT型式之下，EIA標準晶片的各種尺寸的 離散式—^極體，諸如Zener，Schottky等，或者離散式電容，無論是有否 極性，或者離散式電阻，甚至是主動或積體電路本質，不論是需使用二電 性接頭或多於二電性接頭的電路元件，皆是可以適用於本發明所揭示之製 作方法。此外，本發明不但適用於常見的1210, 1206，以及0805等SMT 型EIA標準晶片尺寸，其更係特別適於更為小型的SMT型離散式電路元 件。再例如，說明中基板之晶粒面上之該些導電線路可為固化之膏狀銀膠， 固化之膏狀銅膠，或固化之膏狀銅合金膠。又例如，該板之銲接面上之該 些導電線路上更可覆有一鎳層與或一金層。 因此，前面的描述說明即不應被拿來限定本發明，而其範疇應以後附之 申請專利範圍乙節文字內容來加以界定。 [圖式簡單說明】 圖1顯示用於製作本發明無導接腳平片型封裝較佳實施例電路元件之 基板晶粒面之立體圖。 圖2係為圖1基板之銲接面之立體圖。 圖3顯示典型雙面電路基板鈹覆貫通孔之橫截面圖。 圖4之橫截面圖顯示本發明無接腳電路元件封裝所使用初始基板之橫 截面圖。 圖5之橫截面圖顯示圖3元件基板之貫通孔内先以填充膠塞滿後再行鍍 銅以將貫通孔兩端完全封閉。 圖6之橫截面圖顯示圖3元件基板之貫通孔内利用鍍銅處理而將貫通孔 完全填滿。 圖7之橫截面圖顯示一離散式電路元件被定置於基板之晶粒面上，並形 成元件電極之電性連結。 圖8之橫截面圖顯示圖7之離散式電路元件被水氣密性材料包覆。 200847360 > 圖9之橫截面圖顯示圖8之基板構造被切割成分離之離散式電路元件。 [主要元件符號說明】 100 基板 122 元件範圍 112A, 112B 晶粒面導電線路 132A, 132B 鍍覆貫通孔 212A, 212B 銲接面導電線路 800 水密性密封材料 212C, 212D 導電接面 12200847360 IX. Description of the Invention: [Technical Field of the Invention] The present invention generally relates to a package of circuit components, and more particularly to a method suitable for automated mass production, good heat dissipation performance and suitable for large Leadless Flat Package for power applications. [Prior Art] Active and passive circuit components such as diodes (resistors) and capacitors are widely used in electronic circuits. Circuit components. Whether for small signal or power applications, linear or digital circuits need to be applied to discrete circuit components of different natures. In addition to the diodes in the circuit, resistors and capacitors, diodes in the form of discrete components, resistors and capacitors are electronic components that are extremely useful. Discrete circuit components are available in a variety of packages ( Packaging), commonly used in leaded packages. Based on the demand for miniaturization, discrete components of the surface mount technology (SMT, surf ace-mount technology) have gradually become the required for miniaturized electronic devices. Circuit components, so high-speed mass production at low cost is the direction that must be taken in the manufacture of such discrete circuit components. The SMT type discrete circuit component of the prior art has complicated manufacturing steps, and the component structure is not favorable for heat dissipation, and cannot be made to a size as small as 0402 or less. For example, the invention patent No. 1223580 "has a blind hole in the process stage". The circuit component and the method of fabricating the same, the process steps disclosed therein include a relatively complicated process step of making a blind via, temporarily filling a blind via, and then clearing the blind via. Further, the batch of the discrete component After the production process is completed, the individual components are cut and separated. 5 200847360 %· The cutting of the through holes/blind holes is involved. This cutting of the conductive layer tends to form unfavorable destructive stress on the overall structure of the component. The overall process yield is reduced. Moreover, the stress during cutting may adversely affect the ability of the element die to thermally dissipate. [Invention] Accordingly, it is an object of the present invention to provide a structure of a discrete circuit component and Related manufacturing method, which can simplify the manufacturing process and reduce the manufacturing cost. Another object of the present invention is to provide a The structure of the discrete circuit component and its related fabrication method have a solid configuration and are easy to obtain high process yield. f. Another object of the present invention is to provide a structure of a discrete circuit component and a related manufacturing method thereof, which have Good grain heat dissipation capability. A further object of the present invention is to provide a structure of a discrete circuit component and a related fabrication method thereof, which can be adapted to a very small component package. To achieve the foregoing object, the present invention provides a discrete circuit. An element includes a substrate having a first conductive segment and a second conductive segment electrically independent from each other on a first surface thereof, and a first conductive segment corresponding to each other electrically formed on the second surface And a second conductive segment. a first plated through hole electrically connecting the first conductive segment of the first surface of the substrate to the corresponding first conductive segment of the second surface, and a second plated through hole for the first substrate The second conductive segment of the surface is electrically coupled to the corresponding second conductive segment of the second surface. One element die disposed on the second conductive segment of the first surface, a first electrode is directly electrically coupled to the second conductive segment of the first surface of the substrate, and a second electrode thereof is electrically coupled to The first surface is a first conductive segment. The electrically insulating substance water-tightly completely covers the element crystal grains on the first surface of the substrate and the first and second conductive lines thereof. [Embodiment] Fig. 1 is a perspective view showing a substrate grain surface of a circuit element for fabricating a preferred embodiment of the leadless chip type package of the present invention. As shown in the figure, the substrate ιοα, which is used to carry the entire matrix arrangement, typically has a plurality of 200847360 hundred discrete circuit components, and has a plurality of discrete conductive circuit elements 111A on the surface of the die face u〇, 112A, 112B, ... and 116A, 116B, etc. are arranged, for example, in a two-dimensional orthogonal matrix as shown in the figure. The substrate 100 itself is also used in the early stages of the process as a whole batch of the present invention, and a large number of circuit components are used for the substrate. With respect to the initial conductive path of the die face of FIG. 1, the opposing surface of the die face 110 of FIG. 1 or the soldered surface of the component also has a plurality of initial conductive traces 211 21 and 214, etc. , arranged in a corresponding matrix. 2 is a perspective view of the soldered surface of the substrate of FIG. 1, and the initial conductive traces 211A, 211B, 212A, 212B, ..., and 216A, 216B of the plurality of discrete circuit components are also arranged in the matrix. The substrate soldering surface 210 of FIG. 2 is formed by horizontally flipping the substrate die surface 110 of FIG. 1 and displaying a pattern of the soldering surface conductive line matrix in the initial conductive line of each discrete component (including the die face and the soldering face). Each of the two ends of the conductive line is formed with a through hole substantially perpendicular to the entire thickness of the substrate 100. For example, among the conductive lines 111A, 111B and the corresponding 211 Λ 211B in FIGS. 1 and 2, a plurality of through holes 131A, 131B are inserted through the through holes 133A through the conductive lines 113A, 113B and the corresponding 213A, 213B. , 133B. 3 is a cross-sectional view showing a plated through hole of a typical double-sided circuit substrate, which shows the configuration details of the corresponding initial conductive lines 112B, 212B on the substrate 1 and the solder surface 210, and FIG. 4 Is a cross-sectional view of the substrate of Figures 1 and 2. In Figures 1 and 2, each of the substantially rectangular regions surrounded by dashed lines, as will be described later, represents the physical extent of a discrete circuit component. For example, as shown in FIG. 1, the range indicated by the dashed line 122 is the physical range of a complete discrete circuit component of the present invention, wherein the substantially central portion of the range 122, such as the position indicated by the dashed line region 152, is a component crystal. The position where the grain will be placed. Note that as shown in the perspective view of Fig. 1, the conductive line has a symmetrical pattern in the long axis direction (slightly horizontal direction in the figure) on the substrate 1 〇〇 grain surface Π0. According to a preferred embodiment of the discrete circuit component 7 200847360 of the present invention, the conductive traces are within the component footprint range 122 of a particular component shown in Figure 1, along the minor axis direction (large in the figure) In the vertical direction, the conductive traces 112B are substantially in a substantially asymmetrical pattern. The conductive lines Π2Α and 112B are substantially two electrically conductive patterns that are electrically independent of each other. The conductive lines 112A and 112B are not in contact with each other, and maintain an open state in which the electrical properties are independent of each other. In the embodiment shown in FIG. 1, the conductive line 112B on the left side is a conductive line that extends more toward the center 152 of the element. However, as will be understood by those skilled in the art, it is also feasible to arrange the conductive line on the left side to extend to the center of the element. 4 is a cross-sectional view showing that each through hole is a plated through-hole (PTH). The through holes 131A and 132B form a conductive metal layer on the through hole walls by a technique of manufacturing a printed circuit board including, for example, sputtering, electroplating, or the like. The plated metal layer on the wall of the through hole can electrically connect the die face of the substrate 100 to the conductive trace on the opposite face of the soldered surface. The substrate shown in Figures 1 and 2 serves as the basis for the discrete circuit elements of the present invention. The substrate is an electrically insulating sheet which may be, for example, glass fiber reinforced resin (FRP) or formed into a sheet material using a suitable insulating material using techniques such as molding. Conductive lines on the die face and the tin junction can then be fabricated using, for example, photolithography. Through-holes can be drilled through the positioning using a number of tools (NC tools). Thereafter, as described above, the through-holes can be formed by a process such as sputtering and/or plating. After the furnace through-holes are formed, the substrate 1 shown in Figs. 1 and 2 can be obtained. Next, as shown in Fig. 5, in a preferred embodiment, the filling material of the plug holes can be buried in the through-holes 132A, 132B. The person to be filled in the plated through hole may be a permanent material having good electrical conductivity. As will be appreciated by those skilled in the art, suitable materials include, for example, 'conductive paste, tin tart or solder ball, etc., which can be completely processed after processing. 8 200847360 * Tightly fills the entire PTH. Thereafter, the soldering surface conductive lines 212A and 212B whose plated through holes 132A, 132B have been filled can be subjected to a procedure such as plating to completely cover the opening of the original through hole. In the example shown in Fig. 5, the openings of the through-holes 132A, 132B on the die face 110 are completely covered. Alternatively, according to another preferred embodiment, as shown in Fig. 6, the inner wall plating treatment in the through hole manufacturing process can be continued until the entire through hole is filled with the plating material. The substrate 100 shown in Figs. 5 and 6 has a buried via hole filled in the through hole and has been covered with a conductive material. Using this substrate, as shown in Figure 7, the die of the discrete circuit components can then be placed in position, as shown in Figure 1 of position 152. The cross-sectional view of Figure 7 shows that the die 712 of a discrete circuit component is positioned on the die face 110 of the substrate 100. One of the elements 712 is electrically connected to the conductive line 112B of the die face on the substrate 100. The electrical bonding of the die 712 and the conductive trace 112B can be utilized, for example, by heating in an electric furnace to melt the solder previously formed on the lower surface of the die 712 or the position of the conductive trace 152. After cooling, the die 712 is soldered to the conductive. The 152 of line 112B is positioned. After the electrodes on the lower surface of the circuit element die 712 are firmly electrically bonded to the conductive lines 112B on the die face, the other end of the die 712, that is, the other electrode on the top end, can be utilized, such as a patch cord. 732 is electrically coupled to another conductive line 112A on the die face 110 of the substrate 100 through the wires. When the electrodes of the structural elements of the structural elements shown in Fig. 7 are completed, they are electrically connected to corresponding soldering contact terminals in their respective substrate ranges (the range of elements indicated by broken lines in the figure). At this time, the electrical structure has been constructed, but the discrete circuit elements still arranged in the matrix can be processed by a hermetic seal. The cross-sectional view of Fig. 8 shows the case where the discrete circuit element dies of Fig. 7 are covered by the watertight material 800. Such a sealing coating can be carried out, for example, by die casting. It is only necessary to use a mold to form a space of a suitable height above the grain surface 110 9 200847360 of the substrate 100, so that, for example, a molten (softened) water-sealing material can be injected into the space, which is convenient and easy. Made of water and gas sealed 8 〇〇. This protects the crystal grains 712 and the like therein. It is noted that the water-tight insulating material 800 may be selected to be exactly the same as the user of the substrate 100 itself. Thereafter, the cross-sectional view of Fig. 9 shows that the substrate structure of Fig. 8 can be cut into discrete discrete circuit components by cutting along the positions indicated by the arrows in the figure. In accordance with a preferred embodiment of the present invention, both electrodes may have a conductive junction, i.e., conductive junctions 212C and 212D, having a sufficiently large area and a significantly higher height than the initial conductive line thickness on the substrate. When the discrete circuit components of the present invention are soldered on a printed circuit board, the conductive joints can ensure good soldering quality, and can be melted when the circuit components are soldered on the printed circuit board. The surface tension of the solder contributes to the precise positioning of the components. In the discrete circuit element of the present invention, a substrate having through holes is used as a basis for constructing a plurality of elements of the entire matrix, but at the beginning of the process, the through holes are buried. Therefore, in the specified formation range of each component, since the space for subsequent drilling processing is not required to be reserved, the entire component range can be fully utilized to carry the component die. In other words, the minimum space that the component must occupy on the substrate can be reduced as much as possible. This feature is ideal for making tiny components such as 0603, 0402, or even smaller components. In contrast, in the prior art, since the safe space of the drilled hole must be retained, the component size cannot be minimized as the discrete circuit component disclosed in the present invention. In addition, since the overall structure of the discrete circuit component of the present invention allows the shortest trace between the die and the conductive end of the carrier substrate, it has low resistance and good thermal conductivity, and is suitable for use in power discrete circuit components. . If applied to small signal components, its good electrical properties can also be adapted to high frequency requirements. While the foregoing description is a complete description of a particular embodiment of the invention, various modifications, variations, and equivalents are still possible. For example, although the invention has been described broadly in terms of discrete circuit elements in the detailed description of the foregoing embodiments, as is understood by those skilled in the art, in the SMT version, the discrete dimensions of the EIA standard wafer are various. Equations, such as Zener, Schottky, etc., or discrete capacitors, whether or not they have polarity, or discrete resistors, or even the nature of active or integrated circuits, whether you need to use two electrical connectors or more than two The circuit components of the connector are applicable to the fabrication method disclosed in the present invention. In addition, the present invention is applicable not only to the common SIA type EIA standard wafer sizes such as 1210, 1206, and 0805, but is also particularly suitable for smaller SMT type discrete circuit elements. For example, the conductive lines on the die surface of the medium substrate may be a cured paste silver paste, a cured paste copper paste, or a cured paste copper alloy paste. For another example, the conductive lines on the soldering surface of the board may be covered with a nickel layer or a gold layer. Therefore, the above description should not be taken as limiting the invention, and its scope should be defined by the text of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing a substrate grain surface of a substrate for fabricating a preferred embodiment of the leadless chip type package of the present invention. 2 is a perspective view of the welded surface of the substrate of FIG. 1. Figure 3 is a cross-sectional view showing a through-hole of a typical double-sided circuit substrate. Figure 4 is a cross-sectional view showing a cross-sectional view of an initial substrate used in the pinless circuit component package of the present invention. Fig. 5 is a cross-sectional view showing that the through holes of the element substrate of Fig. 3 are first filled with filler rubber and then plated with copper to completely close both ends of the through hole. Fig. 6 is a cross-sectional view showing that the through holes are completely filled in the through holes of the element substrate of Fig. 3 by copper plating. Figure 7 is a cross-sectional view showing a discrete circuit component positioned on the die face of the substrate and forming an electrical connection of the component electrodes. Figure 8 is a cross-sectional view showing the discrete circuit component of Figure 7 being coated with a water-tight material. 200847360 > A cross-sectional view of Figure 9 shows the substrate structure of Figure 8 being cut into discrete discrete circuit components. [Main component symbol description] 100 Substrate 122 Component range 112A, 112B Grain surface conductive line 132A, 132B Plated through hole 212A, 212B Solder surface conductive line 800 Watertight sealing material 212C, 212D Conductive junction 12