TWI223580B - Circuit component having fabrication-stage blind holes and process of making - Google Patents
Circuit component having fabrication-stage blind holes and process of making Download PDFInfo
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1223580 a » 五、發明說明(1) 領域 本發明大致係有關於電路元件及其製作方法,特別是 有關於一種適於自動化大量生產,具有製程階段盲孔 (blind holes)的電路元件(circuit components)及其製 作方法。 先前技術 諸如二極體(diode),電晶體(transistor),電阻 (resistor)與電容(capacit〇r)等的主動及被動式電路元 件(active and passive circuit components),乃是廣 泛應用於電子電路中之電路元件。不論是小信號(s i gna i ) 或較大功率(power)用途的,線性(1 inear)或數位 (d i g i ta 1 )性質的電路,皆需應用到此些不同性質的離散 式電路元件。除了整合於積體電路之中的二極體,電阻與 電谷之外’離散元件(discrete component)形式的二極 體,電阻與電容元件,是為使用量極大的電子零件。 離散式電路元件有多種型式的包裝(packaging),常 見者諸如導線型包裝(leaded package)。基於小型化的需 求’表面黏著技術(SMT,surface-mount technology)型 式之離散式元件,已逐漸變成微型化電子裝置所需採用的 電路元件’故以低成本進行高速率的大量生產,乃是此類 離散式電路元件之製造所必須採行的方向。 與導線型包裝利用插入至印刷電路板上的零件接腳插 孔吃錫而進行電路元件軟銲有所不同的是,SMT離散式電1223580 a »V. Description of the invention (1) Field The present invention relates generally to circuit components and manufacturing methods thereof, and in particular to a circuit component (circuit components) suitable for automated mass production and having blind holes at the process stage. ) And how to make it. Previous technologies such as diodes, transistors, resistors, and capacitors are active and passive circuit components, which are widely used in electronic circuits. Circuit components. Whether it is small signal (s i gna i) or high power (power) applications, linear (1 inear) or digital (d i g i ta 1) circuits need to be applied to these discrete circuit components of different properties. In addition to diodes, resistors and valleys integrated in integrated circuits, diodes in the form of discrete components, resistors and capacitors, are electronic components that are used in large quantities. There are many types of packaging for discrete circuit components, such as leaded packages. Based on the demand for miniaturization, surface-mount technology (SMT) discrete components have gradually become circuit components required for miniaturized electronic devices. Therefore, high-speed mass production at low cost is The direction in which such discrete circuit components must be manufactured. Different from wire-type packaging, soldering of circuit components is performed by using the pin holes of the parts inserted on the printed circuit board to solder, and SMT discrete electric
1223580 五、發明說明(2) 路元件的電接觸端子係利用其接觸端子的實質面積吃錫而 將元件本身軟銲於印刷電路板上。由於S Μ T元件並無凸形 插入於印刷電路板孔洞内的電接觸端子,故必須依賴足夠 大的吃錫面積才能夠穩固地將元件銲固於印刷電路板的定 位之上,並擁有良好的電接觸品質。1223580 5. Description of the invention (2) The electrical contact terminals of circuit components use the substantial area of their contact terminals to eat tin, and the components themselves are soldered to the printed circuit board. Since the SMT component does not have a convex electrical contact terminal inserted into the hole of the printed circuit board, it must rely on a large enough soldering area to be able to firmly solder the component to the position of the printed circuit board and have a good Electrical contact quality.
不過,習知技術之SMT型式離散式電路元件之電接觸 端子所具有的銲錫面係為平坦之表面。有些種類的S Μ Τ元 件,例如採用圓柱體形包裝之二極體,其吃錫表面甚至是 屬於一種凸形的表面。此等平坦或凸出銲錫表面在電路元 件進行印刷電路板的組裝時有其缺點。例如,電路元件易 於移位,以及發生移位時之自動更正作用力不足等。 另一方面,有些整合多個個別離散式電路元件於單一 個元件包裝之内的排式包裝,例如排二極體,排電晶體及 排電阻排電容等,其各個電接觸端子之銲接面係屬單平面 之構形。由於印刷電路板組裝時諸如錫膏印刷均勻度等諸 多因素之故,此等單平面吃錫面之電接觸端子常有其銲固 品質上的問題。在某些需求功率電流的電接觸端子上,此 等銲錫品質上的不均一極易於造成電路功能上的問題。 發明内容However, the electrical contact terminals of the SMT type discrete circuit components of the conventional technology have a flat solder surface. Some types of SM components, such as diodes in cylindrical packages, have tin-like surfaces that are even convex. These flat or protruding solder surfaces have disadvantages when the circuit components are assembled into a printed circuit board. For example, circuit components are prone to displacement, and insufficient auto-correction forces occur when displacement occurs. On the other hand, there are some row packages that integrate multiple individual discrete circuit components in a single component package, such as diodes, transistors, and resistors. The soldering surfaces of the electrical contact terminals are It is a single plane configuration. Due to various factors such as the uniformity of solder paste printing when the printed circuit board is assembled, these single-plane soldering electrical contact terminals often have problems with their soldering quality. On some electrical contact terminals that require power current, these non-uniformities in solder quality are extremely likely to cause circuit function problems. Summary of the Invention
因此,本發明之目的即在於提供一種製程階段盲孔離 散式電路元件及其製造方法,其元件構造可適合於不同晶 片尺寸,而其製造方法則可適於進行低成本的大量生產。 本發明之目的亦在於提供一種製程階段盲孔離散式電Therefore, an object of the present invention is to provide a blind-hole discrete circuit component and a manufacturing method thereof at a manufacturing stage. The component structure can be suitable for different wafer sizes, and the manufacturing method can be suitable for low-cost mass production. The object of the present invention is also to provide a blind-hole discrete electric
第8頁 1223580 五、發明說明(3) 路元件及其製造方法,可適合於利用相同之製程治具來製 _ 作不同晶片尺寸的離散式電路元件。Page 8 1223580 V. Description of the invention (3) The circuit component and its manufacturing method are suitable for making discrete circuit components with different chip sizes using the same process fixture.
為達前述目的,本發明提供可於一片基板上製作離散 ^ 式電路元件之一種製程階段盲孔之製作方法,該基板之第 I 一表面上形成有一個矩陣複數個的元件晶粒面導電線路, 每一個該些晶粒面導電線路各包含有電性互相獨立之一第 一導電段及一第二導電段,且該基板反對於該第一表面之 第二表面上對應地形成有一個矩陣複數個的銲接面導電線 路,每一個該些銲接面導電線路各包含有電性互相獨立之 一第一導電段及一第二導電段,並有鍍覆盲孔將該晶粒面 導電線路之該第一及第二導電段電性地分別與該銲接面導 籲 電線路之該第一及第二導電段電性連結;該製作方法其步 驟包含有:(a ) 在該第一表面之晶粒導電線路之第一導電 段上定置一元件晶粒,將該晶粒之第一電極電性地連結至 該晶粒導電線路之第一導電段,並將該元件晶粒之第二電 * 極電性地連結至該晶粒導電線路之該第二導電段;(b ) 以 _ 電性絕緣物質水氣密地完全包覆該基板第一表面上之該些 元件晶粒及其所有導電線路;與(c ) 切割該被水氣密封之 基板,以將所有該些元件晶粒分割成為個體獨立之離散式 電子元件。 本發明並提供一種製程階段盲孔離散式電路元件,其 φ 包含有:一基板,一元件晶粒及電性絕緣物質。基板第一 表面上形成有一元件晶粒面導電線路,其包含有電性互相 獨立之一第一導電段及一第二導電段;其反對於該第一表In order to achieve the foregoing object, the present invention provides a method for manufacturing a blind hole in a process stage capable of fabricating discrete circuit elements on a substrate, and a matrix of a plurality of element grain plane conductive lines is formed on the first surface of the substrate. Each of the grain-plane conductive lines includes a first conductive segment and a second conductive segment that are electrically independent of each other, and a matrix is correspondingly formed on the second surface of the substrate opposing the first surface. A plurality of welding surface conductive lines, each of which includes a first conductive segment and a second conductive segment which are electrically independent of each other, and has a plated blind hole to connect the grain surface conductive lines to each other. The first and second conductive segments are electrically connected to the first and second conductive segments of the welding surface conductive line, respectively. The steps of the manufacturing method include: (a) on the first surface An element die is placed on the first conductive section of the die conductive circuit, and the first electrode of the die is electrically connected to the first conductive section of the die conductive circuit, and the second electrode of the die is electrically connected. * Electrode Ground is connected to the second conductive segment of the grain conductive line; (b) the element grains and all conductive lines on the first surface of the substrate are completely covered with water-tight electrical insulating material; and (C) Cutting the water-air-sealed substrate to divide all the element dies into individual discrete electronic components. The present invention also provides a blind-hole discrete circuit element at a manufacturing stage, wherein φ includes: a substrate, an element die, and an electrically insulating substance. An element grain plane conductive line is formed on the first surface of the substrate, and includes a first conductive segment and a second conductive segment that are electrically independent of each other. The object is opposed to the first table.
第9頁 1223580 五、發明說明(」:) 面之第二表面上形成有一銲接面導電線路,其包含有電性 互相獨立之一第一導電段及一第二導電段。一第一鍍覆盲 孔將該晶粒面導電線路之該第一導電段電性地與該銲接面 導電線路之該第一導電段電性連結。一第二鍍覆盲孔則將 該晶粒面導電線路之該第二導電段電性地與該鮮接面導電 線路之該第二導電段電性連結。一元件晶粒係定置於該第 一表面之晶粒導電線路之第一導電段上,該晶粒之第一電 極係電性地連結至該晶粒導電線路之第一導電段;且該晶 粒之第二電極係電性地連結至該晶粒導電線路之該第二導 電段。電性絕緣物質則水氣密地完全包覆該基板第一表面 上之該些元件晶粒及其所有導電線路。 發明實施方式 圖1為本發明製程階段盲孔製程階段盲孔離散式電路 元件一較佳實施例之基板之晶粒面立體圖。如圖所示,用 以承載整個矩陣排列的,典型多達數百個離散式電路元件 的基板1 0 0,其晶粒面1 1 0之表面上有多個離散式電路元件 之初始導電線路1 1 1 ,1 1 2,…及1 1 6等,係排列於,例如 圖中所顯示的,一個二維正交的矩陣之中。注意到基板 1 0 0本身,在此製程早期階段,亦係被使用作為本發明整 批製作,數量眾多的電路元件之基礎承載片板用途。 相對於圖1之晶粒面的初始導電線路,基板1 0 0在其圖 1的晶粒面1 1 0之反對表面,亦即元件之銲接面,亦有一個 由多個初始導電線路2 1 1,2 1 2,…及2 1 4等,排列於一個Page 9 1223580 V. Description of the invention (":") A welding surface conductive line is formed on the second surface of the surface, which includes a first conductive segment and a second conductive segment that are electrically independent of each other. A first plated blind hole electrically connects the first conductive segment of the grain plane conductive circuit with the first conductive segment of the solder plane conductive circuit. A second plated blind hole electrically connects the second conductive segment of the grain-plane conductive line with the second conductive segment of the fresh-face conductive line. An element grain is positioned on the first conductive segment of the grain conductive circuit on the first surface, and the first electrode of the grain is electrically connected to the first conductive segment of the grain conductive circuit; and the crystal The second electrode of the grain is electrically connected to the second conductive segment of the grain conductive circuit. The electrically insulating material completely and water-tightly covers the element crystal grains and all conductive lines on the first surface of the substrate. Embodiments of the invention FIG. 1 is a perspective view of a crystal plane of a substrate of a blind-hole discrete circuit element in a preferred embodiment of a blind-hole process stage in a process stage of the present invention. As shown in the figure, the substrate 100, which typically has hundreds of discrete circuit elements arranged to support the entire matrix arrangement, has a plurality of discrete conductive circuit elements on the surface of the grain plane 1 10. 1 1 1, 1 1 2, ... and 1 1 6 are arranged in, for example, a two-dimensional orthogonal matrix as shown in the figure. It is noted that the substrate 100 itself is also used as a basic carrier sheet for a large number of circuit elements produced in a batch in the present invention at an early stage of the process. With respect to the initial conductive line of the grain surface of FIG. 1, the substrate 100 is on the opposite surface of the grain surface 1 10 of FIG. 1, that is, the welding surface of the component, and there is a plurality of initial conductive lines 2 1 1, 2 1 2, ... and 2 1 4 etc.
1223580 五、發明說明(5) 對應的矩陣之中。圖2係為圖1基板之銲接面之立體圖,其 表面上亦有多個離散式電路元件之初始導電線路2 1 1 , 2 1 2 ,…與2 1 4排列於矩陣之中。注意到圖2之基板銲接面 2 1 0係為圖1之基板晶粒面1 1 0水平翻轉所顯示之銲接面導 電線路矩陣排列圖形。此可由圖1及2中晶粒面1 1 0之線路 1 1 1係與銲接面2 1 0之線路2 1 1對應,線路1 1 2與2 1 2對 應,…及1 1 4與2 1 4對應而得以理解。1223580 V. Description of the invention (5) Among the corresponding matrices. Fig. 2 is a perspective view of the soldering surface of the substrate of Fig. 1. On the surface, there are also a plurality of discrete conductive elements of the initial conductive lines 2 1 1, 2 1 2, ... and 2 1 4 arranged in a matrix. Note that the substrate welding surface 2 1 0 of FIG. 2 is a matrix arrangement pattern of the conductive surface of the welding surface shown by horizontally flipping the substrate grain surface 110 of FIG. 1. This can correspond to the line 1 1 1 of the grain surface 1 1 0 in Figs. 1 and 2 corresponding to the line 2 1 1 of the welding surface 2 1 0, the line 1 1 2 and 2 1 2, ... and 1 1 4 and 2 1 4 corresponds and is understood.
在每一個離散元件的初始導電線路之中(包含晶粒面 及銲接面),在大致位於導電線路的中心位置,各皆形成 有一盲孔,除了晶粒面導電線路層以外,實質上垂直貫穿 了基板1 0 0的整個厚度。例如,圖1及2中的導電線路1 1 1及 對應的2 1 1之中,形成有一盲孔1 3 1,在導電線路1 1 2及對 應的2 1 2之中則形成有一盲孔1 3 2。 每一盲孔與其對應在基板之晶粒面及銲接面上的導電 線路之相對位置關係,係顯示於圖3與4之中。圖3係為圖1 之局部放大圖,其顯示基板晶粒面之初始導電線路之構形 細節,而圖4則為圖1及2之基板之橫截面圖。圖1 ,2及3之A blind hole is formed in each of the discrete conductive elements' initial conductive lines (including the grain surface and the soldering surface) at approximately the center of the conductive lines. Except for the grain surface conductive circuit layer, it passes through substantially vertically. The entire thickness of the substrate 100. For example, a blind hole 1 3 1 is formed in the conductive line 1 1 1 and the corresponding 2 1 1 in FIGS. 1 and 2, and a blind hole 1 is formed in the conductive line 1 1 2 and the corresponding 2 1 2. 3 2. The relative positional relationship between each blind hole and its corresponding conductive line on the grain surface and the soldering surface of the substrate is shown in Figs. FIG. 3 is a partial enlarged view of FIG. 1, which shows the configuration details of the initial conductive lines on the substrate grain surface, and FIG. 4 is a cross-sectional view of the substrate of FIGS. 1 and 2. Figures 1, 2 and 3
中,每一個以虛線所圍繞之大致矩形之區域,如同後面所 將說明的,係代表一個離散電路元件之實體範圍。例如圖 3所示,虛線1 2 1所標示的範圍係為本發明一個完整離散式 電路元件的實體範圍,其中,於範圍1 2 1内大致中心之 處,如虛線區域1 5 1所標示的位置,係為元件晶粒所將定 置之位置。 注意到如圖3之立體圖中所顯示的,導電線路在基板Each substantially rectangular area surrounded by a dotted line, as will be described later, represents the physical range of a discrete circuit element. For example, as shown in FIG. 3, the range indicated by the dashed line 1 2 1 is the physical range of a complete discrete circuit component of the present invention. Among them, the approximate center of the range 1 2 1 is as indicated by the dashed area 1 5 1 The position is the position where the element die will be positioned. Note that as shown in the perspective view of FIG. 3, the conductive lines are on the substrate
第11頁 1223580 五、發明說明(6) 100晶粒面110上沿長轴方向(圖中之水平方向)之不對稱圖 形。依據本發明離散式電路元件之一較佳實施例,其導電 線路於圖3中所顯示一個別元件之元件個體腳印 (component footprint)範圍121内,沿其短軸方向(圖中 之垂直方向)’導電線路1 1 1與1 1 2實質上係呈現大致對稱 的圖形。Page 11 1223580 V. Description of the invention (6) 100 grain plane 110 Asymmetrical pattern along the long axis direction (horizontal direction in the figure). According to a preferred embodiment of the discrete circuit component of the present invention, the conductive circuit is within the component footprint range 121 of a component shown in FIG. 3 along the short axis direction (vertical direction in the figure). 'The conductive lines 1 1 1 and 1 1 2 are substantially symmetrical in shape.
相較之下’線路丨丨1與丨丨2沿元件腳印的長軸方向則顯 現明顯的不對稱。導電線路丨丨1與丨丨2,實質上,係屬互相 電性獨立之兩導電圖形。導電線路111與112兩者各具有一 段朝向το件中心延伸之導電線段。兩導電線路其中之一朝 向元件中心’即元件晶粒所將定置之定位延伸,另一導電 線路則未依相當幅度向中心延伸,以便兩者互不接觸,保 持電性互相獨立的開路狀態。 在圖3所顯示之實施例之中,右側之導電線路1 1 1係為 向元件中心延伸較多的導電線路。不過,如同習於本技藝 者所可以理解的’若安排左側的導電線路延伸到達元件中 心,亦同樣是可行的作法。In comparison, the ‘lines 丨 1 and 丨 丨 2 show significant asymmetry along the long axis of the component footprint. The conductive lines 丨 丨 1 and 丨 丨 2 are essentially two conductive patterns that are electrically independent of each other. Each of the conductive lines 111 and 112 has a conductive line segment extending toward the center of the το member. One of the two conductive lines extends toward the center of the element, that is, the position where the element crystal grains are positioned, and the other conductive line does not extend to the center by a considerable extent so that the two are not in contact with each other and maintain an independent open circuit state of electrical properties. In the embodiment shown in FIG. 3, the conductive line 1 1 1 on the right side is a conductive line extending more toward the center of the element. However, as can be understood by those skilled in the art, it is also feasible to arrange the conductive line on the left to reach the center of the component.
圖4之橫截面圖顯示,各盲孔係為鍍覆表面之盲孔 〔Plated Hole)。如圖所示,盲孔131及132,利用諸如濺 鍵(sputtering),電鍍(electroplating)等製作印刷電路 基板的技術,可以在孔壁上形成導電金屬層。盲孔孔壁上 的此鑛覆金屬層便可以將基板丨〇 〇的晶粒面與相對反面的 銲接面上的導電線路互相電性地連接結起來。 圖1與2所顯示之基板,係作為本發明離散式電路元件The cross-sectional view of FIG. 4 shows that each blind hole is a plated hole of a plated surface. As shown in the figure, the blind holes 131 and 132 can form a conductive metal layer on the wall of the hole by using techniques such as sputtering, electroplating, and the like to make a printed circuit board. This metal-clad metal layer on the hole wall of the blind hole can electrically connect the conductive lines on the grain surface of the substrate and the conductive lines on the welding surface on the opposite side. The substrate shown in Figs. 1 and 2 serves as the discrete circuit element of the present invention.
第12頁 1223580 五、發明說明(7) 之基礎。此基板係為電性絕緣之板材,其可以是,例如玻 璃纖維強化樹酯(F R P ),或者是利用模鑄(m ο 1 d i n g )等技 術,使用適當之絕緣性質材料製作成板材。其後可利用諸 如顯影ϋ刻技術(p h 〇 t ο 1 i t h 〇 g r a p h y )而製作晶粒面及銲接 面上之導電線路。 盲孔可利用適當加工機具,在如圖3所示之定位上鑽 孔形成。其後,如同前述,可利用濺鍍與/或電鍍等製程 而形成鍍覆貫通孔。鍍覆盲孔形成後,即可獲得圖1及2所 顯示之基板1 0 0。 接著,於一較佳實施例之中,各盲孔中可埋入永久性 的埋孔材料。盲孔中所填入者可以是具良好導電性質的永 久性材料。如同習於本技藝者所可以理解的,適用的材質 包含有,例如,導電膠,錫膏或錫球等,此等填充材料經 過製程處理之後可以完全而緊密地塞滿整個盲孔。當然, 盲孔内亦可以保持淨空,不填入任何物質。 圖3及4中所顯示的基板,其鍍覆盲孔内未填充有埋孔 材料。利用此基板,如圖5所示,接著便可以將離散式電 路元件之晶粒定置於圖3所示之定位1 5 1上。圖5之橫截面 圖顯示一離散式電路元件之晶粒5 1 1被定置於基板1 0 0之晶 粒面1 1 0上。元件晶粒5 1 1之電極,並且與基板1 0 0上之晶 粒面1 1 0上導電線路1 1 1 A電性地連結。 晶粒5 1 1與導電線路1 1 1 A之電性接合可以利用,例 如,以電氣爐加熱,使預先形成於晶粒5 1 1下表面或導電 線路1 5 1位置上之銲錫熔化,冷卻後將晶粒5 1 1銲著於導電Page 12 1223580 V. The basis of invention description (7). The substrate is an electrically insulating sheet material, which can be, for example, glass fiber reinforced resin (FRP), or can be made into a sheet material using appropriate insulation properties using techniques such as die casting (m ο 1 d i n g). Thereafter, the conductive lines on the grain side and the solder side can be made by using, for example, a development engraving technique (p h 0 t ο 1 i t h 0 g r a p h y). The blind hole can be formed by drilling a hole at a position as shown in FIG. 3 by using an appropriate processing tool. Thereafter, as described above, a plating through-hole can be formed by a process such as sputtering and / or plating. After the plating blind holes are formed, the substrate 100 shown in Figs. 1 and 2 can be obtained. Then, in a preferred embodiment, a permanent buried material can be buried in each blind hole. The blind hole can be filled with a permanent material with good conductive properties. As can be understood by those skilled in the art, suitable materials include, for example, conductive glue, solder paste or solder balls, etc. After filling, these filling materials can completely and tightly fill the entire blind hole. Of course, the blind hole can also maintain headroom without being filled with any substance. The substrates shown in Figs. 3 and 4 are not filled with the buried hole material in the plated blind holes. Using this substrate, as shown in FIG. 5, the crystal grains of the discrete circuit element can be set on the positioning 151 shown in FIG. The cross-section of FIG. 5 shows that the crystal grain 5 1 1 of a discrete circuit element is set on the crystal grain surface 1 1 0 of the substrate 100. The electrode of the element grain 5 1 1 is electrically connected to the conductive line 1 1 1 A on the crystal grain surface 1 1 0 on the substrate 100. The electrical connection between the die 5 1 1 and the conductive line 1 1 1 A can be used, for example, heating in an electric furnace to melt and cool the solder previously formed on the lower surface of the die 5 1 1 or the position of the conductive line 1 5 1 After the grain 5 1 1 is welded to the conductive
第13頁 1223580 五、發明說明(8) 線路1 1 1 A之1 5 1定位上。 當電路元件晶粒5 1 1下表面之電極與晶粒面上之導電 線路111A達成穩固電性接合之後,晶粒51ι另一端,亦 即,頂端上之另一電極,便可以利用諸如跳接線5 3 i而與 基板100晶粒面110上的另一導電線路112B,透過導線而電 性地接合。 p f當ΐ j 1 5所顯示之架構之後,各元件晶粒之電極便 干,ΐί 12i各自基板範圍(圖1,2及3中以虛線所標 的對應軟鮮接觸端子上。此時,電 一: 、凡成’但仍排列於矩陣中之各個離散式電路 ^ 可以進行水軋选封(hermetic seal)的處理。圖6 =載面圖即顯示圖5之離散式電路元件晶粒被水密性材 =6 0 0包覆^情形。此種密封包覆可以,例如,利用模鑄 =方式,订、。只需利用模具在基板1 0 0的晶粒面1 1 0上方形 成一個南^度^適恰之空間,便可以利用,例如,將熔融(軟 之水^氣^密封材質注入該空間内’而可以方便而容易地 製士水氣密,裝6 〇 〇,以將晶粒5 1 1,5 1 2等保護於其中。 〉主意到’水氣密絕緣材質6 0 0之選定,亦可為與基板1 〇 〇本 身所使用者完全相同之物質。 之後 圖7之橫戴面圖顯示,圖6之基板構造被切割成 士,之,散式電路元件。注意到兩相鄰元件之間的切割, 實質上可以對準兩元件之間的對稱中心線而進行切割。如 ^所示’切割圖7中元件7 1 1即須沿切割道7 4 1與7 4 2進行切 割。此外’如同可以理解的,沿著圖中所未標示,實質上Page 13 1223580 V. Description of the invention (8) Line 1 1 1 A of 1 5 1 is positioned. After the electrode on the lower surface of the circuit element die 5 1 1 and the conductive line 111A on the die face have reached a stable electrical connection, the other end of the die 51 i, that is, the other electrode on the top, can use a jumper, for example. 5 3 i is electrically connected to another conductive line 112B on the grain surface 110 of the substrate 100 through a wire. After pf when the structure shown by 1 j 1 5 is used, the electrodes of each component die are dried, and the respective 12i substrate ranges (the corresponding soft and fresh contact terminals marked by the dashed lines in Figures 1, 2 and 3). : "Fancheng ', but each discrete circuit still arranged in the matrix ^ can be processed by hermetic seal (Figure 6): The surface view shows the watertightness of the discrete circuit element grains of Figure 5 Material = 6 0 0 cladding case. This type of sealing coating can, for example, use die casting = method, order, and just use a mold to form a south face above the grain surface 1 1 0 of the substrate 100. ^ Appropriate space can be used, for example, melting (soft water ^ air ^ sealing material is injected into the space ') can be easily and easily made water and air tight. 1 1, 5 1 2 etc. are protected in it.〉 The idea is that the choice of 'water-tight insulation material 600' can also be exactly the same as that used by the substrate 100 itself. Later, the cross-sectional surface of FIG. 7 The figure shows that the substrate structure of FIG. 6 is cut into shims, in other words, loose circuit components. Note that two adjacent The cutting between the pieces can basically be performed by aligning the symmetrical centerline between the two elements. As shown by ^ 'to cut the element 7 1 1 in FIG. 7 must be cut along the cutting lines 7 4 1 and 7 4 2 In addition, 'as can be understood, along with
第14頁 1223580 五、發明說明(9) 垂直於切割道7 4 1與7 4 2的方向,亦須進行二道切割,才能 完整地將元件7 1 1分離出來。若盲孔内埋入的是永久性 的,具良好導電性質的材料,其所填塞的物質即成為電接 觸端子的一部份。另一面方,若盲孔内未予埋填,在此切 割程序之後,其所露出盲孔本身的表面即可作為電接觸端 子的導電面。Page 14 1223580 V. Description of the invention (9) The direction perpendicular to the cutting lines 7 4 1 and 7 4 2 also requires two cuttings to completely separate the component 7 1 1. If the material buried in the blind hole is permanent and has good conductive properties, the stuffing material becomes part of the electrical contact terminal. On the other hand, if the blind hole is not buried, after the cutting procedure, the surface of the exposed blind hole itself can be used as the conductive surface of the electrical contact terminal.
圖8及9分別顯示依據本發明一較佳實施例製造完成並 經切割分離之一電路元件,其單體構造之背面及銲接面之 立體圖。由於切割係如前述,通過盲孔之對稱中心線而進 行的,故圖9之立體圖顯示,各個元件的兩電極,皆可具 有一個面積夠大,且高度顯著高於基板上之初導電線路厚 度的一個導電接面,如圖9中未填塞之盲孔,沿著垂直於 基板平面之方向所出現的高度。在本發明各個製程階段盲 孔離散式電子元件於印刷電路板上進行軟銲時,此導電接 面可以確保良好的軟銲品質。另一方面,於前述應用永久 性導電填充材料進行盲孔填充之較佳實施例之中,前述之 切割所形成的導電接面即無内凹的表面。8 and 9 respectively show perspective views of the back surface and the soldering surface of a circuit element manufactured in accordance with a preferred embodiment of the present invention and cut and separated. Because the cutting is performed through the symmetrical centerline of the blind hole as described above, the perspective view of FIG. 9 shows that the two electrodes of each component can have a large area and a height that is significantly higher than the initial conductive line thickness on the substrate. The height of a conductive junction, such as the unfilled blind hole in FIG. 9, along the direction perpendicular to the plane of the substrate. The conductive interface can ensure good soldering quality when the blind-hole discrete electronic component is soldered on a printed circuit board at each process stage of the present invention. On the other hand, in the aforementioned preferred embodiment of blind hole filling using a permanent conductive filling material, the conductive junction formed by the aforementioned cutting is a surface without recesses.
圖1 0及1 1分別顯示本發明另一電路元件單體構造之背 面及銲接面之立體圖,其具有四個電接觸端子。此電路元 件可為兩個類如圖8及9中元件單體之連結,其具有四個電 接觸端子。注意到圖中元件1 0 0 0之電接觸端子1 0 1 1,1 0 1 3 等,與圖8及9中元件8 0 0之端子8 1 1相類似的,係具有凹陷 之導電接面。 圖1 2及1 3分別顯示本發明又另一電路元件單體構造之Figs. 10 and 11 respectively show perspective views of a back surface and a soldering surface of another circuit element single structure of the present invention, which have four electrical contact terminals. This circuit element can be a connection of two types of components as shown in Figs. 8 and 9, which have four electrical contact terminals. Note that the electrical contact terminals 1 0 1 1, 1 0 1 3 and the like of the component 1 0 0 0 in the figure are similar to the terminal 8 1 1 of the component 8 0 0 in FIGS. . Figures 1 2 and 1 3 respectively show the structure of another circuit element according to the present invention.
第15頁 1223580 五、發明說明(ίο) 背面及銲接面之立體圖,其具有雙排各四個電接觸端子, . 其可為四個類如圖8中的元件單體之連結,具有雙排各四 _ 個電接觸端子。圖中元件1 2 0 0之電接觸端子1 2 1 1 ,1 2 1 3 等,與圖8中元件8 0 0之端子8 1 1相類似的,亦具有凹陷之 導電接面。圖10至13所顯示的多電接觸端子電路元件可適 用於,例如,排二極體等的整合式主動或被動電路元件。 另一方面,圖14顯示本發明另一電路元件單體構造之銲接 面之立體圖。此電路元件1400之三個電接觸端子1411, 1 4 1 3及1 4 1 2係依不對稱形態安排,可適用於諸如需要使用 三個接腳的電晶體等離散式電路元件的需求。 圖15顯示本發明另一電路元件單體構造之銲接面之立 ® 體圖,其具有四面排列之多個電接觸端子。注意到圖中之 電路元件1 5 0 0在其兩較寬側面各具有四個電接觸端子 (1511,1513,1515 及 1517 與 1512,1514,1516 及 1518), 而其較窄側面則各只有一個電接觸端子1 5 2 1與1 5 2 2。電路 元件1 5 0 0之此種電接觸端子安排同樣可適用於,例如,排 二極體或排電晶體等的整合式主動或被動電路元件。在一 種典型的元件接腳分派方式之中,寬側之電接觸端子可以 為元件1 5 0 0所内含多個個別離散式電路元件之信號接腳, 例如二極體之正負極接腳,而其窄側的電接觸端子則可供 諸如接地,或諸如共陽或共陰排二極體的共同電源或共同 φ 接地端。 如同習於本技藝者可以理解的,雖然圖中之電路元件 1 5 0 0 ,其實質上位於左右兩側的元件側面只具有單一個電Page 15 1223580 V. Description of the invention (ίο) A perspective view of the back surface and the soldering surface, which has four rows of four electrical contact terminals each. It can be a connection of four types of component monomers as shown in Figure 8, with a double row Four _ electrical contact terminals each. The electrical contact terminals 1 2 1 1, 1 2 1 3, etc. of the component 1 2 0 in the figure are similar to the terminal 8 1 1 of the component 8 0 0 in FIG. 8, and also have a recessed conductive connection surface. The multiple electrical contact terminal circuit elements shown in Figs. 10 to 13 can be applied to, for example, integrated active or passive circuit elements such as diodes. On the other hand, Fig. 14 shows a perspective view of a soldering surface of a single circuit element structure of the present invention. The three electrical contact terminals 1411, 1 4 1 3, and 1 4 1 2 of this circuit element 1400 are arranged in an asymmetrical form, which can be adapted to the needs of discrete circuit elements such as transistors that require three pins. FIG. 15 is a perspective view of a soldering surface of a single circuit element structure of the present invention, which has a plurality of electrical contact terminals arranged on four sides. Note that the circuit element 1 500 in the figure has four electrical contact terminals (1511, 1513, 1515, and 1517 and 1512, 1514, 1516, and 1518) on each of its two wider sides, while its narrower sides each have only One electrical contact terminal 1 5 2 1 and 1 5 2 2. Such an electrical contact terminal arrangement of the circuit element 1 500 is equally applicable to, for example, integrated active or passive circuit elements such as a diode or a transistor. In a typical component pin assignment method, a wide-side electrical contact terminal may be a signal pin of a plurality of individual discrete circuit components contained in the component 15500, such as the positive and negative pins of a diode. The narrow-side electrical contact terminals can be used for common ground or common φ ground such as common ground or common cathode diodes. As can be understood by those skilled in the art, although the circuit element 15 0 0 in the figure has substantially a single electrical element on its side
第16頁 1223580 五、發明說明(11) 接觸端子,但 合於不同的元 本發明製 形成有盲孔之 在其製程的初 孑L 。因此,在 要再預留後續 可以充份運用 所必須佔用的 為適合於製作 規格的元件。 雖然前面 整的說明,但 應用仍是可能 廣泛地以離散 藝之士所可以 尺寸的離散式 散式電容,無 動或積體電路 皆是可以適用 不但適用於常 晶片尺寸,其 元件。再例如 為固化之膏狀 其亦可以安排多於一個的電接觸端子,以適 件之需要。 程階段盲孔離散式電路元件,由於使用一片 基板作為建構整個矩陣的多個元件之基礎, 期,此些盲孔即已形成等效於埋實的貫通 每一個元件之指定形成範圍之中,由於不需 鑽孔處理的空間,因此,整個元件之範圍便 來承載元件晶粒。換句話說,元件在基板上 最小空間便可以盡可能地縮小。此種特點極 微小型的元件,諸如0 6 0 3,0 4 0 2,甚至更小 的說明文字已是本發明特定實施例的一個完 其各種的修改變化,變動的構造及等效者的 的。例如,雖然前述實施例之詳細說明中只 式電路元件來說明本發明,但如同習於本技 理解者,SMT型式之下,El A標準晶片的各種 二極體,諸如Zener,Schottky等,或者離 論是有否極性,或者離散式電阻,甚至是主 本質,但只需使用二電性接頭的電子元件, 於本發明所揭示之製作方法。此外,本發明 見的1210,120 6,以及0805等SMT型EIA標準 更係特別適於更為小型的SMT型離散式電路 ’說明中基板之晶粒面上之該些導電線路可 銀膠,固化之膏狀銅膠,或固化之膏狀銅合Page 16 1223580 V. Description of the invention (11) Contact terminals, but combined with different elements The invention has blind holes formed at the beginning of the manufacturing process. Therefore, it is necessary to reserve for subsequent full use, which must be occupied by components suitable for production specifications. Although the entire description is described above, the application is still widely applicable to discrete discrete capacitors of the size that can be used by discrete artisans, and passive or integrated circuits are applicable. Not only are they applicable to ordinary chip sizes and their components. Another example is a solidified paste, which can also arrange more than one electrical contact terminal to suit the needs of the part. In the process stage, blind hole discrete circuit components use a substrate as the basis for constructing multiple elements of the entire matrix. In the meantime, these blind holes have been formed equivalent to the specified formation range that penetrates each component. Because there is no space for drilling, the entire range of components is used to carry component dies. In other words, the smallest space on the substrate can be minimized. Such extremely small components, such as 0 6 0 3, 0 4 0 2 or even smaller explanatory texts, have been a specific embodiment of the present invention, complete with various modifications, changes in construction and equivalent. . For example, although the detailed description of the foregoing embodiments describes only the circuit elements to illustrate the present invention, as understood by those skilled in the art, under the SMT type, various diodes of the El A standard wafer, such as Zener, Schottky, etc., or Whether there is polarity, or discrete resistance, or even the main nature, it is only necessary to use electronic components with two electrical connectors in the manufacturing method disclosed in the present invention. In addition, the SMT EIA standards such as 1210, 120 6, and 0805, which are seen in the present invention, are particularly suitable for smaller SMT discrete circuits. Cured paste copper paste, or cured paste copper compound
第17頁 1223580 . t \ 五、發明說明(12) 金膠。又例如,該板之銲接面上之該些導電線路上更可覆 有一鎳層與或一金層。因此,前面的描述說明即不應被拿 來限定本發明,而其範疇應以後附之申請專利範圍乙節文 字内容來加以界定。Page 17 1223580 .t \ V. Description of the invention (12) Gold glue. For another example, the conductive lines on the welding surface of the board may be further covered with a nickel layer or a gold layer. Therefore, the foregoing description should not be used to limit the present invention, but its scope should be defined in the text of the scope of section B of the attached patent application.
第18頁 1223580 圖式簡單說明 圖1為本發明製程階段盲孔製程階段盲孔離散式電路 元件一較佳實施例之基板之晶粒面立體圖; 圖2為圖1基板之鲜接面之立體圖, 圖3為圖1之局部放大圖,顯示基板晶粒面之初始導電 線路之構形細節; 圖4為圖1及2之基板之橫截面圖; 圖5之橫截面圖顯示一離散式電路元件晶粒被定置於 基板之晶粒面上,並形成元件電極之電性連結; 圖6之橫載面圖顯示圖5之離散式電路元件被水氣密性 材料包覆, 圖7之橫截面圖顯示圖6之基板構造被切割成分離之離 散式電路元件; 圖8及9分別顯示依據本發明一較佳實施例製造完成並 經切割分離之一電路元件,其單體構造之背面及銲接面之 立體圖; 圖1 0及1 1分別顯示本發明另一電路元件單體構造之背 面及銲接面之立體圖,其具有四個電接觸端子; 圖1 2及1 3分別顯示本發明又另一電路元件單體構造之 背面及銲接面之立體圖,其具有雙排各四個電接觸端子; 圖1 4顯示本發明另一電路元件單體構造之銲接面之立 體圖;與 圖1 5顯示本發明另一電路元件單體構造之銲接面之立 體圖,其具有四面排列之多個電接觸端子。Page 18 1223580 Brief description of drawings Figure 1 is a perspective view of a crystal plane of a substrate of a blind hole discrete circuit element in a preferred embodiment of a blind hole process stage of the manufacturing process of the present invention; Figure 3 is a partial enlarged view of Figure 1 showing the configuration details of the initial conductive lines on the substrate grain plane; Figure 4 is a cross-sectional view of the substrate of Figures 1 and 2; Figure 5 is a cross-sectional view of a discrete circuit The element crystal grains are set on the crystal grain surface of the substrate and form the electrical connection of the element electrodes. The cross-sectional view of FIG. 6 shows that the discrete circuit element of FIG. 5 is covered with a water-tight material. The cross-sectional view shows that the substrate structure of FIG. 6 is cut into discrete discrete circuit elements. FIGS. 8 and 9 respectively show a circuit element manufactured in accordance with a preferred embodiment of the present invention and cut and separated. Three-dimensional views of the soldering surface; Figures 10 and 11 show perspective views of the back surface and soldering surface of another circuit element single structure of the present invention, respectively, which have four electrical contact terminals; Figures 12 and 13 respectively show the present invention and another A circuit element A perspective view of the back surface and soldering surface of the body structure, which has four rows of four electrical contact terminals each; FIG. 14 shows a perspective view of the soldering surface of another circuit element single structure of the present invention; and FIG. 15 shows another circuit of the present invention A perspective view of a soldering surface of a single element structure having a plurality of electrical contact terminals arranged on four sides.
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