TW556261B - Buried discrete circuit components and fabricating method thereof - Google Patents

Buried discrete circuit components and fabricating method thereof Download PDF

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Publication number
TW556261B
TW556261B TW91122469A TW91122469A TW556261B TW 556261 B TW556261 B TW 556261B TW 91122469 A TW91122469 A TW 91122469A TW 91122469 A TW91122469 A TW 91122469A TW 556261 B TW556261 B TW 556261B
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Taiwan
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conductive
grain
buried
substrate
patent application
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TW91122469A
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Chinese (zh)
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Wen-Long Chen
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Comchip Technology Co Ltd
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Abstract

A method of fabricating a buried discrete circuit component, its steps includes: (a) a plurality of matrix component grain face conductive circuits are formed on a first surface of a substrate, each grain face conductive circuits comprise electric independent a first conductive part and a second conductive part; (b) a plurality of matrix welding face conductive circuits are formed on a second surface which is corresponding the reverse side of the first surface of the substrate, each welding face conductive circuits comprise electric independent a first conductive part and a second conductive part, and the first conductive part and the second conductive part of the grain face conductive circuits electric connect to the first conductive part and the second conductive part of the welding face conductive circuits by using a Plated Through-Hole of a buried conductive material; (c) a component grain is placed on the first conductive part of grain conductive circuit of the first surface, and the first electrode of the grain electric connect to the first conductive part of the grain conductive circuits; (d) the second electrode of the component grain electric connect to the second conductive part of the grain conductive circuits; (e) using electric insulation material steam completely seal up all component grains and all conductive circuits on the first surface of the substrate; and (f) cutting the steam sealed substrate to dismember all component grains to get individual independent discrete circuit components.

Description

556261 五、發明說明(1) 發明之範圍 本發明大致係有關於電路元件及其製作方法。特定而 言’本發明係有關於一種適於自動化大量生產,適用於電 子電路中之離散式電路元件(discrete circuit components)及其製作方法。 發明之背景 諸如二極體(diode),電晶體(transistor),電阻 (resistor)與電容(capacit〇r)等的主動及被動式電路元 件(active and passive circuit components),乃是廣 泛應用於電子電路中之電路元件。不論是小信號(s i gna j ) 或較大功率(p0Wer)用途的,線性(linear)或數位 (d 1 g 1 t a 1 )性質的電路,皆需應用到此些不同性質的離散 式$路元件。除了整合於積體電路之中的二極體,電阻與 電谷之外’離散元件(discrete component)形式的二極 體’電阻與電容元件,是為使用量極大的電子零件。 由於離散元件形式的電路元件,其在各式各樣電子電 ^中的用量相當大,且其單位售價相對於其他諸如電晶體 專的主動元件又不向’故乃是極為適於,或者是說,極需 ,^動化的大量生產。從另一角度而言,此種數量大而低 單價的凡件’若無法利用自動化高速生產,便難以具有商 業上的競爭力。 離放式電路元件有著多種型式的包裝(packaging), Φ見者諸如導線型包裝(leadec[ package)。基於小型化的 為求’表面黏著技術(SMT, surface-mount technology)556261 V. Description of the invention (1) Scope of the invention The present invention relates generally to circuit components and methods of making the same. In particular, the present invention relates to a discrete circuit component suitable for automated mass production, suitable for use in electronic circuits, and a method for manufacturing the same. BACKGROUND OF THE INVENTION Active and passive circuit components such as diodes, transistors, resistors, and capacitors are widely used in electronic circuits. Circuit components. Whether it is a small signal (si gna j) or high power (p0Wer) application, linear (linear) or digital (d 1 g 1 ta 1) circuits need to be applied to these discrete discrete circuits. element. In addition to diodes, resistors and valleys integrated in integrated circuits, diodes in the form of discrete components are resistors and capacitors, which are electronic components that are used in large quantities. Due to the circuit components in the form of discrete components, they are used in a wide variety of electronic devices, and their unit price is not suitable for other active components such as transistors, so it is extremely suitable, or That is to say, there is a great need for mobilized mass production. From another point of view, if such a large number of low-priced units' cannot be automated and high-speed production, it will be difficult to have commercial competitiveness. There are various types of packaging for off-the-shelf circuit components, such as leade [package]. Based on miniaturization, for the purpose of SMT (surface-mount technology)

10125twfl.ptd10125twfl.ptd

第8頁 556261 五、發明說明(2) 型式之離散式元件,已逐漸變成微型化電子裝置所需採用 的電子元件,故以低成本進行高速率的大量生產,乃是此 類離散式電路元件之製造所必須採行的方向。不過,習知 技術之中製作此等離散式電路元件的方法,仍無法完全脫 離人工加工的步驟。例如,有些型式的離散式二極體電路 元件,仍需要倚賴高比例的人工生產步驟。 另一方面,有些已經自動化的離散式電路元件製造方 法,其所採用的製程步驟之中包含了二道以上的鑽孔操 作。由於板材的機械性鑽孔動作需要一定的操作時間及定 位精確度,基與每一個雙電極元件通常皆需要進行至少二 次鑽孔,因此亦在整體製程之中形成瓶頸。因此,習知技 術之中採用二片以上鑽孔板材的製程,無可避免地會需要 較長的製程時間,並需求較為精密的定位準確度操作。此 兩因素皆會增加元件的單位製作成本。 因此,本發明之目的即在於提供一種埋孔離散式電路 元件及其製造方法,其元件構造可適合於SMD型式的,諸 如E I A標準的晶片尺寸,而其製造方法則可適於進行低成 本的大量生產。 發明之概要 為達前述目的,本發明並提供一種埋孔離散式電路元 件之製作方法,其步驟包含有(a),在一基板之第一表面 上形成一個矩陣複數個的元件晶粒面導電線路,每一個該 些晶粒面導電線路各包含有電性互相獨立之一第一導電段 及一第二導電段;(b ),對應地在該基板反對於該第一表Page 8 556261 V. Description of the invention (2) The type of discrete components has gradually become the electronic components required for miniaturized electronic devices. Therefore, high-speed mass production at low cost is such discrete circuit components. The direction in which it must be manufactured. However, the method of manufacturing such discrete circuit elements in the conventional technology still cannot completely separate the manual processing steps. For example, some types of discrete diode circuit components still rely on a high proportion of manual production steps. On the other hand, some discrete circuit component manufacturing methods that have been automated use process steps that include more than two drilling operations. Since the mechanical drilling action of the plate requires a certain operating time and positioning accuracy, the base and each two-electrode element usually need to be drilled at least twice, so it also forms a bottleneck in the overall process. Therefore, in the conventional technology, the process of using two or more drilled plates will inevitably require a longer process time and require more precise positioning accuracy operations. Both of these factors increase the unit manufacturing cost of the component. Therefore, the object of the present invention is to provide a buried-hole discrete circuit component and a method for manufacturing the component. The component structure can be suitable for SMD types, such as the EIA standard wafer size, and the manufacturing method can be suitable for low-cost Mass production. Summary of the Invention In order to achieve the foregoing object, the present invention also provides a method for manufacturing a buried-hole discrete circuit element, the steps of which include (a) forming a matrix of a plurality of element crystal faces on a first surface of a substrate to conduct electricity Circuit, each of the grain-plane conductive lines includes a first conductive segment and a second conductive segment that are electrically independent of each other; (b), correspondingly, the substrate is opposed to the first table

10125 twfl.ptd 第9頁 556261 路 線 電 導 面 接 焊 的 個 數 複 矩 個 1 成 形 上 面 3)表 二 月 - 辦第 明匕 發之 、」面 五 第一 一第 之該 立之 獨路 相線 互電 性導 電面 有粒 含晶 包該 各且 路, 線段 ^¾^mj 導導面二 接第 焊一 些及 該段 個電 一導 每一 分; 地結 性連 電性 而電 孔段 穿電 貫導覆二 鍍第 之及 質一 物第 電該 導之 埋路 内線 以電 係導 段面 電接 導焊 二該 第與 及別 置 定 上 段 電 導 1 第 之 路 線 導 粒 晶 之 面 表 一 第 該 在 路 線 晶段導 該電粒 將導晶 並一該 ,第至 粒之結 晶路連 件線地 元電性 一 導電 第 之 粒 夂極以晶電, 玄 t 二} 至 e 第C 結之; 連i段 i晶t 性+導冑d 一一 極亥第 今口 電f該 一—之 第 板 基)^ 該(f 覆與 包·, 全路 完線 地電 密導 氣有 水所 質其 物及 緣粒 絕晶 性件 電元 些 該 之 上 面 表 封 密 氣 水 被亥 >·φ 切 散 β 韻 之 立 獨 體 個 為 成 S:.口 分 粒 晶 件 元 些 該 有 所 將。 以件 ,元 板子 基電 之式 含一 包第 件其 元, 該質 ,物 件覆 元包 路之 電緣 式絕 散性 離電 孔及 fml 埋, 參二 L 種粒 一晶 供件 提元 並一 明, 發板 本基 一 有 相表 互一 性第 電該 有於 含對 包反 其其 路段 線電 電導導二 面第 粒一 晶及 件段 元電 一導 有一 成第 形一 上之 面立 表獨 性貫導 電覆 一 有鐘第 含一該 包第之 其一路 ,;Μ 路段電 線電導 電導面 導二粒 面第晶 接一該 焊及將 一段並 有電, 成導質 形一物 上第電 面一導 表之埋 二立内 第獨, 之相孔 面互穿 面 連粒 性晶 電該 段將 電並 導, 一質 第物 該電 之導 -路埋 線内 電, 導孔 面穿 接貫 焊覆 該鍍 與二 地第 性一 電及 段., 電結 該晶 之之 路面 線表 電一 導第 面該 接於 焊置 該定 與被 地粒 性晶 電件 段元 電。 導結 二連 第性 該電 之段 路電 線導 電二 導第10125 twfl.ptd Page 9 556261 Number of joints on the conductive surface of the line complex moments 1 forming the top 3) Table February-the first and the second phase of the five-to-one first phase The electrically conductive surface has grains and crystals, each segment is connected, and the line segment is ^ ¾ ^ mj. The conductive surface is connected to the first welding segment and each electrical segment of this segment is electrically conductive. The ground junction is electrically connected and the electrical hole segment is penetrated. The second line of the first coating and the first line of the first line of the buried line are electrically connected to the second line of the conductive line and the second line is connected to the upper line of the first line. The first conductive particle will be crystallized in the crystal segment of the route, and the crystal grains of the first to the second crystal grains will be electrically connected to the first element of the conductive grain. ; even i i crystalline segment of t + d eleven pilot helmet of this electrode Hai a port of the electrically f - of the first plate-yl) ^ the (f bag and cover the whole road completely dense air conductive wire electrically with a water The quality of the material and the marginal grains of the amorphous element are slightly above the surface seal air and water are cut The scattered β rhyme singularity is made into S :. The mouth split grain crystal element should have some advantages. In the form of element, the element board contains the first element of a package, the quality, the object covers the element and the road Electric edge type isolated ionization hole and fml buried, see the second L seed grain and one crystal supply, and make it clear. The base of the hair board has the phase table mutuality. The electric conductance of the section line has two grains and one crystal on the two sides, and the elementary electric conductance has a first surface and a single surface. The conductive surface is covered with a bell. The first section includes the first section of the package. The conductive surface and the second surface of the conductive surface are connected to each other, and a segment is connected with electricity to form a conductive material. The first surface of the electrical surface and the second surface of the surface are second and second. This section of the crystal power will be electrically connected, the first quality of the electricity-the road buried in the line electricity, the via surface through welding and plating the plating and the second ground of the first electricity and the current. The first surface of the road line meter should be connected to the welding device and the grounded crystal electrical components. Electricity, the second connection, the first part of the electricity

10125 twf1.pt d 第10頁 556261 五、發明說明(4) 粒導電線路之第一導電段上,該晶粒之第一電極係電性地 連結至該晶粒導電線路之第一導電段;且該晶粒之第二電 極係電性地連結至該晶粒導電線路之該第二導電段。電性 絕緣物質則以水氣密封的方式完全包覆該基板第一表面上 之该些元件晶粒及其所有導電線路。 較佳實施例之詳細說明 圖式中之各圖係分別顯示本發明埋孔離散式電路元 件,其較佳實施例製作方法,其中數個選定的過程步驟之 視圖。此些包含了上視圖、橫截面圖以及透視圖等的各種 視圖,係分別顯示本發明埋孔離散式電路元件製作各個步 驟階段之中的階段性構造。下面的說明文字之中將配合此 些選定的階段性步驟,針對本發明埋孔離散式電路元件製 作方法之一較佳實施例來進行詳細說明。 圖1為本發明埋孔離散式電路元件一較佳實施例之基 板之晶粒面平面圖。如圖所示,用以承載整個矩陣排列 的,典型多達數百個離散式電路元件的基板1 0 0 ,晶粒面 110之表面上有多個離散式電路元件之初始導電線路111 , 1 1 2,…及1 1 6等,排列於,例如,二維正交的矩陣之中。 相對於圖1之晶粒面的初始導電線路,基板1 0 0在其圖 1的晶粒面1 1 0之反對表面,亦即元件之焊接面,亦有一個 由多個初始導電線路21 1 ,212,…及214等,排列於對應 的矩陣之中。 圖2係為圖1基板之焊接面之平面圖,其表面上亦有多 個離散式電路元件之初始導電線路排列於矩陣之中。注意10125 twf1.pt d Page 10 556261 V. Description of the invention (4) On the first conductive segment of the grain conductive circuit, the first electrode of the grain is electrically connected to the first conductive segment of the grain conductive circuit; And the second electrode of the grain is electrically connected to the second conductive segment of the grain conductive circuit. The electrically insulating material completely covers the element crystal grains and all conductive lines on the first surface of the substrate in a water-vapor-sealed manner. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Each of the drawings shows a buried-hole discrete circuit element according to the present invention, a method for making the preferred embodiment thereof, and a view of several selected process steps. These include various views such as an upper view, a cross-sectional view, and a perspective view, which respectively show the stepwise structure in each step of manufacturing the buried-hole discrete circuit element according to the present invention. The following explanatory text will cooperate with these selected stepwise steps to describe in detail a preferred embodiment of a method for manufacturing a buried-hole discrete circuit element according to the present invention. FIG. 1 is a plan view of a grain plane of a substrate of a buried-hole discrete circuit component according to a preferred embodiment of the present invention. As shown in the figure, the substrate 100, which typically has hundreds of discrete circuit elements arranged to support the entire matrix arrangement, has a plurality of discrete conductive circuit elements 111, 1 on the surface of the grain plane 110. 1 2,... And 1 1 6 etc. are arranged in, for example, a two-dimensional orthogonal matrix. With respect to the initial conductive line of the grain surface of FIG. 1, the substrate 100 is on the opposite surface of the grain surface 1 10 of FIG. 1, that is, the welding surface of the component, and there is a plurality of initial conductive lines 21 1 , 212, ..., 214, etc. are arranged in the corresponding matrix. Fig. 2 is a plan view of the soldering surface of the substrate of Fig. 1, and the initial conductive lines of a plurality of discrete circuit elements are arranged in a matrix on the surface. note

10125twfl.ptd 第11頁 556261 五、發明說明(5) 到圖2之基板焊接面2 1 0係為圖1之基板晶粒面1 1 〇水平翻轉 所顯示之焊接面導電線路矩陣排列圖形。此可由圖1及2中 晶粒面1 1 0之線路1 1 1係與焊接面2 1 0之線路2 1 1對應,線路 1 1 2與2 1 2對應,…及1 1 4與2 1 4對應而得以理解。 在每一個離散元件的初始導電線路之中(包含晶粒面 及焊接面),在大致位於導電線路的中心位置,各皆形成 有一貫穿孔,實質上垂直貫穿基板1 0 0的整個厚度。例 如,圖1及2中的導電線路1 1 1及對應的2 1 1之中,貫穿有一 貫通孔1 3 1 ,在導電線路1 1 2及對應的2 1 2之中則貫穿有一 貫通孔1 3 2。 每一貫穿孔與其對應在基板之晶粒面及焊接面上的導 電線路之相對位置關係,係顯示於圖3與4之中。圖3係為 圖1之局部放大圖’其顯不基板晶粒面之初始導電線路之 構形細節,而圖4則為圖1及2之基板之橫截面圖。圖1 ,2 及3之中,每一個以虛線所圍繞之大致矩形之區域,如同 後面所將說明的,係代表一個離散電子元件之實體範圍。 例如圖3所示,虛線1 2 1所標示的範圍係為本發明一個完整 埋孔離散式電子元件的實體範圍,其中,於範圍1 2 1内大 致中心之處’如虛線區域1 5 1所標不的位置’係為元件晶 粒所將定置之位置。 注意到圖3之平面圖所顯不’導電線路在基板1 0 0晶粒 面1 1 0上沿長軸方向(圖中之水平方向)之不對稱圖形。依 據本發明埋孔離散式電子元件之一較佳實施例,其導電線 路於圖3中所顯示一個別元件之元件個體腳印(C 〇 m ρ ο n e n t10125twfl.ptd Page 11 556261 V. Description of the invention (5) The substrate welding surface 2 1 to FIG. 2 is the substrate grain surface 1 1 0 of the substrate shown in FIG. This can correspond to the line 1 1 1 of the grain plane 1 1 0 in Figs. 1 and 2 corresponding to the line 2 1 1 of the welding plane 2 1 0, the line 1 1 2 and 2 1 2 correspond to, ... and 1 1 4 and 2 1 4 corresponds and is understood. In the initial conductive lines (including the grain plane and the soldered surface) of each discrete component, a through hole is formed at a position roughly at the center of the conductive line, and penetrates substantially the entire thickness of the substrate 100 vertically. For example, in the conductive lines 1 1 1 and the corresponding 2 1 1 in FIGS. 1 and 2, there is a through hole 1 3 1, and in the conductive lines 1 1 2 and the corresponding 2 1 2, there is a through hole 1. 3 2. The relative positional relationship between each through-hole and its corresponding conductive line on the grain surface and the soldering surface of the substrate is shown in Figs. Fig. 3 is a partial enlarged view of Fig. 1 ', showing details of the configuration of the initial conductive line of the substrate grain plane, and Fig. 4 is a cross-sectional view of the substrate of Figs. In Figs. 1, 2 and 3, each substantially rectangular area surrounded by a dashed line, as will be described later, represents the physical range of a discrete electronic component. For example, as shown in FIG. 3, the range indicated by the dashed line 1 2 1 is the physical range of a complete buried-hole discrete electronic component according to the present invention. Among them, approximately at the center of the range 1 2 1 ′ is indicated by the dashed area 1 5 1. The “not marked position” is the position where the element die will be positioned. It is noted that the asymmetric pattern of the conductive line on the substrate 100 grain surface 1 10 along the long axis (horizontal direction in the figure) shown in the plan view of FIG. 3. According to a preferred embodiment of the buried-hole discrete electronic component according to the present invention, its conductive line is shown in the individual footprint of a component of another component (C 0 m ρ ο n e n t

10125twfl.ptd 第12頁 556261 五、發明說明(6)10125twfl.ptd Page 12 556261 V. Description of the invention (6)

Footprint)範圍121内,沿其短軸方向(圖中之垂直方 向),導電線路1 1 1與1 1 2實質上係呈現大致對稱的圖形。 相較之下,線路1 1 1與1 1 2沿元件腳印的長軸方向則顯 現明顯的不對稱。實質上,導電線路1 1 1與1 1 2係屬互相電 性獨立之兩導電圖形。導電線路1 1 1與1 1 2兩者各具有一段 朝向元件中心延伸之導電線段。兩導電線路其中之一朝向 元件中心,即元件晶粒所將定置之定位延伸,另一導電線 路則未依相當幅度向中心延伸,以便兩者互不接觸,保持 電性互相獨立的開路狀態。 在圖3所顯示之實施例之中,右側之導電線路1 1 1係為 向元件中心延伸較多的導電線路。不過,如同習於本技藝 者所可以理解的,若安排左側的導電線路延伸到達元件中 心,亦同樣是可行的作法。 圖4之橫截面圖顯示,各貫穿孔係為鍍覆貫穿孔(PT Η, Plated Through-Hole)。如圖戶斤示,貫穿孑L131及132 ,利 用諸如ί賤鍵(sputtering),電鑛(electroplating)等製作 印刷電路基板的技術,可以在透通的孔壁上形成導電金屬 層。貫穿孔壁上的此鍍覆金屬層便可以將基板1 0 0的晶粒 面與相對反面的焊接面上的導電線互相電性地連接結起 來。 圖1與2所顯示之基板,係作為本發明埋孔離散式電子 元件之基礎。此基板係為電性絕緣之板材,其可以是,例 如玻璃纖維強化樹酯(F R P ),或者是利用模鑄(m ο 1 d i n g )等 技術,使用適當之絕緣性質材料製作成板材。其後可利用Footprint) In the range 121, along the short axis direction (vertical direction in the figure), the conductive lines 1 1 1 and 1 1 2 are substantially symmetrical figures. In contrast, the lines 1 1 1 and 1 1 2 show a significant asymmetry along the long axis of the component footprint. In essence, the conductive lines 1 1 1 and 1 12 are two conductive patterns that are electrically independent of each other. Each of the conductive lines 1 1 1 and 1 1 2 has a conductive line segment extending toward the center of the element. One of the two conductive lines is oriented toward the center of the component, that is, the positioning of the component grains is extended, and the other conductive line does not extend to the center by a considerable amount so that the two do not contact each other and maintain an electrically open circuit state. In the embodiment shown in FIG. 3, the conductive line 1 1 1 on the right side is a conductive line extending more toward the center of the element. However, as can be understood by those skilled in the art, it is also feasible to arrange the conductive line on the left to reach the center of the component. The cross-sectional view of FIG. 4 shows that each through-hole is a plated through-hole (PTΗ). As shown in the figure, through the 孑 L131 and 132, a conductive metal layer can be formed on the transparent hole wall by using techniques such as duttering, electroplating, etc. to make printed circuit boards. This plated metal layer on the wall of the through hole can electrically connect the conductive lines on the grain surface of the substrate 100 and the soldering surface on the opposite side to each other. The substrate shown in Figs. 1 and 2 serves as the basis for the buried-hole discrete electronic component of the present invention. The substrate is an electrically insulating plate, which can be, for example, glass fiber reinforced resin (F R P), or can be made into a plate using an appropriate insulating material using a technology such as die casting (m ο 1 d i n g). Available later

10125twf1.ptd 第13頁 556261 五、發明說明(7) 諸如顯影餘刻技術(p h 〇 t ο 1 i t h 〇 g r a p h y )而製作晶粒面及焊 接面上之導電線路。 貫穿孔可利用數值加工機具,在如圖3所示之定位 上,鑽孔貫通。其後,如同前述,可利用濺鍍與/或電鍍 等製程而形成鍍覆貫通孔。鍍覆貫通孔形成後,即可獲得 圖1及2所顯示之基板1 0 0。 接著,鍍覆貫通孔内即可埋入具導電性之填充材料。 在本發明埋孔離散式電子元件之一較佳實施例之中,填充 埋入圖1及2所示板之各鍍覆貫通孔内的導電性材料,係 為一般電路板製作所使用之錫,或錫合金導接等物質。 圖3及4中所顯示的基板,其鍍覆貫通孔内已填充埋入 導電性之材質。利用此基板,如圖5所示,接著便可以將 離散式電路元件之晶粒定置於圖3所示之定位1 5 1上。圖5 之橫截面圖顯示一離散式電路元件之晶粒5 1 1被定置於基 板1 0 0之晶粒面1 1 0上。且凡件晶粒5 1 1之電極’並與基板 1 ◦ 0上之晶粒面1 1 0上導電線路1 1 1 A電性地連結。 晶粒5 1 1與導電線路1 1 1 A之電性接合可以利用,例 如,晶粒5 1 1下表面電極上所預先形成之軟焊錫,應用諸 如紅外線迴流(I R R e f 1 〇 w )等類似表面點著元件(S M D )軟焊 之技術而達成。 當電路元件晶粒5 1 1下表面之電極與晶粒面上之導電 線路1 1 1 Α上的達成電性穩固接合之後,晶粒5 1 1另一端, 亦即,頂端上之另一電極,便可以利用諸如跳接線而與基 板1 0 0晶粒面1 1 0上的另一導電線路1 1 2 B,透過導線5 3 1而10125twf1.ptd Page 13 556261 V. Description of the invention (7) The conductive lines on the grain surface and the welding surface are made by the technique of developing after-cut (p h 〇 t ο 1 i t h 〇 g r a p h y). Through-holes can be drilled through numerically-machined tools at the positions shown in Figure 3. Thereafter, as described above, a plating through-hole may be formed by a process such as sputtering and / or plating. After the plated through holes are formed, the substrate 100 shown in Figs. 1 and 2 can be obtained. Then, a conductive filling material can be buried in the plated through hole. In a preferred embodiment of the buried-hole discrete electronic component of the present invention, the conductive material filled in the plated through-holes embedded in the plates shown in FIGS. 1 and 2 is tin used in the manufacture of general circuit boards. Or tin alloy leads. The substrates shown in Figs. 3 and 4 are filled with a conductive material in the plated through holes. Using this substrate, as shown in FIG. 5, the crystal grains of the discrete circuit element can be set on the positioning 1 51 shown in FIG. The cross-sectional view of FIG. 5 shows that the crystal grain 5 1 1 of a discrete circuit element is set on the crystal grain surface 1 1 0 of the substrate 100. Moreover, the electrode ′ of each grain 5 1 1 is electrically connected to the conductive line 1 1 1 A on the grain surface 1 1 0 on the substrate 1 ◦ 0. The electrical connection between the die 5 1 1 and the conductive line 1 1 1 A can be used. For example, a pre-formed solder on the lower surface electrode of the die 5 1 1 is applied, such as infrared reflow (IRR ef 1 〇w). This is achieved by the technology of soldering the surface of the component (SMD). After the electrode on the lower surface of the circuit element die 5 1 1 and the conductive line 1 1 1 A on the die face are electrically and firmly bonded, the other end of the die 5 1 1 is the other electrode on the top. , You can use, for example, a jumper to connect with another conductive line 1 1 2 B on the substrate 100 grain surface 1 1 0 through the wire 5 3 1 and

10125 twfl . ptd 第14頁 556261 五、發明說明(8) 電性地接合。 當完成圖5所顯示之架構之後,各元件晶粒之電極便 已電性地連結到其各自基板範圍(圖1 ,2及3中以虛線所標 示出來之元件範圍)内的對應軟焊接腳上。此時,電性結 構已建構完成,但仍排列於矩陣中之各個埋孔離散式電路 元件,便可以進行水氣密封(sealed hermetically)的處 理。圖6之橫截面圖即顯示圖5之離散式電路元件晶粒被水 密性材料6 0 0包覆之情形。此種密封包覆可以,例如,利 用模鑄的方式進行。只需利用模具在基板1 0 0的晶粒面1 1 0 上方形成一個高度適恰之空間,便可以利用,例如,將熔 融之絕緣材質注入該空間内,便可方便地製成水氣密封裝 6 0 0 ,以將晶粒5 1 1 ,5…等保護於其中。注意到,水氣密 絕緣材質6 0 0之選定,可為與基板1 0 0本身所使用者完全相 同之物質。 之後,圖7之橫截面圖顯示,圖6之基板構造被切割成 分離之離散式電路元件。注意到兩相鄰元件之間的切割, 實質上係對準兩元件之間的埋孔之對稱中心線而進行切割 的。如圖所示,切割圖7中元件7 1 1即須沿切割道7 4 1與7 4 2 進行切割。此外,如同可以理解的,沿著圖中所未標示, 實質上垂直於切割道7 4 1與7 4 2的方向,亦須進行至少二道 切割,才能完整地將元件7 1 1分離出來。 圖8及9之立體圖分別顯示製造完成並經切割分離之單 體離散式電路元件之電極接腳構造。由於切割係如前述, 通過埋孔之對稱中心線而進行的,故圖9之立體圖顯示,10125 twfl. Ptd Page 14 556261 V. Description of the invention (8) Electrically bonding. When the structure shown in Figure 5 is completed, the electrodes of each element die are electrically connected to the corresponding soft soldering pins in their respective substrate ranges (the component ranges indicated by dashed lines in Figures 1, 2 and 3). on. At this time, the electrical structure has been constructed, but the discrete circuit components of each buried hole still arranged in the matrix can be sealed hermetically. The cross-sectional view of FIG. 6 shows a case where the crystal grains of the discrete circuit element of FIG. 5 are covered with a water-tight material 600. This sealing coating can be performed, for example, by die casting. Just use the mold to form a space with an appropriate height above the grain surface 1 10 of the substrate 100, and then use it. For example, injecting molten insulating material into the space, it can be easily made into a water-air seal. Install 6 0 0 to protect the grains 5 1 1, 5 ... It is noted that the choice of the water-air-tight insulating material 600 can be exactly the same as that used by the substrate 100 itself. Thereafter, the cross-sectional view of FIG. 7 shows that the substrate structure of FIG. 6 is cut into discrete discrete circuit elements. Note that the cut between two adjacent elements is essentially a cut made by aligning the symmetrical centerline of the buried hole between the two elements. As shown in the figure, cutting the component 7 1 1 in FIG. 7 requires cutting along the cutting lines 7 4 1 and 7 4 2. In addition, as can be understood, along the directions not shown in the figure, which are substantially perpendicular to the cutting lines 7 4 1 and 7 4 2, at least two cuttings must be performed to completely separate the component 7 1 1. The perspective views of Figs. 8 and 9 respectively show the electrode pin structure of the discrete discrete circuit element which has been manufactured and cut and separated. Since the cutting is performed through the symmetrical centerline of the buried hole as described above, the perspective view of FIG. 9 shows that

10125twfl.ptd 第15頁 556261 五、發明說明(9) 各個元件的兩 高於基板上之 埋孔填充物質 度。在本發明 行軟焊時,此 本發明埋 通孔之基板作 製程的初期, 之指定形成範 空間,因此, 晶粒。換句話 可以盡可能地 件,諸如0 6 0 3 之中使用二道 安全空間,故 離散式電子元 雖然前面 整的說明,但 應用仍是可能 廣泛地以離散 藝之士所可以 尺寸的離散式 散式電容,無 動或積體電路 電極,皆可具有一個面積夠大,且高度顯著 初導電線路厚度的一個導電接面,如圖9中 1 4 2沿著垂直於基板平面之方向所出現的高 各個埋孔離散式電子元件於印刷電路板上進 導電接面可以確保良好的軟焊品質。 孔離散式電路元件’雖然使用一片形成有貫 為建構整個矩陣的多個元件之基礎,但在其 此些貫通孔便被埋實。因此,在每一個元件 圍之中,由於不需要再預留後續鑽孔處理的 整個元件之範圍便可以充份運用來承載元件 說,元件在基板上所必須佔用的最小空間便 縮小。此種特電極為適合於製作微小型的元 甚至0 4 0 2規格的元件。相較之下,習知技術 鑽孔處理程序的製程,由於必須保留鑽孔的 其元件尺寸便無法如同本發明所揭示之埋孔 件一樣地縮到最小。 的說明文字已是本發明特定實施例的一個完 其各種的修改變化,變動的構造及等效者的 的。例如,雖然前述實施例之詳細說明中只 式電路元件來說明本發明,但如同習於本技 理解者,SMT型式之下,El A標準晶片的各種 二極體,諸如Zener,Schottky等,或者離 論是有否極性,或者離散式電阻,甚至是主 本質,但只需使用二電性接頭的電子元件,10125twfl.ptd Page 15 556261 V. Description of the invention (9) Two parts of each component are higher than the buried hole filling material on the substrate. During the soldering process of the present invention, in the initial stage of the manufacturing process of the substrate with buried vias of the present invention, the designated formation space is defined, and therefore, the crystal grains. In other words, it is possible to use as many pieces as possible, such as using two safe spaces in 0 6 0 3. Therefore, although the discrete electronic element has been described in the foregoing, the application is still widely possible with the discrete size of the discrete artisan. The bulk capacitors, either non-moving or integrated circuit electrodes, can have a conductive junction with a large enough area and a highly significant initial conductive line thickness, as shown in Figure 9 along the direction perpendicular to the substrate plane. The emergence of high discrete electronic components with various buried holes on the printed circuit board into the conductive interface can ensure good soldering quality. Although the hole-discrete circuit element 'uses a base formed with a plurality of elements that are used to construct the entire matrix, the through-holes are buried therein. Therefore, in each component area, since the entire component area does not need to be reserved for subsequent drilling processing, it can be fully used to carry the component. The minimum space that the component must occupy on the substrate is reduced. This special electrode is suitable for making micro-sized elements and even 0 4 0 2 components. In contrast, in the conventional drilling process, the component size cannot be reduced to the minimum as the buried hole disclosed in the present invention because the component size of the drilling must be kept. The descriptive text is a specific embodiment of the present invention which has been completed with various modifications, changes in construction, and equivalents. For example, although only the circuit elements are used to describe the present invention in the detailed description of the foregoing embodiments, as understood by those skilled in the art, under the SMT type, various diodes of the El A standard wafer, such as Zener, Schottky, etc., or Whether there is polarity, or discrete resistance, or even the main nature, but only the electronic components of the electrical connector are used.

10125 twfl.ptd 第16頁 556261 五、發明說明(ίο) 皆是可以適用於本發明所揭示之製作方法。此外,本發明 不但適用於常見的1210 ,1206 ,以及0805等SMT型EIA標準 晶片尺寸,其更係特別適於更為小型的S Μ T型離散式電路 元件。再例如,說明中基板之晶粒面上之該些導電線路可 為固化之膏狀銀膠,固化之膏狀銅膠,或固化之膏狀銅合 金膠。又例如,該板之焊接面上之該些導電線路上更可覆 有一鎳層與或一金層。因此,前面的描述說明即不應被拿 來限定本發明,而其範疇應以後附之申請專利範圍乙節文 字内容來加以界定。10125 twfl.ptd Page 16 556261 V. Description of the Invention (ίο) are applicable to the manufacturing methods disclosed in the present invention. In addition, the present invention is not only applicable to the common SMT-type EIA standard chip sizes such as 1210, 1206, and 0805, but it is also particularly suitable for smaller SMT discrete circuit components. For another example, the conductive lines on the grain surface of the substrate may be cured silver paste, cured copper paste, or cured copper alloy paste. For another example, the conductive lines on the welding surface of the board may be further covered with a nickel layer or a gold layer. Therefore, the foregoing description should not be used to limit the present invention, and its scope should be defined in the text of the scope of section B of the attached patent application.

111U1111U1

10125twfl.ptd 第17頁 556261 圖式簡單說明 本發明之前述目的及其他特徵與優點,在參考所附圖 式而於後面的說明文字之中,配合說明而非限定性質的較 佳實施例進行詳細說明之後,當可更易於獲得瞭解。圖式 中之各圖係分別顯示本發明離散式電路元件,於較佳實施 例製作方法之製程步驟過程中,其某些選定階段的構造視 圖,其中: 圖1為本發明埋孔離散式電路元件一較佳實施例之基 板之晶粒面平面圖; 圖2為圖1基板之焊接面之平面圖; 圖3為圖1之局部放大圖,顯示基板晶粒面之初始導電 線路之構形細節; 圖4為圖1及2之基板之橫截面圖; 圖5之橫截面圖顯示一離散式電路元件被定置於基板 之晶粒面上,並形成元件電極之電性連結; 圖6之橫截面圖顯示圖5之離散式電路元件被水密性材 料包覆, 圖7之橫截面圖顯示圖6之基板構造被切割成分離之離 散式電路元件;與 圖8及圖9之立體圖分別顯示製造完成並經切割分離之 離散式電路元件之單體構造。10125twfl.ptd Page 17 556261 The drawings briefly explain the foregoing objects and other features and advantages of the present invention. In the following description with reference to the attached drawings, detailed descriptions are given in conjunction with the description rather than limiting the preferred embodiments of the nature. After explanation, it will be easier to understand. Each of the drawings shows the discrete circuit components of the present invention. During the process steps of the manufacturing method of the preferred embodiment, the structural views of certain selected stages are shown in the drawings. FIG. 1 is a buried-hole discrete circuit of the present invention. A plan view of the grain surface of the substrate of a preferred embodiment of the device; FIG. 2 is a plan view of the soldering surface of the substrate of FIG. 1; FIG. 3 is a partial enlarged view of FIG. Fig. 4 is a cross-sectional view of the substrate of Figs. 1 and 2; Fig. 5 is a cross-sectional view of a discrete circuit element placed on a die surface of the substrate and forming an electrical connection of the element electrodes; The figure shows that the discrete circuit element of FIG. 5 is covered with a water-tight material, the cross-sectional view of FIG. 7 shows that the substrate structure of FIG. 6 is cut into discrete discrete circuit elements; and the perspective views of FIG. 8 and FIG. 9 respectively show that the manufacturing is completed The individual structure of discrete circuit components separated by cutting.

10125twfl.ptd 第18頁10125twfl.ptd Page 18

Claims (1)

556261 六、申請專利範圍 1. 一種埋孔離散式電路元件之製作方法,其步驟包 含有: (a ) 在一基板之第一表面上形成一個矩陣複數個的元 件晶粒面導電線路,每一個該些晶粒面導電線路各包含有 電性互相獨立之一第一導電段及一第二導電段; (b ) 對應地在該基板反對於該第一表面之第二表面上 形成一個矩陣複數個的焊接面導電線路,每一個該些焊接 面導電線路各包含有電性互相獨立之一第一導電段及一第 二導電段,且該晶粒面導電線路之該第一及第二導電段係 以内埋導電物.質之鍍覆貫穿孔而電性地分別與該焊接面導 電線路之該第一及第二導電段電性連結; (c ) 在該第一表面之晶粒導電線路之第一導電段上定 置一元件晶粒,並將該晶粒之第一電極電性地連結至該晶 粒導電線路之第一導電段; (d ) 將該元件晶粒之第二電極電性地連結至該晶粒導 電線路之該第二導電段; (e ) 以電性絕緣物質水氣密地完全包覆該基板第一表 面上之該些元件晶粒及其所有導電線路;以及 (f ) 切割該被水氣密封之基板,以將所有該些元件晶 粒分割成為個體獨立之離散式電子元件。 2. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該基板之該晶粒面上之該些導電線路係 為固化之膏狀銀膠。 3. 如申請專利範圍第1項所述之埋孔離散式電路元件556261 VI. Scope of patent application 1. A method for manufacturing buried-hole discrete circuit elements, the steps include: (a) forming a matrix of a plurality of element grain plane conductive lines on a first surface of a substrate, each The grain-plane conductive lines each include a first conductive segment and a second conductive segment that are electrically independent of each other; (b) correspondingly forming a matrix complex number on a second surface of the substrate opposing the first surface Each of the welding surface conductive circuits each includes a first conductive segment and a second conductive segment which are electrically independent of each other, and the first and second conductive segments of the grain surface conductive circuit The segments are electrically connected to the first and second conductive segments of the conductive line of the welding surface with embedded conductive through-holes through the plated through holes. (C) Grain conductive lines on the first surface. A component die is placed on the first conductive segment, and the first electrode of the die is electrically connected to the first conductive segment of the conductive circuit of the die; (d) the second electrode of the component die is electrically connected; To the die The second conductive segment of the conductive line; (e) completely sealing the element crystal grains and all conductive lines on the first surface of the substrate with an electrically insulating material water-tightly; and (f) cutting the coated water The substrate is hermetically sealed to separate all the element dies into individual discrete electronic components. 2. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of the patent application, wherein the conductive lines on the grain surface of the substrate are solidified silver paste. 3. Buried via discrete circuit components as described in item 1 of the patent application 10125twf1.ptd 第19頁 556261 六、申請專利範圍 之製作方法’其中該基板之該晶粒面上之該些導電線路係 為固化之膏狀銅膠。 4 . 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該基板之該晶粒面上之該些導電線路係 為固化之膏狀銅合金膠。 5. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該基板之該焊接面上之該些導電線路上 更覆有一錄層。 6. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該基板之該焊接面上之該些導電線路上 更覆有一金層。 7. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該電路元件晶粒係為二極體晶粒。 8. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其中該電路元件晶粒係為電晶體晶粒。 9. 如申請專利範圍第1項所述之埋孔離散式電路元件 之製作方法,其令該電路元件晶粒係為電容晶粒。 10. 如申請專利範圍第1項所述之埋孔離散式電路元 件之製作方法,其中該電路元件晶粒係為電阻晶粒。 11. 如申請專利範圍第1項所述之埋孔離散式電路元 件之製作方法,其中該電路元件晶粒係為包含有主動與被 動電路組件之晶粒。 12. 一種埋孔離散式電路元件之製作方法,其步驟包 含有··10125twf1.ptd Page 19 556261 VI. Manufacturing method of patent application scope ', wherein the conductive lines on the grain surface of the substrate are solidified copper paste. 4. The method for manufacturing a buried-hole discrete circuit component as described in item 1 of the scope of the patent application, wherein the conductive lines on the grain surface of the substrate are solidified copper alloy paste. 5. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of the patent application, wherein the conductive lines on the soldering surface of the substrate are further covered with a recording layer. 6. The manufacturing method of the buried-hole discrete circuit element according to item 1 of the scope of patent application, wherein the conductive lines on the soldering surface of the substrate are further covered with a gold layer. 7. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of the patent application, wherein the crystal element of the circuit element is a diode crystal. 8. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of patent application, wherein the crystal element of the circuit element is a transistor crystal. 9. According to the method for manufacturing a buried-hole discrete circuit element described in item 1 of the scope of the patent application, the crystal element of the circuit element is a capacitor crystal. 10. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of patent application, wherein the crystal grain of the circuit element is a resistive crystal grain. 11. The method for manufacturing a buried-hole discrete circuit element as described in item 1 of the scope of the patent application, wherein the circuit element die is a die that includes active and passive circuit components. 12. A method for manufacturing a buried-hole discrete circuit element, the steps include: 10125twfl.ptd 第20頁 556261 六、申請專利範圍 (a) 在一基板之第一表面上形成一個矩陣複數個的元 件晶粒面導電線路,每一個該些晶粒面導電線路各包含有 電性互相獨立之一第一導電段及一第二導電段; (b ) 對應地在該基板反對於該第一表面之第二表面上 形成一個矩陣複數個的焊接面導電線路,每一個該些焊接 面導電線路各包含有電性互相獨立之一第一導電段及一第 二導電段,且該晶粒面導電線路之該第一及第二導電段係 電性地分別與該焊接面導電線路之該第一及第二導電段電 性連結; .(c ) 在該第一表面之晶粒導電線路之第一導電段上定 置一元件晶粒,並將該晶粒之第一電極電性地連結至該晶 粒導電線路之第一導電段; (d ) 將該元件晶粒之第二電極電性地連結至該晶粒導 電線路之該第二導電段; (e ) 以電性絕緣物質水氣密地完全包覆該基板第一表 面上之該些元件晶粒及其所有導電線路,以及 (f ) 切割該被水氣密封之基板,以將所有該些元件晶 粒分割成為個體獨立之離散式電子元件。 13. 如申請專利範圍第1 2項所述之埋孔離散式電路元 件之製作方法,其中該晶粒面導電線路之該第一及第二導 電段係以内埋導電物質之鍍覆貫穿孔而電性地分別與該焊 接面導電線路之該第一及第二導電段電性連結。 14. 一種埋孔離散式電路元件,其包含有: 一基板,其第一表面上形成有一元件晶粒面導電線10125twfl.ptd Page 20 556261 6. Scope of patent application (a) Form a matrix of multiple element grain plane conductive circuits on the first surface of a substrate, each of these grain plane conductive circuits contains electrical properties A first conductive segment and a second conductive segment that are independent of each other; (b) correspondingly forming a matrix of a plurality of bonding surface conductive lines on a second surface of the substrate opposing the first surface, each of which is soldered Each of the surface conductive circuits includes a first conductive segment and a second conductive segment that are electrically independent of each other, and the first and second conductive segments of the grain surface conductive circuit are electrically connected to the welding surface conductive circuit, respectively. The first and second conductive segments are electrically connected; (c) a component die is placed on the first conductive segment of the grain conductive circuit on the first surface, and the first electrode of the die is electrically connected Ground is connected to the first conductive segment of the grain conductive line; (d) the second electrode of the element die is electrically connected to the second conductive segment of the grain conductive line; (e) is electrically insulated Substance water completely and air-tightly covers the base All the plurality of conductive traces and die member, and the substrate (f) cutting the sealed surface of the water vapor of the first, to all of the plurality of elements of the crystal grains is divided into an independent individual discrete electronic components. 13. The method for manufacturing a buried-hole discrete circuit element as described in item 12 of the scope of the patent application, wherein the first and second conductive sections of the grain plane conductive line are plated through-holes with a conductive material embedded therein. Electrically and electrically connected to the first and second conductive sections of the conductive line of the welding surface, respectively. 14. A buried-hole discrete circuit component comprising: a substrate having a component grain plane conductive line formed on a first surface thereof 10125twfl.ptd 第21頁 556261 六、申請專利範圍 路,其包含有電性互相獨立之一第一導電段及一第二導電 段;其反對於該第一表面之第二表面上形成有一焊接面導 電線路,其包含有電性互相獨立之一第.一導電段及一第二 導電段;一第一鍍覆貫穿孔,内埋導電物質,並將該晶粒 面導電線路之該第一導電段電性地與該焊接面導電線路之 該第一導電段電性連結;及一第二鍍覆貫穿孔,内埋導電 物質,並將該晶粒面導電線路之該第二導電段電性地與該 焊接面導電線路之該第二導電段電性連結; 一元件晶粒,定置於該第一表面之晶粒導電線路之第 一導電段上,該晶粒之第一電極係電性地連結至該晶粒導 電線路之第一導電段;且該晶粒之第二電極係電性地連結 至該晶粒導電線路之該第二導電段;以及 電性絕緣物質,水氣密地完全包覆該基板第一表面上 之該些元件晶粒及其所有導電線路。 15. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該基板之該晶粒面上之該些導電線路係為固化之 膏狀銀膠。 16. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該基板之該晶粒面上之該些導電線路係為固化之 膏狀銅膠。 17. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該基板之該晶粒面上之該些導電線路係為固化之 膏狀銅合金膠。 18. 如申請專利範圍第1 4項所述之埋孔離散式電路元10125twfl.ptd Page 21 556261 VI. Patent Application Road, which includes a first conductive segment and a second conductive segment that are electrically independent of each other; it opposes the formation of a welding surface on the second surface of the first surface A conductive circuit including a first conductive segment and a second conductive segment that are electrically independent of each other; a first plated through-hole, a conductive substance is embedded, and the first conductive surface of the grain plane conductive circuit The second conductive segment is electrically connected to the first conductive segment of the conductive line of the welding surface; and a second plated through hole is embedded with a conductive substance, and the second conductive segment of the grain surface conductive line is electrically connected Ground is electrically connected to the second conductive segment of the conductive line of the welding surface; a component grain is placed on the first conductive segment of the grain conductive line on the first surface, and the first electrode of the grain is electrically Ground is connected to the first conductive segment of the grain conductive line; and the second electrode of the grain is electrically connected to the second conductive segment of the grain conductive line; and an electrically insulating substance, water-tightly Completely covering the first surface of the substrate These devices all of the conductive lines and die. 15. The buried-hole discrete circuit element as described in item 14 of the scope of patent application, wherein the conductive lines on the grain surface of the substrate are solidified paste-like silver glue. 16. The buried-hole discrete circuit element according to item 14 of the scope of the patent application, wherein the conductive lines on the grain surface of the substrate are solidified copper paste. 17. The buried-hole discrete circuit element according to item 14 of the scope of the patent application, wherein the conductive lines on the grain surface of the substrate are solidified paste-like copper alloy glue. 18. Buried-hole discrete circuit elements as described in item 14 of the scope of patent application 10125twf1.ptd 第22頁 556261 六、申請專利範圍 件,其中該基板之該焊接面上之該些導電線路上更覆有一 鎳層。 19. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該基板之該焊接面上之該些導電線路上更覆有一 金層。 2 0· 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該電路元件晶粒係為二極體晶粒。 2 1. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該電路元件晶粒係為電晶體晶粒。 22 . 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該電路元件晶粒係為電容晶粒。 2 3. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該電路元件晶粒係為電阻晶粒。 24. 如申請專利範圍第1 4項所述之埋孔離散式電路元 件,其中該電路元件晶粒係為包含有主動與被動電路組件 之晶粒。10125twf1.ptd Page 22 556261 6. The scope of patent application, in which the conductive lines on the soldering surface of the substrate are further covered with a nickel layer. 19. The buried-hole discrete circuit element according to item 14 of the scope of patent application, wherein the conductive lines on the soldering surface of the substrate are further covered with a gold layer. 2 0. The buried-hole discrete circuit element as described in item 14 of the scope of patent application, wherein the crystal element of the circuit element is a diode crystal. 2 1. The buried-hole discrete circuit element as described in item 14 of the scope of patent application, wherein the crystal element of the circuit element is a transistor crystal. 22. The buried-hole discrete circuit element according to item 14 of the scope of patent application, wherein the crystal element of the circuit element is a capacitor crystal. 2 3. The buried-hole discrete circuit element according to item 14 of the scope of patent application, wherein the crystal element of the circuit element is a resistor crystal. 24. The buried-hole discrete circuit element as described in item 14 of the scope of patent application, wherein the die of the circuit element is a die including active and passive circuit components. 10125twfl.ptd 第23頁10125twfl.ptd Page 23
TW91122469A 2002-09-30 2002-09-30 Buried discrete circuit components and fabricating method thereof TW556261B (en)

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