TW200847350A - Package structure and electronic device using the same - Google Patents
Package structure and electronic device using the same Download PDFInfo
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- TW200847350A TW200847350A TW096118601A TW96118601A TW200847350A TW 200847350 A TW200847350 A TW 200847350A TW 096118601 A TW096118601 A TW 096118601A TW 96118601 A TW96118601 A TW 96118601A TW 200847350 A TW200847350 A TW 200847350A
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- Prior art keywords
- wafer
- package structure
- electronic device
- external signal
- window member
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0067—Packages or encapsulation for controlling the passage of optical signals through the package
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0083—Temperature control
- B81B7/009—Maintaining a constant temperature by heating or cooling
- B81B7/0093—Maintaining a constant temperature by heating or cooling by cooling
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/04—Optical MEMS
- B81B2201/042—Micromirrors, not used as optical switches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
200847350200847350
CONFIDENTIAL 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種封裝結構及應用其之電子裝置 裝置,且特別是有關於一種用於接收一外部訊號之封裝結 構及應用其之電子裝置。 【先前技術】 目前市面上投影機之形式包括液晶(Hquid crystal display,LCD)投影機、數位光學處理(digital Hght processing,DLP)投影機及陰極射線管(cath〇de ray tube, CRT)投影機等。 以數位光學處理投影機為例,數位微鏡元件係為投影 成像之關鍵元件。請參照第1圖,其繪示傳統之數位微鏡 元件之示意圖。數位微鏡元件100包括一基板110、一散 熱片120、一封膠130及一玻璃結構160及一晶片14〇。 基板具有一開口 113。散熱片120係覆蓋開口 113。散熱 、 片120用以承載晶片140,並將晶片140產生之熱量傳導 離開晶片140。玻璃結構160係設置於晶片140之上方。 封膠130係覆蓋晶片140、玻璃結構160及基板11〇。 光線150係經由封膠130及玻璃結構160以接觸晶片 140。然而,受限於封膠130之材質特性,封膠130之表 面通常為不平滑之表面。當光線150通過封膠130及玻璃 結構160時往往會產生散射及反射的現象。如此一來,對 於成像之效果即有所影響。 5 200847350TECHNICAL FIELD The present invention relates to a package structure and an electronic device device using the same, and more particularly to a package structure for receiving an external signal and an electronic device using the same . [Prior Art] Currently, the form of the projector on the market includes a liquid crystal (Hquid crystal display (LCD) projector, a digital optical processing (DLP) projector, and a cathode ray tube (CRT) projector. Wait. Taking digital optical processing projectors as an example, digital micromirror components are the key components of projection imaging. Please refer to Fig. 1, which shows a schematic diagram of a conventional digital micromirror device. The digital micromirror device 100 includes a substrate 110, a heat sink 120, an adhesive 130, and a glass structure 160 and a wafer 14A. The substrate has an opening 113. The heat sink 120 covers the opening 113. The heat sink, sheet 120 is used to carry the wafer 140 and conduct heat generated by the wafer 140 away from the wafer 140. The glass structure 160 is disposed above the wafer 140. The sealant 130 covers the wafer 140, the glass structure 160, and the substrate 11A. Light 150 is passed through sealant 130 and glass structure 160 to contact wafer 140. However, limited by the material properties of the sealant 130, the surface of the sealant 130 is typically a non-smooth surface. When the light 150 passes through the sealant 130 and the glass structure 160, scattering and reflection tend to occur. As a result, the effect on imaging is affected. 5 200847350
CONFIDENTIAL 【發明内容】 本發明係有關於一種封裝結構及應用其之電子裝 置,其利用使外部訊號穿透通過一遮罩之方式,避免外部 訊號反射或散射,係可提升封裝結構及應用其之電子裝置 之光學表現。 根據本發明之弟一方面’提出一種封裝結構。此封裝 結構包括一晶片椒組及一遮罩。晶片模組用以接收一外部 號。遮罩係遮蓋於晶片模組上。遮罩具有一視窗件。外 f 部訊號穿透通過視窗件接觸晶片模組。 根據本發明之弟一方面,提出一種電子裝置。電子裝 置包括一外部訊號源及一封裝結構。外部訊號源用以提供 一外部訊號。封裝結構包括一晶片模組及一遮罩。晶片模 組用以接收外部訊號。遮罩係遮蓋於晶片模組上。遮罩具 有一視窗件。外部訊號穿透通過視窗件接觸晶片模組。 為讓本發明之上述内容能更明顯易懂,下文特舉一較 佳貫施例,並配合所附圖式,作詳細說明如下: 【實施方式】 請同時參照第2圖及第3圖,第2圖繪示依照本發明 一較佳實施例之電子裝置之示意圖;第3圖繪示第2圖之 封裝結構之示意圖。電子裝置2〇〇包括一外部訊號源3〇〇 以及一封裝結構400。外部訊號源3〇〇係用以提供一外部 訊號310。封裝結構4〇〇包括一晶片模组41〇及一遮罩43〇 (、’’曰示於第3圖中)。晶片模組4〇〇用以接收外部訊號 6 200847350The present invention relates to a package structure and an electronic device using the same, which utilizes an external signal to penetrate through a mask to avoid reflection or scattering of external signals, thereby improving the package structure and applying the same. Optical performance of electronic devices. According to one aspect of the invention, a package structure is proposed. The package structure includes a wafer set and a mask. The chip module is configured to receive an external number. The mask is covered on the wafer module. The mask has a window piece. The outer f-signal penetrates through the window member to contact the wafer module. According to an aspect of the invention, an electronic device is proposed. The electronic device includes an external signal source and a package structure. The external signal source is used to provide an external signal. The package structure includes a wafer module and a mask. The chip module is used to receive external signals. The mask is covered on the wafer module. The mask has a window member. The external signal penetrates through the window member to contact the wafer module. In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings, in which: FIG. 2 and FIG. 2 is a schematic view of an electronic device according to a preferred embodiment of the present invention; and FIG. 3 is a schematic view showing a package structure of FIG. 2. The electronic device 2 includes an external signal source 3A and a package structure 400. The external signal source 3 is used to provide an external signal 310. The package structure 4 includes a wafer module 41 and a mask 43 (shown in FIG. 3). The chip module 4 is configured to receive an external signal 6 200847350
CONFIDENTIAL 310。遮罩430係遮蓋於晶片模組4i〇上,並具有一視窗 件432。外部訊號310係穿透通過視窗件432接觸晶片模 組 410。 於本實施例中,視窗件432係為表面平滑之平板狀結 構。因此,本實施例之實施方式係可避免外部訊號310於 通過時反射或散射,以增加外部訊號310之利用率。此外, 於本實施例中,外部訊號源300係為一光源,外部訊號310 係為一光線。 1 上述之電子裝置200係以一數位投影機為例作說 明。如第3圖所示,封裝結構400之晶片模組410包括一 基板415、一散熱片413、一第一晶片411及一第二晶片 412。基板415具有一第一表面415a、一第二表面415b及 一開口 415c。第一表面415a係相對於第二表面415b。開 口 415c係貫穿第一表面415a及第二表面415b。於本實施 例中’基板415係可為一印刷電路板(printed circuit board ’ PCB)或一三氮雜苯雙馬來醯亞胺樹脂 、 (bismaleimide triazine,BT)板。此外,封裝結構 400 例 如是一平格陣列(land grid array,LGA)封裝結構或一球格 陣列(ball grid array,BGA)封裝結構。 至於散熱片413係設置於基板415之第一表面415a, 且散熱片413係覆蓋開口 415c。第一晶片411係設置於散 熱片413上,且位於開口 415c内。第一晶片411之一下 表面411a係平貼於散熱片413。散熱片413用以將第一晶 片411產生之熱傳導離開。 7 200847350CONFIDENTIAL 310. The mask 430 is covered on the wafer module 4i and has a window member 432. The external signal 310 penetrates through the window member 432 to contact the wafer module 410. In the present embodiment, the window member 432 is a flat plate-like structure having a smooth surface. Therefore, the embodiment of the embodiment can prevent the external signal 310 from being reflected or scattered when passing, so as to increase the utilization of the external signal 310. In addition, in this embodiment, the external signal source 300 is a light source, and the external signal 310 is a light. 1 The electronic device 200 described above is exemplified by a digital projector. As shown in FIG. 3, the wafer module 410 of the package structure 400 includes a substrate 415, a heat sink 413, a first wafer 411, and a second wafer 412. The substrate 415 has a first surface 415a, a second surface 415b, and an opening 415c. The first surface 415a is relative to the second surface 415b. The opening 415c extends through the first surface 415a and the second surface 415b. In the present embodiment, the substrate 415 can be a printed circuit board (PCB) or a bismaleimide triazine (BT) plate. In addition, the package structure 400 is, for example, a land grid array (LGA) package structure or a ball grid array (BGA) package structure. The heat sink 413 is disposed on the first surface 415a of the substrate 415, and the heat sink 413 covers the opening 415c. The first wafer 411 is disposed on the heat sink 413 and is located in the opening 415c. The lower surface 411a of one of the first wafers 411 is flat on the heat sink 413. The heat sink 413 is used to conduct heat generated by the first wafer 411 away. 7 200847350
uuiN^iubjNTlAL 於本實施例中,第一晶片411係打線接合於基板 15 中,第一晶片411具有至少一第一電性連接墊441, 第一電性連接墊441設置於第一晶片411上。基板415具 有至少一第二電性連接墊443,第二電性連接墊443設置 於^二表面415b。第一電性連接墊441利用一導線442連 接第二電性連接墊443 ’以使第一晶片411與基板415電 ί"連接基板415更具有多個第三電性連接塾445,第三 電性連接墊445設置於第一表面仙。第三電性連接^ 秘用以電性連接基板415及其他電子元件(未繪示)。 此外’本實施例之第二晶# 412係設置於第一晶片 川上’且第二晶片化係電性連接於第一晶片化。較 佳地’第二晶片412係以覆晶方式電性連接第-晶片411, 也就是如第3圖所示,H - ’丁弟一曰日片412利用至少一覆晶凸塊 (mP chlp bumP)447與第一晶片411電性連接。當然,第 一晶片4U與第二晶片412亦可利用例如是打線接合方式 相互電性連接。 本貫知例之第一曰曰片412係接收外部訊號31〇,並輸 測訊號至第-晶片411。第一晶片紹系接收 =此感測訊號,進—步根據❹桃號輸出-電性訊號。電 性訊號係可輸出至基板415上之1他元 = 行其他例如是運算或儲存之動作。 s 進 視窗件432係對應於第二曰曰/片似之位置,且視窗件 432*較佳之尺寸是大於或等於第二晶片412之尺寸。此外, 視固件432係為透光材質,例如是—紅外線濾光片,以於 8 200847350In the present embodiment, the first wafer 411 is bonded to the substrate 15 , and the first wafer 411 has at least one first electrical connection pad 441 . The first electrical connection pad 441 is disposed on the first wafer 411 . . The substrate 415 has at least one second electrical connection pad 443, and the second electrical connection pad 443 is disposed on the second surface 415b. The first electrical connection pad 441 is connected to the second electrical connection pad 443 ′ by a wire 442 to make the first wafer 411 and the substrate 415 electrically connected to the substrate 415 to have a plurality of third electrical connections 445, the third The sexual connection pad 445 is disposed on the first surface. The third electrical connection is used to electrically connect the substrate 415 and other electronic components (not shown). Further, the second crystal #412 of the present embodiment is disposed on the first wafer and the second wafer is electrically connected to the first wafer. Preferably, the second wafer 412 is electrically connected to the first wafer 411 in a flip chip manner, that is, as shown in FIG. 3, the H-'Dingdi 曰 片 412 utilizes at least one flip chip (mP chlp). The bumP) 447 is electrically connected to the first wafer 411. Of course, the first wafer 4U and the second wafer 412 can also be electrically connected to each other by, for example, wire bonding. The first slice 412 of the present example receives the external signal 31 and transmits a signal to the first wafer 411. The first wafer is received = this sensing signal, and the step is based on the output of the peach - electrical signal. The electrical signal can be output to the NAND on the substrate 415 = other actions such as arithmetic or storage. The s-window member 432 corresponds to the second 曰曰/chip-like position, and the window member 432* preferably has a size greater than or equal to the size of the second wafer 412. In addition, the firmware 432 is a light-transmitting material, for example, an infrared filter, for 8 200847350
CUNFlDJbNTIAL 外部訊號310穿透通過視窗件423時,適度地過濾外部訊 號310。於本實施例中,視窗件432係為表面平滑之平板 狀結構,因此,當外部訊號310穿透通過視窗件423時, 係可避免發生反射或散射之現象,進而增加外部訊號310 整體之穿透率,提升了外部訊號310之利用率。 綜上所述,當外部訊號310穿透通過視窗件432後係 接觸晶片模組410之第二晶片412。第二晶片412係接收 外部訊號310,並輸出感測訊號至第一晶片411。第一晶 片411係根據感測訊號輸出電性訊號,以進行電性訊號之 運算或儲存之動作。此外,第一晶片411亦可將運算處理 過後之電性訊號傳輸至第二晶片412,並且由第二晶片412 根據外部訊號310及電性訊號反射一反射訊號550。反射 訊號550係通過電子裝置200(如第2圖所示)之一投影鏡 頭(未繪示),進一步投射於一屏幕(未繪示)上,以顯示晝面。 本發明上述實施例所揭露之封裝結構及應用其之電 子裝置,藉由一外訊號源提供一外部訊號,並且使外部訊 號經由穿透通過遮罩之視窗件接觸第二晶片,藉以使得晶 片模組接收到外部訊號。視窗件係為表面平滑之平板狀結 ,丄避免外部訊號穿透視窗件時發生散射及反射的現象, 提高了晶片模組對於外部訊號之接收效率,進一步提升了 外部訊號之利用率。 、絲上所述,雖然本發明已以一較佳實施例揭露如上, 並非用以限定本發明。本發明所屬技術領域中具有通 ΐ知識者,在不脫離本發明之精神和範圍内,當可作各種 9 200847350When the CUNF1DJbNTIAL external signal 310 penetrates through the window member 423, the external signal 310 is moderately filtered. In the present embodiment, the window member 432 is a flat-shaped flat surface structure. Therefore, when the external signal 310 penetrates through the window member 423, reflection or scattering is prevented, thereby increasing the overall wear of the external signal 310. The penetration rate improves the utilization of the external signal 310. In summary, when the external signal 310 penetrates through the window member 432, it contacts the second wafer 412 of the wafer module 410. The second wafer 412 receives the external signal 310 and outputs a sensing signal to the first wafer 411. The first wafer 411 outputs an electrical signal according to the sensing signal to perform an operation or storage of the electrical signal. In addition, the first chip 411 can also transmit the electrical signal after the processing to the second wafer 412, and the second chip 412 reflects the reflected signal 550 according to the external signal 310 and the electrical signal. The reflection signal 550 is further projected on a screen (not shown) by a projection lens (not shown) of the electronic device 200 (shown in FIG. 2) to display the surface. The package structure and the electronic device using the same according to the above embodiments of the present invention provide an external signal by an external signal source, and the external signal contacts the second wafer via the window member penetrating through the mask, thereby causing the wafer die The group received an external signal. The window member is a flat-shaped flat surface with a smooth surface, which avoids the scattering and reflection of external signals passing through the window member, improves the receiving efficiency of the chip module for external signals, and further improves the utilization of external signals. The invention has been described above in terms of a preferred embodiment, and is not intended to limit the invention. Those skilled in the art having the knowledge of the present invention can make various kinds without departing from the spirit and scope of the present invention.
CONFIDENTIAL > 之更動與潤飾。因此,本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 200847350Change and retouch of CONFIDENTIAL >. Therefore, the scope of the invention is defined by the scope of the appended claims. 200847350
UUNJhiJJbJNTIAL ' 【圖式簡單說明】 第1圖繪示傳統之數位微鏡元件之示意圖。 第2圖繪示依照本發明一較佳實施例之電子裝置之 示意圖。 第3圖繪示第2圖之封裝結構之示意圖。 【主要元件符號說明】 100 : 數位微鏡元件 110、 415 :基板 113 : 開口 120、 413 :散熱片 130 : 封膠 140 : 晶片 150 : 光線 160 : 玻璃結構 200 : 電子裝置 300 : 外部訊號源 310 : 外部訊號 400 : 封裝結構 410 : 晶片模組 411 : 第一晶片 411a :下表面 412 :第二晶片 415a ··第一表面 11 200847350UUNJhiJJbJNTIAL ' [Simple description of the diagram] Figure 1 shows a schematic diagram of a conventional digital micromirror component. 2 is a schematic diagram of an electronic device in accordance with a preferred embodiment of the present invention. FIG. 3 is a schematic view showing the package structure of FIG. 2. [Main component symbol description] 100: Digital micromirror device 110, 415: Substrate 113: Opening 120, 413: Heat sink 130: Sealant 140: Wafer 150: Light 160: Glass structure 200: Electronic device 300: External signal source 310 : External signal 400 : package structure 410 : wafer module 411 : first wafer 411a : lower surface 412 : second wafer 415a · first surface 11 200847350
CUNtlDbNTIAL 415b :第二表面 415c :開口 430 : 遮罩 432 視窗件 441 第一電性連接墊 442 導線 443 第二電性連接墊 445 第三電性連接墊 447 覆晶凸塊 550 : :反射訊號 12CUNtlDbNTIAL 415b: second surface 415c: opening 430: mask 432 window piece 441 first electrical connection pad 442 wire 443 second electrical connection pad 445 third electrical connection pad 447 flip chip bump 550 : : reflection signal 12
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TW096118601A TWI371833B (en) | 2007-05-24 | 2007-05-24 | Package structure and electronic device using the same |
US12/078,076 US7812433B2 (en) | 2007-05-24 | 2008-03-27 | Package structure and electronic device using the same |
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KR101711007B1 (en) * | 2010-04-29 | 2017-03-02 | 삼성전자주식회사 | Image sensor module having image sensor package |
US8605211B2 (en) * | 2011-04-28 | 2013-12-10 | Apple Inc. | Low rise camera module |
JP6720633B2 (en) * | 2016-03-29 | 2020-07-08 | セイコーエプソン株式会社 | Electro-optical device, electro-optical unit and electronic device |
US10678046B2 (en) * | 2018-03-21 | 2020-06-09 | Infineon Technologies Ag | Packages for microelectromechanical system (MEMS) mirror and methods of manufacturing the same |
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US5856911A (en) * | 1996-11-12 | 1999-01-05 | National Semiconductor Corporation | Attachment assembly for integrated circuits |
US6564454B1 (en) * | 2000-12-28 | 2003-05-20 | Amkor Technology, Inc. | Method of making and stacking a semiconductor package |
DE10227544B4 (en) * | 2002-06-17 | 2007-08-02 | Infineon Technologies Ag | Device for optical data transmission |
US7744991B2 (en) * | 2003-05-30 | 2010-06-29 | 3M Innovative Properties Company | Thermally conducting foam interface materials |
US7417293B2 (en) * | 2004-04-27 | 2008-08-26 | Industrial Technology Research Institute | Image sensor packaging structure |
US20070210246A1 (en) * | 2005-04-14 | 2007-09-13 | Amkor Technology, Inc. | Stacked image sensor optical module and fabrication method |
US7514684B2 (en) * | 2006-08-28 | 2009-04-07 | L-3 Communications Corporation | Surface mounted infrared image detector systems and associated methods |
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US20080290489A1 (en) | 2008-11-27 |
US7812433B2 (en) | 2010-10-12 |
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