200837903 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種打線連接之多晶片堆疊構造， 特別係有關於一種可改善晶片由支撐點斷裂之多晶片 堆疊構造。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多 功能、高性能的研發方向，並應滿足半導體封裝構造微 型化的封裝需求。為了提昇單一半導體封裝構造之性能 與容量，以符合電子產品小型化、大容量與高速化之趨 勢，目前多半係將半導體封裝構造以多晶片堆疊的形式 呈現，此種封裝構造亦可縮減整體封裝構造體積並可提 昇電性功能。再者，該多晶片堆疊構造具有較高的運行 速度，可減少晶片間連接線路之長度而降低訊號延遲以 及存取時間。該多晶片堆疊構造係在單一封裝構、生之一 基板上疊δ又至少兩個晶片，並在兩個晶片之間夫置一門 隔物（spacer)，藉由該間隔物將上下兩層晶片分隔開， 並使得位在下層之晶片之銲墊係為顯露，以供打線連 接。 請參閱第1及2圖所示，一種習知的多晶片堆属構 造100主要包含一基板110、一第一晶片12〇、一第一 晶片1 5 0、複數個第一銲線1 3 1、複數個第二鲜線i 3 2 以及一間隔物1 40。該基板11 0係具有一内表面i i}、 一外表面11 2以及複數個形成於該内表面u丨之打線接 5 200837903BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer stack structure for wire bonding, and more particularly to a multi-wafer stack structure for improving wafer breakage from a support point. [Prior Art] With the rapid development of the electronics industry, electronic products are gradually entering the multi-functional, high-performance research and development direction, and should meet the packaging requirements for semiconductor package construction and miniaturization. In order to improve the performance and capacity of a single semiconductor package structure, in order to meet the trend of miniaturization, large capacity and high speed of electronic products, most of the current semiconductor package structures are presented in the form of multi-chip stacks, and the package structure can also reduce the overall package. Constructs volume and enhances electrical functions. Moreover, the multi-wafer stack configuration has a higher operating speed, which reduces the length of the connection line between the wafers and reduces signal delay and access time. The multi-wafer stacking structure stacks δ and at least two wafers on a single package, and places a spacer between the two wafers, and the spacers are used to place the upper and lower layers of the wafer. Separated, and the pads of the wafers located in the lower layer are exposed for wire bonding. Referring to FIGS. 1 and 2 , a conventional multi-wafer stack structure 100 mainly includes a substrate 110 , a first wafer 12 , a first wafer 150 , and a plurality of first bonding wires 1 3 1 . a plurality of second fresh lines i 3 2 and a spacer 1 40. The substrate 110 has an inner surface i i}, an outer surface 11 2 , and a plurality of wire bonds formed on the inner surface u 5 5 200837903
指11 3。該基板1 1 0更具有複數個接觸指〗丨4，其係形 成於該基板110之該外表面H2。該第一晶片12〇之一 背面1 2 2係黏貼於該基板1 i 〇之該内表面1〗i。該第一 晶片120係具有複數個第一銲墊ι23，其係形成於該第 一晶片120之一主動面121之邊緣。利用打線形成之該 些第一銲線131連接該些第一銲墊123至該基板11()之 該些打線接指11 3。該第二晶片！ 5 〇係疊設於該第一晶 片1 2 0之上方’且該間隔物j 4 〇係介設於該第一晶片 1 2 0與該第二晶片1 5 〇之間。該間隔物丨4 〇係用以避免 該第一晶片150之背面152與該些第一銲線131直接接 觸。在製造時，利用一第一黏著層i 41之黏貼，使該間 隔物140黏設於該第一晶片12〇之該主動面I〕〗。請參 閱第2圖所示’該間隔物1 4 0之尺寸應小於該第一晶片 1 2 0之尺寸，其係並顯露該些第一銲墊1 2 3，方可使該 些第一銲線131之一端可連接至該些第一銲墊ι23。通 常該間隔物1 40係可為一膠片、一虛晶片或一金屬片等 等’以如同晶片取放（pick an dplace)方式設置於該第一 晶片1 2 0之主動面1 2 1上。該第二晶片1 5 〇係利用一第 二黏著層142之黏貼，而使該第二晶片15〇之背面152 係黏貼於該間隔物140。該第二晶片150係具有複數個 第二銲墊1 5 3，其係形成於該第二晶片1 5 〇之一主動面 151。該些第二銲線132係連接該些第二銲墊153至該 基板110。通常可另以一封膠體160密封該第一晶片 120、該第二晶片150、該些第一鲜線131與該歧第一 6 200837903 銲線1 3 2。 請再參閱第1圖所示，當該第二晶片15"占設於該 間隔物140上時，由於該第二晶片15〇之周邊不與該間 隔物140黏接的部位無法獲得來自該間隔物14〇之支樓 而成懸空部位，而上述懸空部位即包含該些第二銲墊 153，即該第二晶片15〇設有該些第二銲墊153之位置 將無法得到縱向且直接的打線支撐性。當打線形成該些 第一銲線1 3 2時，一打線機之銲針（圖中未繪出）會施予 該些第二銲墊153 一向下壓力形成力矩，而造成該第二 晶片150於該間隔物14〇黏接邊緣之支撐點產生崩裂之 情況’進而造成結構損壞。 【發明内容】 本發明之主要目的係在於提供一種改善晶片由支撐 點斷裂之多晶片堆疊構造，利用具有支撐指之間隔片之 設計’使在銲接銲線於上層晶片時，該些支撐指得以提 供上層堆疊晶片較大的打線支撐面積，藉此避免上層晶 片由支撐點斷裂之問題，以提高多晶片堆疊構造之產品 良率。 本發明之次一目的係在於提供一種改善晶片由支撐 點斷裂之多晶片堆疊構造，具有支撐指之間隔片特定形 狀可提供晶片堆疊之間隔維持特性，另可避免因晶片堆 疊不正或傾斜之現象導致銲線觸碰上方晶片背面。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種多晶片堆疊構造主要包 7 200837903 含一基板、一第一晶片、複數個第一銲線、一間隔片以 及一第一晶片。該第一晶片係設置於該基板上並具有複 數個第一銲墊。該些第一銲線電性連接該些第一銲墊至 該基板。該間隔片係設置於該第一晶片上。該第二晶片 係設置於該間隔片上並具有複數個第二銲墊。其中，該 間隔片係形成有複數個往該第一晶片邊緣延伸之支撐 指並位於該些第一銲塾之兩側。Refers to 11 3. The substrate 110 further has a plurality of contact fingers 4 formed on the outer surface H2 of the substrate 110. One of the first wafer 12's back surface 1 2 2 is adhered to the inner surface 1 i of the substrate 1 i. The first wafer 120 has a plurality of first pads ι23 formed on the edge of one of the active faces 121 of the first wafer 120. The first bonding wires 131 formed by wire bonding are connected to the first bonding pads 123 to the bonding wires 11 3 of the substrate 11 (). The second wafer! 5 〇 is stacked above the first wafer 120 and the spacer j 4 is interposed between the first wafer 120 and the second wafer 15 5 . The spacers 4 are used to prevent the back surface 152 of the first wafer 150 from directly contacting the first bonding wires 131. At the time of manufacture, the spacer 140 is adhered to the active surface I of the first wafer 12 by using a first adhesive layer i41. Please refer to FIG. 2, the size of the spacer 140 should be smaller than the size of the first wafer 120, and the first pads 1 2 3 are exposed to enable the first soldering. One end of the wire 131 can be connected to the first pads ι23. Typically, the spacers 140 can be a film, a dummy wafer or a metal sheet, etc., disposed on the active surface 112 of the first wafer 120 in a pick an dplace manner. The second wafer 15 is adhered to the spacer 140 by the adhesion of a second adhesive layer 142 to the back surface 152 of the second wafer 15 . The second wafer 150 has a plurality of second pads 153 formed on one of the active faces 151 of the second wafer 15 . The second bonding wires 132 connect the second pads 153 to the substrate 110. The first wafer 120, the second wafer 150, the first fresh lines 131, and the first first 6 200837903 bonding wires 1 3 2 may be sealed by a single colloid 160. Referring to FIG. 1 again, when the second wafer 15" is disposed on the spacer 140, the portion of the second wafer 15 that is not adhered to the spacer 140 cannot be obtained from the spacer. The slab of the slab is a suspended portion, and the vacant portion includes the second pads 153, that is, the positions of the second pads 15 and the second pads 153 are not able to be longitudinally and directly Line support. When the wire is formed into the first bonding wires 133, a soldering pin (not shown) of a wire bonding machine applies the second bonding pads 153 to a downward pressure to form a moment, thereby causing the second wafer 150. The crack occurs at the support point of the spacer 14 〇 the edge of the bond, which in turn causes structural damage. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-wafer stack structure for improving the breakage of a wafer from a support point, and the design of the spacer having the support finger is used to enable the support fingers when the solder wire is soldered to the upper wafer. The larger wire bonding support area of the upper stacked wafer is provided, thereby avoiding the problem that the upper wafer is broken by the support points, so as to improve the product yield of the multi-wafer stacked structure. A second object of the present invention is to provide a multi-wafer stack structure for improving the breakage of a wafer from a support point. The spacer-specific spacer shape can provide the interval maintenance characteristics of the wafer stack, and avoid the phenomenon that the wafer stack is not aligned or tilted. Causes the wire to touch the back of the wafer above. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer stack construction main package 7 200837903 includes a substrate, a first wafer, a plurality of first bonding wires, a spacer, and a first wafer. The first wafer is disposed on the substrate and has a plurality of first pads. The first bonding wires are electrically connected to the first pads to the substrate. The spacer is disposed on the first wafer. The second wafer is disposed on the spacer and has a plurality of second pads. The spacer is formed with a plurality of support fingers extending toward the edge of the first wafer and located on opposite sides of the first solder pads.
本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在則述的多晶片堆疊構造中，該間隔片係可概呈Η 形。 在則述的多晶片堆疊構造中，該些支撐指之邊緣係 可與該第一晶片邊緣切齊。 在刖述的多晶片堆疊構造中，該間隔片之該些支撐 指係可位於該第一晶片之角隅。 在Α述的多晶片堆疊構造中，該間隔片係可為具有 雨面黏性之膠帶。 在刖述的多晶片堆疊構造中，該間隔片同一側邊之 該一支撐指間係可形成有一缺口 ，以顯露該些第一銲 墊。 /日日71唯豐俯攻τ ' 1力包含有一黏晶1 料’其係黏接該第二晶片與該間隔片。 在則述的多晶片堆疊構造中，該黏晶材料係可更J 入於該缺口，以密封該些第一銲線之一端。 8 200837903 在則述的多晶片堆疊構造中，可另包含有複數個第 一鲜線，其係電性逹接該些第二銲整至該基板。 在前述的多晶片堆疊構造中，可另包含有一封膠 體’其係密封該第一晶片、該第二晶片與該些第一銲線。 在前述的多晶片堆叠構造中，該基板係可為一記憶 卡之基板，其係具有複數個外露於該封膠體之接觸指。 【實施方式】 _ 依據本發明之第一具體實施例，揭示一種改善晶片 由支撐點斷裂之多晶片堆疊構造。第3圖係為該多晶片 堆疊構造之截面示意圖。第4圖係為該多晶片堆疊構造 在放置間隔片之後且在堆疊上層晶片之前之立體示意 圖第5圖係為該多晶片堆疊構造在放置間隔片之後之 頂面不意圖。第6圖係為可使用該多晶片堆疊構造之間 隔片在切割前捲帶型態之示意圖。 明參閱第3圖所示’ 一種多晶片堆疊構造2〇〇主要 • 包含一基板210、一第一晶片220、複數個第一銲線 231、一間隔片240以及一第二晶片25〇。該基板21〇 係具有一内表面211及一外表面212，其中該内表面211 係形成有複數個打線接指213(如第4圖所示），以供打 線連接^該基板210係可為一記憶卡之基板，其係具有 複數個外露之接觸指214,其形成於該外表面212。依 應用產品之不同變化，該基板210亦可為一球格陣列封 裝基板（BGA substrate)或一導線架（iead frame)。 該第一晶片2 2 0係具有一主動面2 2 1及一相對之背 9 200837903 面222，其中該主動面221之兩側係形成有複數個第一 知塾223。胡參閱第4圖所示，在本實施例中，該些第 一銲墊223排列方式係可為雙側周邊銲墊。該第一晶片 220之該背面222係黏貼於該基板21〇之該内表面 211，以使該第一晶片220係設置於該基板21〇上。在 黏晶之後，可利用打線形成該些第一銲線23 i，其係電 性連接該些第一銲墊223與該基板21〇之該些打線接指 2 1 3，達到該第一晶片220與該基板2〗〇之内部電性互 請再參閱第4圖所示，該間隔片24〇係形成有複數 個隹該第一晶片220邊緣延伸之支撐指241並位於該些 第銲墊223之兩側。在本實施例中，該間隔片24〇係 β概呈Η开>。該些支撐指2 4 i之邊緣係可與該第一晶片 22〇邊緣切齊，因此，該間隔片24〇之最大長寬可與該 /曰片2 2 0之主動面2 2 1長寬相當，達到較佳的間隔 支撐。請參閱第4及5圖所示，該間隔片240同一侧邊 之該些支撐指24〗間係可形成有一缺口 242，其係顯露 該些第一銲墊223並容納該些第一銲線231之一端。請 參閱第5圖所示，每一缺口 242可顯露該第一晶片22〇 位在同一側之複數個第一銲墊223。因此，該間隔片240 在同一晶片側邊之該些支撐指241係用以提高對該第 ，曰曰片250之打線支撐性，以避免該第二晶片25〇斷 • L常該些第一銲墊223係可位於該間隔片24〇之缺 242較内緣，可避免受到刮傷、磨擦等損傷，故該間 10 200837903 隔\24〇具有保m晶片焊塾之功效。 明再參閱第3圖所示，在本實施例中，該間隔片240 係可為具有兩面黏性之膠帶，該間隔片240係具有一第 黏著層243與—第二黏著層244，其中該第一黏著層 243與該第一黏著層244係分別形成於該間隔片240之 下表面與上表面。該第一黏著層243係黏貼於該第一晶 片220之該主動面221，並顯露該些第一銲墊223。該 第二黏著層244係黏貼於該第二晶片25〇。 在本發明中’該間隔片240係為一種可捲收之介電 性膠膜’ ^聚亞驢胺（PI)或其它塑膠聚合材料。請參閱 第6圖所不’該間隔片240在切割前係可為一捲帶型 態。在該捲帶上打上複數個方型孔，且在該些方型孔中 心係形成有一切割道245，並沿著該切割道245切穿以 形成複數個具有支撐指之間隔片240。 該第二晶片2 5 0係具有一主動面2 5 1及一相對之背The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the multi-wafer stack configuration described above, the spacers can be generally meandered. In the multi-wafer stack configuration described above, the edges of the support fingers can be aligned with the edge of the first wafer. In the multi-wafer stack configuration described above, the support fingers of the spacer may be located at the corners of the first wafer. In the multi-wafer stack configuration described above, the spacer may be a tape having a rain-surface viscous property. In the multi-wafer stack configuration described above, the support finger of the same side of the spacer may be formed with a notch to expose the first pads. / Day 71 Weifeng pitch τ '1 force contains a die 1 material' which adheres to the second wafer and the spacer. In the multi-wafer stack configuration described above, the die-bonding material can be further incorporated into the gap to seal one of the first bonding wires. 8 200837903 In the multi-wafer stack configuration described above, a plurality of first fresh lines may be further included, which electrically connect the second solders to the substrate. In the foregoing multi-wafer stack configuration, a glue may be additionally included which seals the first wafer, the second wafer and the first bonding wires. In the foregoing multi-wafer stack configuration, the substrate may be a substrate of a memory card having a plurality of contact fingers exposed to the sealant. [Embodiment] According to a first embodiment of the present invention, a multi-wafer stack configuration for improving wafer breakage from a support point is disclosed. Figure 3 is a schematic cross-sectional view of the multi-wafer stack configuration. Figure 4 is a perspective view of the multi-wafer stack configuration after placement of the spacers and prior to stacking the upper wafers. Figure 5 is a top plan view of the multi-wafer stack construction after placement of the spacers. Figure 6 is a schematic illustration of the use of the separator between the multi-wafer stack constructions prior to cutting. Referring to Figure 3, a multi-wafer stack structure 2 is mainly provided. The main substrate 210 includes a substrate 210, a first wafer 220, a plurality of first bonding wires 231, a spacer 240, and a second wafer 25A. The substrate 21 has an inner surface 211 and an outer surface 212. The inner surface 211 is formed with a plurality of wire bonding fingers 213 (as shown in FIG. 4) for wire bonding. A substrate of a memory card having a plurality of exposed contact fingers 214 formed on the outer surface 212. The substrate 210 can also be a ball grid array substrate (BGA substrate) or a lead frame (iead frame) depending on the application. The first wafer 220 has an active surface 2 2 1 and an opposite back surface 9200837903 surface 222. The first surface of the active surface 221 is formed with a plurality of first knowledge electrodes 223. Referring to FIG. 4, in the embodiment, the first pads 223 are arranged in a double-sided peripheral pad. The back surface 222 of the first wafer 220 is adhered to the inner surface 211 of the substrate 21 so that the first wafer 220 is disposed on the substrate 21A. After the die bonding, the first bonding wires 23 i can be formed by wire bonding, and electrically connected to the first bonding pads 223 and the bonding wires 2 1 3 of the substrate 21 to reach the first chip. Referring to FIG. 4, the spacers 24 are formed with a plurality of support fingers 241 extending from the edge of the first wafer 220 and located on the pads. On both sides of 223. In the present embodiment, the spacer 24 is substantially cleaved. The edge of the support finger 24 i can be aligned with the edge of the first wafer 22, so that the maximum length and width of the spacer 24 can be longer than the active surface 2 2 1 of the / 2 2 0 Quite, a better spacing support is achieved. Referring to FIGS. 4 and 5, the support fingers 24 of the same side of the spacer 240 may be formed with a notch 242 for exposing the first pads 223 and accommodating the first bonding wires. One end of 231. Referring to FIG. 5, each of the notches 242 can expose a plurality of first pads 223 on the same side of the first wafer 22. Therefore, the support fingers 241 of the spacer 240 on the side of the same wafer are used to improve the wire support of the second wafer 250 to prevent the second wafer 25 from being broken. The solder pad 223 can be located on the inner edge of the spacer 242 and can be protected from scratches, abrasions, etc., so that the 10 200837903 compartment has the effect of protecting the wafer soldering. Referring to FIG. 3 again, in the embodiment, the spacer 240 can be a double-sided adhesive tape, and the spacer 240 has a first adhesive layer 243 and a second adhesive layer 244. The first adhesive layer 243 and the first adhesive layer 244 are respectively formed on the lower surface and the upper surface of the spacer 240. The first adhesive layer 243 is adhered to the active surface 221 of the first wafer 220, and the first pads 223 are exposed. The second adhesive layer 244 is adhered to the second wafer 25A. In the present invention, the spacer 240 is a retractable dielectric film 'polyimide amine (PI) or other plastic polymeric material. Referring to Figure 6, the spacer 240 may be in a tape form prior to cutting. A plurality of square holes are formed in the tape, and a scribe line 245 is formed in the center of the square holes, and cut along the scribe line 245 to form a plurality of spacers 240 having support fingers. The second wafer 250 has an active surface 2 5 1 and an opposite back
面252 ’該第二晶片250之主動面251係形成有複數個 第二銲墊253。該第二晶片25〇之背面252係可藉由該 第二黏著層244之黏貼，使該第二晶片25〇設置於該間 隔片240上。當該第二晶片25〇貼設壓合於該間隔片 240時’該些支撐指241係可用以防止該第二晶片250 之該背面252過於下壓或傾倒而壓損該些第一銲線 231 °其中’該些第二銲墊253係為朝上，可利用複數 個第二銲線232以電性連接該些第二銲墊253至該基板 2 1 0 〇 11 200837903 具體而言，該多晶片堆疊構造200可另包含有 膠體260，其係形成於該基板210之内表面211， 封該第一晶片220、該第二晶片250、該些第一銲線 與該些第二銲線232，使該多晶片堆疊構造200之 元件與外界氣密隔離，以避免受外界水氣或污染 害。該些接觸指2 1 4係形成於該基板2 1 0之該外 212並為顯露狀。在本實施例中，該封膠體260與 p 板2 1 〇之總厚度係可約為1毫米（mm)，並為卡片型 例如微型數位保全卡（Micro SD card)。 因此，在該多晶片堆疊構造200中，利用該些 指241使在銲接該些第二銲線232於該第二晶片 時，該些支撐指24 1得以提供該第二晶片2 5 0較大 線支撐面積，用以提昇該間隔片240之支撐力，藉 免該第一晶片250由支撐點斷裂之問通’以提兩產 良率。另可進一步維持該第二晶片2 5 0於打線作業 # 構之完整，免於受損之虞。此外，可提供晶片堆疊 隔維持特性，不會因晶片堆疊不正或傾斜之現象導 一銲線231觸碰到該第二晶片250之背面252，以 該多晶片堆疊構造2〇〇之可靠性。 在本發明之第二具體實施例’揭示另一種改善 由支撐點斷裂之多晶片堆疊構造。請參閱第7圖所 該多晶片堆疊構造3〇〇主要包含一基板310、~第 片320、複數個第一銲線331、一間隔片340以及 二晶片350。該基板310係具有一内表面311及一 一封 以密 23 1 内部 物侵 表面 該基 態， 支撐 250 的打 此避 品之 時結 之間 致第 增進 晶片 示， 一晶 一第 外表 12 200837903 面3 1 2，該内表面3 1 1係形成有複數個打線接指（圖中未 繪出）。該基板310係可另具有複數個外露接觸指314, 其係形成於該外表面3 1 2。 該第一晶片320係具有一主動面321、一背面322 以及複數個形成於該主動面321之周邊之第一銲墊 3 2 3。請參閱第8圖所示，在本實施例中，該些第一銲 聲3 23排列方式係可為四側周邊排列。如第7圖所示， _ 該第一晶片3 2〇係設置於該基板3 i 〇之該内表面3 1 1， 且該第一晶片320之該主動面321係為朝上。該些第一 鲜線331電性連接該些第一銲墊323至該基板31〇。 請再參閱第8圖所示，該間隔片34〇係形成有複數 個往該第一晶片320邊緣延伸之支撐指341並位於該些 第一銲塾323之兩側。在本實施例中，該間隔片34〇之 該些支撐指3 4 1係可位於該第一晶片3 2 〇之角隅。也就 疋说’該間隔片340之該些支撐指341係可為放射狀。 鲁因此，本發明並不侷限該間隔片34〇之形狀及該些支撐 扣3 4 1之數量，故該間隔片3 4 〇係可依照該第一晶片 320之該些第一銲墊323排列方式作適當的形狀變化， 以達到支撐之功效。其中，該些支撐指341之邊緣係可 ^該第一晶片320邊緣切齊。請參閱第7及8圖所示， 該問隔片340同一側邊之該些支撐指341間係可形成有 缺口 342，以顯露該些第一銲墊323。請再參閱第7 圖所示，該間隔片340係可另具有一黏著層343，其係 黏貼該第一晶片320之該主動面321。 13 200837903 該第二晶片350之一背面352係設置於該間隔片34〇 上，且該第二晶片350之一主動面351係形成有複數個 第二銲墊3 53。利用複數個第二銲線332以電性連接該 些第_銲塾353至該基板310。在本實施例中，第一曰 Θ9 片3 2 0與第二晶片3 5 〇係可為相同尺寸之記憶體晶片， 如快閃記憶體。 ” _而。’該多晶片堆疊構造3Q0可另包含有一The surface 252' of the active surface 251 of the second wafer 250 is formed with a plurality of second pads 253. The back surface 252 of the second wafer 25 is affixed by the second adhesive layer 244 to place the second wafer 25 on the spacer 240. When the second wafer 25 is affixed to the spacer 240, the support fingers 241 can be used to prevent the back surface 252 of the second wafer 250 from being pressed or poured too much to compress and damage the first bonding wires. 231 °, wherein the second pads 253 are facing upwards, and the plurality of second bonding wires 232 are electrically connected to the second pads 253 to the substrate 2 1 0 〇 11 200837903, specifically, The multi-wafer stack structure 200 may further include a colloid 260 formed on the inner surface 211 of the substrate 210 to seal the first wafer 220, the second wafer 250, the first bonding wires and the second bonding wires. 232. The components of the multi-wafer stack structure 200 are hermetically sealed from the outside to avoid external moisture or pollution. The contact fingers 2 1 4 are formed on the outer 212 of the substrate 2 1 0 and are exposed. In this embodiment, the total thickness of the encapsulant 260 and the p-plate 2 1 可 may be about 1 millimeter (mm), and is a card type such as a micro SD card. Therefore, in the multi-wafer stack structure 200, when the second bonding wires 232 are soldered to the second wafer, the supporting fingers 24 1 are provided to provide the second wafer 250. The wire support area is used to increase the supporting force of the spacer 240, and the first wafer 250 is prevented from being broken by the support point to improve the yield. In addition, the second wafer 250 can be further maintained in the integrity of the wire bonding operation, free from damage. In addition, wafer stack isolation characteristics can be provided without the wafer stacking 231 touching the back side 252 of the second wafer 250 due to wafer misalignment or tilting, with the reliability of the multi-wafer stack construction. Another second embodiment of the present invention discloses another multi-wafer stack configuration that is broken by the support points. Referring to FIG. 7, the multi-wafer stack structure 3A mainly includes a substrate 310, a first sheet 320, a plurality of first bonding wires 331, a spacer 340, and two wafers 350. The substrate 310 has an inner surface 311 and an inner surface of the inner surface of the dense inner surface of the inner surface of the inner surface of the inner surface of the inner surface of the substrate. 3 1 2, the inner surface 3 1 1 is formed with a plurality of wire bonding fingers (not shown). The substrate 310 can have a plurality of exposed contact fingers 314 formed on the outer surface 31. The first wafer 320 has an active surface 321 , a back surface 322 , and a plurality of first pads 3 23 formed around the active surface 321 . Referring to Fig. 8, in the embodiment, the first welding sounds 3 23 are arranged in a four-sided peripheral arrangement. As shown in FIG. 7, the first wafer 3 2 is disposed on the inner surface 31 of the substrate 3 i , and the active surface 321 of the first wafer 320 is upward. The first fresh lines 331 are electrically connected to the first pads 323 to the substrate 31. Referring to FIG. 8, the spacer 34 is formed with a plurality of support fingers 341 extending toward the edge of the first die 320 and located on opposite sides of the first pads 323. In this embodiment, the support fingers 34 of the spacer 34 may be located at the corners of the first wafer 3 2 . That is to say, the support fingers 341 of the spacer 340 may be radial. Therefore, the present invention is not limited to the shape of the spacer 34 and the number of the support buckles 341. Therefore, the spacers 34 can be arranged according to the first pads 323 of the first wafer 320. The way to make appropriate shape changes to achieve the effect of support. The edges of the support fingers 341 can be edge-aligned. Referring to Figures 7 and 8, the support fingers 341 of the same side of the spacer 340 may be formed with gaps 342 to expose the first pads 323. Referring to FIG. 7 again, the spacer 340 may further have an adhesive layer 343 attached to the active surface 321 of the first wafer 320. 13 200837903 A back surface 352 of the second wafer 350 is disposed on the spacer 34 , and an active surface 351 of the second wafer 350 is formed with a plurality of second pads 3 53 . A plurality of second bonding wires 332 are used to electrically connect the first solder pads 353 to the substrate 310. In this embodiment, the first Θ 9 片 3 2 0 and the second wafer 3-5 can be memory chips of the same size, such as flash memory. _ _. The multi-wafer stack structure 3Q0 may further include
晶材料3 6 〇，並# 4 一 黏接該第二晶片350與該間隔片34〇。 睛再參閱坌7 is 第一曰 圖所示，該黏晶材料3 60係可完全覆蓋該 日日片350之該背面3S2。該黏晶材料36〇係可選自 用膠？、B階膠體與液態膠之其中之一，較佳地，可選 該請再參閱第7圖所示’當該第二晶片35〇往 明片320壓貼，多餘的黏晶材料360可填入於該 t， 以饴封該些第一銲線331之一端。更具體而 二=多晶片堆叠構造300可另包含有一封膠體37〇， θ 日日片320該第二晶片350、該些第一 知線331與該也第—線 ^ ^ 一弟一紅深332而該些接觸指314係外 路於該封膠體37〇。 二曰上述之該間隔μ 34〇之該些支揮指341係位於該第 :;二35°之四角隅下方，進而可支撐該第二晶片350 角隅’並可提高該第二晶片35〇之4砼±产祕 此，以該”32… 因 該第二日—y ^ ^性連接時，可避免造成 一曰日片350因受力而崩裂損壞。 以上所述，僅是本發明的較佳實施例而已，並非對 14 200837903 本發明作任何形式上的限制，雖然本發明已以較佳實施 例揭露如上，然而並非用以限定本發明，任何熟悉本專 業的技術人員，在不脫離本發明技術方案範圍内，當可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例’但凡是未脫離本發明技術方案的内 谷’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 _ 範圍内。 【圖式簡單說明】 第1圖：一種習知多晶片堆疊構造之截面示意圖。 第2圖：習知多晶片堆疊構造在放置間隔片之後之頂面 示意圖。 第3圖：依據本發明之第一具體實施例，一種改善晶片 由支撐點斷裂之多晶片堆疊構造之截面示意 圖。 •第4圖：依據本發明之第一具體實施例，該多晶片堆疊 構造在放置間隔片之後且在堆疊上層晶片之 前之立體示意圖。 第5圖：依據本發明之第一具體實施例，該多晶片堆疊 構造在放置間隔片之後之頂面示意圖。 第6圖：依據本發明之第一具體實施例，可使用該多晶 片堆疊構造之間隔片在切割前捲帶型態之示 意圖。 第7圖：依據本發明之第二具體實施例，另一種改善晶 15 200837903 片由支撐點斷裂之多晶片堆疊意圖。 第8圖：依據本發明之第二具體實施例， 構造之間隔片 【主要元件符號說明 之頂面示意圖。The crystal material 3 6 〇, and # 4 a is bonded to the second wafer 350 and the spacer 34 〇. The viscous material 3 60 can completely cover the back surface 3S2 of the day sheet 350. The viscous material 36 can be selected from the use of glue? One of the B-stage colloid and the liquid glue, preferably, please refer to FIG. 7 again. When the second wafer 35 is pressed against the clear film 320, the excess adhesive material 360 can be filled. Into the t, one end of the first bonding wires 331 is sealed. More specifically, the two-multi-stack stack structure 300 may further include a colloid 37 〇, the θ-day film 320, the second wafer 350, the first line 331 and the first line-^^^ 332 and the contact fingers 314 are external to the sealant 37〇. The plurality of the fingers 341 of the interval μ 34 are located below the four corners of the second 35°, thereby supporting the second wafer 350 and increasing the second wafer 35〇 4 砼 产 产 产 , , , , , , , , ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” ” 因 因 因 因 因 因 因 因 因 因The preferred embodiment is not intended to limit the invention in any way. Although the invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and In the scope of the present invention, when the above-disclosed technical contents can be used to make some modifications or modifications to equivalent variations, the equivalent embodiment of the present invention can be implemented in accordance with the technical essence of the present invention. Any simple modification, equivalent change and modification made by the example are still within the scope of the technical solution of the present invention. [Simplified description of the drawing] FIG. 1 is a schematic cross-sectional view of a conventional multi-wafer stack structure. Figure 2: Schematic diagram of a top surface of a conventional multi-wafer stack construction after placement of spacers. Figure 3: A schematic cross-sectional view of a multi-wafer stack configuration for improving wafer breakage from support points in accordance with a first embodiment of the present invention. 4 is a perspective view of the multi-wafer stack construction after placing the spacers and before stacking the upper wafers according to the first embodiment of the present invention. FIG. 5: According to the first embodiment of the present invention, the multi-image A top plan view of the wafer stack configuration after placement of the spacers. Figure 6: A schematic view of a tape pattern prior to dicing of the spacer of the multi-wafer stack construction in accordance with a first embodiment of the present invention. According to a second embodiment of the present invention, another improved wafer 15 200837903 sheet is intended to be broken by a support point for multi-wafer stacking. Figure 8: According to a second embodiment of the present invention, the structured spacer [main component symbol The top view of the description.
100 多 晶 片堆疊構造 110 基板 111 113 打 線接指 114 120 第 一 晶片 121 123 第 一 銲墊 131 第 ，丨一 鲜線 132 140 間 隔物 141 150 第 二 晶片 151 153 第 二 銲墊 160 200 多 晶 片堆疊構造 210 基板 211 213 打 線接指 214 220 第 一 晶片 221 223 第 一 銲墊 231 第 一 銲線 232 240 間 隔 片 241 243 第 黏著層 244 250 第 二 晶片 251 253 第 二 銲墊 260 内表面 112 接觸指 主動面 122 第二銲線 第一黏著層 142 主動面 152 封膠體 内表面 212 接觸指 主動面 222 第二銲線 支撐指 242 第一黎著層 245 主動面 252 封膠體 造之截面示 ^多晶片堆疊 外表面 背面 第二黏著層 背面 外表面 背面 缺口 切割道 背面 16 200837903 300 多晶片堆疊: 構造 310 基板 311 314 接觸指 320 第一晶片 321 323 第一銲墊 331 第一鲜線 332 340 間隔片 341 343 黏著層 350 第二晶片 351 353 第二銲墊 360 黏晶材料 370 内表面 312 外表面 主動面 322 背面 第二銲線 支撐指 342 缺口 主動面 352 背面 封膠體 17100 multi-wafer stack configuration 110 substrate 111 113 wire bonding finger 114 120 first wafer 121 123 first pad 131 first, fresh line 132 140 spacer 141 150 second wafer 151 153 second pad 160 200 multi-wafer stack Structure 210 substrate 211 213 wire bonding finger 214 220 first wafer 221 223 first pad 231 first bonding wire 232 240 spacer 241 243 first bonding layer 244 250 second wafer 251 253 second bonding pad 260 inner surface 112 contact finger Active surface 122 second bonding wire first adhesive layer 142 active surface 152 sealing inner surface 212 contact finger active surface 222 second bonding wire support finger 242 first ligament layer 245 active surface 252 sealing body made of cross section Stacked outer surface back second adhesive layer back outer surface back notched scribe back 16 200837903 300 Multi-wafer stack: construction 310 substrate 311 314 contact finger 320 first wafer 321 323 first pad 331 first fresh line 332 340 spacer 341 343 Adhesive layer 350 Second wafer 351 353 Second pad 360 Sticky 370 inner surface 312 outer surface material of the active surface of the back surface 322 of the second bonding wire support means 342 notch 352 colloidal back surface active surface 17