200837854 九、發明說明 【發明所屬之技術領域】 本發明係關於多層互連結構之製造方法、多層互連結 構、電晶體裝置、及影像顯示器。 【先前技術】 在基底上或半導體晶圓上具有電晶體及二極體的傳統 Φ 半導體裝置通常使用多層互連結構以增加集成密度。在多 層互連結構中，使用層間絕緣膜，層間絕緣膜具有通孔以 在互連線之間提供電連接。 近年來，例如多孔二氧化矽膜、氟化矽氧化物膜及矽 與具有甲基的氧之有機絕緣膜等比習知的氧化矽膜具有較 低的相對介電常數之絕緣材料，愈來愈受歡迎作爲層間絕 緣膜的材料。在這些材料中，通常使用的是具有低介電常 數（約2· 2-· 4.0 )的有機絕緣膜。 • 但是’由於使用影技術以在有機絕緣膜中形成通孔， 所以’製造步驟的數目增加，因而以成本觀念而言，使用 有機絕緣膜是不利的。 網版印刷法是將墨水沈積至具有非注入墨水區的網（ 網版印刷遮罩）上，在此區上配置乳膠以防止墨水通過， 以及’藉由滑動輥以使墨水通過網目。此方法由於可以減 少製造步驟及具有更高的材料使用效率，所以是有利的。 網版印刷法能夠以簡單技術形成精密圖案，因此，近年來 被用於形成電晶體之間的互連等等。但是，剛印刷過仍然 200837854 具有流動性之墨水的表面會因重力而變得平坦，造成輕微 污跡。此輕微污跡高度可能塡充小的通孔。因此，1 ΟΟμπι 平方的通孔是傳統的網版印刷法所能取得的最小尺寸。此 外，網版印刷法通常受例如間距（網版遮罩及基底之間的 距離），輥的角度、壓力、及速度等多種參數影響，因此 ，其難以穩定地產生小的通孔。在大面積印刷的情形中， 真正取得的最小尺寸約300μπι平方。 日本專利公開號2006_ 1 20873揭示阻抗受控的線路板 之製造方法。根據此方法，在以網版印刷法在金屬箔上形 成圓錐形導電凸塊之後，在導電凸塊上沈積絕緣體以致於 導電凸塊延伸經過絕緣體。然後，在絕緣體上沈積金屬薄 至與導電凸塊的頭部電連接。此方法之問題係由於藉由加 熱及施壓預浸體，所以絕緣體的材料受限，且導因於熱及 壓力的負載會施加至絕緣體上。在一實施例中取得的導電 凸塊的最小尺寸是150μπι，且未提及降低導電凸塊的尺寸 之可能性。 【發明內容】 慮及上述，本發明提供多層互連結構的製造方法，此 多層互連結構能夠經由具有小通孔的層間絕緣膜而電互連 上及下互連線；多層互連結構，其中，上及下互連線經由 具有小通孔的層間絕緣膜而電互連；包含多層互連結構的 電晶體裝置；及包含電晶體裝置的影像顯示器。 在本發明的實施例中，提供使用網版印刷法之多層互 -5- 200837854 連結構的製造方法。在多層互連結構中，具有其中設有導 電凸塊之通孔的層間絕緣膜、及第二互連線堆疊於基底上 ’其底上形成有第一互連線。第一互連線經由導電凸塊電 連接至第二互連線。方法包含下述步驟··在形成有第一互 連線的基底上形成層間絕緣膜的第一區，第一區包含通孔 的周圍壁之部份；在形成有第一區的基底上形成層間絕緣 膜的第二區，第二區包含通孔的周圍壁的其餘部份；及形 成導電凸塊。本發明的此實施例提供能夠經由小通孔而電 連接上及下互連線之多層互連結構的製造方法。 依據本發明的態樣，提供能夠經由具有小通孔的互連 層絕緣膜而電連接上及下互連線之多層互連結構的製造方 法；多層互連結構，其中，上及下互連線經由具有小通孔 的層間絕緣膜而電互連；包含多層互連結構的電晶體裝置 ;及包含電晶體裝置的影像顯示器。 【實施方式】 於下將參考附圖，說明本發明的較佳實施例。 依據本發明的實施例之多層互連結構的製造方法，使 用網版印刷法，製造多層互連結構，其中，具有其中設有 導電凸塊之通孔的層間絕緣膜、及第二互連線堆疊於基底 上，其底上形成有第一互連線。第一互連線經由導電凸塊 電連接至第二互連線。此外，方法包含下述步驟：在形成 有第一互連線的基底上形成層間絕緣膜的第一區，第一區 包含通孔的周圍壁之部份；在形成有第一區的基底上形成 -6- 200837854 層間絕緣膜的第二區，第二區包含通孔的周圍壁的其餘部 份；及形成導電凸塊。根據此方法，能夠使用簡單的技術 以較少步驟，製造經由小通孔而電連接上及下互連線之高 密度多層互連結構。 圖1顯示依據本發明的實施例之多層互連結構的實施 例。在圖1中所示的多層互連結構1中，在具有第一互連 線2形成於其上的基底〗上，形成具有通孔的層間絕緣膜 3。導電凸塊4塡充於通孔中。層間絕緣膜3上的第二互 連線5經由導電凸塊4電連接至第一互連線2。藉由使用 本發明的實施例之多層互連結構的製造方法，製造圖1中 所示的多層互連結構。 圖2A-2C顯示依據本發明的實施例之多層互連結構的 製造方法。首先，藉由使用網版印刷法，在形成有第一互 連線（未顯示）的基底1上形成層間絕緣膜3的第一區3 a ，以致於形成包含每一通孔的周圍壁的一部份之層間絕緣 膜3的部份（請參考圖2 A )。形成第一區3 a，以致於在 第一互連線（未顯示）.上形成通孔。接著，藉由使用網版 印刷法，形成與通孔的周圍壁的部份相對齊之導電凸塊4 (請參見圖2B )。然後，藉由使用網版印刷法，形成與 第一區3a及導電凸塊4相對齊之層間絕緣膜3的第二區 3b，以致於形成每一通孔的周圍壁的其餘部份（請參見圖 2C )。藉由這些步驟，取得互連結構，其中，導電凸塊4 電連接至凸出於層間絕緣膜3的表面之外的第一互連線。 然後，形成第二互連線5以電連接至導電凸塊4，以致於 200837854 取得雙層互連結構。 在上述前三個步驟中，在導電凸塊4形成於第一互連 線2上之後，形成第一區3 a及第二區3 b。可以視通孔的 目標尺寸及第一區3 a的形狀，適當地選取步驟的次序。 在本發明的實施例中，含有導電材料的商業上可取得 的導電膏可以用於形成導電凸塊/導電材料的實施例包含 銀、銅、碳、及鋁。在這些材料中，金屬材料是較佳的。 可以組合地使用二或更多型式的導電材料。藉由使用已知 的方法，第一互連線及第二互連線可以由上述導電材料之 一或更多形成。 網版印刷法所使用的網版印刷機及網版印刷遮罩可爲 此技術領域中所習知的。網版印刷機需要具有用於間距、 輥角度、壓力及速度之可規劃設定，以及較佳地具有操作 準確度小於1 〇 μπι的基底平台。可以根據每一步驟中要印 刷的區域之形狀、要使用的膏的黏滯度、固體比體、等等 ，適當地選取網版印刷遮罩。藉由調整網的線徑（厚度） 、開α區比例、及乳膠厚度，可以控制膏的注入，因而能 夠印刷具有所需厚度的膜。 在本發明的實施例中，層間絕緣膜較佳地含有有機材 料及粒子。有機材料的實施例包含聚乙烯醇樹脂、聚乙烯 縮醛樹脂、丙烯酸系樹脂、乙基纖維素樹脂、聚乙烯、聚 苯乙烯、及聚醯胺。這些材料可以與它們之中的二或更多 組合地使用。只要是可以以粒子存在於層間絕緣膜中，則 有機及無機粒子中的任一者可爲粒子。但是，由於無機粒 -8 - 200837854 子的大小容易控制’且無機粒子可以散佈於溶劑中，所以 ，無機粒子是較佳的。無機粒子的實施例包含二氧化砍（ Si〇2 )、氧化鋁（A1203 )、氧化鈦（Ti〇2 )、氧化鋅（ ZnO )、及鈦酸鋇（BaTiCh )。在這些材料中，例如氧化 矽、氧化鋁、及氧化鋅等具有相當低的介電常數的材料是 較佳的。也可以使用例如中孔氧化矽等具有中孔或微孔結 構之多孔粒子。 爲了形成層間絕緣膜，可以使用絕緣膏，絕緣膏是藉 由混合有機材料及粒子於溶劑中並選加地添加散佈劑、塑 化劑、及黏滯度調節劑製備而成。有機材料與粒子之間的 混合比未特別限定，可以根據要形成的圖案，適當地調整 以使膏具有適當的物理特性。爲了確保層間絕緣膜的可撓 性，較佳的是增加有機材料的比例。具體而言，層間絕緣 膜中的有機材料的體積比較佳地爲40%或更多，更佳的是 5 0%或更多，以使層間絕緣膜可以平均施加至可撓基底。 雖然絕緣膏可以根據層間絕緣膜的第一區及第二區的形狀 及面積而調整，但是，經過乾燥的第一區及第二區的成份 較佳的是彼此不會相差太大。 圖3A-3C顯示依據本發明的實施例之多層互連結構的 另一製造方法。首先，藉由使用網版印刷法，在形成有第 一互連線（未顯示）的基底1上形成層間絕緣膜3的第一 區3a。形成實質上平行線的第一區3a (請參見圖3a)。 形成第一區3a，以致於在第一互連線（未顯示）上形成通 孔。接著，藉由使用網版印刷法，形成與第一區3 a相對 -9- 200837854 齊之導電凸塊4(請參見圖3B)。然後’藉由使用網版印 刷法，形成與第一區3 a及導電凸塊4相對齊之層間絕緣 膜3的第二區3 b。第二區3 b形成爲不連續的圖案’在排 除第一區3a的區域中延伸（請參見圖3C)。藉由這三個 步驟，取得互連結構，其中，導電凸塊4電連接至凸出於 層間絕緣膜3的表面之外的第一互連線。然後’形成第二 互連線5以電連接至導電凸塊4，以致於取得雙層互連結 構。可以根據通孔之間所需的尺寸及間隔’適當地決定第 一區3a的線圖案的寬度及間隔與第二區3b的不連續圖案 的形狀。由於藉由使用網版印刷法可以相當容易地形成線 圖案及不連續圖案，所以，絕緣膏的物理特性與印刷條件 之可允許範圍會增加，藉以實現穩定的印刷操作。 依據本發明的實施例，如圖2A-2C及圖3A-3C中所 示，較佳的是形成第一區3a、然後形成導電凸塊4、及接 著形成第二區3 b。假使，如圖4 A所示，在形成第一區3 a 之前形成導電凸塊4，則將第一區3a印刷於導電凸塊4上 。亦即，當藉由輥6以將絕緣膏注入經過無乳膠8的網7 的區域時，網7以導電凸塊4的高度與基底1相間隔，以 致於絕緣膏的注入量增加。結果，如圖4B所示，導電凸 塊4容易由層間絕緣膜3的第一區3a覆蓋。此外，第一 區3a的圖案準確度可以縮減。因此，在形成導電凸塊4 之前形成第一區3a可以增加第一區3a的形成準確度。假 使’如圖5所示，在形成第一區3a之後形成導電凸塊4， 導電膏的注入量會增加相當於第一區3 a的高度之量。由 -10- 200837854 於導電凸塊4可以製成凸出於層間絕緣膜3的表面之外， 所以，此方法是較佳的。此外，由於在形成第二區3b之 前形成導電凸塊4，所以，由於絕緣膏的水平而能夠防止 通孔被用於形成第二區3 b之要印刷的第二區3b之絕緣膏 覆蓋，因而能夠在通孔之內形成導電凸塊4。如此，第一 互連線2可以電連接至第二互連線5。 在本發明的實施例中，取決於例如導電凸塊的高度、 導電凸塊之間的距離、及層間絕緣膜的厚度等條件，有時 難以防止導電凸塊4的頂部被層間絕緣膜3部份地或完全 地覆蓋（圖4B )或是難以防止導電凸塊4的合部被層間 絕緣膜3覆蓋。假使層間絕緣膜3配置於導電凸塊4上時 ，則難以電連接導電凸塊4至第二互連線5，造成互連故 障。爲了防止此問題，如圖6A所示，將導電膏4a塗敷於 由層間絕緣膜3覆蓋的導電凸塊4上。然後，導電凸塊4 電連接至包含於導電膏4a中的導電材料，以致於第一互 連線2可以電連接至第二互連線5。關於電連接導電凸塊 4至導電膏4a的導電材料之處理，壓力或熱的施加可以是 有效的。爲了便於設置電連接，層間絕緣膜3較佳地含有 可溶解於包含在導電膏4a之溶劑中的有機材料。然後， 包含於導電膏4a中的溶劑溶解包含於層間絕緣膜3中的 有機材料’以致於包含於導電膏4a中的導電材料穿過層 間絕緣膜3以與導電凸塊4接觸。如此，導電凸塊4可以 電連接至導電膏4a的導電材料。接著，將溶劑乾燥，以 致於形成電連接至第一互連線2的導電凸塊4 (請參見圖 -11 - 200837854 6B )。如圖2A-2C及圖3 A-3C所示，在形成第一區3a之 後形成導電凸塊4的情形中，第二區3b含有可溶解於包 含在導電膏4a中的溶劑之有機材料。 在本發明的實施例中，如圖7A及7B所示，在第一區 3a未與第二區3b適當地對齊之情形中，基底1未被第一 區3a或第二區3b完全地覆蓋。圖7A是頂視圖’圖7B是 延著圖7A的虛線之剖面視圖。爲了防止此缺陷，要用於 形成第一區3a的第一絕緣膏之黏滯度製成高於要用於形 成第二區3b的第二絕緣膏的黏滯度。亦即，由於使用具 有高黏滯度及低流動性的第一絕緣膏以形成第一區3a，所 以，第一區3a可以形成所需的圖案。同時，由於使用具 有低黏滯度及高流動性的第二絕緣膏以形成第二區3b，所 以，印刷的第二絕緣膏在被乾燥之前會變平，因而能夠防 止產生缺陷（請參考圖8 A-8C)。如此，可以形成具有高 可靠度的層間絕緣膜。圖8A是頂視圖，圖8B及8C是分 別延著圖8A的虛線A及B取得的剖面視圖。第二絕緣膏 的流動改進第二區3b的膜厚的均勻度，藉以降低第一區 3a的水平差。雖然可以根據要形成的通孔的尺寸或通孔之 間的距離以適當地決定絕緣膏的黏滯度，但是，第一絕緣 膏的黏滯度一般爲lOOPa· s或更大，較佳地爲150Pa· s 。第二絕緣膏的黏滯度一般爲1 00 Pa · s或更小，較佳地 爲50 Pa · s或更小。 在本發明的實施例中，包含於層間絕緣膜的第一區中 的粒子的比表面積較佳地大於包含於第二區中的粒子的比 -12- 200837854 表面積。雖然，分別形成層間絕緣膜作爲第一區及第二區 ，所以，從第一區與第二區之間的親合性及整個層間絕緣 膜的均勻性的觀點而言，第一區及第二區理想上具有相同 的成份。如上所述，較佳的是使用具有高黏滯度（低流動 性）之第一絕緣膏及具有低黏滯度（高流動性）之第二絕 緣膏。調整膏的黏滯度而不改變固體含量的成份之最容易 方法是調整溶劑的內容。但是，假使爲了調整黏滯度而改 變膏中的溶劑的含量時，膏中的固體含量會改變。亦即’ 假使溶劑的含量增加以降低第二絕緣膏的黏滯度時’固體 的含量降低，以致於所需的第二區的膜厚降低。結果’第 二區的膜厚變成小於第一區的膜厚。如此’層間絕緣膜的 厚度均勻性降低，不利地影響第二互連線。藉由使用具有 不同的比表面積之粒子’可以解決此問題。比表面積是每 單位重量的粒子的總表面積。粒子的增加的黏滯度的特性 與其比表面積成比例。比表面積愈大（亦即，較小的粒子 尺寸），則增加的黏滯度的特性愈大。因此’第一絕緣膏 製成含有具有較大比表面積的粒子以具有更筒的黏滯度， 而第二絕緣膏製成含有較小的比表面積的粒子以具有較低 的黏滯度。如此，能夠製備具有不同的黏滯度而不改變固 體的含量及成份之絕緣膏，以致於層間絕緣膜的成份及厚 度的均勻性可以改良。 在本發明的實施例中，如圖8A-8C所示，層間絕緣膜 較佳地形成爲至少部份第二區形成於第一區上。如上所述 ，在第一區未與第二區適當地對齊之情形中，基底可能無 -13 - 200837854 法由第一區或第二區完全地覆蓋。假使使用具有流動性的 第二絕緣膏’則第二區塡充與第一區的間隙以及部份地配 置於第一區之上，以致於能夠形成高度可靠的層間絕緣膜 ，並防止上述缺陷。 圖9顯示依據本發明的實施例之電晶體的實施例。在 圖9中所示的電晶體裝置中，閘極電極9及閘極絕緣膜1 〇 形成於基底1上。源極電極2a、汲極電極2b、及有機半 φ 導體層1 1形成於閘極絕緣膜1 〇上。此外，形成具有通孔 的層間絕緣膜3以覆蓋源極電極2a、汲極電極2b、有機 半導體層11。導電凸塊4配置於通孔中。上電極5a形成 於層間絕緣膜3之上，層間絕緣膜3具有通孔，在通孔內 設有導電凸塊4。作爲第一互連線之源極電極2a經由導電 凸塊4電連接至作爲第二互連線的上電極5a。藉由使用本 發明的實施例之多層互連結構之製造方法，製造圖9中所 示的電晶體裝置。 • 圖l〇A及10B顯示依據本發明的實施例之電晶體裝置 的另一實施例。圖10A是切開側視圖，圖10B是頂視圖。 在圖10A及10B中，與圖9中所示的元件相同的元件以相 同代號表示且於此不再說明。在圖10A及10B中所示的電 晶體裝置中，層間絕緣膜3的第一區3a配置成覆蓋作爲 通道形成部份的有機半導體層11。以此方式以第一區3a 保護有機半導體層1 1，可以使導因於大氣中的氧及水蒸汽 之電晶體特性變異最小。當網版印刷導電凸塊4及第二區 3b時，這也防止網與有機半導體層11接觸，因而降低物 -14- 200837854 理負載。此外，在採用將包含於第二區3b中的有機材料 溶解於包含於第二導電膏中的溶劑之製程的情形中（請參 見圖6A及6B)，能夠防止有機半導體層11被溶劑傷害 〇 圖11顯示依據本發明的實施例之影像顯示器的實施 例。在圖11中所示的影像顯示器中，在基底1上形成閘 極電極9及閘極絕緣膜1 0。在閘極絕緣膜1 0上，形成源 極電極2a、汲極電極2b、及有機半導體層1 1。此外，形 成具有通孔的層間絕緣膜3以覆蓋源極電極2a、汲極電極 2b、及有機半導體層11。導電凸塊4配置於通孔中。像素 電極5b形成於具有通孔的層間絕緣膜3上，通孔之內設 有導電凸塊4。作爲第一互連線的源極電極2b經由導電凸 塊4電連接至作爲第二互連線的像素電極5b。電泳顯示裝 置16附著至具有此配置的主動矩陣基底，在電泳顯示裝 置16中，透明電極14及微囊15形成於支撐基底13上。 藉由使用本發明的實施例之多層互連結構的製造方法，製 造圖1 1中所示的影像顯示器。 本實施例中可以使用的影像顯示裝置不限於電泳顯示 裝置，而是可包含液晶顯示裝置、有機EL裝置、等等。 使用這些裝置之一可以提供平板型影像顯示器或可撓影像 顯示器’平板型影像顯示器對觀看者的眼睛較不會造成壓 力。 〔實施例〕 -15- 200837854 <實施例1> 藉由使用網版印刷遮罩以印刷之層間絕緣膜3的第一 區3a及第二區3b的圖案具有160 μιη寬的線之注入區及 8 Ομπι寬的線之非注入區。所使用的網版印刷遮罩是不銹 鋼網號500，其具有19 μπι線徑，其上沈積有15 μιη厚的乳 膠。要藉由網版印刷遮罩以印刷的導電凸塊4之圖案具有 50μιη直徑圓（以矩陣形式配置）的注入區，這些圓以 240μηι間距相隔。所使用的網版印刷遮罩是不銹鋼網號 400，其具有23 μιη線徑，其上沈積有3 Ομηι厚的乳膠。 藉由將聚乙烯醇樹脂溶入乙二醇丁基醚與α品醇的混 合溶劑中並接著添加具有50m2/g比表面積的氧化鋁塡充 物以調整黏滯度至約150Pa · s，以製成所使用的絕緣膏。 所使用的導電膏是熱固型膏，含有銀作爲導電材料。 參考圖1，第一區3a的圖案被對齊以致於不會與第二 互連線5 (稍後形成）的接點部相重疊，然後，藉由使用 絕緣膏，將此圖案網版印刷至形成有第一互連線2之玻璃 基底1上。在1 00 °C的熱爐中將產品乾燥3 0分鐘，藉以取 得第一區3a。真正取得的第一區3a是具有約1 80-1 90μπι 寬度的線，以2 4 0 μ m間距配置。 然後，導電凸塊4的圖案被對齊以致於與第二S連線 5 (稍後形成）的接點部相重疊，然後，藉由使用導電膏 ，網版印刷此圖案。在1 20°C的熱爐中將產品乾燥1小時 ，藉以取得導電凸塊4。真正取得的導電凸塊4是具有 5 5 -60μιη直徑的圓形且部份地配置於第一區3a的相鄰相 -16- 200837854 對線上。 在與第一區3a的線垂直的方向上，第二區3b的圖案 被對齊，以致於不會重疊第一區3a及導電凸塊4，然後藉 由使用絕緣膏以網版印刷此圖案。在1 〇〇 °C的熱爐中將產 品乾燥30分鐘，藉以取得第二區3b。所取得的第二區3b 塡充第一區3a與導電凸塊4之間的空間，以及被部份地 配置於第一區3a及導電凸塊4上。在光學顯微鏡下，觀 察到所有的導電凸塊4凸出於層間絕緣膜3的表面之外。 最後，形成第二互連線5以致於重疊導電凸塊4，藉 以取得多層互連結構。 然後，評估第一互連線2與第二互連線5的接觸鏈。 從2 00個接觸鏈中的1 0個位置之評估，發現每一通孔的 平均電阻在所有位置爲8 Ω，取得適當的接觸電阻。 <實施例2> 圖1 2A及1 2B顯示藉由使用網版印刷遮罩以印刷之層 間絕緣膜3的圖案。具體而言，圖1 2A及1 2B分別顯示第 一區3a及第二區3 b的圖案。圖12A中所示的圖案具有 170μπι寬的線之注入區及70μιη寬的線之非注入區。所使 用的網版印刷遮罩是不銹鋼網號500，其具有19μιη線徑 ，其上沈積有15μιη厚的乳膠。圖12Β中所示的圖案具有 60 μιη長及170 μπι寬的長方形注入區（以矩陣形式配置） ，這些長方形注入區以240 μιη的間距相間隔。所使用的網 版印刷遮罩是具有1 9 μπι線徑之被施予金屬電鍍處理的不 -17- 200837854 銹鋼網號5 00，其上沈積有15μιη厚的乳膠。要藉由使用 網版印刷遮罩以印刷的導電凸塊4之圖案具有5 0 μπι直徑 圓（以矩陣形式配置）的注入區，這些圓以24 0 μιη間距相 隔。所使用的網版印刷遮罩是不銹鋼網號400，其具有 2 3 μπι線徑，其上沈積有30μπι厚的乳膠。 所使用的絕緣膏如下所述：藉由將聚乙烯丁醛樹脂溶 入乙二醇單己醚並接著添加具有80m2/g比表面積的氧化 鋁塡充物以調整黏滯度至約250 Pa · s，而製成的絕緣膏 A;以及，藉由將聚乙烯丁醛樹脂溶入乙二醇單己醚並接 著添加具有30m2/g比表面積的氧化鋁塡充物以調整黏滯 度至約80 Pa · s，而製成的絕緣膏B。絕緣膏A及B可以 調整成具有相同的成份重量比。所使用的導電膏與實施例 1中所使用的相同。 參考圖1，圖12A中所示的圖案被對齊以致於不會與 第二互連線5 (稍後形成）的接點部相重疊，然後，藉由 使用絕緣膏A，將此圖案網版印刷至形成有第一互連線2 之玻璃基底1上。在100°C的熱爐中將產品乾燥30分鐘， 藉以取得第一區3a。真正取得的第一區3a是具有約185-195 μπι寬度的線，以240 μηι間距配置。 然後，導電凸塊4的圖案被對齊以致於與第二互連線 5 (稍後形成）的接點部相重疊，然後，藉由使用導電膏 ，網版印刷此圖案。在120 °C的熱爐中將產品乾燥1小時 ，藉以取得導電凸塊4。真正取得的導電凸塊4是具有 5 5-60 μιη直徑的圓形且部份地配置於第一區3a的相鄰相 -18- 200837854 對線上。 圖12B中所示的圖案被對齊以致於不會與第一區3a 及導電凸塊4相重疊，然後，藉由使用絕緣膏B，網版印 刷此圖案。在100°C的熱爐中將產品乾燥30分鐘，藉以取 得第二區3b。取得的第二區3b塡充第一區3a與導電凸塊 4之間的空間，以及被部份地配置於第一區3 a及導電凸塊 4上。在光學顯微鏡下，觀察到所有的導電凸塊4凸出於 層間絕緣膜3的表面之外。 最後，形成第二互連線5以致於重疊導電凸塊4，藉 以取得多層互連結構。 然後，評估第一互連線2與第二互連線5的接觸鏈。 從200個接觸鏈中的10個位置之評估，發現每一通孔的 平均電阻在所有位置爲1 2 Ω，取得適當的接觸電阻。 <實施例3> 所使用之用於層間絕緣膜3的網版印刷遮罩、用於導 電凸塊4的網版印刷遮罩、絕緣膏、及導電膏與實施例2 中所使用的相同。 導電凸塊4的圖案被對齊以致於與第二互連線5 (稍 後形成）的接點部相重疊，然後，藉由使用導電膏，將此 圖案網版印刷至形成有第一互連線2的玻璃基底1上。在 1 20 °C的熱爐中將產品乾燥1小時，藉以取得導電凸塊4。 真正取得的導電凸塊4是具有5 5 - 6 0 μ m直徑的圓形。 圖12A中所示的圖案被對齊以致於不會與導電凸塊4 -19- 200837854 相重疊，然後，藉由使用絕緣膏A，網版印刷此圖案。在 1 00 °C的熱爐中將產品乾燥30分鐘，藉以取得第一區3a。 真正取得的第一區3a是具有約185-195μιη寬度的線，以 240 μπι間距配置，以及，部份地配置於導電凸塊4上。 圖1 2Β中所示的圖案被對齊以致於不會與第一區3 a 及導電凸塊4相重疊，然後，藉由使用絕緣膏B，網版印 刷此圖案。在lOOt的熱爐中將產品乾燥30分鐘，藉以取 得第二區3b。取得的第二區3 b塡充第一區3a與導電凸塊 4之間的空間，以及被部份地配置於第一區3 a及導電凸塊 4上。在光學顯微鏡下，觀察到所有的導電凸塊4被層間 絕緣膜3部份地覆蓋。 最後，形成第二互連線5以致於重疊導電凸塊4，藉 以取得多層互連結構。 然後，評估第一互連線2與第二互連線5的接觸鏈。 從200個接觸鏈中的10個位置之評估，發現每一通孔的 平均電阻在1 〇個位置中的4個位置爲20或更小，取得適 當的接觸電阻。但是，在其餘的6個位置中，接觸電阻高 ，且存在有未與第一互線2及第二互連線5互連之一或更 多通孔。 <實施例4> 參考圖6A及6B，以同於實施例2的方式，在形成有 第一互連線2的玻璃基底1上，形成第一區3a、導電凸塊 4、及第二區3b。然後，以同於導電凸塊4的方式，導電 -20- 200837854 凸塊4a的圖案被對齊以重疊導電凸塊4，藉由使用 以網版印刷此圖案，然後乾燥，藉以取得導電凸塊 使用的導電膏除了含有與絕緣膏中的乙二醇單己醚 乙二醇單己醚之外，其餘與實施例1中所使用的相 正取得的導電凸塊4是具有55-60 μπι直徑的圓形。 顯微鏡下，觀察到所有的導電凸塊4凸出於層間絕 的表面之外。 最後，參考圖1，形成第二互連線5以致於重 凸塊4，藉以取得多層互連結構。 然後，評估第一互連線2與第二互連線5的接 從2 00個接觸鏈中的10個位置之評估，發現每一 平均電阻在所有位置爲7 Ω，取得適當的接觸電阻 的結果顯示電阻比實施例2降低。亦即，施加導1 會增強第一互連線2與第二互連線5之間的連接。 <實施例5> 圖1 3 Α及1 3 Β顯示藉由使用網版印刷遮罩所印 間絕緣膜3的圖案。具體而言，圖1 3 A及1 3 B分別 一區3a及第一區3b的圖案。圖13A中所示的圖 5 5 μ m寬的線之注入區及7 2 μ m寬的線之非注入區。 的網版印刷遮罩是不銹鋼網號500，其具有19μιη 其上沈積有15μιη厚的乳膠。圖13Β中所示的圖 55 μπι乘55 μπι的正方形注入區（以矩陣形式配置） 正方形注入區以127 μπι的間距相間隔。所使用的網 導電膏 4 a。所 相同的 同。真 在光學 緣膜3 疊導電 觸鏈。 通孔的 。評估 霄 4 a 刷之層 顯示第 案具有 所使用 線徑， 案具有 ，這些 版印刷 -21 - 200837854 遮罩是具有19 μπι線徑之被施予金屬電鍍處理的不銹鋼網 號500，其上沈積有15μηι厚的乳膠。要藉由使用網版印 刷遮罩以印刷的導電凸塊4之圖案具有5 Ομπι直徑圓（以 矩陣形式配置）的注入區，這些圓以1270111間距相隔。所 使用的網版印刷遮罩是不銹鋼網號400，其具有23 μπι線 徑，其上沈積有30μιη厚的乳膠。 所使用的絕緣膏如下所述：藉由將聚合度約400的聚 φ 乙烯丁醛樹脂溶入乙二醇單己醚並接著添加具有80m2/g 比表面積的氧化矽塡充物及20m2/g的鈦酸鋇塡充物以調 整黏滯度至約160 Pa · s，而製成絕緣膏C ;以及，藉由 將聚合度約400的聚乙烯丁醛樹脂溶入乙二醇單己醚並接 著添加具有30m2/g比表面積的氧化砂塡充物及20m2/g的 鈦酸鋇塡充物以調整黏滯度至約80 Pa · s，而製成的絕緣 膏D。絕緣膏C及D可以調整成具有相同的成份重量比。 所使用的導電膏與實施例1中所使用的相同。 • 參考圖1 ’圖1 3 A中所示的圖案被對齊以致於不會與 第二互連線5 (稍後形成）的接點部相重疊，然後，藉由 使用絕緣膏C，將此圖案網版印刷至形成有第一互連線2 之聚碳酸酯基底1上。在1 〇〇它的熱爐中將產品乾燥3 〇分 鐘，藉以取得第一區3a。真正取得的第一區3a是具有約 80μιη寬度的線，以Ι27μιη間距配置。 然後’導電凸塊4的圖案被對齊以致於與第二互連線 5 (稍後形成）的接點部相重疊，然後，藉由使用導電膏 ，將此圖案網版印刷至第一互連線2。在120°C的熱爐中 -22- 200837854 將產品乾燥1小時，藉以取得導電凸塊4。真正取得的導 電凸塊4是具有5 5-60μιη直徑的圓形且部份地配置於第一 區3a的相鄰相對線上。 圖1 3 B中所示的圖案被對齊以致於不會與第一區3 a 及導電凸塊4相重疊，然後，藉由使用絕緣膏D，網版印 刷此圖案。在lOOt：的熱爐中將產品乾燥30分鐘，藉以取 得第二區3b。取得的第二區3b塡充第一區3a與導電凸塊 φ 4之間的空間，以及被部份地配置於第一區3 a及導電凸塊 4上。在光學顯微鏡下，觀察到所有的導電凸塊4凸出於 層間絕緣膜3的表面之外。 最後，形成第二互連線5以致於重疊導電凸塊4，藉 以取得多層互連結構。 然後，評估第一互連線2與第二互連線5的接觸鏈。 從200個接觸鏈中的1 0個位置之評估，發現每一通孔的 平均電阻在所有位置爲6 Ω，取得適當的接觸電阻。 <實施例6> 如圖10A及10B所示，以噴墨法將奈米銀墨水圖型化 印刷至聚碳酸酯基底1上，接著將其乾燥，藉以取得閘極 電極9。然後，以旋轉塗敷，塗敷熱聚合的聚醯乙胺，及 以1 90°C加熱，藉以取得閘極絕緣膜1 〇。所取得的閘極絕 緣膜10具有3.6的特定介電常數及0·4μιη的膜厚。接著 ，紫外光照射經過用於表面調節的光罩而至源極電極2a 與汲極電極2b要形成的區域上。然後，以噴墨法將奈米 -23 - 200837854 銀墨水圖型化印刷，接著將其乾燥，藉以取得源極電極2a 和汲極電極2b。接著，以噴墨法將墨水圖型化印刷’接著 將其乾燥，藉以取得有機半導體層11。如此，取得有機電 晶體。藉由將下述結構式所代表的有機半導體材料溶解於 二甲苯中以製備所使用的墨水。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a multilayer interconnection structure, a multilayer interconnection structure, a transistor device, and an image display. [Prior Art] Conventional Φ semiconductor devices having a transistor and a diode on a substrate or on a semiconductor wafer typically use a multilayer interconnection structure to increase integration density. In the multi-layer interconnect structure, an interlayer insulating film having via holes to provide an electrical connection between the interconnect lines is used. In recent years, for example, a porous cerium oxide film, a lanthanum fluoride oxide film, and an organic insulating film of lanthanum and a metal having a methyl group have a relatively low dielectric constant insulating material, and the like. The more popular it is as a material for the interlayer insulating film. Among these materials, an organic insulating film having a low dielectric constant (about 2. 2 - 4.0) is usually used. • However, since the shadow technique is used to form the through holes in the organic insulating film, the number of manufacturing steps is increased, and thus it is disadvantageous to use the organic insulating film in terms of cost. Screen printing is the deposition of ink onto a web (screen printing mask) having a non-injected ink zone where latex is placed to prevent ink from passing through, and by sliding the roller to pass the ink through the mesh. This method is advantageous because it can reduce manufacturing steps and has higher material use efficiency. The screen printing method is capable of forming a precise pattern with a simple technique, and thus has been used in recent years to form interconnections between transistors and the like. However, the surface of the ink that has just been printed still in 200837854 is flat due to gravity, causing slight smudges. This slight smudge height may fill a small through hole. Therefore, a 1 ΟΟμπι square via is the smallest size that can be achieved with conventional screen printing. Further, the screen printing method is generally affected by various parameters such as the pitch (the distance between the screen mask and the substrate), the angle of the roller, the pressure, and the speed, and therefore, it is difficult to stably produce small through holes. In the case of large-area printing, the smallest size actually achieved is about 300 μm square. Japanese Patent Publication No. 2006_1 20873 discloses a method of manufacturing an impedance controlled circuit board. According to this method, after the conical conductive bumps are formed on the metal foil by screen printing, an insulator is deposited on the conductive bumps so that the conductive bumps extend through the insulator. Then, a thin metal is deposited on the insulator to electrically connect to the head of the conductive bump. The problem with this method is that the material of the insulator is limited by heating and applying the prepreg, and a load due to heat and pressure is applied to the insulator. The minimum size of the conductive bumps obtained in one embodiment is 150 μm, and there is no mention of the possibility of reducing the size of the conductive bumps. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method of fabricating a multilayer interconnection structure capable of electrically interconnecting upper and lower interconnect lines via an interlayer insulating film having small via holes; a multilayer interconnection structure, Wherein the upper and lower interconnect lines are electrically interconnected via an interlayer insulating film having small via holes; a transistor device including a multilayer interconnect structure; and an image display including the transistor device. In an embodiment of the present invention, a method of manufacturing a multilayer structure using a screen printing method is provided. In the multilayer interconnection structure, an interlayer insulating film having a via hole in which a conductive bump is provided, and a second interconnect line are stacked on the substrate, and a first interconnect line is formed on the bottom thereof. The first interconnect is electrically connected to the second interconnect via the conductive bumps. The method comprises the steps of: forming a first region of an interlayer insulating film on a substrate on which a first interconnect line is formed, the first region comprising a portion of a peripheral wall of the via hole; and forming on the substrate on which the first region is formed a second region of the interlayer insulating film, the second region including the remaining portion of the surrounding wall of the via hole; and the formation of the conductive bump. This embodiment of the invention provides a method of fabricating a multilayer interconnect structure capable of electrically connecting upper and lower interconnect lines via small vias. According to an aspect of the present invention, a method of manufacturing a multilayer interconnection structure capable of electrically connecting upper and lower interconnection lines via an interconnection insulating film having small via holes; a multilayer interconnection structure in which upper and lower interconnections are provided The wires are electrically interconnected via an interlayer insulating film having small via holes; a transistor device including a multilayer interconnect structure; and an image display including a transistor device. [Embodiment] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. According to the manufacturing method of the multilayer interconnection structure of the embodiment of the present invention, a multilayer interconnection structure is manufactured using a screen printing method, wherein an interlayer insulating film having a via hole in which a conductive bump is provided, and a second interconnection line Stacked on the substrate, a first interconnect line is formed on the bottom. The first interconnect is electrically connected to the second interconnect via a conductive bump. Further, the method includes the steps of: forming a first region of the interlayer insulating film on the substrate on which the first interconnect line is formed, the first region including a portion of the surrounding wall of the via hole; on the substrate on which the first region is formed Forming a second region of the interlayer insulating film of -6-200837854, the second region including the remaining portion of the surrounding wall of the via hole; and forming the conductive bump. According to this method, it is possible to manufacture a high-density multilayer interconnection structure electrically connecting the upper and lower interconnection lines via small via holes in a small number of steps using a simple technique. Figure 1 shows an embodiment of a multilayer interconnect structure in accordance with an embodiment of the present invention. In the multilayer interconnection structure 1 shown in Fig. 1, an interlayer insulating film 3 having a via hole is formed on a substrate having a first interconnection 2 formed thereon. The conductive bumps 4 are filled in the through holes. The second interconnection 5 on the interlayer insulating film 3 is electrically connected to the first interconnection 2 via the conductive bumps 4. The multilayer interconnection structure shown in Fig. 1 is fabricated by using the fabrication method of the multilayer interconnection structure of the embodiment of the present invention. 2A-2C show a method of fabricating a multilayer interconnect structure in accordance with an embodiment of the present invention. First, the first region 3a of the interlayer insulating film 3 is formed on the substrate 1 on which the first interconnect line (not shown) is formed by using a screen printing method, so that one of the surrounding walls including each via hole is formed. Part of the interlayer insulating film 3 (refer to Figure 2 A). The first region 3a is formed such that a via hole is formed on the first interconnect (not shown). Next, by using the screen printing method, the conductive bumps 4 are formed to be aligned with the portions of the peripheral walls of the via holes (see Fig. 2B). Then, by using the screen printing method, the second region 3b of the interlayer insulating film 3 which is aligned with the first region 3a and the conductive bump 4 is formed so that the remaining portion of the surrounding wall of each via hole is formed (see Figure 2C). By these steps, the interconnection structure is obtained in which the conductive bumps 4 are electrically connected to the first interconnection lines protruding beyond the surface of the interlayer insulating film 3. Then, the second interconnect 5 is formed to be electrically connected to the conductive bumps 4, so that the double-layer interconnection structure is obtained in 200837854. In the first three steps described above, after the conductive bumps 4 are formed on the first interconnect 2, the first region 3a and the second region 3b are formed. The order of the steps can be appropriately selected depending on the target size of the through hole and the shape of the first area 3a. In an embodiment of the invention, a commercially available conductive paste containing a conductive material may be used to form a conductive bump/conductive material comprising silver, copper, carbon, and aluminum. Among these materials, a metal material is preferred. Two or more types of conductive materials may be used in combination. The first interconnect line and the second interconnect line may be formed of one or more of the above-described conductive materials by using a known method. Screen printing and screen printing masks used in screen printing processes are well known in the art. Screen printers are required to have a planable setting for pitch, roll angle, pressure and speed, and preferably a substrate platform with an operational accuracy of less than 1 〇 μπι. The screen printing mask can be appropriately selected depending on the shape of the area to be printed in each step, the viscosity of the paste to be used, the solid ratio, and the like. By adjusting the wire diameter (thickness) of the web, the ratio of the opening alpha zone, and the thickness of the latex, the injection of the paste can be controlled, so that a film having a desired thickness can be printed. In the embodiment of the invention, the interlayer insulating film preferably contains an organic material and particles. Examples of the organic material include polyvinyl alcohol resin, polyvinyl acetal resin, acrylic resin, ethyl cellulose resin, polyethylene, polystyrene, and polyamine. These materials can be used in combination with two or more of them. Any of the organic and inorganic particles may be particles as long as it can exist as particles in the interlayer insulating film. However, since the size of the inorganic particles -8 - 200837854 is easily controlled 'and the inorganic particles can be dispersed in a solvent, inorganic particles are preferable. Examples of the inorganic particles include cerium oxide (Si〇2), aluminum oxide (A1203), titanium oxide (Ti〇2), zinc oxide (ZnO), and barium titanate (BaTiCh). Among these materials, materials having a relatively low dielectric constant such as cerium oxide, aluminum oxide, and zinc oxide are preferred. Porous particles having a mesoporous or microporous structure such as mesoporous cerium oxide can also be used. In order to form an interlayer insulating film, an insulating paste may be used. The insulating paste is prepared by mixing an organic material and particles in a solvent and optionally adding a dispersing agent, a plasticizer, and a viscosity adjusting agent. The mixing ratio between the organic material and the particles is not particularly limited, and may be appropriately adjusted depending on the pattern to be formed so that the paste has appropriate physical properties. In order to secure the flexibility of the interlayer insulating film, it is preferred to increase the proportion of the organic material. Specifically, the volume of the organic material in the interlayer insulating film is preferably 40% or more, more preferably 50% or more, so that the interlayer insulating film can be applied to the flexible substrate on average. Although the insulating paste may be adjusted according to the shape and area of the first region and the second region of the interlayer insulating film, the components of the dried first region and the second region are preferably not too different from each other. 3A-3C illustrate another method of fabricating a multilayer interconnect structure in accordance with an embodiment of the present invention. First, the first region 3a of the interlayer insulating film 3 is formed on the substrate 1 on which the first interconnect (not shown) is formed by using the screen printing method. A first zone 3a of substantially parallel lines is formed (see Figure 3a). The first region 3a is formed such that a via hole is formed on the first interconnect (not shown). Next, by using the screen printing method, the conductive bumps 4 which are aligned with the first region 3a -9-200837854 are formed (see Fig. 3B). Then, by using the screen printing method, the second region 3b of the interlayer insulating film 3 which is aligned with the first region 3a and the conductive bumps 4 is formed. The second region 3b is formed as a discontinuous pattern' extending in the region where the first region 3a is excluded (see Fig. 3C). By these three steps, the interconnection structure is obtained in which the conductive bumps 4 are electrically connected to the first interconnection lines protruding beyond the surface of the interlayer insulating film 3. Then, a second interconnect 5 is formed to be electrically connected to the conductive bumps 4 so as to obtain a two-layer interconnect structure. The width and the interval of the line pattern of the first region 3a and the shape of the discontinuous pattern of the second region 3b can be appropriately determined in accordance with the required size and interval between the through holes. Since the line pattern and the discontinuous pattern can be formed relatively easily by using the screen printing method, the physical properties of the insulating paste and the allowable range of the printing conditions are increased, thereby realizing a stable printing operation. In accordance with an embodiment of the present invention, as shown in Figures 2A-2C and Figures 3A-3C, it is preferred to form the first region 3a, then form the conductive bumps 4, and then form the second regions 3b. If, as shown in Fig. 4A, the conductive bumps 4 are formed before the formation of the first region 3a, the first region 3a is printed on the conductive bumps 4. That is, when the insulating paste is injected into the region of the web 7 through the latex-free 8 by the roller 6, the web 7 is spaced apart from the substrate 1 by the height of the conductive bump 4, so that the amount of the insulating paste injected is increased. As a result, as shown in Fig. 4B, the conductive bump 4 is easily covered by the first region 3a of the interlayer insulating film 3. Further, the pattern accuracy of the first zone 3a can be reduced. Therefore, forming the first region 3a before forming the conductive bump 4 can increase the formation accuracy of the first region 3a. If the conductive bump 4 is formed after the formation of the first region 3a as shown in Fig. 5, the amount of the conductive paste implanted is increased by the amount corresponding to the height of the first region 3a. This method is preferable in that the conductive bump 4 can be formed outside the surface of the interlayer insulating film 3 by -10-200837854. Further, since the conductive bumps 4 are formed before the formation of the second region 3b, it is possible to prevent the via holes from being covered by the insulating paste for forming the second region 3b of the second region 3b to be printed due to the level of the insulating paste, Thus, the conductive bumps 4 can be formed within the via holes. As such, the first interconnect 2 can be electrically connected to the second interconnect 5. In the embodiment of the present invention, it is sometimes difficult to prevent the top of the conductive bump 4 from being interposed by the interlayer insulating film 3 depending on conditions such as the height of the conductive bump, the distance between the conductive bumps, and the thickness of the interlayer insulating film. It is difficult to prevent the joint portion of the conductive bump 4 from being covered by the interlayer insulating film 3, either partially or completely (Fig. 4B). If the interlayer insulating film 3 is disposed on the conductive bumps 4, it is difficult to electrically connect the conductive bumps 4 to the second interconnect lines 5, causing interconnection failure. In order to prevent this, as shown in Fig. 6A, the conductive paste 4a is applied onto the conductive bumps 4 covered by the interlayer insulating film 3. Then, the conductive bumps 4 are electrically connected to the conductive material contained in the conductive paste 4a, so that the first interconnecting wires 2 can be electrically connected to the second interconnecting wires 5. With regard to the treatment of electrically connecting the conductive bump 4 to the conductive material of the conductive paste 4a, application of pressure or heat may be effective. In order to facilitate the electrical connection, the interlayer insulating film 3 preferably contains an organic material which is soluble in the solvent contained in the conductive paste 4a. Then, the solvent contained in the conductive paste 4a dissolves the organic material contained in the interlayer insulating film 3 so that the conductive material contained in the conductive paste 4a passes through the interlayer insulating film 3 to be in contact with the conductive bumps 4. Thus, the conductive bumps 4 can be electrically connected to the conductive material of the conductive paste 4a. Next, the solvent is dried so as to form conductive bumps 4 electrically connected to the first interconnect 2 (see Figs. -11 - 200837854 6B). As shown in Figs. 2A to 2C and Figs. 3 to 3C, in the case where the conductive bumps 4 are formed after the formation of the first region 3a, the second region 3b contains an organic material which is soluble in the solvent contained in the conductive paste 4a. In the embodiment of the present invention, as shown in Figs. 7A and 7B, in the case where the first zone 3a is not properly aligned with the second zone 3b, the substrate 1 is not completely covered by the first zone 3a or the second zone 3b. . Fig. 7A is a top view 'Fig. 7B is a cross-sectional view taken along the broken line of Fig. 7A. In order to prevent this defect, the viscosity of the first insulating paste to be used for forming the first region 3a is made higher than the viscosity of the second insulating paste to be used for forming the second region 3b. That is, since the first insulating paste having high viscosity and low fluidity is used to form the first region 3a, the first region 3a can form a desired pattern. At the same time, since the second insulating paste having a low viscosity and high fluidity is used to form the second region 3b, the printed second insulating paste is flattened before being dried, thereby preventing the occurrence of defects (refer to the figure). 8 A-8C). Thus, an interlayer insulating film having high reliability can be formed. Fig. 8A is a top view, and Figs. 8B and 8C are cross-sectional views taken along the broken lines A and B of Fig. 8A, respectively. The flow of the second insulating paste improves the uniformity of the film thickness of the second region 3b, thereby lowering the level difference of the first region 3a. Although the viscosity of the insulating paste may be appropriately determined depending on the size of the through hole to be formed or the distance between the through holes, the viscosity of the first insulating paste is generally 100 Pa·s or more, preferably. It is 150Pa·s. The viscosity of the second insulating paste is generally 100 Pa·s or less, preferably 50 Pa·s or less. In an embodiment of the invention, the specific surface area of the particles contained in the first region of the interlayer insulating film is preferably larger than the ratio of the particles contained in the second region to -12 - 200837854. Although the interlayer insulating film is separately formed as the first region and the second region, the first region and the first region are from the viewpoint of the affinity between the first region and the second region and the uniformity of the entire interlayer insulating film. The second zone ideally has the same composition. As described above, it is preferred to use a first insulating paste having a high viscosity (low fluidity) and a second insulating paste having a low viscosity (high fluidity). The easiest way to adjust the viscosity of the paste without changing the solids content is to adjust the contents of the solvent. However, if the content of the solvent in the paste is changed in order to adjust the viscosity, the solid content in the paste changes. That is, if the content of the solvent is increased to lower the viscosity of the second insulating paste, the content of the solid is lowered, so that the film thickness of the desired second region is lowered. As a result, the film thickness of the second region became smaller than that of the first region. Thus, the thickness uniformity of the interlayer insulating film is lowered to adversely affect the second interconnect. This problem can be solved by using particles having different specific surface areas. The specific surface area is the total surface area of the particles per unit weight. The increased viscosity of a particle is proportional to its specific surface area. The larger the specific surface area (i.e., the smaller particle size), the greater the characteristic of increased viscosity. Therefore, the first insulating paste is made to contain particles having a large specific surface area to have a more compact viscosity, and the second insulating paste is made into particles having a smaller specific surface area to have a lower viscosity. Thus, it is possible to prepare an insulating paste having different viscosities without changing the content and composition of the solid, so that the uniformity of the composition and thickness of the interlayer insulating film can be improved. In an embodiment of the invention, as shown in Figs. 8A-8C, the interlayer insulating film is preferably formed such that at least a portion of the second region is formed on the first region. As described above, in the case where the first zone is not properly aligned with the second zone, the substrate may be completely covered by the first zone or the second zone. If the second insulating paste having fluidity is used, the second region is filled with the gap of the first region and partially disposed over the first region, so that a highly reliable interlayer insulating film can be formed and the above defects are prevented. . Figure 9 shows an embodiment of a transistor in accordance with an embodiment of the present invention. In the transistor device shown in Fig. 9, a gate electrode 9 and a gate insulating film 1 are formed on the substrate 1. The source electrode 2a, the drain electrode 2b, and the organic half φ conductor layer 1 1 are formed on the gate insulating film 1 。. Further, an interlayer insulating film 3 having via holes is formed to cover the source electrode 2a, the drain electrode 2b, and the organic semiconductor layer 11. The conductive bump 4 is disposed in the through hole. The upper electrode 5a is formed on the interlayer insulating film 3, and the interlayer insulating film 3 has a through hole in which the conductive bump 4 is provided. The source electrode 2a as the first interconnect line is electrically connected to the upper electrode 5a as the second interconnect line via the conductive bumps 4. The transistor device shown in Fig. 9 is fabricated by using the manufacturing method of the multilayer interconnection structure of the embodiment of the present invention. • Figures 1A and 10B show another embodiment of a transistor device in accordance with an embodiment of the present invention. Fig. 10A is a cutaway side view, and Fig. 10B is a top view. In Figs. 10A and 10B, the same elements as those shown in Fig. 9 are denoted by the same reference numerals and will not be described again. In the transistor device shown in Figs. 10A and 10B, the first region 3a of the interlayer insulating film 3 is disposed to cover the organic semiconductor layer 11 as a channel forming portion. Protecting the organic semiconductor layer 1 1 with the first region 3a in this manner minimizes variation in transistor characteristics due to oxygen and water vapor in the atmosphere. When the conductive bump 4 and the second region 3b are screen-printed, this also prevents the mesh from coming into contact with the organic semiconductor layer 11, thereby lowering the physical load of the -14-200837854. Further, in the case of a process of dissolving the organic material contained in the second region 3b in a solvent contained in the second conductive paste (see FIGS. 6A and 6B), it is possible to prevent the organic semiconductor layer 11 from being damaged by the solvent. Figure 11 shows an embodiment of an image display in accordance with an embodiment of the present invention. In the image display shown in Fig. 11, a gate electrode 9 and a gate insulating film 10 are formed on the substrate 1. On the gate insulating film 10, a source electrode 2a, a drain electrode 2b, and an organic semiconductor layer 11 are formed. Further, an interlayer insulating film 3 having a via hole is formed to cover the source electrode 2a, the drain electrode 2b, and the organic semiconductor layer 11. The conductive bump 4 is disposed in the through hole. The pixel electrode 5b is formed on the interlayer insulating film 3 having a via hole in which the conductive bump 4 is provided. The source electrode 2b as the first interconnect is electrically connected to the pixel electrode 5b as the second interconnect via the conductive bump 4. The electrophoretic display device 16 is attached to the active matrix substrate having this configuration, and in the electrophoretic display device 16, the transparent electrode 14 and the microcapsule 15 are formed on the support substrate 13. The image display shown in Fig. 11 is fabricated by using the manufacturing method of the multilayer interconnection structure of the embodiment of the present invention. The image display device which can be used in the embodiment is not limited to the electrophoretic display device, but may include a liquid crystal display device, an organic EL device, and the like. One of these devices can be used to provide a flat-panel image display or a flexible image display. The flat-panel image display does not cause pressure on the viewer's eyes. [Embodiment] -15- 200837854 <Embodiment 1> The pattern of the first region 3a and the second region 3b of the interlayer insulating film 3 to be printed by using the screen printing mask has a line injection region of 160 μm wide and a line of 8 Ομπι wide Injection area. The screen printing mask used was a stainless steel mesh number 500 having a 19 μπι wire diameter on which 15 μm thick latex was deposited. The pattern of the conductive bumps 4 to be printed by the screen printing mask has an implantation area of 50 μm diameter circle (arranged in a matrix) which are spaced by 240 μm. The screen printing mask used was a stainless steel mesh number 400 having a wire diameter of 23 μηη on which 3 Ομη thick latex was deposited. The viscosity is adjusted to about 150 Pa · s by dissolving a polyvinyl alcohol resin in a mixed solvent of ethylene glycol butyl ether and alpha alcohol and then adding an alumina crucible having a specific surface area of 50 m 2 /g. Make the insulating paste used. The conductive paste used is a thermosetting paste containing silver as a conductive material. Referring to FIG. 1, the pattern of the first region 3a is aligned so as not to overlap with the contact portion of the second interconnect 5 (formed later), and then the pattern is screen-printed by using an insulating paste to The glass substrate 1 on which the first interconnect 2 is formed is formed. The product was dried in a hot oven at 100 ° C for 30 minutes to obtain the first zone 3a. The first region 3a actually obtained is a line having a width of about 1 80-1 90 μm and is arranged at a pitch of 240 μm. Then, the pattern of the conductive bumps 4 is aligned so as to overlap with the contact portion of the second S wiring 5 (formed later), and then this pattern is screen-printed by using a conductive paste. The product was dried in a hot oven at 1200 ° C for 1 hour to obtain conductive bumps 4 . The actually obtained conductive bump 4 is a circular shape having a diameter of 5 5 - 60 μm and partially disposed on the adjacent phase -16-200837854 of the first region 3a. In the direction perpendicular to the line of the first region 3a, the pattern of the second region 3b is aligned so that the first region 3a and the conductive bump 4 are not overlapped, and then the pattern is screen-printed by using an insulating paste. The product was dried in a hot oven at 1 °C for 30 minutes to obtain a second zone 3b. The obtained second region 3b fills the space between the first region 3a and the conductive bump 4, and is partially disposed on the first region 3a and the conductive bump 4. Under the optical microscope, it was observed that all of the conductive bumps 4 protruded beyond the surface of the interlayer insulating film 3. Finally, the second interconnect lines 5 are formed so as to overlap the conductive bumps 4, thereby obtaining a multilayer interconnection structure. Then, the contact chain of the first interconnect 2 and the second interconnect 5 is evaluated. From the evaluation of 10 locations in the 200 contact chains, it was found that the average resistance of each via was 8 Ω at all positions, and the appropriate contact resistance was obtained. <Embodiment 2> Figs. 1A and 1B show a pattern of the interlayer insulating film 3 printed by using a screen printing mask. Specifically, Figures 1 2A and 1 2B show the patterns of the first zone 3a and the second zone 3b, respectively. The pattern shown in Fig. 12A has an injection region of a line of 170 μm wide and a non-implantation region of a line of 70 μm wide. The screen printing mask used was a stainless steel mesh number 500 having a 19 μm diameter wire with a 15 μm thick latex deposited thereon. The pattern shown in Fig. 12A has a rectangular injection region (arranged in a matrix form) of 60 μm long and 170 μm wide, and these rectangular injection regions are spaced by a pitch of 240 μm. The screen printing mask used was a non--17-200837854 stainless steel mesh number 500 having a wire diameter of 19 μπι, which was deposited with a 15 μm thick latex. The circles are separated by a pitch of 50 μm by using a screen printing mask to have a pattern of printed conductive bumps 4 having a diameter of 50 μm (disposed in a matrix). The screen printing mask used was a stainless steel mesh number 400 having a 2 3 μπι wire diameter on which a 30 μm thick latex was deposited. The insulating paste used was as follows: the viscosity was adjusted to about 250 Pa by dissolving a polyvinyl butyral resin in ethylene glycol monohexyl ether and then adding an alumina crucible having a specific surface area of 80 m 2 /g. s, and the resulting insulating paste A; and, by dissolving the polyvinyl butyral resin into ethylene glycol monohexyl ether and then adding an alumina cerium having a specific surface area of 30 m 2 /g to adjust the viscosity to about 80 Pa · s, and made of insulating paste B. The insulating pastes A and B can be adjusted to have the same composition-to-weight ratio. The conductive paste used was the same as that used in Example 1. Referring to FIG. 1, the pattern shown in FIG. 12A is aligned so as not to overlap with the contact portion of the second interconnect 5 (formed later), and then the pattern is screened by using the insulating paste A. Printing onto the glass substrate 1 on which the first interconnect 2 is formed. The product was dried in a hot oven at 100 ° C for 30 minutes to obtain the first zone 3a. The first region 3a actually obtained is a line having a width of about 185-195 μm, and is arranged at a pitch of 240 μm. Then, the pattern of the conductive bumps 4 is aligned so as to overlap the contact portion of the second interconnect 5 (formed later), and then the pattern is screen-printed by using a conductive paste. The product was dried in a hot oven at 120 ° C for 1 hour to obtain conductive bumps 4 . The actually obtained conductive bump 4 is a circular shape having a diameter of 5 5-60 μm and partially disposed on the adjacent phase -18-200837854 pair line of the first region 3a. The pattern shown in Fig. 12B is aligned so as not to overlap the first region 3a and the conductive bump 4, and then the pattern is printed by using the insulating paste B. The product was dried in a hot oven at 100 ° C for 30 minutes to obtain a second zone 3b. The obtained second region 3b fills the space between the first region 3a and the conductive bump 4, and is partially disposed on the first region 3a and the conductive bump 4. Under the optical microscope, it was observed that all of the conductive bumps 4 protruded beyond the surface of the interlayer insulating film 3. Finally, the second interconnect lines 5 are formed so as to overlap the conductive bumps 4, thereby obtaining a multilayer interconnection structure. Then, the contact chain of the first interconnect 2 and the second interconnect 5 is evaluated. From the evaluation of 10 locations in 200 contact chains, it was found that the average resistance of each via was 12 Ω at all positions, and the appropriate contact resistance was obtained. <Example 3> The screen printing mask used for the interlayer insulating film 3, the screen printing mask for the conductive bump 4, the insulating paste, and the conductive paste were the same as those used in Example 2 . The pattern of the conductive bumps 4 is aligned so as to overlap the contact portion of the second interconnect 5 (formed later), and then the pattern is screen-printed to form the first interconnect by using a conductive paste. On the glass substrate 1 of the line 2. The product was dried in a hot oven at 1 20 ° C for 1 hour to obtain conductive bumps 4. The actually obtained conductive bump 4 is a circle having a diameter of 5 5 - 60 μm. The pattern shown in Fig. 12A is aligned so as not to overlap with the conductive bumps 4 -19 - 200837854, and then the pattern is screen printed by using the insulating paste A. The product was dried in a hot oven at 100 ° C for 30 minutes to obtain the first zone 3a. The actually obtained first region 3a is a line having a width of about 185 to 195 μm, is disposed at a pitch of 240 μππ, and is partially disposed on the conductive bump 4. The pattern shown in Fig. 1 is aligned so as not to overlap the first region 3a and the conductive bump 4, and then the pattern is printed by using the insulating paste B. The product was dried in a lOOt hot oven for 30 minutes to obtain a second zone 3b. The obtained second region 3b fills the space between the first region 3a and the conductive bump 4, and is partially disposed on the first region 3a and the conductive bump 4. Under the optical microscope, it was observed that all of the conductive bumps 4 were partially covered by the interlayer insulating film 3. Finally, the second interconnect lines 5 are formed so as to overlap the conductive bumps 4, thereby obtaining a multilayer interconnection structure. Then, the contact chain of the first interconnect 2 and the second interconnect 5 is evaluated. From the evaluation of 10 locations in 200 contact chains, it was found that the average resistance of each via was 20 or less at 4 of the 1 , positions, and the appropriate contact resistance was obtained. However, in the remaining six positions, the contact resistance is high, and there is one or more via holes that are not interconnected with the first interconnect 2 and the second interconnect 5. <Embodiment 4> Referring to Figs. 6A and 6B, in the same manner as in Embodiment 2, on the glass substrate 1 on which the first interconnect 2 is formed, the first region 3a, the conductive bump 4, and the second are formed. District 3b. Then, in the same manner as the conductive bumps 4, the patterns of the conductive -20-200837854 bumps 4a are aligned to overlap the conductive bumps 4, and the pattern is printed by screen printing, and then dried to obtain conductive bumps. The conductive paste 4 has a diameter of 55-60 μm in addition to the ethylene glycol monohexyl ether glycol monohexyl ether in the insulating paste, and the conductive bump 4 obtained in the same manner as used in the embodiment 1. Round. Under the microscope, it was observed that all of the conductive bumps 4 protruded out of the surface between the layers. Finally, referring to Fig. 1, a second interconnect 5 is formed so as to be heavily bumped 4, thereby obtaining a multilayer interconnect structure. Then, the evaluation of the connection of the first interconnect 2 and the second interconnect 5 from 10 locations in the 200 contact chains was evaluated, and it was found that each average resistance was 7 Ω at all positions, and the appropriate contact resistance was obtained. The results showed that the electrical resistance was lower than that of Example 2. That is, applying the conduction 1 enhances the connection between the first interconnect 2 and the second interconnect 5. <Embodiment 5> Figs. 1 3 and 13 show the pattern of the insulating film 3 by using a screen printing mask. Specifically, Fig. 13 A and Fig. 3 B are patterns of a region 3a and a first region 3b, respectively. The injection region of the 5 μ μ wide line and the non-implantation region of the 7 2 μ m wide line shown in Fig. 13A are shown in Fig. 13A. The screen printing mask is a stainless steel mesh number 500 having a 19 μm thick latex deposited thereon with a thickness of 15 μm. Fig. 13A is a diagram of a 55 μπι by 55 μπ square injection region (configured in a matrix). The square injection regions are spaced at a pitch of 127 μm. The mesh conductive paste used 4 a. The same as the same. True in the optical film 3 stack of conductive contacts. Through hole. Evaluation 霄 4 a The layer of the brush shows that the case has the wire diameter used, and the case has, these prints - 21 - 200837854 The mask is a stainless steel mesh number 500 with a metal plating treatment of 19 μπι wire diameter, deposited thereon There is 15μηι thick latex. The pattern is printed by using a screen printing mask having a pattern of conductive bumps 4 having a 5 Ομπ diameter circle (arranged in a matrix) which are spaced by 1270111. The screen printing mask used was a stainless steel mesh number 400 having a 23 μπι wire diameter on which a 30 μm thick latex was deposited. The insulating paste used was as follows: a polyφ ethylene butyral resin having a polymerization degree of about 400 was dissolved in ethylene glycol monohexyl ether and then a cerium oxide filling having a specific surface area of 80 m 2 /g and 20 m 2 /g were added. a barium titanate filling to adjust the viscosity to about 160 Pa · s to form an insulating paste C; and, by dissolving a polyethylene butyral resin having a polymerization degree of about 400 into ethylene glycol monohexyl ether Next, an insulating paste D prepared by adding a cerium oxide lanthanum having a specific surface area of 30 m 2 /g and a barium titanate filling of 20 m 2 /g to adjust the viscosity to about 80 Pa · s was added. The insulating pastes C and D can be adjusted to have the same composition weight ratio. The conductive paste used was the same as that used in Example 1. • Referring to FIG. 1 'the pattern shown in FIG. 1 3 A is aligned so as not to overlap the contact portion of the second interconnect 5 (formed later), and then, by using the insulating paste C, The pattern is screen printed onto the polycarbonate substrate 1 on which the first interconnect 2 is formed. The first zone 3a is obtained by drying the product in a hot oven at 1 Torr for 3 minutes. The first region 3a actually obtained is a line having a width of about 80 μm, and is arranged at a pitch of μ27 μm. Then the pattern of the conductive bumps 4 is aligned so as to overlap the contact portion of the second interconnect 5 (formed later), and then the pattern is screen printed to the first interconnect by using a conductive paste. Line 2. The product was dried in a hot oven at 120 ° C for -22-200837854 to obtain conductive bumps 4 . The actually obtained conductive bumps 4 are circular with a diameter of 5 5-60 μm and are partially disposed on adjacent opposite lines of the first region 3a. The pattern shown in Fig. 1 3 B is aligned so as not to overlap the first region 3 a and the conductive bump 4, and then the pattern is printed by using the insulating paste D. The product was dried in a lOOt: hot oven for 30 minutes to obtain a second zone 3b. The obtained second region 3b fills the space between the first region 3a and the conductive bump φ 4 and is partially disposed on the first region 3 a and the conductive bump 4 . Under the optical microscope, it was observed that all of the conductive bumps 4 protruded beyond the surface of the interlayer insulating film 3. Finally, the second interconnect lines 5 are formed so as to overlap the conductive bumps 4, thereby obtaining a multilayer interconnection structure. Then, the contact chain of the first interconnect 2 and the second interconnect 5 is evaluated. From the evaluation of 10 locations in 200 contact chains, it was found that the average resistance of each via was 6 Ω at all positions, and the appropriate contact resistance was obtained. <Example 6> As shown in Figs. 10A and 10B, a nano silver ink was patterned onto the polycarbonate substrate 1 by an inkjet method, and then dried to obtain a gate electrode 9. Then, the thermally polymerized polyethylamine was applied by spin coating, and heated at 1 90 ° C to obtain a gate insulating film 1 〇. The obtained gate insulating film 10 has a specific dielectric constant of 3.6 and a film thickness of 0.4 μm. Next, the ultraviolet light is irradiated through the mask for surface adjustment to the region where the source electrode 2a and the drain electrode 2b are to be formed. Then, the nano -23 - 200837854 silver ink was patterned by an ink jet method, and then dried to obtain the source electrode 2a and the drain electrode 2b. Next, the ink is patterned by the ink jet method, and then dried, whereby the organic semiconductor layer 11 is obtained. Thus, an organic transistor is obtained. The ink used was prepared by dissolving an organic semiconductor material represented by the following structural formula in xylene.
所取得的有機電晶體具有ΙΟμπι的通道長度及200μπι的通 道寬度。 所使用之用於層間絕緣膜3及導電凸塊4的網版印刷 遮罩與實施例2中所使用的相同。所使用的絕緣膏如下所 述：藉由將聚乙烯丁醛樹脂溶入乙二醇單己醚並接著添加 具有80m2/g比表面積的氧化矽塡充物及20m2/g比表面積 的鈦酸鋇塡充物以調整黏滯度至約250 Pa · s，而製成的 絕緣膏E ;以及，藉由將聚乙烯丁醛樹脂溶入溶劑中並接 著添加具有30m2/g比表面積的氧化矽塡充物及20m2/g比 表面積的鈦酸鋇塡充物以調整黏滯度至約100.Pa· s，而 製成的絕緣膏F。絕緣膏E及F可以調整成具有相同的成 份重量比。所使用的導電膏與實施例1中所使用的相同。 圖1 2 A中所示的圖案被對齊以致於不會與上電極5 ( •24- 200837854 稍後要形成）的接觸部相重疊，然後，藉由使用絕緣膏E ，網版印刷此圖案至有機電晶體上。在降壓下，在100 r 的真空熱爐中將產品乾燥，藉以取得第一區3 a。然後，導 電凸塊4的圖案被對齊以致於不會與上電極5a (稍後要形 成）的接觸部相重疊，然後，藉由使用導電膏，網版印刷 此圖案至源極電極2a。在120°C將產品乾燥，藉以取得導 電凸塊4。圖1 2B中所示的圖案會被對齊以致於不會重疊 第一區3a及導電凸塊4,然後，藉由使用絕緣膏F，網版 印刷此圖案。在100°C將產品乾燥，藉以取得第二區3b。 最後，藉由使用銀粒子、丙烯酸系樹脂、及溶劑製成的銀 膏，網版印刷上電極5 a的圖案以重疊導電凸塊4，然後將 其乾燥，藉以取得與有機電晶體相通的上電極5a。如此， 取得主動矩陣基底，其中，電晶體裝置以格子狀配置。 然後，以微波混合及分散20重量份的氧化鈦、1重量 份的酸聚合物、2重量份的矽聚合物分枝碳墨MX3-GRX-001 (由 Nippon Shokubai Co. Ltd.製造）、及 77 重量份的 矽油 KF96L-lcs (由 Shin-Etsu Chemical Co” Ltd.製造） 一小時，以取得具有黑色及白色粒子的散佈液體。以使用 明膠及阿拉伯膠的複雜凝聚法，形成具有黑色及白色粒子 分散液體的微囊。微囊的平均粒徑約爲60μιη。將微囊分 散在胺甲酸酯樹脂溶劑中以取得分散液體。以線刀法將散 液體散佈至形成有透明電極膜的膜基底上，藉以形成均勻 的微囊片。如此，取得電泳顯示裝置。 所取得的電泳顯示裝置附著至主動矩陣基底，藉以取 -25- 200837854 得如圖11所示的影像顯示器。確認取得的影像顯示器能 夠以實質上200 ppi的解析度，取得單色顯示影像。 <實施例7> 如圖10A及10B所示，以噴墨法將奈米銀墨水圖型化 印刷至玻璃基底1上，接著將其乾燥，藉以取得閘極電極 9。然後，以旋轉塗敷，塗敷熱聚合的聚醯乙胺，及以280 °C加熱，藉以取得閘極絕緣膜1 0。所取得的閘極絕緣膜 10具有3.6的特定介電常數及0.4 μηι的膜厚。接著，紫外 光照射經過用於表面調節的光罩而至源極電極2a與汲極 電極2b要形成的區域上。然後，以噴墨法將奈米銀墨水 圖型化印刷，接著將其乾燥，藉以取得源極電極2a和汲 極電極2b。接著，以噴墨法將墨水圖型化印刷，並將其乾 燥，藉以取得有機半導體層1 1。如此，取得有機電晶體。 藉由將與實施例6中所使用的相同的有機材料溶解於二甲 苯中以製備所使用的墨水。所取得的有機電晶體具有1 0 // m的通道長度及70 μπι的通道寬度。 所使用之用於層間絕緣膜3及導電凸塊4的網版印刷 遮罩、絕緣膏、及導電膏與實施例6中所使用的相同。 .如圖10Α及10Β中所示般，圖13Α中所示的圖案被 對齊以致於不會與上電極5 (稍後要形成）的接觸部相重 疊，然後，藉由使用絕緣膏C，網版印刷此圖案至有機電 晶體上。在降壓下，在l〇〇°C的真空熱爐中將產品乾燥， 藉以取得第一區3 a。然後，導電凸塊4的圖案被對齊以致 -26- 200837854 於與上電極5a (稍.後要形成）的接觸部相重疊，然後，藉 由使用導電膏，網版印刷此圖案至源極電極2a。在1 20 °C 將產品乾燥，藉以取得導電凸塊4。圖13B中所示的圖案 會被對齊以致於不會重疊第一區3a及導電凸塊4，然後， 藉由使用絕緣膏D，網版印刷此圖案。在1 〇〇°C將產品乾 燥，藉以取得第二區3b。最後，藉由使用銀粒子、丙烯酸 系樹脂、及溶劑製成的銀膏，網版印刷上電極5 a的圖案 以重疊導電凸塊4，然後將其乾燥，藉以取得能夠連接至 有機電晶體的上電極5a。如此，取得主動矩陣基底，其中 ，電晶體裝置以格子狀配置。 然後，以微波混合及分散20重量份的氧化鈦、1重量 份的酸聚合物、2重量份的矽聚合物分枝碳墨MX3-GRX-001(由1^??〇11311〇1^1^&1(：〇.1^(1.製造）、及 77 重量份的 矽油 KF96L-lcs (由 Shin-Etsu Chemical Co.，Ltd·製造） 一小時，以取得具有黑色及白色粒子的散佈液體。以使用 明膠及阿拉伯膠的複雜凝聚法，形成具有黑色及白色粒子 分散液體的微囊。微囊的平均粒徑約爲6〇μιη。將微囊分 散在胺甲酸酯樹脂溶劑中以取得分散液體。以線刀法將散 液體散佈至形成有透明電極膜的膜基底上，藉以形成均勻 的微囊片。如此，取得電泳顯示裝置。 所取得的電泳顯示裝置附著至主動矩陣基底，藉以取 得如圖11所示的影像顯示器。確認取得的影像顯示器能 夠以實質上200 ppi的解析度，取得單色顯示影像。 -27- 200837854 【圖式簡單說明】 圖1係切開側視圖，例舉依據本發明的實施例之多層 互連結構的實施例； 圖2A-2C係例舉依據本發明的實施例之多層互連結構 的製造方法； 圖3A-3C係例舉依據本發明的實施例之多層互連結構 的另一製造方法； φ 圖4A係例舉形成導電凸塊之後形成層間絕緣膜的第 一區的印刷方法之視圖； 圖4B係例舉使用圖4A的印刷方法之印刷結果的視圖 9 圖5係例舉形成層間絕緣膜的第一區之後形成導電凸 塊的印刷方法之視圖； 圖6 A及6 B係切開側視圖，例舉塗敷導電膏於導電凸 塊上的印刷方法之視圖； # 圖7 A及7 B係例舉造成層間絕緣膜的第一區及第二區 未適當地對齊之情形的印刷之視圖； 圖8A-8C係例舉造成第一絕緣膏的黏滯度高於第二絕 緣膏的黏滯度之情形的印刷之視圖； 圖9係切開側視圖，例舉依據本發明的實施例之電晶 體裝置的實施例； 圖1 0A及10B係例舉依據本發明的實施例之電晶體裝 置的另一實施例之視圖； 圖1 1係切開側視圖，例舉依據本發明的實施例之影 -28- 200837854 像顯示器的實施例； 圖1 2A及1 2B係例舉使用實施例2中網版印刷遮罩要 印刷的層間絕緣膜的圖案之視圖；及 圖13A及13B係例舉使用實施例5中網版印刷遮罩要 印刷的層間絕緣膜的圖案之視圖。 【主要元件符號說明】 φ 1 :基底 2 :第一互連線 2 a :源極電極 2b :汲極電極 3 :層間絕緣膜 3 a :第一區 3b :第二區 4 :導電凸塊 # 4a :導電膏 5 :第二互連線 5 a :上電極 5b :像素電極 6 :輕 7 :網 8 :乳膠 9 :閘極電極 1 〇 :閘極絕緣膜 -29- 200837854The obtained organic transistor has a channel length of ΙΟμπι and a channel width of 200 μm. The screen printing mask used for the interlayer insulating film 3 and the conductive bumps 4 was the same as that used in Example 2. The insulating paste used was as follows: by dissolving a polyvinyl butyral resin in ethylene glycol monohexyl ether and then adding a cerium oxide filling having a specific surface area of 80 m 2 /g and a barium titanate having a specific surface area of 20 m 2 /g An insulating paste E prepared by adjusting the viscosity to about 250 Pa · s; and by dissolving the polyvinyl butyral resin in a solvent and then adding cerium oxide having a specific surface area of 30 m 2 /g The insulating paste F was prepared by filling and filling a barium titanate having a specific surface area of 20 m 2 /g to adjust the viscosity to about 100 Pa.s. The insulating pastes E and F can be adjusted to have the same component weight ratio. The conductive paste used was the same as that used in Example 1. The pattern shown in Fig. 1 2 A is aligned so as not to overlap the contact portion of the upper electrode 5 (which is to be formed later), and then the pattern is screen printed by using the insulating paste E. On organic transistors. The product was dried in a 100 r vacuum oven under reduced pressure to obtain a first zone 3 a. Then, the pattern of the conductive bumps 4 is aligned so as not to overlap with the contact portion of the upper electrode 5a (to be formed later), and then this pattern is screen-printed to the source electrode 2a by using a conductive paste. The product was dried at 120 ° C to obtain the conductive bumps 4. The pattern shown in Fig. 1 2B is aligned so as not to overlap the first region 3a and the conductive bumps 4, and then the pattern is screen-printed by using the insulating paste F. The product was dried at 100 ° C to obtain a second zone 3b. Finally, by using a silver paste made of silver particles, an acrylic resin, and a solvent, the pattern of the upper electrode 5 a is screen-printed to overlap the conductive bumps 4 and then dried to obtain an upper surface in communication with the organic transistor. Electrode 5a. In this manner, an active matrix substrate is obtained in which the transistor devices are arranged in a lattice shape. Then, 20 parts by weight of titanium oxide, 1 part by weight of an acid polymer, 2 parts by weight of a ruthenium polymer branched carbon ink MX3-GRX-001 (manufactured by Nippon Shokubai Co. Ltd.), and 77 parts by weight of eucalyptus oil KF96L-lcs (manufactured by Shin-Etsu Chemical Co. Ltd.) for one hour to obtain a dispersion liquid having black and white particles, and formed into a black and white color by a complicated coacervation method using gelatin and gum arabic. The particles disperse the liquid microcapsules. The microcapsules have an average particle diameter of about 60 μm. The microcapsules are dispersed in a urethane resin solvent to obtain a dispersion liquid, and the scattered liquid is dispersed by a wire knife method to a film on which a transparent electrode film is formed. On the substrate, a uniform microcapsule sheet is formed. Thus, the electrophoretic display device is obtained. The obtained electrophoretic display device is attached to the active matrix substrate, so as to take the image display shown in Fig. 11 from -25 to 200837854. The display can obtain a monochrome display image with a resolution of substantially 200 ppi. <Embodiment 7> As shown in Figs. 10A and 10B, the nano silver ink pattern is printed by an inkjet method. On the glass substrate 1, it is then dried to obtain the gate electrode 9. Then, the thermally polymerized polyethylamine is applied by spin coating, and heated at 280 ° C to obtain the gate insulating film 10 The obtained gate insulating film 10 has a specific dielectric constant of 3.6 and a film thickness of 0.4 μm. Then, ultraviolet light is irradiated through the mask for surface adjustment to be formed to the source electrode 2a and the drain electrode 2b. Then, the nano silver ink is patterned by an inkjet method, and then dried to obtain the source electrode 2a and the drain electrode 2b. Then, the ink is patterned by an inkjet method, and This was dried to obtain an organic semiconductor layer 11. Thus, an organic transistor was obtained. The same organic material as used in Example 6 was dissolved in xylene to prepare an ink to be used. The electromechanical crystal has a channel length of 10 // m and a channel width of 70 μm. The screen printing mask, the insulating paste, and the conductive paste used for the interlayer insulating film 3 and the conductive bump 4 are the same as in the sixth embodiment. The same is used. Figure 10 As shown in FIG. 10, the pattern shown in FIG. 13A is aligned so as not to overlap with the contact portion of the upper electrode 5 (to be formed later), and then the pattern is screen-printed by using the insulating paste C. Onto the organic transistor. Under depressurization, the product is dried in a vacuum oven at 10 ° C to obtain the first region 3 a. Then, the pattern of the conductive bumps 4 is aligned so that -26-200837854 The contact portion of the upper electrode 5a (slightly formed later) is overlapped, and then this pattern is screen-printed to the source electrode 2a by using a conductive paste. The product was dried at 1 20 ° C to obtain conductive bumps 4. The pattern shown in Fig. 13B is aligned so as not to overlap the first region 3a and the conductive bumps 4, and then the pattern is screen-printed by using the insulating paste D. The product is dried at 1 °C to obtain the second zone 3b. Finally, by using a silver paste made of silver particles, an acrylic resin, and a solvent, the pattern of the upper electrode 5 a is screen-printed to overlap the conductive bumps 4 and then dried to obtain a connection capable of being connected to the organic transistor. Upper electrode 5a. Thus, an active matrix substrate is obtained in which the transistor devices are arranged in a lattice shape. Then, 20 parts by weight of titanium oxide, 1 part by weight of an acid polymer, and 2 parts by weight of a ruthenium polymer branched carbon ink MX3-GRX-001 (by 1^??〇11311〇1^1) are mixed and dispersed by microwave. ^&1 (: 〇.1^ (manufactured by 1:1), and 77 parts by weight of eucalyptus oil KF96L-lcs (manufactured by Shin-Etsu Chemical Co., Ltd.) for one hour to obtain a dispersion having black and white particles Liquid. Microcapsules with black and white particle-dispersed liquids formed by complex coacervation using gelatin and gum arabic. The average particle size of the microcapsules is about 6 μm. The microcapsules are dispersed in a urethane resin solvent. Obtaining a dispersion liquid. Dispersing the liquid on the film substrate on which the transparent electrode film is formed by a wire cutter method to form a uniform microcapsule sheet. Thus, an electrophoretic display device is obtained. The obtained electrophoretic display device is attached to the active matrix substrate. The image display shown in FIG. 11 is obtained. It is confirmed that the obtained image display can obtain a monochrome display image with a resolution of substantially 200 ppi. -27- 200837854 [Simplified illustration] FIG. 1 is a side view, According to the invention Embodiments of the multilayer interconnect structure of the embodiment; FIGS. 2A-2C illustrate a method of fabricating a multilayer interconnect structure in accordance with an embodiment of the present invention; FIGS. 3A-3C illustrate multilayer interconnects in accordance with an embodiment of the present invention Another manufacturing method of the structure; φ Fig. 4A is a view showing a printing method of forming the first region of the interlayer insulating film after forming the conductive bump; Fig. 4B is a view 9 showing the printing result using the printing method of Fig. 4A 5 is a view showing a printing method for forming a conductive bump after forming a first region of an interlayer insulating film; FIGS. 6A and 6B are cutaway side views, and a view showing a printing method of applying a conductive paste on a conductive bump ; Figure 7 A and 7 B are diagrams showing the printing of the first and second regions of the interlayer insulating film which are not properly aligned; Figures 8A-8C illustrate the viscosity of the first insulating paste. FIG. 9 is a cutaway side view showing an embodiment of a crystal device according to an embodiment of the present invention; FIGS. 10A and 10B are based on the present invention. Another embodiment of the transistor device of the embodiment of the invention Figure 1 is a cutaway side view, illustrating an embodiment of a display -28-200837854 according to an embodiment of the present invention; Figure 1 2A and 1 2B illustrate the use of screen printing in Example 2 A view of the pattern of the interlayer insulating film to be printed; and FIGS. 13A and 13B are views showing a pattern of the interlayer insulating film to be printed by using the screen printing mask in Embodiment 5. [Description of main component symbols] φ 1 Substrate 2: first interconnect 2a: source electrode 2b: drain electrode 3: interlayer insulating film 3a: first region 3b: second region 4: conductive bump #4a: conductive paste 5: second Interconnection line 5 a : Upper electrode 5b : Pixel electrode 6 : Light 7 : Net 8 : Latex 9 : Gate electrode 1 〇: Gate insulating film -29 - 200837854
11 :有機半導體層 1 3 :支撐基底 1 4 :透明電極 15 :微囊 1 6 :電泳顯示裝置 -3011 : organic semiconductor layer 1 3 : support substrate 1 4 : transparent electrode 15 : microcapsule 1 6 : electrophoretic display device -30