JP2005183782A - Pattern formation method based on lift-off method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern formation method based on a lift-off method which enables a resist layer to be peeled rapidly from a base in a pattern non-formation region of the base when a pattern is formed by a lift-off method on a pattern formation region of the base, and does not cause lowering of alignment accuracy between layers and lowering of pattern dimensional accuracy in the pattern formation region even if the base has elasticity. <P>SOLUTION: In the method for forming a pattern 16 on the pattern formation region of the base 11 by a lift-off method, a dummy pattern 116 is formed by a lift-off method also on the pattern non-formation region of the base except the pattern formation region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a pattern forming method based on a lift-off method.

  In manufacturing methods of various semiconductor devices and display devices, a pattern forming method based on a lift-off method is often employed. For example, an outline of a method of forming the wiring 206 on the substrate 201 made of a film by the lift-off method will be described below with reference to FIGS. 5A, 5C, and 5E are schematic partial end views in a part of the pattern formation region. FIGS. 5B, 5D, and 5F are FIGS. FIG. 3 is a schematic partial end view of a part of a pattern non-formation region. Usually, the pattern formation region is located in the central portion of the base 201, and the pattern non-formation region is located in the peripheral portion of the base 201 so as to surround the pattern formation region.

[Step-10]
First, a resist layer 202 is formed on a substrate 201 made of a plastic film by a spin coating method, and then an opening is formed in the resist layer 202 based on a lithography technique so that a portion of the substrate 201 where a wiring is to be formed is exposed. 203 is provided. This state is shown in the schematic partial end views of FIGS. The opening 203 is formed so that the planar shape of the opening 203 is larger in the lower part than in the upper part. That is, the opening 203 is formed so that the side wall 204 of the opening 203 expands downward, and the opening 203 has an overhang shape (undercut shape).

[Step-20]
Next, a conductive material layer 205 constituting a wiring is formed on the resist layer 202 including the inside of the opening 203 by, for example, a sputtering method. This state is shown in the schematic partial end views of FIGS. 5C and 5D. In general, the conductive material layer 205 is in a kind of stepped state on the side wall 204 of the opening 203.

[Step-30]
Thereafter, the resist layer 202 is peeled from the base 201 using a resist stripping solution, whereby the wiring 206 made of the conductive material layer 205 can be obtained on the base 201. This state is shown in the schematic partial end views of FIGS. 5E and 5F.

JP-A-8-44037 JP2002-189279 JP 2002-368103 A

  In the lift-off method, in [Step-30], the resist stripping solution usually enters the interface between the substrate 201 and the resist layer 202 from the side wall 204 of the opening 203 where the conductive material layer 205 is in a kind of stepped state. By entering, the resist layer 202 is peeled from the substrate 201.

  However, in the pattern non-formation region, there is usually no break in the resist layer 202 as shown in FIG. Therefore, it is difficult for the resist stripping solution to enter the interface between the substrate 201 and the resist layer 202, and stripping of the resist layer 202 in the pattern non-formation region requires a longer time than stripping of the resist layer 202 in the pattern formation region. Generally, the resist stripping solution is made of an organic solvent. Therefore, if the peeling time of the resist layer 202 becomes long, the base 201 may be contaminated or damaged.

  Finally, the wiring 206 is formed in the pattern formation region, and nothing is formed in the pattern non-formation region (see FIGS. 5E and 5F). Therefore, when the substrate has stretchability, in the state shown in FIGS. 5E and 5F, the stretch amount of the substrate changes depending on the presence or absence of the wiring 206, and so-called alignment between layers is performed. There is a risk that the accuracy may be lowered, or the pattern dimension accuracy in the pattern formation region may be lowered.

  A technique of forming a dummy pattern portion for adjusting a plating distribution when performing metal plating is known from, for example, Japanese Patent Application Laid-Open No. 8-44037. Further, a technique for forming a pseudo pattern in manufacturing a photomask is known from Japanese Patent Application Laid-Open No. 2002-189279. Furthermore, a technique for providing a dummy pattern in manufacturing a semiconductor device is known from Japanese Patent Laid-Open No. 2002-368103. However, none of these patent publications mentions problems in the lift-off method and means for solving such problems.

  Therefore, an object of the present invention is to quickly remove the resist layer from the substrate in the pattern non-formation region of the substrate when the pattern is formed on the pattern formation region of the substrate by the lift-off method. An object of the present invention is to provide a pattern forming method based on the lift-off method, which does not cause a decrease in so-called alignment accuracy between layers or a decrease in pattern dimensional accuracy in a pattern formation region even when it has elasticity.

  The pattern forming method based on the lift-off method of the present invention for achieving the above object is a method of forming a pattern on the pattern forming region of the substrate by the lift-off method, and does not form the pattern on the substrate other than the pattern forming region. A dummy pattern is also formed on the region by a lift-off method.

  In the pattern forming method based on the lift-off method of the present invention, the dummy pattern can be essentially any shape, for example, a closed curve having any shape, a closed line segment having any shape. A combination, a closed curve and line segment having any shape, a stripe shape, or any combination thereof, more specifically, for example, a circle, an ellipse, a polygon and a stripe It can be set as the structure which has at least 1 sort (s) of shape selected from the group which consists of shapes. The stripe shape includes not only a so-called line and stripe shape but also a mesh shape or a lattice shape. The dummy pattern may be formed periodically or may not be formed periodically (that is, it may be formed aperiodically).

In the pattern formation method based on the lift-off method of the present invention including the above preferred embodiment, when the area of the pattern formation region is S ₁ and the area of the pattern non-formation region is S ₂ ,
0.1 ≦ S ₂ / S ₁ ≦ 10 (1-1)
Preferably,
0.1 ≦ S ₂ / S ₁ ≦ 1 (1-2)
It is desirable to satisfy

When one pattern formation region is provided on the substrate, S ₀ = S ₁ + S ₂ when the substrate area is S ₀ . On the other hand, when N pattern forming regions are provided on the substrate, S ₀ = N × S ₁ + S ′ ₂ . Here, S ′ ₂ is the total area of the pattern non-formation regions. In such a case, it is only necessary that S ₂ = S ′ ₂ / N and that S ₂ satisfies the above formula (1-1) or the above formula (1-2).

  In the pattern forming method based on the lift-off method of the present invention including the various preferred embodiments described above, a pattern is not formed after a dummy pattern is formed on the pattern non-formation region of the substrate other than the pattern formation region by the lift-off method. The substrate portion in the region and the substrate portion in the pattern formation region may be left as they are, or the substrate portion in the pattern non-formation region and the substrate portion in the pattern formation region are separated and the substrate portion in the pattern non-formation region is separated. It may be removed. Examples of the separation method include a method of cutting the substrate at a boundary region between the substrate portion in the non-pattern forming region and the substrate portion in the pattern forming region.

In the pattern forming method based on the lift-off method of the present invention, as a substrate,
(1) Various semiconductor substrates including a silicon semiconductor substrate for manufacturing a semiconductor device (2) Various types of GaAs substrates, sapphire substrates, GaN substrates, etc. for manufacturing various light emitting elements such as semiconductor lasers and light emitting diodes Semiconductor substrates, semi-insulating substrates, insulating substrates (3) Various glass substrates such as non-alkali glass substrates, low alkali glass substrates, quartz glass substrates, quartz substrates, semiconductor substrates (3) for manufacturing various display devices 4) Plastic films, plastic sheets and plastic substrates composed of polymer materials exemplified by polyethersulfone (PES), polyimide, polycarbonate, and polyethylene terephthalate (PET). The various substrates, films, and sheets described in (1) to (4) may be collectively referred to as a substrate. In addition, elements constituting a semiconductor device, a light-emitting element, a display device, and other various devices formed on a substrate or the like may be hereinafter referred to as device constituent elements for convenience.

Furthermore, as a substrate,
(5) Insulating layer in which an insulating layer is formed on the surface of a substrate or the like (6) Device constituent elements in which an apparatus component is formed on a substrate or the like. In the case of (5) and (6), the substrate or the like corresponds to the base material.

Here, more specifically, as the glass constituting the glass substrate, high strain point glass, soda glass (Na ₂ O · CaO · SiO ₂ ), borosilicate glass (Na ₂ O · B ₂ O ₃ · SiO _2). ), Forsterite (2MgO · SiO ₂ ), and lead glass (Na ₂ O · PbO · SiO ₂ ). In addition, as a material constituting the insulating layer, not only inorganic insulating materials exemplified by SiO ₂ materials, SiN materials, and metal oxide high dielectric insulating films, but also polymethyl methacrylate (PMMA) and polyvinyl phenol (PVP) ), Organic insulating materials exemplified by polyvinyl alcohol (PVA), and combinations thereof can also be used. As SiO ₂ materials, silicon dioxide (SiO ₂ ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin on glass), low dielectric constant SiO ₂ materials (for example, polyaryl) And ether, cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG).

  Moreover, in the pattern formation method based on the lift-off method of the present invention, examples of the pattern obtained include various electrodes, wirings, insulating films, and protective films.

The material constituting the pattern may be any material suitable for the pattern to be formed. For example, platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al ), Silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), or an alloy containing these metal elements, Conductive particles composed of these metals, conductive particles of alloys containing these metals; metal compounds such as metal oxides and metal nitrides; organic semiconductor materials such as pentacene; for example poly (3,4-ethylenedioxythiophene) / Organic conductive material such as polystyrene sulfonic acid [PEDOT / PSS]; for example, graphite, carbon nano tube and carbon nano Organic material such Aiba; for example SiO ₂ based materials and SiN-based materials, inorganic insulating film made of a metal oxide; for example PMMA or PVP, can be exemplified organic insulating film made of PVA, lamination of these layers structure It can also be.

  In the pattern forming method based on the lift-off method, a resist layer is formed on a substrate. The resist material constituting the resist layer may be a known material, and the resist layer forming method is also a known lithography. Adopt technology. The resist material may be an organic material or an inorganic material. A mask (for example, a photomask) used in the lithography technique can also be a mask manufactured by a known method. In the lift-off method, after a resist layer is formed on the substrate by a known forming method such as a spin coating method, an opening is formed in the resist layer so that a portion of the substrate on which a pattern and a dummy pattern are to be formed is exposed. Provide. Then, a material layer for forming a pattern and a dummy pattern is formed on the resist layer including the inside of the opening.

Here, examples of a method for forming a material layer for forming a pattern and a dummy pattern include various physical vapor deposition methods (PVD methods), coating methods such as a dipping method and a spin coating method. More specifically, as a PVD method,
(A) Various vacuum deposition methods such as electron beam heating, resistance heating, flash deposition,
(B) plasma deposition,
(C) Various sputtering methods such as bipolar sputtering method, direct current sputtering method, direct current magnetron sputtering method, high frequency sputtering method, magnetron sputtering method, ion beam sputtering method, bias sputtering method,
(D) Various ion plating methods such as DC (direct current) method, RF method, multi-cathode method, activation reaction method, field evaporation method, high-frequency ion plating method, reactive ion plating method,
Can be mentioned.

  Thereafter, the resist layer is peeled from the substrate using a resist stripping solution, and the resist stripping solution to be used may be a stripping solution suitable for the resist material constituting the resist layer to be used.

  In the pattern forming method based on the lift-off method of the present invention, a dummy pattern is formed by the lift-off method also on the pattern non-formation region of the substrate other than the pattern formation region. Therefore, even in the pattern non-formation region, when the resist layer is peeled off with the resist stripping solution, the resist layer can be easily peeled off from the substrate in a short time. Therefore, it is possible to avoid the problem that the substrate or the substrate supporting material is contaminated or damaged by the resist stripping solution, and the yield of pattern formation can be improved.

  In addition, finally, a pattern is formed in the pattern formation region, and a dummy pattern is also formed in the pattern non-formation region. Therefore, even when the substrate or the substrate support material has elasticity, the difference in the amount of expansion or contraction of the substrate or the substrate support material in the pattern formation region and the pattern non-formation region can be reduced, and the substrate (substrate etc.) As a result, the so-called alignment accuracy between layers and the pattern dimensional accuracy in the pattern formation region can be improved, and it is possible to obtain device components as designed.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to a pattern forming method based on the lift-off method of the present invention. In the first embodiment, more specifically, an array of so-called bottom gate type and bottom contact type organic thin film transistors (abbreviated as organic TFTs) is manufactured on a substrate made of a plastic film. The pattern formation method based on the lift-off method of the present invention is applied to the formation of the gate electrode of the organic TFT. In Example 1, a portion where an organic TFT array composed of a large number of organic TFTs is to be formed corresponds to a pattern formation region, and a portion surrounding the pattern formation region corresponds to a pattern non-formation region.

  In the first embodiment, the dummy pattern has a circular shape formed periodically. Here, the diameter of the circle constituting the dummy pattern was 0.1 mm, and the dummy pattern was arranged so that the center of each circle was located at the apex of a regular triangle (length of one side: 0.5 mm).

In Example 1, the size of the pattern formation region was 40 mm × 40 mm (area S ₁ : 1600 mm ² ), and the size outside the pattern non-formation region was 30 mm × 20 mm (area S ₂ : 600 mm ² ). .

  Hereinafter, a pattern forming method based on the lift-off method of Example 1 will be described with reference to FIGS. 1A to 1F which are schematic partial end views of a substrate and the like. FIG. , (C) and (E) are schematic partial end views in a part of the pattern formation region, and (B), (D) and (F) in FIG. 1 are a part of the pattern non-formation region. It is a typical partial end view in FIG.

[Step-100]
First, for example, a resist layer 12 is formed by a spin coating method on a plastic film 11 (hereinafter referred to as a film 11) made of polyethersulfone (PES) corresponding to a substrate. In the formation region, an opening 13 is provided in the resist layer 12 so that a portion of the substrate (film 11) where the gate electrode is to be formed is exposed. On the other hand, in the pattern non-formation region, an opening 113 is provided in the resist layer 12 so that the base (film 11) where the dummy pattern is to be formed is exposed. This state is shown in the schematic partial end views of FIGS. 1A and 1B, respectively. The openings 13 and 113 are formed so that the planar shape of the openings 13 and 113 is larger in the lower part than in the upper part. That is, the openings 13 and 113 are formed so that the side walls 14 and 114 of the openings 13 and 113 expand downward and the openings 13 and 113 are in an overhang shape (undercut shape).

[Step-110]
Next, the conductive material layer 15 constituting the gate electrode 16 and the dummy pattern 116 is formed on the resist layer 12 including the openings 13 and 113 by, for example, sputtering. Specifically, for example, a titanium (Ti) layer and then a gold (Au) layer are sequentially formed on the entire surface by sputtering. In the drawing, the gate electrode 16 and the dummy pattern 116 or the conductive material layer 15 are shown as one layer. This state is shown in the schematic partial end views of FIGS. 1C and 1D, respectively. In general, the conductive material layer 15 is in a kind of stepped state on the side walls 14 and 114 of the openings 13 and 113.

[Step-120]
Thereafter, the resist layer 12 is peeled from the base (film 11) using a resist stripping solution, whereby a gate electrode 16 made of the conductive material layer 15 formed on the base (film 11) is obtained in the pattern formation region. be able to. On the other hand, in the pattern non-formation region, a dummy pattern 116 made of the conductive material layer 15 formed on the substrate (film 11) can be obtained simultaneously. This state is shown in the schematic partial end views of FIGS. 1E and 1F, respectively.

  In Example 1, in the pattern formation region, the resist stripping solution is applied to the interface between the substrate (film 11) and the resist layer 12 from the side wall 14 of the opening 13 where the conductive material layer 15 is in a kind of stepped state. By entering, the resist layer 12 is peeled from the substrate (film 11). On the other hand, in the pattern non-formation region, the resist stripping solution enters the interface between the substrate (film 11) and the resist layer 12 from the side wall 114 of the opening 113 where the conductive material layer 15 is in a kind of stepped state. The resist layer 12 is peeled from the substrate (film 11). Therefore, it is possible to avoid the problem that the substrate (film 11) is contaminated or damaged by the resist stripping solution, and the yield of pattern formation can be improved. In addition, finally, the gate electrode 16 which is a pattern is formed in the pattern formation region, and the dummy pattern 116 is also formed in the pattern non-formation region. Therefore, even when the film 11 has stretchability, the difference in stretch amount of the film 11 in the pattern formation region and the pattern non-formation region can be reduced, and the film 11 can be stretched isotropically. Thus, the alignment accuracy between the so-called layers and the pattern dimension accuracy in the pattern formation region can be improved, and the device components and the like as designed can be obtained.

  Example 2 also relates to a pattern forming method based on the lift-off method of the present invention. In the second embodiment, more specifically, the source / drain of the organic TFT when manufacturing the so-called bottom gate type and bottom contact type organic TFT array on the base made of the gate insulating film 17. The pattern formation method based on the lift-off method of the present invention is applied to the formation of the electrode. Even in Example 2, a portion where an organic TFT array composed of a large number of organic TFTs is to be formed corresponds to a pattern formation region, and a portion surrounding this pattern formation region corresponds to a pattern non-formation region.

  Even in the second embodiment, the dummy pattern has a circular shape formed periodically. Here, the diameter of the circle constituting the dummy pattern was 0.5 mm, and the dummy pattern was arranged so that the center of each circle was located at the apex of the regular triangle (length of one side: 2 mm).

  In the second embodiment, the size of the pattern formation region and the non-pattern formation region is the same as the size of the pattern formation region and the non-pattern formation region in the first embodiment.

  Hereinafter, the pattern forming method based on the lift-off method of Example 2 will be described with reference to FIGS. 2A to 2F which are schematic partial end views of the substrate and the like. FIG. , (C) and (E) are schematic partial end views in a part of the pattern formation region, and (B), (D) and (F) in FIG. 2 are a part of the pattern non-formation region. It is a typical partial end view in FIG.

[Step-200]
Subsequent to [Step-120] in Example 1, the gate insulating film 17 is formed on the entire surface (specifically, on the film 11 including the gate electrode 16). Specifically, the gate insulating film 17 made of SiO ₂ is formed on the gate electrode 16 and the film 11 based on the sputtering method. When the gate insulating film 17 is formed, by covering a part of the gate electrode 16 with a hard mask, an extraction portion of the gate electrode 16 can be formed without a photolithography process. In the second embodiment, the gate insulating film 17 and the insulating film 117 that is an extension of the gate insulating film 17 correspond to a base and correspond to a device component.

[Step-210]
Next, after a resist layer 22 is formed on the substrate (gate insulating film 17) by a spin coating method, in the pattern formation region, a portion of the substrate (where source / drain electrodes are to be formed) is formed based on the lithography technique. An opening 23 is provided in the resist layer 22 so that the gate insulating film 17) is exposed. On the other hand, in the pattern non-formation region, an opening 123 is provided in the resist layer 22 so that the base (the insulating film 117 that is an extension of the gate insulating film 17) where the dummy pattern is to be formed is exposed. This state is shown in the schematic partial end views of FIGS. 2A and 2B, respectively. The openings 23 and 123 are formed so that the planar shape of the openings 23 and 123 is larger in the lower part than in the upper part. That is, the openings 23 and 123 are formed so that the side walls 24 and 124 of the openings 23 and 123 expand downward and the openings 23 and 123 are in an overhang shape (undercut shape).

[Step-220]
Next, a conductive material layer 25 constituting the source / drain electrode 26 and the dummy pattern 126 is formed on the resist layer 22 including the openings 23 and 123 by, for example, sputtering. Specifically, for example, a titanium (Ti) layer and then a gold (Au) layer are sequentially formed on the entire surface by sputtering. In the drawing, the source / drain electrode 26 and the dummy pattern 126 or the conductive material layer 25 are shown as one layer. This state is shown in the schematic partial end views of FIGS. 2C and 2D, respectively. In general, the conductive material layer 25 is in a kind of stepped state on the side walls 24 and 124 of the openings 23 and 123.

[Step-230]
Thereafter, the resist layer 22 is peeled off from the gate insulating film 17 and the insulating film 117 serving as the base using a resist stripping solution, whereby the conductive material layer formed on the gate insulating film 17 serving as the base in the pattern formation region. 25 source / drain electrodes 26 can be obtained. On the other hand, in the pattern non-formation region, a dummy pattern 126 made of the conductive material layer 25 formed on the insulating film 117 serving as the substrate can be obtained simultaneously. This state is shown in the schematic partial end views of FIGS. 2E and 2F, respectively.

  In Example 2, in the pattern formation region, the resist stripping solution is formed between the substrate (gate insulating film 17) and the resist layer 22 from the side wall 24 of the opening 23 in which the conductive material layer 25 is in a kind of stepped state. By entering the interface, the resist layer 22 is peeled off from the base body (gate insulating film 17). On the other hand, in the pattern non-formation region, the resist stripping solution enters the interface between the substrate (insulating film 117) and the resist layer 22 from the side wall 124 of the opening 123 where the conductive material layer 25 is in a kind of stepped state. As a result, the resist layer 22 is peeled off from the substrate (insulating film 117). Therefore, it is possible to avoid the problem that the base (gate insulating film 17 or insulating film 117) or the film 11 (corresponding to the base support material) is contaminated or damaged by the resist stripping solution. The yield can be improved. In addition, finally, the source / drain electrodes 26 which are patterns are formed in the pattern formation region, and the dummy pattern 126 is formed also in the pattern non-formation region. Therefore, even when the film 11 corresponding to the substrate support material has stretchability, the difference in stretch amount of the film 11 in the pattern formation region and the pattern non-formation region can be reduced, and the film 11 is isotropic. As a result, it is possible to improve the alignment accuracy between so-called layers and the pattern dimension accuracy in the pattern formation region, and it is possible to obtain device components as designed.

  Example 3 also relates to a pattern forming method based on the lift-off method of the present invention. In the third embodiment, more specifically, the formation of the wiring of the organic TFT when manufacturing the so-called bottom gate type and bottom contact type organic TFT array on the base made of the interlayer insulating layer 28. Further, the pattern forming method based on the lift-off method of the present invention is applied. Even in Example 3, a portion where an organic TFT array composed of a large number of organic TFTs should be formed corresponds to a pattern formation region, and a portion surrounding this pattern formation region corresponds to a pattern non-formation region.

  Even in the third embodiment, the dummy pattern has a circular shape formed periodically. Here, the diameter of the circle constituting the dummy pattern was 1 mm, and the dummy pattern was arranged so that the center of each circle was located at the apex of a regular triangle (length of one side: 4 mm).

  In the third embodiment, the size of the pattern formation region and the non-pattern formation region is the same as the size of the pattern formation region and the non-pattern formation region in the first embodiment.

  A pattern forming method based on the lift-off method of Example 3 with reference to FIGS. 3A to 3F and FIGS. 4A and 4B, which are schematic partial end views of the substrate and the like. 3 (A), (C) and (E) and FIG. 4 (A) are schematic partial end views of a part of the pattern formation region. (B), (D) and (F), and (B) of FIG. 4 are schematic partial end views of a part of the pattern non-formation region.

[Step-300]
Subsequent to [Step-230] in Example 2, an organic semiconductor thin film made of pentacene is vacuum-deposited on the entire surface of the pattern formation region (specifically, on the gate insulating film 17 including the source / drain electrode 26). After the formation by the method, the organic semiconductor thin film is patterned by a well-known method so as to extend from one source / drain electrode 26 to the other source / drain electrode 26, and on the gate insulating film 17, a channel made of the organic semiconductor thin film is formed. A formation region 27 can be formed. Thereafter, an interlayer insulating layer 28 having an opening 29 is formed above the source / drain electrode 26 in the pattern formation region by screen printing. The non-pattern forming region is covered with the interlayer insulating layer 28. This state is shown in the schematic partial end views of FIGS. 3A and 3B, respectively. In the third embodiment, the interlayer insulating layer 28 corresponds to a base and corresponds to a device component.

[Step-310]
Next, after a resist layer 32 is formed on the substrate (interlayer insulating layer 28) by a spin coating method, based on the lithography technique, in the pattern formation region, the substrate (opening 29) where a wiring is to be formed. An opening 33 is provided in the resist layer 32 so that the portion of the interlayer insulating layer 28 including the exposed portion is exposed. On the other hand, in the pattern non-formation region, an opening 133 is provided in the resist layer 32 so that the base (interlayer insulating layer 28) where the dummy pattern is to be formed is exposed. This state is shown in the schematic partial end views of FIGS. 3C and 3D, respectively. The openings 33 and 133 are formed so that the planar shape of the openings 33 and 133 is larger in the lower part than in the upper part. That is, the openings 33 and 133 are formed so that the side walls 34 and 134 of the openings 33 and 133 expand downward and the openings 33 and 133 are in an overhang shape (undercut shape).

[Step-320]
Next, on the resist layer 32 including the openings 33 and 133 and the opening 29, the conductive material layer 35 that forms the wiring 36, the connection hole 37, and the dummy pattern 136 is formed by sputtering, for example. Specifically, for example, a titanium (Ti) layer and then a gold (Au) layer are sequentially formed on the entire surface by sputtering. In the drawing, the wiring 36, the connection hole 37, the dummy pattern 136, or the conductive material layer 35 is represented by one layer. This state is shown in the schematic partial end views of FIGS. 3E and 3F, respectively. Generally, in the side walls 34 and 134 of the openings 33 and 133, the conductive material layer 35 is in a kind of stepped state.

[Step-330]
Thereafter, the resist layer 32 is peeled off from the interlayer insulating layer 28 serving as the base using a resist stripping solution, so that in the pattern forming region, the wiring made of the conductive material layer 35 formed on the interlayer insulating layer 28 serving as the base. 36 can be obtained. On the other hand, in the pattern non-formation region, a dummy pattern 136 made of the conductive material layer 35 formed on the interlayer insulating layer 28 as a base can be obtained at the same time. This state is shown in the schematic partial end views of FIGS. 4A and 4B, respectively.

[Step-340]
Thereafter, if necessary, the base portion of the pattern non-formation region and the base portion of the pattern formation region are separated.

  In Example 3, in the pattern formation region, the resist stripping solution is formed between the substrate (interlayer insulating layer 28) and the resist layer 32 from the side wall 34 of the opening 33 where the conductive material layer 35 is in a kind of stepped state. By entering the interface, the resist layer 32 is peeled off from the substrate (interlayer insulating layer 28). On the other hand, in the pattern non-formation region, the resist stripping solution enters the interface between the substrate (interlayer insulating layer 28) and the resist layer 32 from the side wall 134 of the opening 133 where the conductive material layer 35 is in a kind of stepped state. As a result, the resist layer 32 is peeled off from the substrate (interlayer insulating layer 28). Therefore, it is possible to avoid the problem that the substrate (interlayer insulating layer 28) or the film 11 (corresponding to the substrate support material) is contaminated or damaged by the resist stripping solution, and the yield of pattern formation is improved. Can be planned. In addition, finally, a wiring pattern 36 is formed in the pattern formation region, and a dummy pattern 136 is also formed in the pattern non-formation region. Therefore, even when the film 11 corresponding to the substrate support material has stretchability, the difference in stretch amount of the film 11 in the pattern formation region and the pattern non-formation region can be reduced, and the film 11 is isotropic. As a result, it is possible to improve the alignment accuracy between so-called layers and the pattern dimension accuracy in the pattern formation region, and it is possible to obtain device components as designed.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and manufacturing conditions of the organic TFT are exemplary and can be changed as appropriate, and the materials used are also exemplary and can be changed as appropriate. For example, in [Step-300] of Example 3, a channel formation region constituted by an organic semiconductor thin film made of pentacene is formed in the pattern formation region. The present invention is applied to the formation (patterning) of this channel formation region. A pattern forming method based on the lift-off method can also be applied.

As the structure of the organic TFT, besides the structure described in the embodiment,
(A-1) A gate electrode formed on the substrate,
(B-1) a gate insulating film formed on the gate electrode;
(C-1) a channel forming region made of an organic semiconductor thin film formed on the gate insulating film, and
(D-1) Source / drain electrodes formed on the organic semiconductor thin film,
(Bottom gate type and top contact type organic TFT),
(A-2) a channel formation region comprising an organic semiconductor thin film formed on a substrate,
(B-2) Source / drain electrodes formed on the organic semiconductor thin film,
(C-2) a source / drain electrode, a gate insulating film formed on the organic semiconductor thin film, and
(D-2) a gate electrode formed on the gate insulating film,
(Top gate type and top contact type organic TFT),
(A-3) Source / drain electrodes formed on the substrate,
(B-3) a channel forming region comprising a source / drain electrode and an organic semiconductor thin film formed on the substrate;
(C-3) a gate insulating film formed on the organic semiconductor thin film, and
(D-3) a gate electrode formed on the gate insulating film,
(Top gate type and bottom contact type organic TFT).

1A to 1F are schematic partial end views of a substrate and the like for explaining a pattern forming method based on the lift-off method of Example 1. FIG. 2A to 2F are schematic partial end views of a substrate and the like for explaining a pattern forming method based on the lift-off method of Example 2. FIG. 3A to 3F are schematic partial end views of a substrate and the like for explaining a pattern forming method based on the lift-off method of Example 3. FIG. 4A and 4B are schematic partial end faces of a substrate and the like for explaining the pattern forming method based on the lift-off method of Example 3 following FIGS. 3E and 3F. FIG. 5A to 5F are schematic partial end views of a substrate and the like for explaining a pattern forming method based on a conventional lift-off method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Plastic film, 12, 22, 32 ... Resist layer, 13, 113, 23, 123, 33, 133 ... Opening, 14, 114, 24, 124, 34, 134 ... Side wall , 15, 25, 35 ... conductive material layer, 16 ... gate electrode, 17 ... gate insulating film, 117 ... insulating film, 26 ... source / drain electrode, 27 ... channel formation. Region, 28 ... interlayer insulating layer, 29 ... opening, 36 ... wiring, 37 ... connection hole, 116, 126, 136 ... dummy pattern

Claims (4)

A method of forming a pattern by a lift-off method on a pattern formation region of a substrate,
A pattern formation method based on a lift-off method, wherein a dummy pattern is formed by a lift-off method on a pattern non-formation region of a substrate other than the pattern formation region. 2. The pattern forming method according to claim 1, wherein the dummy pattern has at least one shape selected from the group consisting of a circle, an ellipse, a polygon, and a stripe shape. _2. The lift-off method according to claim 1, wherein 0.1 ≦ S ₂ / S ₁ ≦ 10 is satisfied, where S _{1 is} an area of the pattern formation region and S ₂ is an area of the non-pattern formation region. Pattern forming method based. 2. The substrate portion in the non-pattern forming region and the substrate portion in the pattern forming region are separated after forming a dummy pattern on the non-pattern forming region of the substrate other than the pattern forming region by a lift-off method. A pattern forming method based on the lift-off method described in 1.

Images