TW200826206A - Semiconductor fabrication method and structure thereof - Google Patents

Semiconductor fabrication method and structure thereof Download PDF

Info

Publication number
TW200826206A
TW200826206A TW095146075A TW95146075A TW200826206A TW 200826206 A TW200826206 A TW 200826206A TW 095146075 A TW095146075 A TW 095146075A TW 95146075 A TW95146075 A TW 95146075A TW 200826206 A TW200826206 A TW 200826206A
Authority
TW
Taiwan
Prior art keywords
nickel
gold
silver
palladium
semiconductor package
Prior art date
Application number
TW095146075A
Other languages
English (en)
Inventor
Chi-Chih Lin
Bo Sun
Hung-Jen Wang
Jen-Feng Tseng
Original Assignee
Taiwan Solutions Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Solutions Systems Corp filed Critical Taiwan Solutions Systems Corp
Priority to TW095146075A priority Critical patent/TW200826206A/zh
Priority to US12/000,021 priority patent/US20080135939A1/en
Publication of TW200826206A publication Critical patent/TW200826206A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85411—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85416—Lead (Pb) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

200826206 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體封裝之製造方法及其結構，特別 是一種焊墊處具有高度差之半導體製造方法及其結構。 【先前技術】 按，半導體科技隨著電腦與網路通訊等產品功能急速提 幵，必需具備多元化、可攜性與輕薄微小化之需求，使晶片封 裝業必須朝高功率、高密度、輕'薄與微小化等高精密度製程 务展，除此之外，電子封裝(Electronics Packaging)仍需具備高 可罪度、政熱性仏專特性，以作為傳遞訊號、電能，以及提供 良好的散熱途徑及結構保護與支持等作用。 習知半導體封裝製程，係先於載板上以飯 後，設置晶片，接著，電性連接晶片與導電線路，之後，利用 封裝膠體包覆上述元件後蝕刻金屬載板。為於導電線路上_置 與外界電性接觸之凸塊，在導電線路上須預留導電線，^欲 焊接部位進行電鍍金屬凸塊之流程。此種製造方法，於姓刻載 板時，由於_㈣需掌㈣要錄乡，目此_結果較不易 控制，常見的問題如濕蝕刻時容易產生『麻 « a ί 你卞刀』(undercut)的 現象使㈣形無法精確轉移至載板，騎若在刻處進 行電鍍金屬表面處理層’在打線作„，因必須要打線於一曲 面上，打線良率較差，其製㈣度也較高。再者，大多知 封裝結構焊域僅底部可塗佈焊料，且在表面黏著製程 (surface m〇unt techn〇i〇gy，SMT)後亦有不易目檢焊料塗佈情 況之問_生。這些問題都會影響到晶片封 品的信賴度。 不艮午以及座 良率及信賴度將是 故，如何顧及簡化製作流程、提高製程 半導體產業製作薄型化產品一個重要議題。 5 200826206 【發明内容】 本發明目的之-係提供—財㈣ 成之表面處理層為一平面，致使可提 良率，此外，亦可簡化打線作業的難度。 了捕業之 社接本&明目的之―係提供—種半導體封裝之f造方法及並 t構，所形成料體之輝墊 ^方法及，、 錫厚度。 m冑㈤度產’可增加谭接時上 本㉝明目的之—係提供_種半導體封裝 結構，除可增加焊接時上錫厚 匕 亦方便檢謂接時設置闕讀況。之特性 本!X明目的之—係提供—種半導 :=封裝膠體形成複數凹槽以完成高度差St:: 高焊接製封⑽體㈣處或包覆表面處理層側邊以提 製造2達^述明:實施例之-種半導體封裝之
It開:以暴露出部分載板;形成-金屬層於暴h ，板，形成-表面處理層於金屬層上；移除遮罩；進行—曰 娜除載板與金屬層以形成複數凹槽並暴露； 之製造方法，包：目二本::又:實施例之-種半導體封装 匕3 ·挺供一載板，其上設置一第一遮罩，苴中 處==有複數圖案化開口以暴露出部分載板；形成-i面 ^層於暴露出之載板上；移除第一遮罩；形成一第二遮罩覆 八^面處理層’其中第二遮罩具有複數圖案化開口以暴露出部 、板，开y成金屬層於暴露出之載板上；移除第二遮罩；進 200826206 订:晶片封装步驟；以及移除載板與金屬層以形成複數凹槽並 暴露出表面處理層之側邊。 為了達到上述目的，本發明又一實施例之一種半導體封裝 結構，包括：一表面處理層，定義出至少一晶片承載區與複數 ‘電連接點’其中導電連接點係設置於每—晶片承載區周緣； 至夕曰曰片，设置於晶片承載區内，並利用一導電連接結構電 性連，晶片與導電連接點；以及-封裝膠體，係直接覆蓋晶 片、導電連接結構與表面處理層，其中表面處理層係暴露出封裝 膠體並與封裝膠體形成高低差。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易 瞭解本發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 其詳細說明如下，所述較佳實施例僅做一說明，非用以限 定本發明。 第1A圖、第1B圖、第lc圖、第1D圖、第ie圖、第 1F圖、第1G圖及第in圖所示為根據本發明半導體封裝製 方法之第-實施例之各步驟結構剖面示意圖。首先，請先^ 第1A圖，提供一載板1〇，其上設置一遮罩，其中遮罩 具有複數圖案化開π 21以暴露出部分餘1G。接著，參考第 1B圖，以遮罩20為罩幕，形成一金屬| 3〇，例如銅(Cu)材質 所構成’於暴露出之載板1〇上。於一實施例中，金屬層％係 ，用電鍍法、無電解電鍍法與印刷法其中之任—所形成。接 著，叫參閱第ic圖，形成一表面處理層4〇於金屬層3〇上， 其2表面處理層40係填遮罩20上之圖案化開口 21之線路。 實施例中’表面處理層4〇可以是利用電鑛法、化學替 法與印刷法其中之任-所形成。上述製程方法所形成之結構^ 7 200826206 簡化後續打線作業之難度以及提高打線作業之良率。之後，如 第1D圖所示，移除遮罩20，則載板10上剩下由金屬層30與 表面處理層4G所形成的圖案化線路。再來，請參考第1E圖， 進行=片封裝步驟。於—實施财，晶片封裝步驟包括，設 置至少一晶片50於表面處理層40 ;接著，電性連接晶片50 ，表面處理層40;以及利用灌模方式形成一封裝滕體6〇覆蓋 晶片50以保護晶片5〇與外界氣密隔絕。於一實施例中，電性 晶片50與表面處理層4G之方法可以是姻打線方式或覆 曰曰Chlp)方式完成。最後，如第ιρ圖所*，移除金屬層 及載板10以形成複數凹槽62並暴露出表面處理層4〇。於 一=施例中，可利用姓刻方式移除金屬層3〇及載板1〇 ;於又 例巾’如餘1G可重複制，亦刊關时式或其 也適*方切除，· 1G移除後再使㈣财法移除金屬層 30 °
一、也列中’遮罩20可為具有複數圖案化開口 21(如第 阻層’ μ這些圖案化開σ 21可以是利用直 ^成，（laser d爾t lmaging，LDI)形成，之後，再利用電鑛 ,、‘…電解電鍍法、化學電鏟法或印刷之方法透過遮罩2〇上 3之0圖^化ΐ 口 21(如第1A圖所示）分別於載板1〇上形成金屬層 或表面處理層4G。但可以理解的，遮罩2()並不限於此，於 =-實施例中，遮罩2〇也可以是圖案化模板，於相同圖案設 。十之製程中，圖案化模板可重複制，減少製程及生產成本。 德，=上述，明’於一實施例中，移除載板10及金屬層3〇 1G 括以母—晶片％為單位進行切冑，以形成數個如第 實施例之半導體封裝結構，如圖所示，表面 4:』中莫：：義出至少一晶片承載區42與複數導電連接點 1位;電連接點44係設置於每—晶片«區42周緣，但 ”位置不限定於週邊。至少—^ 5Q，設置於 8 200826206 内，並利用一導電連接結構70電性連接晶片50與導電連接點 44，於一實施例中，導電連接結構70包括至少一引線或至少 一連接墊，以打線方式電性連接晶片50與導電連接點44。於 又一實施例中，導電連接結構70也可利用一金屬凸塊(Bump) 以Flip Chip方式電性連接晶片50與導電連接點44。封裝膠體 60，例如由環氧樹脂（epoxy)或其他樹脂材質所形成，直接覆 蓋晶片50、導電連接結構70與表面處理層40,其中表面處理 層40之一側係暴露出封裝膠體60並與封裝膠體60形成高低 差hi。其中，此半導體封裝結構中之承載部分只包括一層表 面處理層40，故可達到薄型化之要求。 於一實施例中，表面處理層40之材質包括金鎳金、金I巴 鎳把金、金鎳Ιε金、金Ιε鎳金、銀、銀鎳Ιε金、金Ιε鎳銀、銀 鎳金、金鎳銀、銀鎳銀、把銀鎳銀、銀鎳銀Ιε、金鎳銀I巴、 ί巴銀鎳金、把銀鎳錫、銀鎳錫、金鎳锡、金Ιε鎳錫、金鎳銅鎳 金、金鈀鎳銅鎳鈀金、金鎳銅鎳鈀金、金鈀鎳銅鎳金、銀、銀 鎳銅鎳鈀金、金鈀鎳銅鎳銀、銀鎳銅鎳金、金鎳銅鎳銀、銀鎳 銅鎳銀、鈀銀鎳銅鎳銀、鈀銀鎳銅鎳銀鈀、金鎳銅鎳銀鈀、鈀 銀鎳銅鎳金、鈀銀鎳銅鎳錫、銀鎳銅鎳錫、金鎳銅鎳錫、金鈀 ^ 鎳銅鎳錫、鈀銀鎳銅錫、銀鎳銅錫、金鎳銅錫與金鈀鎳銅錫其 中之任一，但可以理解的，其材質並不限於此。於又一實施例 中，表面處理層40可包括複數金屬薄膜，其材質包括金鎳金、 金I巴鎳Is金、金錄la金、金把錄金、銀、銀鎳Ιε金、金ίε鎳銀、 銀鎳金、金鎳銀、銀鎳銀、鈀銀鎳銀、鈀銀鎳銀鈀、金鎳銀鈀、 I巴銀鎳金、Ιε銀鎳錫、銀鎳錫、金鐮錫、金ίε錄錫、金鎳銅鎳 金、金Ιε鎳銅鎳把金、金鎳銅鎳把金、金把鎳銅鎳金、銀、銀 鎳銅鎳鈀金、金鈀鎳銅鎳銀、銀鎳銅鎳金、金鎳銅鎳銀、銀鎳 銅鎳銀、鈀銀鎳銅鎳銀、鈀銀鎳銅鎳銀鈀、金鎳銅鎳銀鈀、鈀 銀錄銅錄金、Ιε銀錄銅錄錫、銀鎳銅錄錫、金錄銅錄錫、金I巴 9 200826206 錄銅鎳錫、把銀鎳銅錫、銀鎳銅錫、金鎳銅錫與金把鎳銅錫其 中之任一，但可以理解的，其材質並不限於此。其中表面處理 層40因一側與晶片50電性連接，而暴露出封裝膠體60之一 側其後欲焊接至其他電子裝置，故要與晶片50電性連接之一 側的金屬薄膜，其材質係為方便打線作業或覆晶作業製程之金 屬；而暴露出封裝膠體60之一側的金屬薄膜，其材質係為可 供焊接或方便焊接之金屬。如此一來，表面處理層40之兩側（與 晶片電性連接之一側及與電子裝置焊接之一側）依不同需求， 皆可提供良好鍵結。 請繼續參照第1G圖，於此實施例中，複數凹槽62形成 於晶片承載區42與導電連接區44並暴露出表面處理層40以 形成高低差hi，其中高度差hi有助於其後焊接至其他電子裝 置時，填充焊料之用。如第1H圖，當焊接至其他電子裝置時， 此半導體封裝結構更包括複數焊接元件80,例如由錫（Sn)所構 成之焊料，設置於暴露出之表面處理層40上以方便焊接至其 他電子裝置（如圖式中之電路板90)上。如圖所示，焊接元件 80係填滿凹槽62使得焊接元件80與表面處理層40有良好的 電性接觸，其中凹槽62設計不僅可輔助提高填充焊接元件80 I 的量，亦可因此而提高產品信賴度。 第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、第 2F圖、第2G圖、第2H圖、第21圖、第2J-1圖及第2J-2圖所 示為根據本發明半導體封裝製造方法之第二實施例之各步驟 結構剖面示意圖。如第2A圖所示，首先，提供一載板10，其 上設置一第一遮罩，如遮罩22，其中遮罩22具有複數圖案化 開口 23以暴露出部分載板10。接著，參考第2B圖及第2C圖， 以遮罩22為罩幕，形成一表面處理層40於暴露出之載板10 上，其後移除遮罩22。之後，如第2D圖所示，設置一第二遮 罩，如遮罩24，覆蓋表面處理層40，其中遮罩24具有複數圖 200826206 ”化25以暴露出部分載板1G，於-實施例中，表面處理 層4〇係、凡王或部份被遮罩24覆蓋，且圖案化開口 25僅暴# 出部分載板ίο。再來，請參考第2E圖與第2F圖，以遮罩^ 二幕再:成:金屬層曰3°於暴露出之載板10上，其後移除遮 體封裝結構。於此實施例中，晶片封裝步驟包括：以適當$ 设置至少「晶片5G於表面處理層你以打線或覆晶㈣ 方式電性連接晶片5〇與表面處理層4〇;以及利 成一封裝膠體60覆蓋晶U、金屬層、表面 部分載板1G以將晶片5G與外界氣密隔絕。最後，移除載板w 與金屬層3〇，請搭配參照第2G圖及帛2H圖，如圖所示，被移 除的金屬層30在封裝膠體6〇上形成複數凹槽 ‘ 面處理層40之一側及其側邊。 *路出表 〃接續上述說明，於一實施例中，第一遮罩，如遮罩22及 第二遮罩’如遮罩24,可為圖㈣之絲層，利用電鑛法、 無電解電鍍法、化學電鍍法或印刷之方法透過遮罩22、又24上 之圖案化開口 23、24(如第2A圖及第2D圖所示）於載板i 〇上 分別形成金屬層30或表面處理層4〇。於一實施例中、 24上之圖案化開口 23、24(如第2A圖及第2d圖所示）可以是 利用直接成像法形成。但可以理解的，遮罩22、Μ並於 此，於：-實施例中’遮罩22、24也可以是圖案化模板二 相同圖案設計之製程中，圖案化模板可重複使 生產成本。 表枉汉 與上-實施例相同之處在於，形成金屬層3〇之方法可以 是利用電鐘法、印刷法和無電解電鍍法其中之任 形成表面處理層40之方法’可以是利用無電解電鍵法、^刷 法、電鑛法與化學魏法其中之任—卿成，而—實施财， 表面處理層40亦可包括複數金屬薄臈以方便與晶片％電性連 200826206 接以及方便焊接至其他裳置。又，可利賴财式移除金屬層 3〇及載板10 ;此外，若載板10可重複使用，亦可使用剝除方 式或其他適當方式移除载板10,移除後再使用蝕刻方法移陕 金屬層30。 於一實施例中，在移除載板1〇及金屬層3〇後，更包括以 每一晶片50為單位進行切割，以形成數個第二實施例之半導 體封裝結構，如第21圖所示，與第一實施例之半導體封裝結 構不同之處在於，複數凹槽64形成於晶片承載區42及導電^ 接區44週緣以暴露出表面處理層4〇之側邊，使得凹槽内 的封裝膠體60與表面處理層4〇形成如圖所示之高低^ h2。 於又一實施例中，請參考第2J·〗圖及第2J_2圖，第2J_2圖係 ，第jJ-丨圖之局部放大示意圖，半導體封裝結構更包括複數 焊接π件80設置於表面處理層4〇下以方便 焊接至如電路板90的外界電子裝置上。如第2 = 接το件80可沿著封裝膠體6〇上的凹槽料包覆表面處理層 的側邊，如此一來即可大幅增加焊接元件8〇的厚度以提高 接製程之良率。
+依據上述，本發明的特徵之一係可利用圖案化薄膜或圖案 化杈板作為遮罩進行金屬層或表面處理層之製作，製程上相當 彈性，且對於相同圖案設計之製程，圖案化模板可重複使用田， 以=少製造成本；又，本發明的特徵之一在於封裝後之半導體 封:結構焊墊處之高低差可以是利用複數凹槽實作成焊墊處 2縮或是焊墊處外凸之結構以增加焊接時焊料厚度，製程上相 备彈性；再者，本發明的特徵之-在於承載部分只包括表面處 理層，相當符合結構㈣化之m，表面處理層亦可包括 複數金屬薄膜以提供電性連接側與焊接側都有良好的鍵結。 12 200826206 綜合上述，本發明係提供一種半導體封裝之製造方法及其 結構，所形成之表面處理層為一平面致使提高打線作業之良 率，此外，亦可簡化打線作業的難度。又，所形成之封裝體， 其上之焊墊處具有一高度差，可增加焊接時上錫厚度。除可增 加焊接時上錫厚度之外，具有高度差之特性亦方便檢視焊接時 上錫料之狀況。更者，利用封裝膠體形成複數凹槽以完成高度 差，致使上錫作業時，錫料可充滿封裝膠體凹槽處或包覆表面 處理層側邊以提高焊接製程信賴度。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容並 據以實施，當不能以之限定本發明之專利範圍，即大凡依本發 明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之 專利範圍内。 【圖式簡單說明】
第1A圖、第1B圖、第1C圖、第1D圖、第1E圖、第1F圖、第1G 圖及第1H圖所示為根據本發明半導體封裝製造方法第一實施例之 各步驟結構剖面示意圖。 第2A圖、第2B圖、第2C圖、第2D圖、第2E圖、第2F圖、第2G 圖、第2H圖、第21圖、第2J-1圖及第2J-2圖所示為根據本發明半導 體封裝製造方法之第二實施例之各步驟結構剖面示意圖。 【主要元件符號說明】 10 載板 20, 22, 24 遮罩 21，23, 25 圖案化開口 13 200826206 30 金屬層 40 表面處理層 42 晶片承載區 44 導電連接點 50 晶片 60 封裝膠體 62,64 凹槽 70 導電連接結構 80 焊接元件 90 電路板 hl，h2 高度差 14

Claims (1)

  1. 200826206 十、申請專利範圍： 1·一種半導體封裝製造方法，包含： 提供一載板，其上設置一遮罩，其中該遮罩具有複數圖案化開口以 暴露出部分該載板； 形成一金屬層於暴露出之該載板； 幵;成一表面處理層於該金屬層上； 移除該遮罩； 進行一晶片封裝步驟；以及 f
    移除該載板與該金屬層以形成複數凹槽並暴露出該表面處理 2.如請求項1所述之半導體封裝製造方法，其中該遮罩係為光 阻層。 3·如請求項2所述之半導體封裝製造方法，其中該些圖案化開 係利用直接成像(laser direct imaging，LDI)法形成。 案^^項1所述之半導體封裝製造方法，其中該遮罩係為圖 5田t請求項1 2 3所述之半導體封裝製造方法，其中該金屬層係利 6。f法、無電解電鍍法與印刷法其中之任一所形成。 、 们所述之半導體封裝製造方法，其巾該表面處理層 7 口^電鍍法、化學電鍍法與印刷法其中之任一所形成。 法述之半導體封裝製造方法，其中係利用钱刻方 求，1所述之半導體封裝製造方法，其中係彻餘刻方 广移二該金屬層與該載板。 蚀到方 15 1 所述之半導體封裝製造方法，其中該晶片封裝步 2 叹置至少一晶片於該表面處理層，· 3 %丨生連接5亥晶片與該表面處理層；以及 200826206 形成一封裝膠體包覆該晶片。 10. 如請求項9所述之半導體封裝製造方法，其中係以打線方式 電性連接該晶片與該表面處理層。 11. 如請求項9所述之半導體封裝製造方法，其中係以覆晶方式 電性連接該晶片與該表面處理層。 12. 如請求項1所述之半導體封裝製造方法，更包含以每一該晶 片為單位進行切割，以形成數個半導體封裝結構。 13. —種半導體封裝製造方法，包含： 提供一載板，其上設置一第一遮罩，其中該第一遮罩具有複數圖案 化開口以暴露出部分該載板； 形成一表面處理層於暴露出之該載板上； 移除該第一遮罩； 設置一第二遮罩覆蓋該表面處理層，其中該第二遮罩具有複數圖案 化開口以暴露出部分該載板； 形成一金屬層於暴露出之該載板上； 移除該第二遮罩； 進行一晶片封裝步驟；以及 移除該載板與該金屬層以形成複數凹槽並暴露出該表面處理 層之側邊。 14. 如請求項13所述之半導體封裝製造方法，其中該遮罩係為 光阻層。 15. 如請求項14所述之半導體封裝製造方法，其中該些圖案化 開口係利用直接成像(laser direct imaging, LDI)法形成。 16. 如請求項13所述之半導體封裝製造方法，其中該遮罩係為 圖案化模板。 17. 如請求項13所述之半導體封裝製造方法，其中該金屬層係 利用電鍍法、無電解電鍍法與印刷法其中之任一所形成。 16 200826206 18.如請求項13所述之半導體封裝製造方法，其中該表面處理 層係利用電鍍法、化學電鍍法與印刷法其中之任一所形成。 19·如請求項13所述之半導體封裝製造方法，其中係利用蝕刻 方法移除該金屬層。 20.如請求項13所述之半導體封裝製造方法，其中係利用蝕刻 方法移除該金屬層與該載板。 21·如請求項13所述之半導體封裝製造方法，其中該晶片封裝 步驟包含： 設置至少一晶片於該表面處理層； 電性連接該晶片與該表面處理層；以及 形成一封裝膠體包覆該晶片。 22.如請求項21所述之半導體封裝製造方法，其中係以打線方 式電性連接該晶片與該表面處理層。 23·如請求項21所述之半導體封裝製造方法，其中係以覆晶方 式電性連接該晶片與該表面處理層。 24.如請求項13所述之半導體封裝製造方法，更包含以每一該 晶片為單位進行切割，以形成數個半導體封裝結構。 25·—種半導體封裝結構，包含： 一表面處理層，定義出至少一晶片承載區與複數導電連接點，其中 該些導電連接點係設置於每一該晶片承載區周緣； 至少一晶片，設置於該晶片承載區内，並利用一導電連接結構電性 連接該晶片與該些導電連接點；以及 一封裝膠體，係直接覆蓋該晶片、該導電連接結構與該表面處理層， 其中該表面處理層係暴露出該封裝膠體並與該封裝膠體形成高低差。 26·如請求項25所述之半導體封裝結構，其中該表面處理層包 含複數金屬薄膜，該些金屬薄膜之材質包含金鎳金、金鈀鎳纪 金、金鎳Ιε金、金Ιε鎳金、銀、銀鎳Ιε金、金Ιε鎳銀、銀錄金、 金鎳銀、銀鎳銀、鈀銀鎳銀、鈀銀鎳銀鈀、金鎳銀鈀、把銀錄 17 200826206 金、鈀銀鎳錫、銀鎳錫、金鎳錫、金鈀鎳錫、金鎳銅鎳金、金 鈀鎳銅鎳鈀金、金鎳銅鎳鈀金、金鈀鎳銅鎳金、銀、銀鎳銅鎳 鈀金、金鈀鎳銅鎳銀、銀鎳銅鎳金、金鎳銅鎳銀、銀鎳銅鎳銀、 I巴銀鎳銅鎳銀、Ιε銀鎳銅鎳銀Ιε、金鎳銅鎳銀Ιε、Ιε銀鎳銅鎳 金、鈀銀鎳銅鎳錫、銀鎳銅鎳錫、金鎳銅鎳錫、金鈀鎳銅鎳錫、 鈀銀鎳銅錫、銀鎳銅錫、金鎳銅錫與金鈀鎳銅錫其中之任一。 27. 如請求項25所述之半導體封裝結構，其中該表面處理層之 材質包含金鎳金、金纪鎳把金、金鎳把金、金把錄金、銀、銀 錄Ιε金、金Is錄銀 '銀鎳金、金錄銀、銀錄銀、Ιε銀鎳銀、I巴 銀鎳銀鈀、金鎳銀鈀、鈀銀鎳金、鈀銀鎳錫、銀鎳錫、金鎳錫、 金鈀鎳錫、金鎳銅鎳金、金鈀鎳銅鎳鈀金、金鎳銅鎳鈀金、金 鈀鎳銅鎳金、銀、銀鎳銅鎳鈀金、金鈀鎳銅鎳銀、銀鎳銅鎳金、 金鎳銅鎳銀、銀鎳銅鎳銀、鈀銀鎳銅鎳銀、纪銀鎳銅鎳銀鈀、 金鎳銅鎳銀鈀、鈀銀鎳銅鎳金、鈀銀鎳銅鎳錫、銀鎳銅鎳錫、 金鎳銅鎳錫、金鈀鎳銅鎳錫、鈀銀鎳銅錫、銀鎳銅錫、金鎳銅 錫與金鈀鎳銅錫其中之任一。 28. 如請求項25所述之半導體封裝結構，其中該導電連接結構 包含至少一引線或至少一連接塾。 \ 29. 如請求項25所述之半導體封裝結構，其中該導電連接結構 包含至少一金屬凸塊或至少一連接墊。 其中該封裝膠體之材 30. 如請求項25所述之半導體封裝結構 質包含環氧樹脂。 其中複數凹槽形成於 31. 如請求項25所述之半導體封裝結構 該晶片承載區與該導電連接區以暴露出該表面處理層。 32. 如請求項31所述之半導體封裝結構，更包含複數焊接元件 設置於暴露出之該表面處理層上。 33. 如請求項32所述之半導體封裝結構，其中該些焊接元件係 填滿該些凹槽。 18 200826206 3 4如言奢/-n 該晶片承奸體封裝結構，其中複數凹槽形成於 邊。μ與料電連接區週緣以暴露出該表面處理層之側 ='=:r結構 更包含複數焊接元件 其中該些焊接元件係 更包含複數焊接元件 項35所述之半㈣封裂結構 …些凹槽包覆該表面處理層之側邊 37.如請求項25所述之半導體封裝= 設置於暴露出之該表面處理芦。、、。構 19
TW095146075A 2006-12-08 2006-12-08 Semiconductor fabrication method and structure thereof TW200826206A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095146075A TW200826206A (en) 2006-12-08 2006-12-08 Semiconductor fabrication method and structure thereof
US12/000,021 US20080135939A1 (en) 2006-12-08 2007-12-07 Fabrication method of semiconductor package and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095146075A TW200826206A (en) 2006-12-08 2006-12-08 Semiconductor fabrication method and structure thereof

Publications (1)

Publication Number Publication Date
TW200826206A true TW200826206A (en) 2008-06-16

Family

ID=39496962

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095146075A TW200826206A (en) 2006-12-08 2006-12-08 Semiconductor fabrication method and structure thereof

Country Status (2)

Country Link
US (1) US20080135939A1 (zh)
TW (1) TW200826206A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2501644A1 (en) * 2009-11-20 2012-09-26 Unimicron Technology Corp. Lid, fabricating method thereof, and mems package made thereby
DE102011084393A1 (de) * 2011-10-13 2013-04-18 Robert Bosch Gmbh Mikromechanische Funktionsvorrichtung, insbesondere Lautsprechervorrichtung, und entsprechendes Herstellungsverfahren
ITTO20120976A1 (it) 2012-11-09 2014-05-10 St Microelectronics Srl Procedimento per la fabbricazione di un cappuccio per una struttura di incapsulamento di dispositivi elettronici e cappuccio per una struttura di incapsulamento di dispositivi elettronici
CN108242403A (zh) * 2016-12-27 2018-07-03 冠宝科技股份有限公司 一种无基板半导体封装制造方法
CN112968119B (zh) * 2020-12-18 2022-02-18 重庆康佳光电技术研究院有限公司 芯片的转移方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation

Also Published As

Publication number Publication date
US20080135939A1 (en) 2008-06-12

Similar Documents

Publication Publication Date Title
KR100838440B1 (ko) 전자 장치용 기판과 그 제조 방법, 및 전자 장치와 그 제조방법
US8230591B2 (en) Method for fabricating an electronic device substrate
TW398063B (en) Lead frame and its manufacturing method thereof
TWI316749B (en) Semiconductor package and fabrication method thereof
US6291271B1 (en) Method of making semiconductor chip package
US6025650A (en) Semiconductor device including a frame terminal
TWI331797B (en) Surface structure of a packaging substrate and a fabricating method thereof
US6608374B1 (en) Semiconductor chip assembly with bumped conductive trace
KR100437437B1 (ko) 반도체 패키지의 제조법 및 반도체 패키지
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
TW200950006A (en) Circuit board process
US6576493B1 (en) Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US20060118940A1 (en) Semiconductor device and method of fabricating the same
US20060030140A1 (en) Method of making bondable leads using positive photoresist and structures made therefrom
KR100611291B1 (ko) 회로 장치, 회로 모듈 및 회로 장치의 제조 방법
JP4446772B2 (ja) 回路装置およびその製造方法
US6667229B1 (en) Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip
KR101009110B1 (ko) 매립 솔더 범프를 갖는 인쇄회로기판 및 그 제조방법
TW200826206A (en) Semiconductor fabrication method and structure thereof
JP3524441B2 (ja) 配線形成方法
JP3522403B2 (ja) 半導体装置
JPH06177315A (ja) 多層リードフレーム
TW200901419A (en) Packaging substrate surface structure and method for fabricating the same
JPH10340925A (ja) 半導体装置およびその製造方法
US6949408B1 (en) Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps