TW200825906A - Method and system to combine multiple register units within a microprocessor - Google Patents

Method and system to combine multiple register units within a microprocessor Download PDF

Info

Publication number
TW200825906A
TW200825906A TW096128461A TW96128461A TW200825906A TW 200825906 A TW200825906 A TW 200825906A TW 096128461 A TW096128461 A TW 096128461A TW 96128461 A TW96128461 A TW 96128461A TW 200825906 A TW200825906 A TW 200825906A
Authority
TW
Taiwan
Prior art keywords
unit
register
register unit
temporary
temporary storage
Prior art date
Application number
TW096128461A
Other languages
English (en)
Chinese (zh)
Inventor
Lucian Codrescu
Erich Plondke
Mao Zeng
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of TW200825906A publication Critical patent/TW200825906A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
TW096128461A 2006-08-02 2007-08-02 Method and system to combine multiple register units within a microprocessor TW200825906A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/498,627 US8417922B2 (en) 2006-08-02 2006-08-02 Method and system to combine multiple register units within a microprocessor

Publications (1)

Publication Number Publication Date
TW200825906A true TW200825906A (en) 2008-06-16

Family

ID=38745271

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096128461A TW200825906A (en) 2006-08-02 2007-08-02 Method and system to combine multiple register units within a microprocessor

Country Status (7)

Country Link
US (1) US8417922B2 (ja)
EP (1) EP2069913A1 (ja)
JP (5) JP2009545823A (ja)
KR (1) KR101048234B1 (ja)
CN (1) CN101495959B (ja)
TW (1) TW200825906A (ja)
WO (1) WO2008016902A1 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8898436B2 (en) 2009-04-20 2014-11-25 Oracle America, Inc. Method and structure for solving the evil-twin problem
CN102457268B (zh) * 2010-10-15 2014-10-22 北京德威特继保自动化科技股份有限公司 32位捕获寄存器的实现方法
KR101801920B1 (ko) 2010-12-17 2017-12-28 삼성전자주식회사 동적 클러스터링이 가능한 레지스터 파일 및 동적 클러스터링이 가능한 레지스터 파일을 이용한 재구성 가능 컴퓨팅 장치
WO2013100927A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Reducing the number of io requests to memory when executing a program that iteratively processes contiguous data
US9323529B2 (en) 2012-07-18 2016-04-26 International Business Machines Corporation Reducing register read ports for register pairs
US9323532B2 (en) 2012-07-18 2016-04-26 International Business Machines Corporation Predicting register pairs
US9298459B2 (en) * 2012-07-18 2016-03-29 International Business Machines Corporation Managing register pairing
US9026791B2 (en) * 2013-03-11 2015-05-05 Qualcomm Incorporated Linear feedback shift register (LFSR)
US10228941B2 (en) * 2013-06-28 2019-03-12 Intel Corporation Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
US9582419B2 (en) * 2013-10-25 2017-02-28 Arm Limited Data processing device and method for interleaved storage of data elements
US9886276B2 (en) * 2014-10-10 2018-02-06 Arm Limited System register access
US9952865B2 (en) * 2015-04-04 2018-04-24 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
US10162634B2 (en) * 2016-05-20 2018-12-25 International Business Machines Corporation Extendable conditional permute SIMD instructions
CN107621949A (zh) * 2016-07-15 2018-01-23 龙芯中科技术有限公司 内存拷贝方法及装置
US10747531B1 (en) * 2018-04-03 2020-08-18 Xilinx, Inc. Core for a data processing engine in an integrated circuit

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0779577B1 (en) * 1993-10-18 2002-05-22 VIA-Cyrix, Inc. Micoprocessor pipe control and register translation
US5564056A (en) 1994-03-01 1996-10-08 Intel Corporation Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
JPH07262010A (ja) * 1994-03-25 1995-10-13 Hitachi Ltd 演算処理装置および演算処理方法
EP0743591B1 (en) 1995-05-16 2002-01-02 Océ-Technologies B.V. Printing system comprising a communication control apparatus
GB9509987D0 (en) 1995-05-17 1995-07-12 Sgs Thomson Microelectronics Manipulation of data
JP3526976B2 (ja) * 1995-08-03 2004-05-17 株式会社日立製作所 プロセッサおよびデータ処理装置
WO1997009679A1 (en) 1995-09-01 1997-03-13 Philips Electronics North America Corporation Method and apparatus for custom processor operations
US5854939A (en) * 1996-11-07 1998-12-29 Atmel Corporation Eight-bit microcontroller having a risc architecture
US6052522A (en) * 1997-10-30 2000-04-18 Infineon Technologies North America Corporation Method and apparatus for extracting data stored in concatenated registers
US6041404A (en) * 1998-03-31 2000-03-21 Intel Corporation Dual function system and method for shuffling packed data elements
US6247112B1 (en) * 1998-12-30 2001-06-12 Sony Corporation Bit manipulation instructions
US6463525B1 (en) * 1999-08-16 2002-10-08 Sun Microsystems, Inc. Merging single precision floating point operands
US6631460B1 (en) 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
AU2001259555A1 (en) 2000-05-05 2001-11-20 Ruby B. Lee A method and system for performing subword permutation instructions for use in two-dimensional multimedia processing
US7120781B1 (en) * 2000-06-30 2006-10-10 Intel Corporation General purpose register file architecture for aligned simd
JP2002132499A (ja) * 2000-10-27 2002-05-10 Hitachi Ltd データ処理装置及び記録媒体
JP3779540B2 (ja) * 2000-11-08 2006-05-31 株式会社ルネサステクノロジ 複数レジスタ指定が可能なｓｉｍｄ演算方式
US7228403B2 (en) * 2000-12-23 2007-06-05 International Business Machines Corporation Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture
JP3776732B2 (ja) * 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
WO2004015563A1 (en) 2002-08-09 2004-02-19 Intel Corporation Multimedia coprocessor control mechanism including alignment or broadcast instructions
US7103756B2 (en) 2002-09-30 2006-09-05 Hewlett-Packard Development Company, L.P. Data processor with individually writable register subword locations
GB2411976B (en) * 2003-12-09 2006-07-19 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
GB2409066B (en) 2003-12-09 2006-09-27 Advanced Risc Mach Ltd A data processing apparatus and method for moving data between registers and memory
GB2409064B (en) * 2003-12-09 2006-09-13 Advanced Risc Mach Ltd A data processing apparatus and method for performing in parallel a data processing operation on data elements
JP4202244B2 (ja) 2003-12-22 2008-12-24 Ｎｅｃエレクトロニクス株式会社 Ｖｌｉｗ型ｄｓｐ，及びその動作方法
US7177876B2 (en) * 2004-03-04 2007-02-13 Texas Instruments Incorporated Speculative load of look up table entries based upon coarse index calculation in parallel with fine index calculation
US7376813B2 (en) * 2004-03-04 2008-05-20 Texas Instruments Incorporated Register move instruction for section select of source operand
US7237096B1 (en) * 2004-04-05 2007-06-26 Sun Microsystems, Inc. Storing results of producer instructions to facilitate consumer instruction dependency tracking
US8621444B2 (en) 2004-06-01 2013-12-31 The Regents Of The University Of California Retargetable instruction set simulators
US8127117B2 (en) 2006-05-10 2012-02-28 Qualcomm Incorporated Method and system to combine corresponding half word units from multiple register units within a microprocessor
US8445994B2 (en) 2009-05-07 2013-05-21 Qualcomm Incorporated Discontinuous thin semiconductor wafer surface features
US20100314725A1 (en) 2009-06-12 2010-12-16 Qualcomm Incorporated Stress Balance Layer on Semiconductor Wafer Backside
US8076762B2 (en) 2009-08-13 2011-12-13 Qualcomm Incorporated Variable feature interface that induces a balanced stress to prevent thin die warpage

Also Published As

Publication number Publication date
US8417922B2 (en) 2013-04-09
CN101495959B (zh) 2012-04-25
KR101048234B1 (ko) 2011-07-08
JP2013218709A (ja) 2013-10-24
US20080184007A1 (en) 2008-07-31
JP2009545823A (ja) 2009-12-24
JP2015201216A (ja) 2015-11-12
KR20090042294A (ko) 2009-04-29
JP2017138993A (ja) 2017-08-10
CN101495959A (zh) 2009-07-29
EP2069913A1 (en) 2009-06-17
JP5680709B2 (ja) 2015-03-04
WO2008016902A1 (en) 2008-02-07
JP2013242879A (ja) 2013-12-05

Similar Documents

Publication Publication Date Title
TW200825906A (en) Method and system to combine multiple register units within a microprocessor
CN105453071B (zh) 用来提供向量族群计数功能的方法、设备、指令和逻辑
TWI223196B (en) Method, apparatus, and system for exception handling in a pipelined processor
US8074051B2 (en) Multithreaded processor with multiple concurrent pipelines per thread
CN105359129B (zh) 用于提供用于基因组测序和比对的族群计数功能的方法、装置、指令以及逻辑
TW201106263A (en) Instruction process methods, and superscalar pipelined microprocessors
JP6242615B2 (ja) マイクロプロセッサ内において複数のレジスタユニットからの対応する半語ユニットを結合するための方法及びシステム
TW201203110A (en) Mapping between registers used by multiple instruction sets
TW201007472A (en) Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
US7809894B2 (en) Compare, swap and store facility with no external serialization
TWI288350B (en) Method for multi-pipe dispatch and execution of complex instructions in a superscalar processor
TW201337738A (zh) 用以提供向量水平式多數決投票功能之指令與邏輯
BR112015022683B1 (pt) Sistema de processamento e método de realização de uma operação de manipulação de dados
JP2001500641A (ja) 並列データプロセッサにおけるアクティブ命令を回転させる方法および装置
TW408269B (en) A method and system for handling multiple store instruction completions in a processing system
CN101322111A (zh) 每个线程具有多个并发流水线的多线程处理器
EP1050800A1 (en) A pipelined execution unit
TW201028917A (en) Data storing method and processor using the same
JPH0311479A (ja) ストリーム演算終了検知方法及びその装置