TW200824105A - Package structure for thin type image chip - Google Patents

Package structure for thin type image chip Download PDF

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Publication number
TW200824105A
TW200824105A TW095143604A TW95143604A TW200824105A TW 200824105 A TW200824105 A TW 200824105A TW 095143604 A TW095143604 A TW 095143604A TW 95143604 A TW95143604 A TW 95143604A TW 200824105 A TW200824105 A TW 200824105A
Authority
TW
Taiwan
Prior art keywords
wafer
cover
package structure
image
chip package
Prior art date
Application number
TW095143604A
Other languages
Chinese (zh)
Other versions
TWI321846B (en
Inventor
cheng-jiao Wu
Original Assignee
Taiwan Electronic Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Electronic Packaging Co Ltd filed Critical Taiwan Electronic Packaging Co Ltd
Priority to TW095143604A priority Critical patent/TW200824105A/en
Publication of TW200824105A publication Critical patent/TW200824105A/en
Application granted granted Critical
Publication of TWI321846B publication Critical patent/TWI321846B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention provides a package structure for thin type image chip. It includes a carrier body, an image chip, a cover body, and several conducting wires. One end surface of the said image chip is connected with the said carrier body. The other end surface of the said image chip forms an image sensing area. The outer peripheral of the said image sensing area forms several chip-bonding pads. The cover body has a connecting section and a top cover section. The connecting section is connected with the image chip. It is located between the image sensing area and the chip-bonding pads. The top cover section is connected with the connecting section. It is located above the image sensing area. One end of the conducting wire is connected with the chip-bonding pad. The other end of the conducting wire is connected with the carrier body. The conducting wire connects electricity between the image chip and the carrier body. The cover body has a sidewall and a top board. The sidewall is connected with the carrier body. The top board is connected with the sidewall. The top board has a perforation. The top cover section is located within the perforation and connected to the outside. The top board can entirely cover the conducting wire.

Description

200824105 九、發明說明: 【發明所屬之技術領域】 本發明係與晶片封裝結構有關,更詳而言之是指_種 薄型影像晶片封裝結構。200824105 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a chip package structure, and more particularly to a thin image chip package structure.

【先前技術】 按,以習知之積體電路 一晶片貼接於一電路板上, 之焊墊及電路板上,使該晶 與該電路板呈電性之連通。 晶片構裝而言,一般係直接將 再利用金屬導線焊接至該晶片 片可藉由該金屬導線之連接而 ’ L、構衣之晶片為—種攝取影像用之晶片時,該 曰曰=之頂面乃為-影像感測區,以藉由該影像感測區加以 成像,因此該影像感測區須為極度之乾淨,但由於在構裝 之加工過程中,仍必須有焊接導線··等之作業,因此極易 造成影像感囊有污染物_之情料生,㈣致成像之 歧甚有111焊接導線之不慎1¾誤撞料彡像感測 _ 區之情形,進而造成損壞。 再者’由於影像用晶片之構裝必須再藉由一封裝體直 接將整個晶片加以包覆,但受限於導線之焊接及避免有誤 觸衫像感測區之情形,而必須將其封裝體設置於距該晶片 ⑼有-預定距離之位置上,此對現今要求輕薄短小之晶片構 衣而a,無旋不付現今之時勢。 【發明内容】 有鑑於此’本發明之主要目的乃在提供一種薄型影像 4 200824105 晶片=結構,係可有效減少整體構裝後之體積者。 構,係T目的乃在提供—種薄型影像日日日片射裝結 者。 免/、影像感測區於施打導線時受到污染戒損傷 5 15 晶 片封裝:槿?土述目的’本發明所提供—種薄型影像 面連結於_=有」Γ載體;—影像晶片,係以其一端 感測區丨上’錄像晶片之另—端上形成有〆影像 焊墊.1骑該影縣砸之外周邊上形财若干之晶片 結於該射一連接部及1罩部,該連接部係連 間,使片亚位於該影像感測區與該晶片焊替之 之間,部加以阻隔於該影像感測區與該晶片焊藝 2 於該連接部上,並位於該影像二 另一 * 右干之導線,係以其一端連接於該晶片焊藝上, 钱ί則連接於該紐上,使該影像日日日片與該載體間辑* 電性連通;一蓋體’具有一側壁及一頂板,二 土係連接於該載體上’該頂板係連接於該側壁上,且該两 板形成有—穿孔,使該鮮部位於該穿孔巾,而與外 通,且該頂板係可將該導線完全蓋覆。 目 2〇【實施方式】 為使貴審查委員,能對本發明之特徵及目的有更進一 步之瞭解與認同,茲列舉以下較佳之實施例,並配合圖: 說明於後: ^ 請麥閱第一及第二圖,係本發明第一較佳實施例所提 5 200824105 供一種薄型影像晶片封裝結構(IQ),其主要包含有一載體 (11)、一影像晶片(12)、一罩體(13)、若干之導線(14)----蓋 體(15)及一黏著物(16);其中: ^ 禮載體(丨1)’係可為塑膠、強化塑膠、玻璃纖維、陶瓷… • 5等材質所製成之電路板或花架預鑄(PrintedCircuitB〇ard、 PCB、PRE-MOLD),作為該封裝結構(1〇)與外界電性連接 之橋樑;該載體(11)呈一平板狀,具有一頂面(111)及一與該 • 頂面(111)相背之底面(H2),該頂面(111)上佈設有呈預^態 樣及數罝之電路佈線(圖中未示)及若干與該電路佈線電性 10 相通之電路焊墊(113)。 邊影像晶片(12),具有一頂面及一與該頂面相背之底 面,其底面係藉由環氧樹脂、石夕樹脂、低熔點之玻璃或雙 面膠帶…等黏性材料,而黏著貼附於該載體(11)之頂面(m) 上,該影像晶片(12)之頂面中央位置處設置有一影像感測區 I5 (121)用以成像,並於影像晶片(12)之頂面上位於該影像感 馨 ’則區(121)之外部周邊處,設置有若干與該影像晶片(12)呈 電性導通之晶片焊墊(122)。 該罩體(13),包含有一連接部(131)及一頂罩部(132); 及連接部(131)於本貫施例中為一轴心呈透空狀之環形體, 2〇係可由塑膠、玻璃、玻璃纖維、金屬或陶瓷…材質所製成, 使其軸心内部形成一罩設空間(133),該連接部(13ι)係以其 一^緣(底緣)藉由一黏膠(圖中未示)而連接抵於該影像晶 片(12)頂面之影像感測區(121)周圍外,且係連接於該影像 感測區(121)與該各晶片焊墊(122)之間,使該影像感測區 6 200824105 (m)位在該罩設空間(133)内,而由該連接部(1川將該影像 感測區(121)之外周邊加以封閉,並使得該晶片渾塾⑽換 該影像感測區(121)得以由該連接部(131)而加以隔開,該連 _接部(131)外側邊上並再以-快乾膠(m)黏接於該影像晶 5片(12)上,以迅速固定該連接部(131)與該影像晶片(12)之相 關位置,該頂罩部(132)於本實施例中為一絕緣之圓盤狀薄 板(亦可為矩形狀薄板),係可由玻璃等透光材料所製成,該 丨 頂罩部(132)係藉由一黏著物(圖中未示)而黏接於該連接部 (131) 之另一端緣(頂緣)上,使該頂罩部(132)正位於該影像 ίο感測區(121)之上方,並藉由與該連接部(131)之連接而距該 影像感測區(121)有一預定之距離,使由該頂罩部(132)將該 罩設空間(133)之上方加以封閉;於本實施例中,該頂罩部 (132) 之寬度面積係相等於該連接部(131)之寬度面積,但於 實際設計時,該頂罩部之寬度面積亦可大於該連接部之寬 15度面積。 ,該等導線(14),係由黃金、鋁…等導電金屬材質所製 • 成,係利用打線技術將該各導線(14)分別與該載體(11)之電 - 路焊墊(H3)及該晶片(12)之晶片焊墊(122)電性連接;於打 線作業時,該導線(14)首先以垂直該載體(11)電路焊墊(113) 2〇 之方式與該電路焊墊(113)牢固地銜接(為第一焊接點),再將 導線(14)往上拉伸至晶片(12)頂面之位置時,以近乎水平之 方式延伸至與該晶片焊墊(122)銜接(為第二焊接點),藉 此,該晶片(12)上方供導線(14)容置之空間即可加以扁平化 而大幅縮減封裝結構(10)之高度。 200824105 該蓋體(15),係可由一不透明之塑膠、玻璃纖維、金屬、 陶瓷或透明之玻璃、石英、塑膠材質所製成;該蓋體(15) 具有一側壁(151)及一頂板(152),該側壁(151)於本實施例中 ’ 為一軸向呈透空狀之矩形體(亦可為環形體),使其軸向内部 -5形成一蓋設空間(153),該侧壁(151)係以其一端緣(底緣)藉 由一黏著物(圖中未示)而連接於該載體(11)之頂面(H1) 上,且係位於該電路焊墊(113)之外周圍,使該晶片(12)、電 籲 路焊墊(113)及各導線(14)皆位在封裝之蓋設空間(153)内, 該頂板(152)於本實施例中為一矩形狀薄板(亦可為環形狀 10薄板),該頂板(152)係以其外側緣連接於該側壁(151)之另一 端緣(頂緣),且該頂板(152)中央位置並形成有一穿孔 (154),該穿孔(154)之孔徑略大於該罩體(π)之頂罩部(132) 外徑,使該頂罩部(132)正位於該穿孔(154)中,且該頂板(152) 係可將該導線(14)完全蓋覆。 15 該黏著物(16),可為矽樹脂(Silicones)、環氧樹脂 ⑩ (Epoxles)、丙烯酸樹脂(Acrylics)、聚醯亞胺(P〇lyamides)、 低熔點之玻璃…等材質所製成,該黏著物(丨6)係佈設於該罩 - 體(13)頂罩部(132)之外側與該蓋體(15)之穿孔(154)之内壁 面間’使該罩體(13)與該蓋體(15)加以黏接,以將該晶片(12) 2〇及導線(14)加以封閉於該蓋體(15)之蓋設空間(153)内,而完 成整體之封裝作業。 由於本發明之封裝結構(1〇)於進行打線作業(即將導線 與晶片焊墊及電路焊墊連接之作業)前,已藉由該罩體(13) 將景》像感測區(121)與晶片焊墊(122)加以阻隔,可避免於打 8 200824105 線作業時有誤觸或污染影像感測區(121)之情事發生。另 外,由於導線(14)係以近乎水平之方式延伸至與該晶片焊墊 (U2)銜接,因此,該晶片(Π)上方供導線(1句容置之空間即 可加以扁平化而大幅縮減封裝結構(10)之高度。 5 再者,該罩體(13)之連接部(131)與頂罩部(132)亦可採 一體成形所製成,而該蓋體(15)之侧壁(151)與該頂板(152) 亦可採一體成形所製成,可更加簡化整體組裝之作業。 請參閱第三圖,係本發明第二較佳實施例所提供之一 種薄型影像晶片封裝結構(20),其與上述實施例相同包含有 10 一載體(21)、一影像晶片(22)、一罩體(23)、若干之導線(24)、 一盍體(25)及一黏著物(26),惟與上述實施例之差異在於: 該蓋體(25)之蓋設空間(253)内更佈設有一包覆體 (27) ’係覆皇於该晶片(22)及該導線(24)上,該包覆體(27) 係可為矽樹脂(Silicones)、環氧樹脂(Epoxies)、丙烯酸樹脂 15 (Acrylics)、聚醯亞胺(Polyamides)、低熔點之玻璃…等材質 所製成,該包覆體(27)於初期係呈膠狀,而後可乾燥固化成 硬貝之保濩體,藉以保濩該晶片(22)及該導線(24)。 請參閱第四圖,係本發明第三較佳實施例所提供之一 種薄型影像晶片封裝結構(30),其與第一較佳實施例相同包 2〇含有一載體(31)、一影像晶片(32)、一罩體(33)、若干之導 線(34)、一蓋體(35)及一黏著物(36),惟與第一較佳實施例 之差異在於: 該導線(34),係以其一端焊接於該晶片(32)之晶片焊墊 (322)上,再將另一端焊接於該載體(川之頂面(3⑴上,且 9 200824105 該導線(3句係由其一端與載體(31)焊接後,而逐漸地呈往晶 片(32)中心之方向傾斜地拉伸至由另—端與該晶片^ (322)焊接’如此一來,該導線(34)便呈傾斜狀,雖其導線㈣ ' 所佔之空間較大,但卻較便於打線之作業者。 • 5 該蓋體(35)之側壁(351)鄰近於與該载體卯頂面即) 連接之内側部位上,形成有—容置空間(355),該容置空間 (355)係用以供鄰近於載體⑼之導線(34)部位容置,即形成 • 該容置空間(355)之側壁(351)其厚度較薄,且呈現盘該導線 (34)同-走向之斜切態樣。如此—來,原本為便於㈣作業 K)而將該導線(34)呈斜接狀態所增加之耗佔空間,料由該導 線(34)^(立於該容置空間(355)内所加以補償,使得蓋體⑽ ^體高度及寬度皆無f增加,而可同樣使封裝結構⑽ 呈薄型化,而能減少打線作業之進行難度及增進打線作業 之效率。 15 —明苓閱第五圖,係本發明第四較佳實施例所提供之一 ^ 種薄型影像晶片封裝結構(4〇),其與第-較佳實施例相同包 含有一載體(41)、一影像晶片(42)、一罩體(43)、若干之導 ’ 線(44)、一 1體(45)及一黏著物(46),惟與第一較佳實施例 之差異在於: 2〇言亥蓋體(45)更於其頂板(452)上凸伸形成有-容置部 (456) ,篇容置部(456)内部係呈上下透空而形成有一容室 (457) ,σ亥谷至(457)並與該穿孔(454)連通,該容室(457)之内 側壁面上形成有_第—螺紋部(458),該第—螺紋部(458)為 一内螺紋。 10 200824105 _型影像晶片封裝結構(4〇)更包含有-鏡頭(47),該 鏡頭(47)具有-管體(471)及若干固設於該管_71)内之鏡 一2) ’該管體(471)之外周面上設有-第二做部(473), 4第—d卩(473)為—外螺紋,係螺接於該蓋體⑷)之第 .5 -歡部(458)上.,使可藉由鄉該f酬⑽造成該鏡頭 (47)^V下位移’以調整鏡頭(47)中之鏡片(472)焦距。 *請參閱第六圖,係本發明第五較佳實施例所提供之一 種薄型影像晶片封裝結構(5 〇),其與第一較佳實施例相同包 含有-載體(51)、-影像晶片(52)、一罩體(53)、若干之導 10線(54)、-蓋體(55)及一黏著物(56),惟與第一較佳實施例 之差異在於: 忒罩體(53)之頂罩部(532)為一鏡片,係貼接於該連接 部(531)上,使該頂罩部(532)正位於該影像感測區(521)之上 方,並藉由與該連接部(531)之連接,而使得該頂罩部(532) 15與。亥衫像感測區(521)間距有一預定之距離,使可由該頂罩 部(532)提供聚焦之效果。 ' 該蓋體(55)更於其頂板(552)上凸伸形成有一容置部 (556) ,該容置部(556)内部係呈上下透空而形成有一容室 (557) ,該容室(557)並與該穿孔(554)連通,該容室(557)内則 2〇固設置有一鏡片(559)。 當然,該頂罩部(532)可為與該連接部(531)所一體製 成,而該鏡片(559)亦可與該容置部(556)所一體製成。 請參閱第七圖,係本發明第六較佳實施例所提供之一 種薄型影像晶片封裝結構(60),其與第一較佳實施例相同包 η 200824105 含有一載體(61)、一影像晶片(62)、——罩體(63)、若干之導 線(64)、一蓋體(65)及一黏著物(66),惟與第一較佳實施例 之差異在於: “ 。亥載體(61)之頂面(611)上以一預定之寬度及深度向下 5凹陷延伸有一凹陷區(614),該影像晶片(62)係設置於該凹 P曰區(614)内,該各導線(64)則係利用打線技術將其兩端分 別連接於該影像晶片(62)之晶片焊墊(622)及該載體(61)頂 藝面(611)上之電路焊墊(圖中未示)上。 忒盍體(65)僅具有一頂板(652)且藉由一可撕離性之黏 10性體(651)以其一面黏貼於該載體(61)之頂面(6ιι)上,使該 罩體(63)之頂罩部(632)同樣位於該蓋體(65)之穿孔(654) 中,且同樣由該黏著物(66)將該蓋體(65)與該罩體(63)加以 黏結。 另外,該黏性體(651)亦可為多數個之黏性體,係採用 多點方式聽貼於該載體(⑷之頂面(611)上。如此一來,不僅 • <達成本發明之目的’更可藉由該黏性體_離之特性, . 將該蓋體(65)與該載體(61)分離使封裝内部維修更為簡易。 , 軸於本實施例巾’該载體之電路焊墊係設置於复頂 面上’但實際上亦設置於該凹陷區中,而使得整體之封、 20結構可更加地降低高度。 、 12 200824105 【圖式簡單說明】 第圖係本發明第一較佳實施例之剖視示意圖。 第一圖係第一圖所示較佳實施例之頂面示意圖。 第三圖係本發明第二較佳實施例之剖視示意圖。 第四圖係本發明第三較佳實施例之剖視示意圖。 第五圖係本發明第四較佳實施例之剖視示意圖。 第六圖係本發明第五較佳實施例之剖視示意圖。 第七圖係本發明第六較佳實施例之剖視示意圖。 10 15[Prior Art] According to the conventional integrated circuit, a wafer is attached to a circuit board, a pad and a circuit board, so that the crystal is electrically connected to the circuit board. In the case of a wafer package, the metal wire is directly soldered to the wafer. The wafer can be connected by the metal wire, and the wafer is a wafer for image capturing. The top surface is an image sensing area for imaging by the image sensing area, so the image sensing area must be extremely clean, but since there is still a welding wire during the processing of the structure, Waiting for the operation, it is very easy to cause the image sensory capsule to have contaminants, and (4) the imaging is inconsistent with the 111 welding wire inadvertently, and the damage is caused by the image sensing area. Furthermore, since the image wafer is mounted, the entire wafer must be directly coated by a package, but it is limited by soldering of the wires and avoiding accidental contact with the sensing area, and must be packaged. The body is disposed at a predetermined distance from the wafer (9), which requires a light and thin wafer coating to be a today, and no rotation is required to pay the current situation. SUMMARY OF THE INVENTION In view of the above, the main object of the present invention is to provide a thin image 4 200824105 wafer = structure, which can effectively reduce the volume after the overall assembly. The purpose of T is to provide a thin image of the day and day film. Free/, the image sensing area is contaminated or damaged when the wire is applied. 5 15 Chip package: 槿 土 土 ' ' ' 本 本 本 本 本 本 本 本 本 本 本 本 本 本 薄 薄 薄 薄 薄 薄 薄 薄 薄 薄 薄 影像 影像 影像 影像 影像 影像 影像 影像 影像A 〆 image solder pad is formed on the other end of the recording chip on the one end of the sensing area. 1 The chip on the periphery of the shadow 砸 结 is attached to the connecting portion and the hood portion. The connecting portion is connected between the image sensing region and the wafer soldering portion, and the portion is blocked on the image sensing region and the soldering die 2 on the connecting portion, and is located in the image The other *right-handed wire is connected to the wafer soldering art at one end thereof, and the money is connected to the button to electrically connect the image of the day and the day to the carrier; 'Having a side wall and a top plate, the two soils are attached to the carrier', the top plate is attached to the side wall, and the two plates are formed with a perforation, so that the fresh part is located in the perforated towel, and is externally connected, and The top plate can completely cover the wire.目 〇 实施 实施 实施 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为And the second figure is a thin image chip package structure (IQ) for the first preferred embodiment of the present invention. The invention mainly comprises a carrier (11), an image chip (12), and a cover (13). ), a number of wires (14)----cover (15) and an adhesive (16); wherein: ^ Gift carrier (丨1)' can be plastic, reinforced plastic, fiberglass, ceramic... 5 A circuit board or a flower frame (PrintedCircuitB〇ard, PCB, PRE-MOLD) made of a material is used as a bridge for electrically connecting the package structure (1〇) to the outside; the carrier (11) has a flat shape. The utility model has a top surface (111) and a bottom surface (H2) opposite to the top surface (111). The top surface (111) is provided with circuit wirings in a pre-measured state and a plurality of turns (not shown) And a plurality of circuit pads (113) in communication with the circuit wiring electrical 10 . The edge image wafer (12) has a top surface and a bottom surface opposite to the top surface, and the bottom surface is adhered by an adhesive material such as epoxy resin, Shishi resin, low melting glass or double-sided tape. Attached to the top surface (m) of the carrier (11), an image sensing area I5 (121) is disposed at a central position of the top surface of the image chip (12) for imaging, and is formed on the image wafer (12) The top surface is located at the outer periphery of the image sensing area (121), and is provided with a plurality of wafer pads (122) electrically connected to the image wafer (12). The cover body (13) includes a connecting portion (131) and a top cover portion (132); and the connecting portion (131) is a ring-shaped annular body in the present embodiment, It can be made of plastic, glass, fiberglass, metal or ceramic material, and has a cover space (133) inside its axis. The connection part (13ι) is made up of one edge (bottom edge) by one An adhesive (not shown) is connected to the periphery of the image sensing area (121) on the top surface of the image chip (12), and is connected to the image sensing area (121) and the wafer pads ( 122), the image sensing area 6 200824105 (m) is located in the cover space (133), and the connection portion (1) is closed to the periphery of the image sensing area (121). And the wafer 浑塾 (10) is replaced by the connecting portion (131) for the image sensing region (121), and the outer side of the connecting portion (131) is further provided with a quick-drying glue (m) Adhering to the image crystal 5 (12) to quickly fix the position of the connecting portion (131) and the image wafer (12), the top cover portion (132) is an insulating layer in this embodiment Disc-shaped thin The plate (which may also be a rectangular thin plate) may be made of a light transmissive material such as glass, and the dome cover portion (132) is adhered to the connecting portion by an adhesive (not shown) (131). The other end edge (top edge) is such that the top cover portion (132) is located above the image ίο sensing region (121) and is connected to the image by the connection with the connecting portion (131) The measuring area (121) has a predetermined distance to close the upper portion of the covering space (133) by the top cover portion (132); in the embodiment, the width of the top cover portion (132) is phased It is equal to the width area of the connecting portion (131), but in actual design, the width of the top cover portion may also be larger than the width of the connecting portion by 15 degrees. The wires (14) are made of gold, aluminum... The conductive metal material is made by electrically connecting the wires (14) to the electric pad (H3) of the carrier (11) and the wafer pad (122) of the wafer (12) by wire bonding technology. Sexual connection; the wire (14) is first firmly connected to the circuit pad (113) in a manner perpendicular to the carrier (11) circuit pad (113) during wire bonding operation (for The first solder joint), when the wire (14) is stretched up to the top surface of the wafer (12), extends in a nearly horizontal manner to engage with the wafer pad (122) (as a second solder joint) Therefore, the space for the wire (14) to be placed above the wafer (12) can be flattened to greatly reduce the height of the package structure (10). The cover body (15) can be made of an opaque plastic, Made of glass fiber, metal, ceramic or transparent glass, quartz or plastic material; the cover body (15) has a side wall (151) and a top plate (152), which is in the embodiment a rectangular body (also an annular body) axially vacant, such that the axial inner portion -5 forms a cover space (153), the side wall (151) being borrowed from one end edge (bottom edge) Attached to the top surface (H1) of the carrier (11) by an adhesive (not shown), and located around the circuit pad (113), the wafer (12), the electric circuit The soldering pad (113) and each of the wires (14) are located in the covering space (153) of the package. The top plate (152) is a rectangular thin plate (also a ring in this embodiment). The top plate (152) is connected to the other end edge (top edge) of the side wall (151) with its outer edge, and the top plate (152) is centrally formed with a through hole (154), the perforation ( 154) the aperture is slightly larger than the outer diameter of the top cover portion (132) of the cover (π) such that the top cover portion (132) is located in the through hole (154), and the top plate (152) is adapted to the wire (14) Completely covered. 15 The adhesive (16) can be made of materials such as Silicone, Epoxles, Acrylics, P〇lyamides, and low melting glass. The adhesive (丨6) is disposed between the outer side of the cover-body (13) top cover portion (132) and the inner wall surface of the through-hole (154) of the cover body (15) to make the cover body (13) The cover body (15) is adhered to close the wafer (12) 2 and the wire (14) in the cover space (153) of the cover body (15) to complete the overall packaging operation. Since the package structure (1) of the present invention is used for the wire bonding operation (that is, the operation of connecting the wires to the wafer pads and the circuit pads), the image sensing area (121) has been used by the cover (13). Blocking with the wafer pad (122) can avoid accidental touch or contamination of the image sensing area (121) during the 200824105 line operation. In addition, since the wire (14) extends to be close to the wafer pad (U2) in a nearly horizontal manner, the wire is provided above the wafer (the space for one sentence can be flattened and greatly reduced) The height of the package structure (10). Further, the connecting portion (131) of the cover (13) and the top cover portion (132) may be integrally formed, and the side wall of the cover (15) (151) The top plate (152) can also be integrally formed, which can simplify the overall assembly operation. Please refer to the third figure, which is a thin image chip package structure provided by the second preferred embodiment of the present invention. (20), which comprises the same as the above embodiment, a carrier (21), an image wafer (22), a cover (23), a plurality of wires (24), a body (25) and an adhesive. (26), but differs from the above embodiment in that: the cover space (253) of the cover body (25) is further provided with a covering body (27) which is attached to the wafer (22) and the wire ( 24), the coating body (27) may be Silicone, Epoxies, Acrylics, Polyamides, low. Made of glass, etc., the covering body (27) is gelatinized in the initial stage, and then can be dried and solidified into a hard shell to protect the wafer (22) and the wire (24). Referring to FIG. 4, a thin image chip package structure (30) according to a third preferred embodiment of the present invention, which comprises the same package as the first preferred embodiment, includes a carrier (31) and an image. The wafer (32), a cover (33), a plurality of wires (34), a cover (35) and an adhesive (36), but differ from the first preferred embodiment in that: the wire (34) One end is soldered to the wafer pad (322) of the wafer (32), and the other end is soldered to the carrier (the top surface of the river (3 (1), and 9 200824105 the wire (3 sentences are by one end thereof) After soldering with the carrier (31), it is gradually stretched obliquely toward the center of the wafer (32) to be soldered to the wafer (322) from the other end. Thus, the wire (34) is inclined. Although the wire (4)' has a larger space, it is easier for the operator to wire. • 5 The side wall (351) of the cover (35) is adjacent to the top surface of the carrier. The inner portion is formed with an accommodating space (355) for accommodating a portion of the wire (34) adjacent to the carrier (9), that is, forming the accommodating space (355) The side wall (351) has a thinner thickness and exhibits a chamfered state of the wire (34) in the same direction. Thus, the wire (34) is obliquely connected to facilitate the (4) operation K). The space occupied by the wire is compensated by the wire (34) ^ (standing in the accommodating space (355), so that the height and width of the cover body (10) are not increased by f, and the package structure (10) can also be made thin. It can reduce the difficulty of the wire-laying operation and improve the efficiency of the wire-laying operation. 15 is a thin image-mounting package structure (4〇) according to a fourth preferred embodiment of the present invention, which comprises a carrier (41) as in the first preferred embodiment. An image wafer (42), a cover (43), a plurality of guide wires (44), a body (45) and an adhesive (46), but differs from the first preferred embodiment in that: 2 The hainan cover body (45) is further formed with a receiving portion (456) on the top plate (452), and the inside of the article receiving portion (456) is vertically emptied to form a chamber (457). The sigma valley to (457) is in communication with the perforation (454), and the inner wall surface of the chamber (457) is formed with a _-thread portion (458), and the first thread portion (458) is an internal thread. 10 200824105 _ type image chip package structure (4〇) further includes a lens (47) having a tube body (471) and a plurality of mirrors fixed in the tube_71) 2) The outer peripheral surface of the pipe body (471) is provided with a second making portion (473), and the fourth d-th (473) is an external thread which is screwed to the fifth part of the cover body (4). (458) Upper, so that the lens (47) can be displaced by (10) to adjust the focal length of the lens (472) in the lens (47). Please refer to a sixth embodiment, which is a thin image chip package structure (5 〇) according to a fifth preferred embodiment of the present invention, which comprises a carrier (51), an image chip, as in the first preferred embodiment. (52), a cover (53), a plurality of guide wires 10 (54), a cover body (55) and an adhesive (56), but differ from the first preferred embodiment in that: a cover body ( 53) The top cover portion (532) is a lens attached to the connecting portion (531) such that the top cover portion (532) is located above the image sensing region (521), and The connection portion (531) is connected such that the top cover portion (532) 15 is coupled. The galvanic image sensing area (521) is spaced apart by a predetermined distance so that the top cover portion (532) can provide a focusing effect. The cover body (55) is further formed with a receiving portion (556) protruding from the top plate (552), and the inside of the receiving portion (556) is vertically emptied to form a cavity (557). The chamber (557) is in communication with the perforation (554), and a lens (559) is disposed in the chamber (557). Of course, the top cover portion (532) may be formed integrally with the connecting portion (531), and the lens (559) may also be integrally formed with the receiving portion (556). Referring to the seventh embodiment, a thin image chip package structure (60) according to a sixth preferred embodiment of the present invention is the same as the first preferred embodiment. The package η 200824105 includes a carrier (61) and an image chip. (62), a cover (63), a plurality of wires (64), a cover (65) and an adhesive (66), but differs from the first preferred embodiment in that: a top surface (611) has a recessed area (614) extending downwardly by a predetermined width and depth, and the image wafer (62) is disposed in the concave P-shaped area (614). (64) is a circuit pad on the wafer pad (622) of the image chip (62) and the top surface (611) of the carrier (61) by wire bonding technology (not shown) The body (65) has only one top plate (652) and is adhered to the top surface (6 ιι) of the carrier (61) by a peelable adhesive 10 (651). The top cover portion (632) of the cover body (63) is also located in the through hole (654) of the cover body (65), and the cover body (65) and the cover body are also made of the adhesive (66). 63) to bond. In addition, the viscosity The body (651) may also be a plurality of viscous bodies, which are attached to the carrier ((4) on the top surface (611) by a multi-point method. Thus, not only • < achieving the purpose of the present invention is more By separating the cover body (65) from the carrier (61), the internal maintenance of the package is made easier. The shaft is in the circuit pad of the carrier of the embodiment. It is disposed on the top surface but is actually disposed in the recessed area, so that the overall sealing and 20 structure can be further reduced in height. 12 200824105 [Simplified illustration] The first preferred embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS The first drawing is a schematic view of a top view of a preferred embodiment of the first embodiment. The third drawing is a schematic cross-sectional view of a second preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a cross-sectional view showing a fourth preferred embodiment of the present invention. FIG. 6 is a cross-sectional view showing a fifth preferred embodiment of the present invention. A schematic cross-sectional view of a preferred embodiment. 10 15

【主要元件符號說明】 「第一較佳實施例」 薄型影像晶片封裝結構(10) 载體(11) 頂面(111) 底面(112) 電路焊墊(113) 影像晶片(12) 影像感測區(121) 晶片焊墊(122) 罩體(13) 連接部(131) 頂罩部(132) 罩設空間(133) 快乾膠(134) 導線(14) 蓋體(15) 側壁(151) 頂板(152) 蓋設空間(153) 穿孔(154) 黏著物(16) 第二較佳實施例」 薄型影像晶片封裝結構(20) 13 20 200824105 載體(21) 罩體(23) 蓋體(25) 黏著物(26) 5 「第三較佳實施例」 薄型影像晶片封裝結構(30) 載體(31) • 影像晶片(32) 罩體(33) 1〇 蓋體(35) 容置空間(355) 「第四較佳實施例」 薄型影像晶片封裝結構(40) 載體(41) 15 罩體(43) φ 蓋體(45) ^ 容置部(456) ^ 穿孔(454) 黏著物(46) 2〇 管體(471) 第二螺紋部(473) 「第五較佳實施例」 薄型影像晶片封裝結構(50) 載體(51) 影像晶片(22) 導線(24) 蓋設空間(253) 包覆體(27) 頂面(311) 晶片焊墊(322) 導線(34) 侧壁(351) 黏著物(36) 影像晶片(42) 導線(44) 頂板(452) 容室(457) 第一螺紋部(45 8) 鏡頭(47) 鏡片(472) 影像晶片(52) 14 200824105 影像感測區(521) 連接部(531) 導線(54) . 頂板(552) • 5 容室(557) 鏡片(559) 「第六較佳實施例」 • 薄型影像晶片封裝結構(60) 載體(61) ίο 凹陷區(614) 晶片焊墊(622) 頂罩部(63 2) 蓋體(65) 頂板(652) 15 黏著物(66) 罩體(53) 頂罩部(532) 蓋體(55) 容置部(556) 穿孔(554) 黏著物(56) 頂面(611) 影像晶片(62) 罩體(63) 導線(64) 黏性體(651) 穿孔(654) 15[Main Component Symbol Description] "First Preferred Embodiment" Thin Image Chip Package Structure (10) Carrier (11) Top Surface (111) Bottom Surface (112) Circuit Pad (113) Image Chip (12) Image Sensing Area (121) Wafer Pad (122) Cover (13) Connection (131) Top Cover (132) Cover Space (133) Quick Adhesive (134) Wire (14) Cover (15) Side Wall (151 Top plate (152) Covering space (153) Perforation (154) Adhesive (16) Second preferred embodiment Thin image chip package structure (20) 13 20 200824105 Carrier (21) Cover (23) Cover ( 25) Adhesive (26) 5 "Third Preferred Embodiment" Thin Image Chip Package Structure (30) Carrier (31) • Image Wafer (32) Cover (33) 1 Cover (35) Housing Space ( 355) "Fourth Preferred Embodiment" Thin Image Chip Package Structure (40) Carrier (41) 15 Cover (43) φ Cover (45) ^ Housing (456) ^ Perforation (454) Adhesive (46) 2〇管体(471) Second threaded part (473) "Fifth preferred embodiment" Thin image chip package structure (50) Carrier (51) Image chip (22) Wire (24) Covering space (253) Cover (27) top surface (311) Wafer Pad (322) Wire (34) Sidewall (351) Adhesive (36) Image Wafer (42) Wire (44) Top Plate (452) Housing (457) First Thread (45 8) Lens (47) Lens (472) Image Wafer (52) 14 200824105 Image Sensing Area (521) Connection (531) Wire (54). Top Plate (552) • 5 Chamber (557) Lens (559) "Sixth Preferred Embodiment • Thin Image Chip Package Structure (60) Carrier (61) ίο Recessed Area (614) Wafer Pad (622) Top Cover (63 2) Cover (65) Top Plate (652) 15 Adhesive (66) Cover (53) Top cover (532) Cover (55) Housing (556) Perforation (554) Adhesive (56) Top surface (611) Image wafer (62) Cover (63) Conductor (64) Viscosity Body (651) perforation (654) 15

Claims (1)

200824105 十、申請專利範園: 1·一種薄型影像晶片封裝結構,包含有: ,一載體; 一影像晶片,係以其一端面連結於該載體上,該影像 晶片之另一端上形成有/影像感測區,並於該影像感測區 5之外周邊上形成有若干之晶片焊墊; °° 一罩體,具有一連接部及一頂罩部,該連接部係連钟 於该景>像晶片上,並位於該影像感測區與該晶片焊墊之 間’使由該連接部加以阻隔於該影像感測區與該晶片焊塾 之間’該頂罩部係連結於該連接部上,並位於該影像感測 10 區之上方; 若干之導線,係以其一端連接於該晶片焊墊上,另_ 端則連接於該載體上,使該影像晶片與該載體間藉由該導 線而電性連通; 一蓋體’係連接於該載體上用以封裝晶片及各導線, 15並具有一頂板,且該頂板形成有一穿孔,使該頂罩部位於 该穿孔中’而與外界相通,且該頂板係可將該導線完全蓋 覆。 2·依據申請專利範圍第1項所述薄型影像晶片封裝結 ΐ中更包含有一黏著物,係設於該罩體之外側與該蓋 體之穿孔間,以黏接該罩體之頂罩部與該蓋體之頂板。 3·依據申請專利範圍第i項所述薄型影像晶片封裝結 其中该載體具有_頂面及一與該頂面相背之底面,該 佈设有呈預定態樣及數量之電路佈線及若干與該電 、4電性相通之電路焊墊;該影像晶片係連結於該頂面 16 20200824105 X. Patent application garden: 1. A thin image chip package structure comprising: a carrier; an image chip connected to the carrier by one end surface thereof, and an image formed on the other end of the image chip a sensing area, and a plurality of wafer pads are formed on the periphery of the image sensing area 5; °° a cover having a connecting portion and a top cover portion, the connecting portion is connected to the scene On the wafer, between the image sensing region and the wafer pad, such that the connection portion is blocked between the image sensing region and the wafer pad. The top portion is coupled to the connection Above the image sensing 10 region; a plurality of wires are connected to the wafer pad with one end thereof, and the other end is connected to the carrier, so that the image chip and the carrier are separated by the a wire is electrically connected; a cover is attached to the carrier for packaging the wafer and the wires, and has a top plate, and the top plate is formed with a through hole so that the top portion is located in the through hole and is external to the outside Interconnected, and the top plate The wire can be completely covered. 2. The thin image chip package package according to claim 1 further includes an adhesive disposed between the outer side of the cover and the perforation of the cover to adhere the cover portion of the cover. With the top plate of the cover. 3. The thin image chip package according to claim i, wherein the carrier has a top surface and a bottom surface opposite to the top surface, the cloth is provided with a predetermined pattern and a number of circuit wirings and a plurality of Electrically and electrically connected circuit pads; the image wafer is coupled to the top surface 16 20 200824105 上,该等導線係電性連接於 4·依財請專利朗第f f路焊墊與該晶片焊墊上。 構,其中該載體具有-頂乐項所述薄型影像晶片封裝結 頂面上凹陷有-凹顧,兮及''與該頂面相背之底面,該 量之電路佈線及若干陷區佈設有呈預定態樣及數 該影像日日日Μ料置於:二 _電性㈣之電路悍墊; 晶片焊塾及電路焊墊i㉘内,該㈣線係電性連接於 構,其圍第1項所述薄型影像晶片封裝結 广亥載粗具有一頂面及—與該頂面相背之底面,該 量之中=有—凹陷區,該71面上佈設有呈财態樣及數 屯路佈線及若干與該電路佈線電性相通之電路焊塾; ΓΓ像晶片係設置於該凹陷區内,該等導線係電性連接於 日日片焊墊及電路焊墊上。 、 15 6.依據申請專利範圍第1項所述薄型影像晶片封裝結 15構,其中該連接部係由塑膠、玻璃、玻璃纖維、金屬 瓷所製成。 ^ 7.依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該連接部内形成一罩設空間,該影像感測區係位 在該罩設空間内。 20 8·依據申請專利範圍第1項所述薄型影像晶片封裝結 構’其中該頂罩部係由透光材質製成。 9·依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該導線係以垂直該載體之方式連接於該載體上, 並以近乎水平之方式與該晶片焊墊速接。 17 200824105 ιο·依據申請專利範圍第i項所述薄型影像晶片封裝結 構,其中該蓋體更設有一側壁,該側壁為一軸向呈透空狀 之形體,其内部形成一蓋設空間,該侧壁係以其一端緣連 接於該載體上,而以另一端緣連接於該頂板上。 5 11.依據申請專利範圍第10項所述薄型影像晶片封裝 結構,其中該侧壁與該頂板係由一體製成。 12. 依據申請專利範圍第10項所述薄型影像晶片封裝 結構,其中該導線係由與載體連接之一端,逐漸地往晶片 …中心之方向呈傾斜k態;該侧壁之内側形 > 成有一容置空 10 間,用以供導線容置。 13. 依據申請專利範圍第12項所述薄型影像晶片封裝 結構,其中形成該容置空間之侧壁其厚度較薄。 1屯依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該連接部與頂罩部係由一體製成。 15 15.依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該蓋體内設有一包覆體,係覆蓋於該影像晶片及 該導線上。 16. 依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該頂板上具有一容置部,該容置部形成有一容室, 20 該容室係與該穿孔連通;該薄型影像晶片封裝結構更包含 有一鏡頭,該鏡頭係設置於該容室中。 17. 依據申請專利範圍第16項所述薄型影像晶片封裝 結構,其中該容室之内侧壁面上形成有一第一螺紋部;該 鏡頭外側形成有一第二螺紋部,該第二螺紋部係與該第一 18 200824105 螺紋部螺接。 18. 依據申請專利範圍第16項所述薄型影像晶片封裝 結構,其中該容室内設有一内螺紋;該鏡頭具有一管體及 若干固設於該管體内之鏡片,該管體外周上設有一外螺 5 紋,係與該内螺紋螺接,使該鏡頭可相對該容室作上、下 之位移。 19. 依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該頂罩部為一鏡片。 20. 依據申請專利範圍第1項所述薄型影像晶片封裝結 1〇 構,更包含有一可撕離性的黏性體,係位於該蓋體與該載 體之間。 21. 依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中該黏性體以多點方式黏貼。 22. 依據申請專利範圍第1項所述薄型影像晶片封裝結 15 構,其中該連接部係藉由一黏膠而連接於該影像晶片上。 23. 依據申請專利範圍第1項所述薄型影像晶片封裝結 構,其中更由一快乾膠黏接於連接部之外側邊及該影像晶 片上,以迅速固定該連接部與該影像晶片之相關位置。 19On 200824105, the wires are electrically connected to the patented metric ff solder pad and the pad. The carrier has a recessed surface on the top surface of the thin image chip package, and a bottom surface opposite to the top surface, the amount of circuit wiring and a plurality of recessed regions are provided The predetermined pattern and the number of the image day and day are placed in: a circuit breaker of the second (electricity) (4); in the wafer soldering pad and the circuit pad i28, the (four) wire is electrically connected to the structure, and the first item is The thin image chip package junction has a top surface and a bottom surface opposite to the top surface, wherein the quantity is a recessed area, and the surface of the 71 surface is provided with a financial state and a plurality of circuit lines. And a plurality of circuit pads electrically connected to the circuit wiring; the imaging chip is disposed in the recessed area, and the wires are electrically connected to the solar pad and the circuit pad. 15. The thin image chip package structure according to claim 1, wherein the connection portion is made of plastic, glass, fiberglass, or metal porcelain. The thin image chip package structure according to claim 1, wherein a cover space is formed in the connection portion, and the image sensing region is located in the cover space. 20 8. The thin image chip package structure according to claim 1, wherein the top cover portion is made of a light transmissive material. 9. The thin image wafer package structure of claim 1, wherein the wire is attached to the carrier in a manner perpendicular to the carrier and is spliced to the wafer pad in a substantially horizontal manner. The invention relates to a thin image chip package structure according to the invention of claim 1, wherein the cover body further comprises a side wall, wherein the side wall is an axially transparent shape, and a cover space is formed inside the cover body. The side wall is attached to the carrier with one end edge and to the top plate with the other end edge. The thin image chip package structure according to claim 10, wherein the side wall and the top plate are integrally formed. 12. The thin image chip package structure according to claim 10, wherein the wire is connected to one end of the carrier and gradually inclined to the center of the wafer; the inner shape of the sidewall is > There is a space of 10 for the conductors to be placed. 13. The thin image chip package structure according to claim 12, wherein the sidewall of the accommodating space is thinner. The thin image chip package structure according to claim 1, wherein the connecting portion and the top cover portion are integrally formed. 15. The thin image chip package structure of claim 1, wherein the cover body is provided with a covering body covering the image wafer and the wire. The thin image chip package structure according to claim 1, wherein the top plate has a receiving portion, the receiving portion is formed with a chamber, and the chamber is connected to the through hole; the thin image wafer The package structure further includes a lens disposed in the chamber. The thin image chip package structure according to claim 16, wherein a first thread portion is formed on an inner wall surface of the chamber; a second thread portion is formed on the outer side of the lens, and the second thread portion is The first 18 200824105 threaded part is screwed. 18. The thin image chip package structure according to claim 16, wherein the chamber is provided with an internal thread; the lens has a tube body and a plurality of lenses fixed in the tube body, and the tube is disposed on the outer circumference of the tube. There is a five-threaded outer thread that is screwed to the internal thread to allow the lens to be displaced upward and downward relative to the chamber. 19. The thin image chip package structure of claim 1, wherein the top cover portion is a lens. 20. The thin image wafer package structure according to claim 1, further comprising a peelable adhesive body between the cover and the carrier. 21. The thin image wafer package structure of claim 1, wherein the adhesive is adhered in a multi-point manner. 22. The thin image chip package structure of claim 1, wherein the connection portion is attached to the image wafer by an adhesive. 23. The thin image chip package structure according to claim 1, wherein a quick-drying adhesive is adhered to the outer side of the connecting portion and the image wafer to quickly fix the connecting portion and the image wafer. Relevant location. 19
TW095143604A 2006-11-24 2006-11-24 Package structure for thin type image chip TW200824105A (en)

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