TW200824064A - Package structure of image chip with accurate position - Google Patents

Package structure of image chip with accurate position Download PDF

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Publication number
TW200824064A
TW200824064A TW095143608A TW95143608A TW200824064A TW 200824064 A TW200824064 A TW 200824064A TW 095143608 A TW095143608 A TW 095143608A TW 95143608 A TW95143608 A TW 95143608A TW 200824064 A TW200824064 A TW 200824064A
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TW
Taiwan
Prior art keywords
image
wafer
limiting
lens
area
Prior art date
Application number
TW095143608A
Other languages
Chinese (zh)
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TWI318446B (en
Inventor
cheng-jiao Wu
Original Assignee
Taiwan Electronic Packaging Co Ltd
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Publication date
Application filed by Taiwan Electronic Packaging Co Ltd filed Critical Taiwan Electronic Packaging Co Ltd
Priority to TW095143608A priority Critical patent/TW200824064A/en
Publication of TW200824064A publication Critical patent/TW200824064A/en
Application granted granted Critical
Publication of TWI318446B publication Critical patent/TWI318446B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention provides a package structure of image chip with accurate position. It includes a carrier body, an image chip, several conducting wires, and a lens module. The bottom surface of image chip is connected with the said carrier body. The top surface of image chip forms an image sensing area. The conducting wires connect electricity between the image chip and the carrier body. The lens module includes a positioning component, a cover body and a lens component. The bottom point of the positioning component is connected with the carrier body. The positioning component has a first restraining position area. The cover body has a supporting section, a second restraining position area, and a lens containing section. The supporting section, the second restraining position area and the lens containing section are formed as a single unit. The bottom fringe of the supporting section is connected with the top surface of the said image chip. The second restraining position area and the lens containing section are formed extending upward from the supporting section. The lens component is contained in the said lens containing section. The first constraining position area of the positioning component contacts the second constraining position area of the said cover body. Therefore, the relative X, Y axial positions of the said cover body can be restricted. The Z axial position between the carrier body and the image chip can also be restricted.

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200824064 九、發明說明： 【發明所屬之技術領域】 本發明係與晶片封裝結構有關，更詳而言之是指一種 定位精確之影像晶片封裝結構。 【先前技術】 按，以習知之積體電路晶片構裝而言，一般係直接將 一晶片貼接於一電路板上，再利用金屬導線焊接至該晶片 之焊墊及電路板上，使該晶片可藉由該金屬導線之連接而 與該電路板呈電性之連通。 田其構裝之晶片為一種攝取影像用之晶片時，該晶片 之頂面乃為-影像感測區，以藉由該影像感測區加以成 像’由於必須於該電路板上設置一位在該影像感測區上方 j鏡#，以透過該鏡頭或鏡#將外部之絲聚焦於 该景>像感測區上加以成傻〆 15 少玛@曰μ 攻像。但，如第一圖所示，一般習知 貼:於:電路二片⑴利用-黏膠(2)而 貼接於該電路_上，❹m之底部制—黏膠⑸ 部’再將-鏡片⑹或鏡頭利用二二亥盍體⑷内 之頂部上，使能由該則⑹將=接該蓋體(4) 片⑴之影像感測區⑻上。，卜#之光源聚焦於該影像晶 精確然方^間之定位必須相當之 上，但由於此1知結構於奸焦於該影像感剛區（8) 具有過多之不可靠因素，、以、兄片（6)至該影像感測區（8)間 ” ^為5亥影像晶片（1)與該電路板 4 20 200824064 (3)間猎由黏膠(2)之貼接，將有可能因黏膠⑺之不平均塗佈 而發生影像晶片⑴與該電路板(3)間之水平及高度有戶^差 異’ t為蓋體(4)與該電路板(3)間藉由黏卵)之貼接，將 =可能因黏，(5)之不平均塗麵發生蓋體⑷與該電路板⑺ “之水平及回度有所差異；其三為該蓋體⑷與該鏡片⑹間 猎+由黏膠⑺之貝占接’將有可能因黏膠⑺之不平均塗佈而發 生蓋體(4)與該鏡#⑹間之水平及高度有所差度。而上述三 種水平度及尚度不精確之因素有可能僅發生其—或其二， 田也有可月匕二種皆同時存在，因此導致鏡片⑹與該晶片 ⑴影像感測區(8)無法位在正確之相對位置上以提供聚焦 ，功效’而必須將鏡片⑹作一額外且巨量(就微小之晶片封 裝結構而f)之位置調整，找正確喊供聚焦之功效，此 不僅將耗費額外之時程及人力加以調整，更將導致成品之 良率不佳。 Μ ▲日另外’當其構裝之晶片為-種攝取影像用之晶片時， 該晶片之頂面乃為-影像感測區，以藉由該影像感測區加 =成像因此该影像感測區須為極度之乾淨，但由於在構 裝之加工過程中，仍必須有焊接導線…等之作業，因此極 易造成影像感測區有污染物濺佈之情形發生，而導致成像 2〇之效果不佳，或更甚有因焊接導線之不慎而誤撞擊影像感 測區之情形，進而造成損壞。 【發明内容】 有鑑於此，本發明之主要目的乃在提供一種定位精確 5 200824064 =像晶片縣結構’錢減少各構件間組料之定位誤 封f 明ί另—目的乃在提供—種定位精確之影像晶片 或損i者’係可避免其影縣測區於施打導料受到污染 旦ιϊϊ ’為達上述目的’本發明所提供—蚊位精確之 =曰=封裝結構，包含有:―載體；—影像晶片，係以盆 10 15 20 億^機舰上，該影像^之職均成有—影 1測區’並賊影職砸之外周邊 片焊墊；一罩體，呈 乂令右十之日日 連蛀於m ，、有—連接°卩鮮部，該連接部係 之片上’並位於該影像感測區與該晶片焊墊 塾^ 錢接部加峨隔於該影像感龍與該晶片焊 =上:頂Γ::連r該連接部上，並— 卜，兑方，右干之導線，係以其一端連接於該晶片焊墊 藉由該導r而==載體二片:，與該载體間 一…二通，一鏡片早兀，包含有-定位件、 上：;d，該定位件係以其底端連接於該載體 -第：…上有—第一限位區’該蓋體具有-支撐部、 驶鏡片容置部’該支撐部、第二限位區及 係為—體成型，該支#部係以其底緣連接於 θθ頂面上，該第二限位區與該鏡片容置部俜自 =擇部:斤，而成，該鏡片組係容置於該鏡片： 且边定位件係以其第一限位區與該蓋體第二限位區 6 200824064 抵接，猎此，可由蚊位件與該蓋體之抵接而 =x'W目對位置，而㈣支撐部無影像晶片 接而蚊該蓋體與該影像晶片間之z_位置。 5【實施方式】 - 為使貝番查委員，能對本發明之特徵及目的有更進一 步之瞭解與認同，兹列舉以下較佳之實施例，並配 說明於後： 請參閱第二及第三圖，係本發明第一較佳實施例所提 10供一種定位精確之影像晶片封裝結構(10)，其主要包含有一 載體(11)、-影像晶片（12)、—罩體(13)、若干之導線(14) 及一鏡片單元(15);其中： 該載體(11)，係可為塑膠、強化塑膠、玻璃纖維、陶瓷… 專材貝所製成之電路板或花架預鑄(printed Circuit 、 15 PCB、PRE_M0LD)，作為該封裝結構(10)與外界電性連接 之橋樑；該載體(11)呈一平板狀，具有一頂面（111)及一與該 頂面（111)相背之底面（112)，該頂面（m)上佈設有呈預定態 木八及數里之笔路佈線（圖中未示）及若干與該電路佈線電性 k 相通之電路焊墊(113)。 —20 θ亥影像晶片（12)，具有一頂面（121)及一與該頂面（121) 相背之底面（122)，其底面（122)係藉由環氧樹脂、矽樹脂、 低溶點之玻璃或雙面膠帶…等黏性材料，而黏著貼附於該 載體（11)之頂面（111)上，該影像晶片（12)之頂面（121)中央位 置處設置有一影像感測區（123)用以成像，並於影像晶片（a) 7 200824064 之頂面（121)上位於該影像感測區（123)之外部周邊處，設置 有若干與該影像晶片（12)呈電性導通之晶片焊墊(124)。< 該罩體(13)，包含有一連接部（131)及一頂罩部（132); 邊連接部（131)於本實施例中為一轴心呈透空狀之環形體， 5係可由塑膠、玻璃、玻璃纖維、金屬或陶瓷…材質所製成， 使其轴心内部形成一罩設空間（133)，該連接部（13丨)係以其 一端緣(底緣)藉由一黏膠（圖中未示）而連接於該影像晶片 (12)頂面之衫像感測區（123)周圍外，且係連接於該影像感 測區（123)與該各晶片焊墊(124)之間，使該影像感測區（123) 1〇位在該罩設空間（133)内，而由該連接部（131)將該影像感測 區（123)之外周邊加以封閉，並使得該晶片焊墊(12句與該影 像感測區（123)得以由該連接部（131)而加以隔開；該頂罩部 (132)於本實施例中為一絕緣之圓盤狀薄板（亦可為矩形狀 薄板）’係可由玻璃等透光材料所製成，該頂罩部（132)係藉 15由一黏著物（圖中未示）而黏接於該連接部（131)之另一端緣 (頂緣)上，使該頂罩部（132)正位於該影像感測區（丨23)之上 方，並藉由與該連接部（131)之連接而距該影像感測區（123) 有一預定之距離，使由該頂罩部（132)將該罩設空間（133)之 上方加以封閉；於本實施例中，該頂罩部（132)之寬度面積 20係相專於该連接部（13丨)之寬度面積，但於實際設計時，該 頂罩部之寬度面積亦可大於該連接部之寬度面積。 該等導線(14)，係由黃金、鋁…等導電金屬材質所製 成，係利用打線技術將該各導線(丨4)分別與該載體(u)之電 路太干墊（113)及该晶片（12)之晶片焊墊（124)電性連接；打線 8 200824064 作業時，該導線(14)首先以垂直該載體(11)電路焊墊(ιΐ3)之 方式與該電路焊塾(133)牢固地銜接（為第一焊接點），再將 導線(14)往上拉伸至晶片（12)頂面（121)之位置時，以近乎水 平之方式延伸至與該晶片焊墊(124)銜接（為第二焊接點）， 5藉此，該晶片（12)上方供導線(14)容置之空間即可加以扁平 化而大幅縮減封裝結構(10)之高度。 該鏡片單元（15)，包含有一定位件（16)、一蓋體（17)及 一鏡片組(18);該定位件（16)為一中空之矩形體(亦可為環形 體），用以覆蓋於該載體（11)之電路焊墊（U3)、該影像晶 ίο片（12)及導線(14)外，係以其底面連接於該載體（11)之頂面 (111)上，且該定位件（16)之頂面外側並形成有一第一限位區 (161) ，該第一限位區（161)為一自該定位件幻之頂面上所 向下凹陷之區域，使該第一限位區（16丨）具有一限位側壁 (162) 及一限位底壁（163)，該限位側壁（162)係垂直於該影像 15晶片（12)之頂面（121)而為一平整面，該限位底壁（163)係垂 直於該限位側壁（162)而與該影像晶片（12)之頂面（121)呈平 行狀態，為一平整面；該蓋體(17)係由一體所製成，具有一 支撐部（171)、一頂板(172)、一鏡片容置部（173)及一第二限 位區（174)，該支撐部（171)於本實施例中為一軸向呈透空狀 2〇之矩形體（亦可為環形體），使其軸向内部形成一蓋設空間， 该支撐部（171)係以其一端緣(底緣)藉由一黏著物（圖中未示） 而連接抵於該影像晶片（12)之頂面（121)上，且係位於該罩 肢(13)之外周圍與該晶片焊墊（124)之間，使該罩體（13)位於 5亥盖設空間内，該頂板(172)於本實施例中為一矩形狀薄板 9 200824064 (亦可為環形狀薄板），該頂板(172)係自該支撐部（171)之頂 緣所水平向外延伸而成，並於該頂板(172)之外周緣向不延 伸形成有一第二限位區（174)，且該第二限位區（174)之底面 係未與該定位件（16)之限位底壁（163)有所接觸，而係由該 5第二限位區（174)之内側壁面（175)與該第一限位區（161)之 限位側壁（162)抵接（亦即該第一限位區（161)與該第二限位 區（174)側面產生抵接，但不宜產生底面抵接，因為本發明在 设计上係利用該支樓部（171)連接抵於該影像晶片（12)之頂 面（121)上，以產生z軸向之精確高度定位），該頂板（172) 1〇中央位置形成有一穿孔(176)，該穿孔（176)之孔徑略大於該 罩體（13)之頂罩部（132)外徑，使該頂罩部（132)正位於該穿 孔（176)中，並由該頂板(172)將該導線(14)完全蓋覆，該鏡 片容置部（173)係於該頂板（172)之穿孔（176)周緣頂面上所 凸伸形成，鏡片容置部（173)内部係呈上下透空而與該穿孔 15 (176)連通；該鏡片組U8)，為一鏡片，係固設於該鏡片容 置部（173)内。 由於本發明之封裝結構(1 〇)於進行打線作業（即將導線 粤晶片焊墊及電路焊墊連接之作業）前，已藉由該罩體（13) 將衫像感測區（123)與晶片焊墊（124)加以阻隔，可避免於打 2〇線作業時有誤觸或污染影像感測區（123)之情事發生。再 者，該罩體(13)之連接部（131)與頂罩部（132)亦可採一體成 幵^所製成，可更加簡化整體組裝之作業。 由於用於容置鏡片組（18)之鏡片容置部（173)，係與該 支撐部（171)—體所製成(可由一不透明之塑膠、玻璃纖維、 10 200824064 金屬、陶竟或透明之玻璃、石英、塑膠材質所一體製成）， 且该支撐部（171)係直接地撐抵於該影像晶片（丨2)之頂面 (121)上，使違鏡片組(18)與該影像感測區（us)間呈直接相 對關係，痛需如習用結構藉由過多之間接關係及黏接構 5件，可使得組裝後之鏡片組(18)位置與該影像感測區（123) 間之位置可相當之精確。況且，由於該支撐部（171)可提供 該鏡片組(18)—軸向之定位(z軸向定位），而該第一限位區 (161)之限位側壁（162)與該第二限位區（174)之内側壁面 (175)間之接觸，則可加以提供該鏡片組（18)另二轴向之定 ίο位(X及Y軸向定位），使鏡片組(18)之三維空間位置皆受限 制，以維組裝時之定位精確。 請芩閱第四及第五圖，係本發明第二較佳實施例所提 供之一種定位精確之影像晶片封裝結構(2〇)，其與上述實施 例相同包含有一載體(21)、一影像晶片（22)、一罩體(23)、 I5若干之導線(24)及一鏡片單元(25)，該鏡片單元(25)同樣具 有一定位件(26)、一蓋體(27)及一鏡片組(28);惟與上述實 施例之主要差異在於： ' 該鏡片單元(25)之蓋體(27)支撐部(271)為多數個圓柱 而同時於其外周面形成了多數第二限位區(274)，係分別位 2〇於該罩體(23)與該晶片焊墊(224)間，而分別以其底端與該 影像晶片（22)頂面(221)連接，該頂板(272)則係由該支撐部 (271)之頂緣水平地往影像晶片（22)中心所延伸而成，使該 頂板(272)中央位置形成有該穿孔(276)，該穿孔(276)之周緣 頂面則向上延伸有該鏡片容置部(273)，該鏡片容置部(273) 200824064 内4係主透空而與該罩體(23)連通，該鏡片容置部(273)内 =面上並形成有-内螺紋；該定位件(26)係以其底緣與該載 體(21)連接’並往上垂直延伸一段距離後再水平向内彎折， 使，定位件(26)之頂面内侧壁上形有該第一限位區（261)， 3該第-F艮位區(261)為多數個位置及形狀分別對應該第二限 位區(274)之凹槽，使該第二限位區(274)(多數圓柱之外周 面）可位於該第一限位區(261)(多數與第二限位區外周面對 形狀對應之凹槽）内，並由該支撐部(271)之第二限位區(274) 與該第一限位區(261)之限位側壁(262)接觸，而能加以提供 10疋位之效果(X、Y軸向之定位）。 該鏡片組(28)具有一管體(281)及若干鏡片（282)，該鏡 片（282)係容置於該管體(281)内，該管體(281)之外周面上形 成有一外螺紋，係藉由該外螺紋與該鏡片容置部(273)之内 螺紋螺接，使能藉由旋轉該管體(281)以帶動該鏡片（282)之 15上、下位移，以利調整鏡片（282)之焦距。 雖本貫施例之鏡片單元構造不同於上述之實施例，但 其同樣能達成本發明之目的。 藉由上述之說明，本發明第一及第二實施例係以容置 鏡片組之鏡片容置部，係與該支撐部一體所製成，且該支 標。卩係直接地樓抵於該影像晶片之頂面上，達成Z軸向之 定位，並藉由該第一限位區與該第二限位區之側面抵接， 則可加以提供該鏡片組X及γ轴向定位，使鏡片組之三維 空間位置皆受限制，以維組裝時之定位精確。 再進一步說明的是，本發明第一及第二限位區係用以 12 200824064 界定該鏡片組x及γ軸向定位，因此並不限制於上述實施 例中之形狀，且其分別所處之位置亦不限制，例如本發明 之第一限制區係形成於定位件上，但亦不排除直接設計於 晶片上，因此，本發明之權利保護，應以申請專利範圍為 5 依據，而非僅限本發明實施例之說明。 13 200824064 【圖式簡單說明】 第一圖係一種習知影像晶片之封裝結構剖視示意圖。 第二圖係本發明第一較佳實施例之剖視示意圖。 第三圖係第二圖所示較佳實施例沿3-3線之剖視示意 5圖。 第四圖係本發明第二較佳實施例之剖視示意圖。 第五圖係第四圖所示較佳實施例沿5-5線之剖視示意 10 【主要元件符號說明】 15 Γ'習用」 影像晶片（1) 電路板(3) 黏膠(5) 黏膠⑺ 「本發明」 「第一較佳實施例」 定位精確之影像晶片封裝結構(10) 載體(11) 黏膠(2) 蓋體(4)鏡片⑹ 影像感測區(8) 頂面（111) 底面（112) 影像晶片（12) 底面（122) 晶片焊墊(124) 連接部（131) 電路焊墊(113) 頂面（121) 影像感測區（123) 罩體(13) 頂罩部（132) 14 • 20 200824064 罩設空間（133) 導線(14) 鏡片單元(15) 定位件（16) 第一限位區（161) 限位側壁（162) 限位底壁（163) 蓋體(17) 5 支撐部（171) 頂板(172) 第二限位區（174) 内壁侧面（175) 穿孔(176) 鏡片組(18) 「第二較佳實施例」 定位精確之影像晶片封裝結構(20) 鏡片容置部（173) 載體(21) 影像晶片（22) 頂面(221) 晶片焊墊(224) 罩體(23) 導線(24) 鏡片單元(25) 定位件(26) 15 第一限位區(261) 限位側壁(262) 蓋體(27) 支撐部(271) 第二限位區(274) 頂板(272) 穿孔(276) 鏡片容置部(273) 鏡片組(28) 2〇 鏡片（282) 管體(281) 15200824064 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure, and more particularly to a positionally accurate image chip package structure. [Prior Art] In the conventional integrated circuit wafer assembly, a wafer is directly attached to a circuit board, and then soldered to the pad and the circuit board of the wafer by a metal wire. The wafer can be in electrical communication with the circuit board by the connection of the metal wires. When the wafer is a wafer for capturing images, the top surface of the wafer is an image sensing area to be imaged by the image sensing area because it is necessary to set a bit on the board. The j-mirror # above the image sensing area is used to focus the outer wire through the lens or the mirror # to focus on the sensing area to form a silly 15 Shao Ma @曰μ attack image. However, as shown in the first figure, the general conventional stickers: in: two pieces of circuit (1) with - adhesive (2) attached to the circuit _, the bottom of the ❹m - viscose (5) part will be - lens (6) Or the lens is used on the top of the body (2), so that the (6) will be connected to the image sensing area (8) of the cover (4) piece (1). The light source of the Bu is focused on the position of the image crystal, and the positioning must be quite above. However, due to the fact that the structure is too unreliable in the image sensing area (8), From the film (6) to the image sensing area (8) ^ ^ 5 image wafer (1) and the circuit board 4 20 200824064 (3) between the patch by the adhesive (2), it is possible Due to the uneven coating of the adhesive (7), the level and height of the image wafer (1) and the circuit board (3) are different. The difference between the cover (4) and the circuit board (3) is caused by the sticky egg. ), the connection may be due to stickiness, (5) the uneven coating surface of the cover (4) and the circuit board (7) "the level and the difference are different; the third is between the cover (4) and the lens (6) Hunting + by the adhesive (7) shells will be likely due to the uneven coating of the adhesive (7) and the difference between the level and height of the cover (4) and the mirror # (6). However, the above three levels of inaccuracy may only occur - or two, and there may be both moons and moons, so that the lens (6) and the wafer (1) image sensing area (8) are not available. In the correct relative position to provide focus, efficiency, and the lens (6) must be adjusted for an extra and huge amount (in the case of a tiny chip package structure and f), to find the correct call for focus, this will not only cost extra The timing and manpower will be adjusted, which will lead to poor yield of finished products. ▲ ▲In addition, when the wafer to be mounted is a wafer for image capturing, the top surface of the wafer is an image sensing area, and the image sensing area is added with the image sensing The area must be extremely clean, but because of the work of soldering wires, etc. during the processing of the structure, it is easy to cause the contamination of the image sensing area to occur, resulting in imaging. The effect is not good, or even the accidental impact of the welding wire on the image sensing area, resulting in damage. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a positioning accuracy 5 200824064 = like a wafer county structure 'money to reduce the positioning of the components between the components of the mis-sealing, the other is to provide - accurate positioning The image wafer or the damager's system can avoid the contamination of the shadowing area in the shadowing area. For the above purpose, the present invention provides the mosquito net accurate = 曰 = package structure, including: Carrier; image wafer, with a basin of 10 15 2 billion ^ on the ship, the image of the ^ ^ has a - shadow 1 test area and the thief shadows outside the peripheral film pad; a cover, a 乂Let the right day of the tenth day be connected to the m, and the connection is connected to the fresh part, and the connection part is on the slice and is located in the image sensing area and the wafer pad 塾^ the money joint is interspersed with the image. Sense dragon and the wafer soldering = top: top Γ:: 连 r the connection part, and - 卜, 兑, right trunk wire, with one end connected to the wafer pad by the guide r == Two pieces of carrier: one to two with the carrier, one lens early, including - positioning member, upper:; d, the positioning The bottom end is connected to the carrier - the first: - the first limit area - the cover has a - support portion, the lens receiving portion 'the support portion, the second limit portion and the body Forming, the branch portion is connected to the top surface of θθ by a bottom edge thereof, and the second limiting portion is formed by the lens receiving portion from the knuckle portion: the lens group is accommodated in the lens The side positioning member abuts the second limiting area 6 200824064 of the cover body, and the position of the mosquito bit member and the cover body can be met by the position of the mosquito seat member. And (4) the support portion has no image wafer and the z_ position between the cover and the image wafer. 5 [Embodiment] - In order to make the members and objectives of the present invention more fully understood and recognized, the following preferred embodiments are listed and described below: Please refer to the second and third figures. According to a first preferred embodiment of the present invention, a video chip package structure (10) for positioning is provided, which mainly includes a carrier (11), an image chip (12), a cover (13), and a plurality of a wire (14) and a lens unit (15); wherein: the carrier (11) is a plastic, reinforced plastic, fiberglass, ceramic... circuit board or flower frame made of special material (printed circuit) , 15 PCB, PRE_M0LD), as a bridge connecting the package structure (10) to the outside; the carrier (11) has a flat shape, has a top surface (111) and a back surface (111) a bottom surface (112), the top surface (m) is provided with a strip circuit (not shown) in a predetermined state and a plurality of miles, and a plurality of circuit pads (113) communicating with the circuit wiring electrical k . The 20 θ hai image wafer (12) has a top surface (121) and a bottom surface (122) opposite the top surface (121), and the bottom surface (122) is made of epoxy resin, enamel resin, low a viscous material, such as a glass or a double-sided tape, adhered to the top surface (111) of the carrier (11), and an image is disposed at a central position of the top surface (121) of the image wafer (12). The sensing area (123) is used for imaging, and is located at the outer periphery of the image sensing area (123) on the top surface (121) of the image wafer (a) 7 200824064, and is provided with a plurality of image wafers (12) A wafer pad (124) that is electrically conductive. < The cover body (13) includes a connecting portion (131) and a top cover portion (132); the side connecting portion (131) is a ring-shaped annular body in the present embodiment, the 5 series It can be made of plastic, glass, fiberglass, metal or ceramic material to form a cover space (133) inside the axis, and the connection portion (13丨) is formed by one end edge (bottom edge) An adhesive (not shown) is connected around the top of the image sensing area (123) of the top surface of the image chip (12), and is connected to the image sensing area (123) and the wafer pads ( Between 124), the image sensing area (123) 1 is clamped in the cover space (133), and the periphery of the image sensing area (123) is closed by the connecting portion (131). And the wafer pad (12 sentences and the image sensing region (123) are separated by the connecting portion (131); the top cover portion (132) is an insulating disk in this embodiment. The thin plate (which may also be a rectangular thin plate) is made of a light transmissive material such as glass, and the top cover portion (132) is adhered to the connecting portion by an adhesive (not shown). ) The other edge (top edge) is such that the top cover portion (132) is located above the image sensing region (丨23) and is connected to the image sensing region by being connected to the connecting portion (131). (123) having a predetermined distance such that the top cover portion (132) closes the upper portion of the cover space (133); in the embodiment, the width of the top cover portion (132) is 20 The width of the connecting portion (13丨), but in actual design, the width of the top portion can also be greater than the width of the connecting portion. The wires (14) are made of gold, aluminum, etc. The metal material is made by electrically connecting the wires (丨4) to the circuit dry pad (113) of the carrier (u) and the die pad (124) of the wafer (12) by wire bonding technology; When the wire 8 200824064 is operated, the wire (14) is first firmly connected to the circuit pad (133) in a manner perpendicular to the carrier (11) circuit pad (ι), and then the wire (the first solder joint), and then the wire ( 14) extending upward to the position of the top surface (121) of the wafer (12), extending in a nearly horizontal manner to interface with the wafer pad (124) (for 2, the soldering point), 5, the space above the wafer (12) for the wire (14) can be flattened to greatly reduce the height of the package structure (10). The lens unit (15), including a positioning a member (16), a cover (17) and a lens group (18); the positioning member (16) is a hollow rectangular body (also an annular body) for covering the circuit of the carrier (11) The pad (U3), the image chip (12) and the wire (14) are connected to the top surface (111) of the carrier (11) with the bottom surface thereof, and the top surface of the positioning member (16) A first limiting area (161) is formed on the outer side, and the first limiting area (161) is an area recessed downward from the top surface of the positioning part of the positioning member, so that the first limiting area (16丨) Having a limiting sidewall (162) and a limiting bottom wall (163), the limiting sidewall (162) is perpendicular to the top surface (121) of the image 15 wafer (12) and is a flat surface. The bottom wall (163) is perpendicular to the limiting sidewall (162) and parallel to the top surface (121) of the image wafer (12), and is a flat surface; the cover (17) is made of one body. Cheng, with a a portion (171), a top plate (172), a lens receiving portion (173), and a second limiting portion (174). The supporting portion (171) is an axially transparent shape in the embodiment. The rectangular body (which may also be a ring body) has a cover space formed in the axial direction, and the support portion (171) is terminated by an adhesive (not shown) at one end edge (bottom edge) thereof. Connected to the top surface (121) of the image wafer (12), and between the periphery of the cover body (13) and the wafer pad (124), so that the cover (13) is located at 5 In the cover space, the top plate (172) is a rectangular thin plate 9 200824064 (also a ring-shaped thin plate) in the embodiment, and the top plate (172) is horizontally from the top edge of the support portion (171). The outer limiting portion is formed, and a second limiting region (174) is formed on the outer periphery of the top plate (172), and the bottom surface of the second limiting portion (174) is not associated with the positioning member (16). The limiting bottom wall (163) is in contact with the inner side wall surface (175) of the 5 second limiting area (174) and the limiting side wall (162) of the first limiting area (161). (that is, the first limit zone ( 161) abutting the side of the second limiting area (174), but it is not suitable to generate a bottom surface abutment, because the present invention is designed to be connected to the top of the image wafer (12) by using the branch portion (171). The surface (121) is positioned to produce a precise height of the z-axis. The top plate (172) has a through hole (176) formed at a central position thereof. The hole (176) has a hole slightly larger than the top of the cover (13). The outer diameter of the cover portion (132) is such that the top cover portion (132) is located in the through hole (176), and the wire (14) is completely covered by the top plate (172), and the lens receiving portion (173) Attached to the top surface of the perforation (176) of the top plate (172), the lens receiving portion (173) is vertically permeable to the perforation 15 (176); the lens group U8), A lens is fixed in the lens receiving portion (173). Since the package structure (1) of the present invention performs the wire bonding operation (ie, the operation of connecting the wire bonding pad and the circuit pad), the shirt image sensing area (123) is used by the cover body (13). The wafer pad (124) is blocked to avoid accidental contact or contamination of the image sensing area (123) during the 2-wire operation. Further, the connecting portion (131) of the cover (13) and the top cover portion (132) can be integrally formed, which simplifies the overall assembly work. Since the lens receiving portion (173) for accommodating the lens group (18) is made of the supporting portion (171) (can be made of an opaque plastic, fiberglass, 10 200824064 metal, ceramic or transparent) The glass, quartz, and plastic materials are integrally formed, and the support portion (171) is directly supported on the top surface (121) of the image wafer (丨2), so that the lens group (18) is There is a direct relative relationship between the image sensing areas (us), and the pain needs to be as many as the conventional structure, and the position of the assembled lens group (18) and the image sensing area (123) The position between the two can be quite accurate. Moreover, since the support portion (171) can provide the lens group (18) - axial positioning (z axial positioning), the first limiting portion (161) of the limiting sidewall (162) and the second The contact between the inner side wall surfaces (175) of the limiting area (174) can be provided with the other axial direction of the lens group (18) (X and Y axial positioning), so that the lens group (18) The position of the three-dimensional space is limited, and the positioning is accurate when the dimension is assembled. Please refer to the fourth and fifth figures, which are a precise positioning image chip package structure (2) provided by the second preferred embodiment of the present invention, which comprises a carrier (21) and an image as in the above embodiment. a wafer (22), a cover (23), a plurality of wires (24) of I5, and a lens unit (25). The lens unit (25) also has a positioning member (26), a cover (27) and a The lens group (28); the main difference from the above embodiment is that: 'The cover (27) of the lens unit (25) has a plurality of cylinders and a plurality of second limits on the outer peripheral surface thereof. The bit region (274) is respectively disposed between the cover body (23) and the die pad (224), and is respectively connected to the top surface (221) of the image chip (22) by a bottom end thereof, the top plate (272) extending from the top edge of the support portion (271) horizontally toward the center of the image wafer (22) such that the perforation (276) is formed at a central position of the top plate (272), the perforation (276) The lens receiving portion (273) extends upwardly from the top surface of the periphery, and the lens receiving portion (273) 200824064 communicates with the cover body (23) through the main system, and the lens receiving portion (273) Inside = The upper part is formed with an internal thread; the positioning member (26) is connected with the carrier (21) with its bottom edge and extends vertically upward for a distance, and then is bent horizontally inward, so that the positioning member (26) The first inner limiting surface is formed with the first limiting area (261), and the first -F clamping area (261) has a plurality of positions and shapes respectively corresponding to the grooves of the second limiting area (274), so that The second limiting area (274) (most of the outer peripheral surface of the cylinder) may be located in the first limiting area (261) (most of the grooves corresponding to the outer peripheral surface of the second limiting area) and supported by the support The second limiting area (274) of the portion (271) is in contact with the limiting side wall (262) of the first limiting area (261), and can provide a 10-inch effect (position of the X and Y axes) . The lens group (28) has a tube body (281) and a plurality of lenses (282). The lens unit (282) is housed in the tube body (281), and an outer surface is formed on the outer surface of the tube body (281). The thread is screwed to the internal thread of the lens receiving portion (273) by the external thread to enable the upper and lower displacement of the lens (282) 15 by rotating the tube body (281). Adjust the focal length of the lens (282). Although the lens unit configuration of the present embodiment is different from the above-described embodiment, it can also achieve the object of the present invention. According to the above description, the first and second embodiments of the present invention are for accommodating the lens accommodating portion of the lens group, which is integrally formed with the support portion, and the support. The 卩 is directly connected to the top surface of the image wafer to achieve the Z-axis positioning, and the lens group can be provided by the first limiting area contacting the side of the second limiting area The axial positioning of X and γ allows the three-dimensional spatial position of the lens group to be limited, so that the positioning during the assembly is accurate. It is further illustrated that the first and second limiting regions of the present invention are used to define the axial positioning of the lens group x and γ for 12 200824064, and thus are not limited to the shapes in the above embodiments, and are respectively located The position is not limited. For example, the first restricted area of the present invention is formed on the positioning member, but it is not excluded to be directly designed on the wafer. Therefore, the protection of the present invention should be based on the patent scope of 5, rather than only The description of the embodiments of the present invention is limited. 13 200824064 [Simple description of the drawings] The first figure is a schematic cross-sectional view of a package structure of a conventional image wafer. The second drawing is a schematic cross-sectional view of a first preferred embodiment of the present invention. The third drawing is a cross-sectional view of the preferred embodiment shown in the second figure along line 3-3. Figure 4 is a schematic cross-sectional view showing a second preferred embodiment of the present invention. Figure 5 is a cross-sectional view of the preferred embodiment shown in Figure 4 along line 5-5. [Main component symbol description] 15 Γ 'Utility' Image chip (1) Circuit board (3) Adhesive (5) Adhesive Glue (7) "Invention" "First Preferred Embodiment" Positioning Accurate Image Chip Package Structure (10) Carrier (11) Adhesive (2) Cover (4) Lens (6) Image Sensing Area (8) Top Surface ( 111) Bottom surface (112) Image wafer (12) Bottom surface (122) Wafer pad (124) Connection (131) Circuit pad (113) Top surface (121) Image sensing area (123) Cover (13) Top Cover (132) 14 • 20 200824064 Covering space (133) Conductor (14) Lens unit (15) Positioning member (16) First limit area (161) Limit side wall (162) Limit bottom wall (163) Cover (17) 5 Support (171) Top plate (172) Second limit area (174) Inner wall side (175) Perforation (176) Lens group (18) "Second preferred embodiment" Positioning accurate image wafer Package Structure (20) Lens Housing (173) Carrier (21) Image Wafer (22) Top Surface (221) Wafer Pad (224) Cover (23) Wire (24) Lens Unit (25) Positioning (26 ) 15 First Limit Zone (261) Limit Side wall (262) Cover (27) Support (271) Second limit (274) Top plate (272) Perforation (276) Lens housing (273) Lens group (28) 2" Lens (282) Tube (281) 15

Claims (1)

200824064 申請專利範圍 種定位精確之影像晶片封裝結構，包含有： 1.- 一載 -影像；，似其-底面連結於輯體上，該影像 ==頂面上形成有-影賴麻，並於鄉像感測區之 外周邊上形成有若干之晶片焊墊； 山若干之導線，係以其一端連接於該晶片焊墊上，另一 、!連接於.域體上，使$影像晶片與該載體間藉由該 猓而電性連通； ―一鏡片單it，包含有—蓋體及—鏡片組，該蓋體具有 :支撐部及-鏡片容置部，該支撐部及該鏡片容置部係為 :體成型，該支撐耗以γ_定位方式並將其底緣 妾於该影像晶片之頂面上，該鏡片容置部係自該支撐部 所向上延伸而成，該鏡片組係容置於該鏡片容置部内；藉 15 20 可限疋垓盍體之X、γ軸向相對位置，而由該支撐部 與該影像晶片之連接而限定該蓋體與該影像晶片間之Ζ軸 向位置。 、壯2·依據申請專利範圍第丨項所述定位精確之影像晶片 封f結構，其中該鏡片單元更包含有一體成型之定位件， 邊，位件為一中空體，用以覆蓋該載體之電路焊墊、該影 像，片及導線，該定位件底面連接於該載體之頂面上，且 該疋位件之頂面外側並形成有一第一限位區，且該蓋體具 有一第二限位區，該第一限位區與該第二限位區產生側面 抵接以產生X及γ軸向定位方式。 3·依據申請專利範圍第2項所述定位精確之影像晶片 16 200824064 封裝結構，其中該第一限位區具有一限位側壁及一限位底 壁，該限位側壁係垂直於該影像晶片之頂面而為一平整 面’該限位底壁係垂直於該限位側壁而與該影像晶片之頂 面壬平行狀悲而為一平整面；該蓋體更設有一頂板，該丁頁 5板係自該支撐部之頂緣所水平向外延伸而成，並於該頂板 之外周緣向下延伸形成有該第二限位區，且該頂板之底面 係未與該定位件之限位底壁有所接觸，而係由該第二限位 區之内側壁面與該第一限位區之限位側壁抵接。 4·依據申請專利範圍第2項所述定位精確之影像晶片 1〇封裝結構’其中該第二限位區係形成於該支撐部上為多數 個圓柱外周面；該第一限位區為多數個位置及形狀分別對 應該第二限位區之凹槽，使該第二限位區可位於該第一限 位區内，並由該第二限位區之外側壁面與該第一限位區之 限位側壁接觸，而能加以提供X、Y軸向之定位效果。 15 5·依據申請專利範圍第1項所述定位精確之影像晶片 封裝結構，其中晶片設有一第一限位區，且該蓋體具有一 第一限位區，該第一限位區與該第二限位區產生側面抵接 以產生X及Υ軸向定位方式。 . 6·依據申請專利範圍第1項所述定位精確之影像晶片 • 20封裝結構，其中更包含有一罩體，具有一連接部及一頂罩 部，該連接部係連結於該影像晶片上，並位於該影像感測 區與該晶片焊墊之間，使由該連换部加以阻隔於該影像感 測區與該晶片焊墊之間，該頂罩部係連結於該連接部上， 係可由玻璃等透光材料所製成。 17 200824064 7·依據申請專利範圍第6 封裝結構’其中該頂罩部之寬 寬度面積。 項所述定位精確之影像晶片 X面^係相等於該連接部之 8·依據申請專利範圍第6 封裝結構’其中該頂罩部之寬 面積。 員所述疋位精確之影像晶片 度面積大於該連接部之寬度 •,甲請專利· $ G J:轉述定位精確之影 封裝結構，其中該芸體中本付罢/ 曰曰片 一 、甲^皿虹中央位置形成有一穿孔，該穿$丨夕 孔徑略大輯鮮部外徑，使_罩部正㈣該穿孔中。 脖1〇·依據申請專利範圍第1項所述定位精確之影像晶片 封裝結構，其中該蓋體為由不透明之塑膠、玻璃纖維、金 屬、陶瓷或透明之玻璃、石英、塑膠材質所一體製成。土 11·依據申請專利範圍第1項所述定位精確之影像晶片 封裝結構’其中該鏡片容置部内壁面上形成有一内螺紋； is該鏡片組具有一管體及若干鏡片，該鏡片係容置於該管體 内，泫管體之外周面上形成有一外螺紋，係藉由該外螺紋 與該鏡片容置部之内螺紋螺接，使能藉由旋轉該管體以帶 動該鏡片之上、下位移。 12·依據申請專利範圍第丨項所述定位精確之影像晶片 20封裝結構，其中該導線係以垂直該載體之方式連接於該與 该載體上’並以近乎水平之方式與該晶片焊塾連接。 13·—種定位精確之影像晶片封裝結構，包含有： 一載體； 一影像晶片，係以其一底面連結於該載體上’該影像 18 200824064 曰曰片之頂面上形成有，影像感咖，並於該影像 外周邊上形成有若子之晶片焊墊; 心、區之 i -罩體，具有二連接部及1罩部，該連接部 於该影像晶片上’難於該影像感·與該晶片焊塾^ 間，使由該連接部沪以阻隔於該影像感測區與該晶片焊墊 之間，該頂罩部係連結於該連接部上，並位於該影像感測 區之上方； 若干之導線，.以其一端連接於該晶片焊墊上，另一 端則連接於該載體上’使該影像晶片與該載體間藉由該導 10線而電性連通。 19200824064 Patent application for accurate positioning of the image chip package structure, comprising: 1.- a load-image; as if the bottom surface is connected to the set body, the image == the top surface is formed with a shadow, and A plurality of wafer pads are formed on the periphery of the sensing area of the township; the wires of the mountain are connected to the wafer pad by one end thereof, and the other is connected to the domain body to make the image wafer and The carrier is electrically connected by the cymbal; a lens single ITE includes a cover body and a lens group, the cover body has a support portion and a lens accommodating portion, and the support portion and the lens accommodating portion The part is: body forming, the support is γ-positioned and the bottom edge is placed on the top surface of the image chip, and the lens receiving portion is extended upward from the support portion, the lens group is The lens is placed in the lens receiving portion; the relative position of the X and γ of the body can be limited by 15 20 , and the connection between the cover and the image wafer is defined by the connection of the supporting portion and the image chip. Axial position. According to the scope of the patent application, the precise positioning of the image wafer package f structure, wherein the lens unit further comprises an integrally formed positioning member, and the edge member is a hollow body for covering the carrier. a circuit pad, the image, a sheet and a wire, the bottom surface of the positioning member is connected to the top surface of the carrier, and a first limiting area is formed outside the top surface of the clamping member, and the cover body has a second The limiting area, the first limiting area and the second limiting area are laterally abutted to generate X and γ axial positioning modes. 3. According to the scope of claim 2, the accurate positioning of the image wafer 16 200824064 package structure, wherein the first limiting area has a limiting sidewall and a limiting bottom wall, the limiting sidewall is perpendicular to the image wafer The top surface is a flat surface. The bottom wall of the limiting portion is perpendicular to the limiting sidewall and is parallel with the top surface of the image wafer. The lid is further provided with a top plate. The fifth plate is formed by extending horizontally outward from the top edge of the support portion, and the second limiting portion is formed to extend downwardly from the outer periphery of the top plate, and the bottom surface of the top plate is not limited by the positioning member. The bottom wall of the bit is in contact with the inner side wall surface of the second limiting area and the limiting side wall of the first limiting area. 4, according to the scope of claim 2, the accurate positioning of the image wafer 1 〇 package structure 'where the second limiting area is formed on the support portion is a plurality of cylindrical outer peripheral surface; the first limiting area is a majority Positions and shapes respectively corresponding to the grooves of the second limiting area, such that the second limiting area can be located in the first limiting area, and the outer limiting side of the second limiting area and the first limiting position The limit of the side wall of the zone is contacted, and the positioning effect of the X and Y axes can be provided. 15 5. The accurate positioning of the image chip package structure according to the first aspect of the patent application, wherein the wafer is provided with a first limiting area, and the cover body has a first limiting area, the first limiting area and the The second limiting zone creates a side abutment to create an X and Υ axial positioning. 6. The image processing chip according to the first aspect of the patent application, wherein the image package further comprises a cover having a connecting portion and a top cover portion, the connecting portion being coupled to the image wafer. And being disposed between the image sensing area and the die pad, so that the connecting portion is blocked between the image sensing area and the die pad, and the top cover portion is coupled to the connecting portion. It can be made of a light-transmitting material such as glass. 17 200824064 7. The wide package area of the top cover portion according to the scope of the patent application. The X-faced image of the image-preferred image is equivalent to the joint portion. The width of the top cover portion is according to the sixth package structure of the patent application. The accurate image area of the image is larger than the width of the connection part. • A patent, $ GJ: Description of the positioning of the precise shadow package structure, in which the body of the body is paid / 曰曰片一,甲^ The central position of the dish is formed with a perforation, which is slightly larger than the outer diameter of the fresh part, so that the hood portion is positively (four) in the perforation. 〇1〇·According to the patented scope item 1, the accurate image chip package structure, wherein the cover body is made of opaque plastic, glass fiber, metal, ceramic or transparent glass, quartz, plastic material. . The invention relates to an image-accurate package structure according to the first aspect of the patent application, wherein an inner thread is formed on an inner wall surface of the lens receiving portion; the lens group has a tube body and a plurality of lenses, and the lens is received In the tube body, an external thread is formed on the outer peripheral surface of the fistula body, and the external thread is screwed with the internal thread of the lens receiving portion to enable the lens to be driven by rotating the tube body. Lower displacement. 12. Locating an accurate image wafer 20 package structure according to the scope of the application of the patent application, wherein the wire is connected to the carrier in a manner perpendicular to the carrier and is connected to the wafer solder joint in a nearly horizontal manner . 13·--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- And forming a wafer pad on the outer periphery of the image; the i-cover of the core and the area has two connecting portions and a cover portion, and the connecting portion is difficult to image on the image wafer. The soldering pad is disposed between the image sensing region and the die pad, and the cap portion is coupled to the connecting portion and located above the image sensing region; A plurality of wires are connected to the wafer pad at one end and connected to the carrier at the other end to electrically connect the image wafer and the carrier through the wire 10. 19
TW095143608A 2006-11-24 2006-11-24 Package structure of image chip with accurate position TW200824064A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562220B (en) * 2014-05-22 2016-12-11 Xintec Inc Manufacturing method of semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562220B (en) * 2014-05-22 2016-12-11 Xintec Inc Manufacturing method of semiconductor structure

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