200822124 九、發明說明： 【發明所屬之技術領域】 本發明係關於用於按一方式管理儲存裝置内之資料儲存 及抹除的裝置，以便在消除較不關鍵資料前消除較關鍵資 料。 【先前技術】 4除儲存裝置内t資料的需要在電腦工程技術中係熟知 的，且一般取決於兩種替代需要：200822124 IX. INSTRUCTIONS: [Technical Field of the Invention] The present invention relates to a device for managing data storage and erasing in a storage device in a manner to eliminate more critical information before eliminating less critical data. [Prior Art] 4 The need to store t-data in storage devices is well known in computer engineering and generally depends on two alternative needs:
(1) 用於新資料之乾淨空間的需要；以及 (2) 破壞用於具有安全區域之儲存裝置的機密資訊之需 要0 雖然第一種原因不且腎抬Μ 雄 « 八緊迫，第二種原因在關鍵情況中 至關重要。消除資料之決i盥啟左 成朿興儲存裝置控制遺失間的，，時 間視窗”可能很短。通常，可 j用於消除儲存裝置之時間比 整個儲存裝置之完全消除所需卑 叮而日等間更短。不幸的是，先前 技術未教導用於組織消除裎床 - 于柱序之方法，以便在消除較不關 鍵資料前消除較關鍵資料。 需要用於消除之裝置，當需要關鍵消除時，首先 關鍵資料。此-優Μ除程序將在時„ 供 佳選擇解決方案。 Τ权t、耳 【發明内容】 本發明之目的係提供用 料儲存及抹除的裝置，以 關鍵資料。 於按一#式管理儲存裝置内之資 便在消除較不關鍵資料前消除較 124523.doc 200822124 /1青楚起見，以下若干術語係明確定義供本文使用。術 ^ 使用之！語，，消除程序，，指用以使區塊内容無用(1) the need for clean spaces for new materials; and (2) the need to destroy confidential information for storage devices with safe areas. 0 The first reason is not that the kidneys are squatting. The reason is crucial in critical situations. The decision to eliminate the data is not possible. The time window may be very short. Usually, the time required to eliminate the storage device is more than the total elimination of the entire storage device. The space is shorter. Unfortunately, the prior art does not teach methods for organizing the elimination of the trampoline-column sequence to eliminate more critical data before eliminating less critical data. Devices needed for elimination, when critical elimination is required When, first of all, the key information. This - excellent program will be available at the time of the choice of solutions. SUMMARY OF THE INVENTION The object of the present invention is to provide a means for storing and erasing materials, with key information. The elimination of less-critical data before the elimination of the less critical data is based on the fact that the following terms are clearly defined for use herein. Surgery ^ Use it! Language, elimination procedure, means to make the block content useless
V 子㈣其係猎由·⑴將區塊所有單元設定為相同邏 輯值，或⑺隨機化區塊所有單元之内容。本文所使用之術 語”優。先消除"指依據消除優先權協定消除記憶體之部分的 省除知序。本文所使用之術語"區塊”指快閃記憶體儲存裝 置之實體部分。本文所使用之術語，，清潔消除"指用以破壞 數位記憶體内容之消除程序，以便無法藉由任何法醫方式 還原内容。此清潔消除係相對於普通消除程序，其使内容 無法用於普通讀取命令，但不會防止先進技術方式之還 原。本文所使用之術語”快閃單元"指快閃記憶體裝置内快 閃記憶體之部分。 本發明適用於單層單元（SLC)快閃記憶體與多層單元 (MLC)快閃記憶體。儘管後面的說明主要集中於單 儿，但熟習此項技術者會明白本發明在MLC單元（以及其 他一般非揮發性儲存裝置）中的應用方式。本文中所使用 的術語，，抹除”及”寫入”表示設定一記憶體單元之臨界電 壓’其中針對SLC單it，抹除通常將電壓設定為對應於邏 輯值一’而寫入通常將電壓設定為對應於邏輯值零。術語 寫入與程式化”在本文中可互換使用。本發明特別可適 用於NAND型快閃記憶體，其係以一次一頁面之方式來讀 取並程式化。 表1顯示本發明之三項替代具體實施例。 124523.doc 200822124V sub (4) is based on (1) setting all the blocks of the block to the same logical value, or (7) randomizing the contents of all the blocks. The term "excellent" is used herein to mean the elimination of memory from the portion of memory that is eliminated by the prioritization agreement. The term "block" as used herein refers to the physical portion of the flash memory storage device. The term "cleaning elimination" as used herein refers to the elimination procedure used to destroy digital memory content so that it cannot be restored by any forensic method. This cleaning is eliminated from the normal elimination procedure, which makes the content unusable for normal read commands, but does not prevent the restoration of advanced technology. The term "flash unit" as used herein refers to a portion of a flash memory within a flash memory device. The invention is applicable to single layer unit (SLC) flash memory and multi-level cell (MLC) flash memory. Although the following description focuses primarily on a single child, those skilled in the art will appreciate the manner in which the present invention can be used in MLC units (and other general non-volatile storage devices). The terminology used herein, erases and "Write" means setting a threshold voltage of a memory cell 'where a single it for SLC, the erase typically sets the voltage to correspond to a logic value of one' and the write typically sets the voltage to correspond to a logic value of zero. The term "writing and stylization" is used interchangeably herein. The invention is particularly applicable to NAND-type flash memory, which is read and programmed one page at a time. Table 1 shows three items of the present invention. Instead of the specific embodiment. 124523.doc 200822124
具體 實施 例 第一快 閃單元 其他快 閃單元 1 任意 任意 P 斤有高消除 優先權位置 依據曰誌 寫入時最簡單的區 塊配置 2 規定 規定 N/A ，據規定 最有效的緊急消除 3 任思 __ 對第一快閃 j元對準 僅第一快閃 單元 依據日誌 具體實施例1與2之 間的最佳化性能 —------ 表ι·本發明之三項替代具體實施例。 本發明之較佳具體實施例中，以不對寫入配置規定任何 約束的任意方式將資料儲存於快閃記憶體中，如表1、具 體實施例1所示，如下所述。相&，記錄包含關鍵資料的 寫入區塊的位置，且依據該等記錄執行消除。 +赞明之另一較佳 h、 /、只W π , ，Μ碉际、向凋除優先權 貧料之最快消除的方式將資料儲存於快閃單元内，如表 1、具體實施例2所示，如下所述。將快閃單元之特定區域 保遠用於鬲消除優先權區塊。緊急情況中，在消除快閃單DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First flash unit Other flash unit 1 Any arbitrary P kg has a high elimination priority position. According to the simplest block configuration when writing, 2 specifies N/A, and the most effective emergency elimination is specified.任思__ Aligning the first flashing j-element with only the first flashing unit according to the log optimization performance between the specific embodiments 1 and 2 ------- Table 3 Specific embodiment. In a preferred embodiment of the invention, the data is stored in the flash memory in any manner that does not impose any constraints on the write configuration, as shown in Table 1, specific embodiment 1, as described below. Phase & records the location of the write block containing the key material and performs the elimination based on the records. + praising another preferred h, /, only W π , , Μ碉 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Shown as follows. The specific area of the flash unit is used to eliminate the priority block. In an emergency, the flash is eliminated
先權？:其他部分丽消除保留區域。依據各區塊之消除優 預疋可用於寫入資料之區塊的位置。 所：發1月之另一較佳具體實施例中(如表丨、具體實施例3 斤不*下所述），以組合具體實施例 ，錯存於快閃單元内。具體實施例3中，二= 除。具體♦施…，”具體實施例2同樣快地執行消 第-快閃: (類似於具體實施例D以隨機順序執行 單元之剩餘部分内著依據第一快閃單元對準快閃 -快閃單元時且體實：先權區域之位置。在寫入第 實施例3與具體實施例1同樣快，且在緊 124523.doc 200822124 急消除後與具體實施例2同樣快。 使用至少三個不同程序實施快閃記憶體之優先消除·· ⑴普通消除命令，例如可從南韓Suw〇n市Samsung Electromcs公司獲得的K9F1G08U0A快閃記憶體之技術 資料表袼内所述。 ⑺清潔消除，例如Koren等人之美國專利申請案第 20040188710號内所教導；以及 (3)中斷消除，例如以下所詳細說明。 ( 本發明說明的優先消除程序包括消除程序及消除順序之 選擇。 因此，依據本發明，第-次提供_種具有優先消除能力 之非揮發性儲存裝置，該裝置包括：⑷一儲存記憶體，其 用於將資料儲存於儲存裝置内，該儲存記憶體具有至少一 個快閃單元’其中各快閃單元具有複數個區塊；以及⑻一 儲存裝置控制器，其經組態用以：（i 人⑴將该貢料寫入該複數 t區塊"Π)對各區塊指派一消除優先權，其中該消除優 先權與該資料之-消除優先權相關；以及㈣在接收一緊 急消除命令後，依據各區塊之該消 y、憂先權消除各區塊内 之該資料。 較佳的係，控制器經組態用以在住 入 ^ 仕思選疋區塊上執行寫 入’以及依據資料之消除優先權執行指派。 較佳的係，控制經組態用以在資料 權”〆 貝枓寫入前執行消除優先 權之礼派，以及依據各區塊之消除優先權執疒、 較佳的係，控制器經組態用以執行嗲仃”’、入。 Μ貝料以一任意順序 124523.doc 200822124 對第一快閃單元内的該複數個區塊之寫入，並與該第一 快閃單元内之該順序相關地執行對隨後快閃單元之寫入。 取仏的係，控制n進一步經組態用以··（iv)對每 快閃單元内具有-共同相對位置的區塊指派-共同消除優 先權。 較佳的係’控制器進一步經組態用以·· (iv)儲存用於各 品龙之/肖除優先權的日諸’·以及（v)在接收緊急消除命令 後’依據儲存於日諸内之消除優先權消除各區塊 ί、 料。 貝 較佳的係，控制器之消除包括在完成消除前針對該複數 個區塊之至少一些來中止消除。 依據本發明’第_次提供—種具有優先消除能力之硬碟 機，δ亥硬碟機包括··⑷一儲存記憶體，其用於將資料儲存 於該硬碟機内，該儲存記憶體具有至少兩個區段；(b)一指 派機制彡用於對各區段指派一消除優先權，其中該消除 優先權與該資料之一消除優先權相關；以及⑷一消除機 "制，其用於依據各區段之該消除優先權消除該等區段。 從隨後的詳細說明及範例將明白此等及其他具體實施 例。 【實施方式】 本發明係關於用於按—方式f理儲存裝置内之資料儲存 及抹除的裝i以便在消除較不關鍵資料前消除較關鍵資 料。參考隨附說明及圖式，可更佳地瞭解依據本發明用於 管理儲存裝置内資料儲存及消除的原理及操作。 124523.doc 200822124 上述表1之具體實施例丨中，寫入程序係任意的，日誌證 明各種消除優先權層級之區塊配置，以及依據日誌執行消 除。 上述表1之具體實施例2中，依據高消除優先權層級之區 塊保留配置執行寫入程序，以及依據該配置執行消除。 上述表1之具體實施例3中，如同具體實施例1，任意地 執仃第-快閃單元之寫入。此一任意配置接著規定快閃單 Ο 元剩餘部分内的配置，且如具體實施例2内-樣執行消 除。 /現在：考圖式，圖1係使用優先消除程序之快閃記憶體 系統之簡化示意性方塊圖，其依據本發明之較佳具體實施 例使用實體消除片段進行消除。主機系統2〇係顯示為連接 ，决己fe體裝置22，其具有快閃控制器24及複數個快閃 、1單元26具有若干區塊28，其可針對消除單獨定 =用於快閃記憶體磁碟機之此—結構係本技術中所熟知 古且可在某些組件中找到，例如可從以色列Kefar SabaFirst right? : Other parts of the Philip eliminate the reserved area. According to the elimination of each block, the location of the block that can be used to write data is used. In another preferred embodiment of the present invention (as described in the following table, the specific embodiment is not described below), in combination with the specific embodiment, it is stored in the flash unit. In the third embodiment, two = divided. Specifically, the specific embodiment 2 performs the same fast-flashing as fast: (similar to the specific embodiment D, the remaining part of the unit is executed in a random order, and the flashing-flashing is performed according to the first flash unit. When the unit is in the real part: the position of the pre-emption area is as fast as in the first embodiment, and is as fast as the specific embodiment 2 after the emergency elimination of 124523.doc 200822124. Use at least three different The program implements the priority elimination of the flash memory. (1) The general elimination command, for example, can be described in the technical data sheet of the K9F1G08U0A flash memory obtained from Samsung Electromcs, Suw〇n City, South Korea. (7) Cleaning elimination, such as Koren et al. U.S. Patent Application Serial No. 20040188710; and (3) Interrupt cancellation, such as described in detail below. (The prioritized elimination procedure described herein includes the elimination procedure and the elimination of the order. Thus, in accordance with the present invention, Providing a non-volatile storage device having priority elimination capability, the device comprising: (4) a storage memory for storing data in the storage device, The storage memory has at least one flash unit 'where each flash unit has a plurality of blocks; and (8) a storage device controller configured to: (i) (1) write the tribute to the complex number t Block "Π) assigns an elimination priority to each block, wherein the elimination priority is related to the data-elimination priority; and (4) after receiving an emergency cancellation command, according to the block The prioritization eliminates this information in each block. Preferably, the controller is configured to perform the write on the live sector and to perform the assignment based on the data elimination priority. Of the system, the control is configured to perform the priority elimination prior to the data right", and the controller is configured according to the elimination priority of each block. The execution of the plurality of blocks in the first flash unit is performed in an arbitrary order 124523.doc 200822124, and is associated with the order in the first flash unit. Perform a write to the subsequent flash unit. The control n is further configured to (iv) assign a block with a common relative position in each flash cell - collectively eliminate the priority. The preferred system controller is further configured to (iv) Store the days for each product dragon's priority, and (v) after receiving the emergency elimination command, 'removal of the blocks according to the elimination priority stored in the day. Preferably, the elimination of the controller includes discontinuing the cancellation for at least some of the plurality of blocks before the elimination is completed. According to the present invention, the first time provides a hard disk drive with priority elimination capability. The disc drive comprises: (4) a storage memory for storing data in the hard disk drive, the storage memory having at least two segments; and (b) an assignment mechanism for assigning an elimination to each segment Priority, wherein the elimination priority is associated with one of the data elimination priorities; and (4) a cancellation machine system for eliminating the segments based on the cancellation priority of each segment. These and other specific embodiments will be apparent from the following detailed description and examples. [Embodiment] The present invention relates to an apparatus for storing and erasing data in a storage device in order to eliminate more critical information before eliminating less critical data. With reference to the accompanying description and drawings, the principles and operations for managing the storage and elimination of data in a storage device in accordance with the present invention are better understood. 124523.doc 200822124 In the specific embodiment of Table 1 above, the writing process is arbitrary, the log proves the block configuration of various elimination priority levels, and the deletion is performed according to the log. In the specific embodiment 2 of the above Table 1, the writing process is executed in accordance with the block reservation configuration of the high erasure priority level, and the elimination is performed in accordance with the configuration. In the specific embodiment 3 of the above Table 1, as in the specific embodiment 1, the writing of the first-flash unit is arbitrarily performed. This arbitrary configuration then specifies the configuration within the remainder of the flash unit and performs the elimination as in the specific embodiment 2. /Now: Test Pattern, Figure 1 is a simplified schematic block diagram of a flash memory system using a prioritization cancellation procedure, which is eliminated using a solid elimination segment in accordance with a preferred embodiment of the present invention. The host system 2 is shown as a connection, a device 22 having a flash controller 24 and a plurality of flashes, and a unit 26 having a plurality of blocks 28, which can be individually determined for cancellation = for flash memory This is a well-known structure in the art and can be found in certain components, for example from Kefar Saba, Israel.
SanD=k IL Ud•公司獲得的 FFD-25-UATA-8192-A。 資=了6内之某些區塊28係選擇成容納高消除優先權 之“I將其顯示為區似）。區塊H之位置對主機系統 可為：撼-制已知。寫入機制通常係快閃控制器24，但亦 J马主機系統2〇。窝 从 給區塊Η。快閃… 接者將高消除優先權資料配置 R 早l Μ内之其他區塊Μ係選擇成容納中等 及低沩除優先L /门 T ^ 、，（圖1内分別顯示為區塊“及L)。區塊 124523.doc 200822124 Μ及L之位置亦對主機系絲 機糸、、先20之寫入機制已知。 接著將較低消除優先權資料 … 權貝科配置給區塊Μ及L。可存在任 何數目之消除優先權声幼 、，， 塊2 8 θ1便將資料選擇性地配置給區 本發明之較佳具體實施例中，採㈣除消除優先權指定 某二區塊28其攸優先 >肖除程序排除指定區塊（圖1内顯示 為區塊E)。可將資料配置給區塊E，其在緊急消除情況事 件中不需要加以消除。若需要緊急消除快閃記憶體裝置22 内之資料’消除機制依據其指定消除優先權消除區塊”， 從而確保以正確順序消除資料。 1體消除片段"係來自數個快閃單元之區塊的集合，其 中選定區塊之各個具有其個別快閃單元内之相同位址。若 在寫入後配置區塊，以便各快閃單元内之選定消除優先權 區塊共享相同位址，則可藉由實體消除片段執行最佳優先 消除。 圖1中顯示實體消除片段30，其代表橫跨數個快閃單元 26之區塊28的集合。雖然圖！内將區塊11顯示為實體消除片 段30之部分，實體消除片段3〇可包括區塊28之任何，，片段”。 本發明之較佳具體實施例中，同時執行實體消除片段％内 之區塊28的消除。 某些快閃記憶體架構中，由於快閃記憶體之異質結構， 某些區塊之消除比其他區塊快。圖1所述之本具體實施例 中’其中針對高消除優先權預定配置區塊，較佳的係使用 固有快速消除區塊，以便配置給高消除優先權資料。•可應 124523.doc • 11 - 200822124 用一協定，其中高消除優先權資料駐留於快速消除區塊 中。此類系統中，快速消除區塊係選擇成容納較高消除優 先權資料。如此，將更快地消除高消除優先權資料。SanD=k IL Ud• Company obtained FFD-25-UATA-8192-A. Some blocks 28 in the group = 6 are selected to accommodate the high elimination priority "I will display it as a zone." The location of the block H to the host system can be: 撼 - system known. Write mechanism Usually, it is a flash controller 24, but it is also a J-horse host system. The socket is from the given block. Flashing... The receiver will set the high-priority priority data configuration R to the other blocks in the first block. Medium and low 优先 priority L / gate T ^ ,, (shown in Figure 1 as block "and L". Block 124523.doc 200822124 The position of the Μ and L is also known for the writing mechanism of the host ray and the first 20. Then, the lower elimination priority data ... is assigned to the block Μ and L. There may be any number of cancellation priority sounds, and block 2 8 θ1 selectively configures the data to the preferred embodiment of the present invention, and the fourth block 28 is excluded from the priority. The Priority > Divide program excludes the specified block (shown as Block E in Figure 1). The data can be configured for block E, which does not need to be eliminated in the emergency elimination event. If it is necessary to urgently eliminate the data in the flash memory device 22, the elimination mechanism eliminates the priority elimination block according to its designation, thereby ensuring that the data is eliminated in the correct order. 1 body elimination fragment " is from a region of several flash units a collection of blocks, each of the selected blocks having the same address within its individual flash cells. If the blocks are configured after writing so that the selected cancellation priority blocks within each flash cell share the same address, then The best priority cancellation can be performed by the entity elimination segment. The entity elimination segment 30 is shown in Figure 1, which represents a collection of blocks 28 that span several flash units 26. Although the block 11 is shown as an entity elimination Part of the segment 30, the entity elimination segment 3 can include any of the blocks 28, ". In a preferred embodiment of the invention, the elimination of block 28 within the segment % of the entity is performed simultaneously. In some flash memory architectures, certain blocks are eliminated faster than other blocks due to the heterogeneous structure of the flash memory. In the present embodiment illustrated in Figure 1, where a predetermined configuration block is reserved for high cancellation priority, it is preferred to use an inherent fast cancellation block in order to configure for high cancellation priority data. • Can be used 124523.doc • 11 - 200822124 Use an agreement in which high elimination priority data resides in the fast elimination block. In such systems, the fast elimination block is selected to accommodate higher elimination priority data. In this way, high elimination priority data will be eliminated more quickly.
Ο 應注意，在本具體實施例中，將高消除優先權區塊隨機 配置給快閃單元。由於消除程序在一消除週期期間消除各 快閃單元内之一區塊，其可能發生，某些快閃單元中可能 存在欲消除的剩餘區塊，而在其他快閃單元中，已消除高 消除優先權區塊。此-情況導致效率損失。消除程序= 在各週期中消除較小數目的區塊’直至消除最後快閃單元 内之最後高消除優先權區塊。 圖2係使用優先消除程序之快閃記憶體系統之簡化示意 性方塊圖，其依據本發明之較佳具體實施例使用邏輯消： 片段進行消除。此具體實施例中，藉由與本發明無關之工 程考量最佳化寫人程序，而其係在快閃記憶體裝置㈣之 =技術中教導，例如在G(m)bets之美國專利第Μ98；；62 5虎中。 執行寫…如-個 快閃單元26上。心，在：：將資料並列地寫入數個 叫即寫入高消除/先權^//「寫入區塊28(或至少區塊 在三個消除優先❹級，並示本發明…，假定存 優先權_E)。；此，「部分區塊不具有任何消除 險。 右區塊E内資料未消除，則無風 124523.doc 200822124 如快閃記憶體工程技術中所熟 同時消除各快閃單元内之區塊時除週期期間 之消除最有效。然而，若 早凡快閃記憶體裝置 塊’則無法執行實體消除 -置- 輯消除片段此^中，可執行"邏 ’’邏輯消除片段"係各快閃單元26 以(例如圖2中之區塊Η、Μ、或表性區塊 Ο 利用單-消除週期可在一次摔 ^本具體實施例 同位置之區塊的事實。可，由接徂夂快閃單元26内不 ^ 了稭由棱供各快閃單元26内之選定 區塊28的位址同時消除邏 廡田私略“ 、得錢片&，並然後將消除命令 應用於所有快閃單元26，其令 區揷Μ „ ，、甲在各快閃早兀26内消除選定 肉—私序提供依據其相對消除優先權消除各快閃 早兀26内區塊28的方式。 快閃記憶體裝置22可在單-消除週期中消除實體消除片 段或邏輯消除片段。圖丨尹， 自除片 在對實體消除片段内之區塊 消除最佳的架構中組織資料。圖2中，任意地組織資料； 因此，必須實施藉由邏輯消除片段消除區塊之機制。 當需要緊急消除快閃記憶體裝置22時，快閃控制器墙 查曰誌表以找到各快閃單元26内之最高消除優先權區塊。 來自各快閃單元26之-組區塊Η變為邏輯消除片段32，如 圖2内所示。消除邏輯消除片段32，並更新日諸表以反映 已4除该等區塊。應注意，並非消除邏輯消除片段U内之 所有區塊Η ’僅消除來自各快閃單元％之一個區塊η。快 閃控制器24接著拾取各快閃單元洲之下一最高消除優先 124523.doc -13· 200822124 權區塊(例如區塊Μ)。來自各快閃單元26之—組區 為欲消除之邏輯消除片段34’並再次更新曰諸表。此 繼續（例如邏輯消除片段36及38)，直至任何快閃單元=内 不再存在高消除優先權區塊。實務中，消除邏輯消除片段 32後，選擇的下-邏輯消除片段亦可僅包括區塊η。此： 程序可繼續，直至區塊Η不再位於日諸表内，接著可消除 邏輯消除片段34(即區塊Μ)，或者直至從外部停止消除程 序。 Ο 圖3係依據本發明之較佳具體實施例的優先消除程序之 簡化流程圖。從主機系統接收緊急消除命令後，快閃記憶 體裝置之控制器開始優先消除程序（步驟4〇)。控制器檢查 是否存在欲消除之消除優先權區塊（步驟42)。若不存 消除之消除優先權區塊，優先消除程序結束（步驟44)。= 存在欲消除之消除優先權區塊，控制器檢查是否存在任何 ，要檢驗之快閃單元（步驟46)。若仍存在需要檢驗之快閃 早兀，控制器尋求下一快閃單元内之最高消除優先權區塊 (步驟48)，並繼續將區塊新增至當前邏輯消除片段（步驟 5〇)。接著，控制器再次檢查是否存在任何需要檢驗之快 閃單元（步驟46)。-旦已檢驗所有快閃單元，消除當前邏 輯消除片段（步驟52) ’所有區塊係包含於並列消除的邏輯 消除片段中。接著相應地更新日誌表（步驟54)。 本發明之較佳具體實施例中，使用"中斷消除,,週期代替 "完整消除"週期。完整消除週期係耗費較長時間之消除程 序’通常係2.5毫秒，並確保消除在記憶體區塊所有位元 124523.doc -14· 200822124 已被設定為一邏輯的意義上係”乾淨的"。若消除程序變得 車乂短存在某些位元未被設定為一邏輯的風險。當必須消 除具有數千個區塊之快閃記憶體時，而使用完整消除週期 消除各區塊，總消除時間可耗費數十秒。緊急情況中，存 在消除程序在消除所有區塊前被切短的風險。 藉由將2·5 ms週期之一分數專用於消除區塊，可更有效 地使用緊急消除時間，從而可在2·5 ms内消除更多區塊。 通常，大多數位元在已執行完整消除週期之少於5〇%後遺 f) 失其最初邏輯狀態。未完整消除的剩餘位元數量彳艮少，使 得資訊實質上無用。因此較佳的係使用完整消除週期時間 之50%清除雙倍區塊數量，而非使用完整消除週期時間消 除50%之區塊。顯然，可使用工程考量，及假定可用於優 先消除程序之總時間，將中斷消除週期之持續時間之決定 設定為標稱完整消除週期之〇%與1 〇〇%間。 實施中斷消除週期之一可能方式係利用快閃記憶體（用 於NOR及NAND型快閃記憶體）雖然在消除週期期間”看不 ( 到”許多命令，回應專用”中止”命令之事實，例如： (1) NOR型快閃記憶體内之"重設”命令，例如 http://www.samsung.eom/Products/Semiconductor/M CP/NOR_based/K5L5628JBM/K5L5628JBM.htm 中所 述； (2) NOR型快閃記憶體内之”暫停消除”命令，例如 http://www.electronicstalk.com/news/sor/sorlOO.html 中所述；以及 124523.doc -15- 200822124 (3) NAND型快閃記憶體内之”重設”命令，例如Samsung K9FIG08U0A 資料表袼中所述：http://wwwesamsung· com/Produets/Semiconductor/NANDFlash/SLC 一 Large Block/lGbit/K9FIG08U0A/ds—k9flg08x0a一revl0.pdf。Ο It should be noted that in this embodiment, the high cancellation priority block is randomly configured to the flash unit. Since the cancellation process eliminates one of the blocks within each flash cell during an erasure period, it may occur that some of the flash cells may have remaining blocks to be eliminated, while in other flash cells, high cancellation is eliminated. Priority block. This - the situation leads to loss of efficiency. Elimination Procedure = Eliminate a smaller number of blocks in each cycle' until the last high cancellation priority block in the last flash cell is eliminated. 2 is a simplified schematic block diagram of a flash memory system using a prioritization cancellation procedure that uses logic cancellation: segments for cancellation in accordance with a preferred embodiment of the present invention. In this particular embodiment, the writing process is optimized by engineering considerations that are not relevant to the present invention, and is taught in the flash memory device (4) = technology, for example, in G(m)bets, U.S. Patent No. 98 ;;62 5 tigers. Execute write... such as a flash unit 26. Heart, at:: Write data side by side into several calls called write high elimination/first power ^//" write block 28 (or at least block in three elimination priority levels, and show the invention... Assume that priority _E).; This, "Some blocks do not have any elimination risk. If the data in the right block E is not eliminated, then there is no wind 124523.doc 200822124 If you are familiar with flash memory engineering technology, eliminate each fast Blocking within the flash cell is most effective except during the period of the cycle. However, if the flash memory device block is not able to perform the physical erase-set-up elimination segment, the executable "logical' logic Eliminating Fragments" Each flash unit 26 (e.g., block Η, Μ, or pheno-block in Figure 2) The fact that the single-elimination cycle can be used in the same location in the same embodiment Alternatively, the address of the selected block 28 in each flash unit 26 is not removed by the flash unit 26, and the address of the selected block 28 is simultaneously eliminated, and the money sheet & The elimination command is applied to all flash units 26, which makes the area „ „, and A flashes in each flash 2 The selected meat is eliminated within 6 - the private order provides a way to eliminate each of the flash blocks 26 in accordance with its relative elimination priority. The flash memory device 22 can eliminate the physical cancellation segments or the logical cancellation segments in the single-elimination cycle. Tu Yuyin, the self-division slice organizes the data in the best architecture for the block elimination in the entity elimination segment. In Figure 2, the data is organized arbitrarily; therefore, the mechanism for eliminating the block by logic elimination must be implemented. When it is desired to urgently eliminate the flash memory device 22, the flash controller wall checks the table to find the highest erasure priority block in each flash unit 26. The block from each flash unit 26 is changed. The segment 32 is logically eliminated, as shown in Figure 2. The logic elimination segment 32 is eliminated, and the daily tables are updated to reflect that the blocks have been removed. It should be noted that not all logic blocks within the segment U are eliminated. One block η from each flash cell is eliminated. The flash controller 24 then picks up the highest cancellation priority of each flash cell 124523.doc -13·200822124 weight block (eg block Μ). Flash unit 26 - The group area is the logical cancellation segment 34' to be eliminated and updated again. This continues (eg, logically cancels segments 36 and 38) until there is no longer a high cancellation priority block in any flash cell = in practice. After the logic elimination segment 32 is eliminated, the selected lower-logic cancellation segment may also only include the block η. This: The program may continue until the block Η is no longer in the daily table, and then the logical elimination segment 34 (ie, the block) may be eliminated. Μ), or until the program is stopped from the outside. Ο Figure 3 is a simplified flow chart of the priority elimination procedure in accordance with a preferred embodiment of the present invention. The controller of the flash memory device after receiving the emergency cancellation command from the host system Start the priority elimination procedure (step 4〇). The controller checks if there is a cancellation priority block to be eliminated (step 42). If the elimination priority block is not eliminated, the priority elimination procedure ends (step 44). = There is an elimination priority block to be eliminated, and the controller checks if there is any flash cell to be verified (step 46). If there is still a flash that needs to be verified, the controller seeks the highest erasure priority block in the next flash unit (step 48) and continues to add the block to the current logical cancellation segment (step 5). Next, the controller checks again if there are any flash units that need to be verified (step 46). Once all flash units have been verified, the current logical cancellation segment is eliminated (step 52). All blocks are included in the logical elimination segment of the parallel elimination. The log table is then updated accordingly (step 54). In a preferred embodiment of the invention, "interrupt cancellation, "cycle is used instead of "complete elimination &" period. The complete elimination cycle takes a long time to eliminate the program 'usually 2.5 milliseconds, and ensures that all bits in the memory block 124523.doc -14· 200822124 have been set to a logical sense of "clean" If the elimination procedure becomes short, there is a risk that some bits are not set to a logic. When it is necessary to eliminate the flash memory with thousands of blocks, use the complete elimination period to eliminate the blocks, total Eliminating time can take tens of seconds. In an emergency, there is a risk that the elimination process will be cut short before all blocks are eliminated. By using one of the 2.5 ms periods for the elimination of blocks, the emergency can be used more effectively. Eliminate time so that more blocks can be eliminated in 2.5 ms. Typically, most of the bits lose their initial logic state after less than 5〇% of the complete elimination period has been performed. The remaining bits are not completely eliminated. The small amount makes the information virtually useless. Therefore, it is better to use the complete elimination cycle time to eliminate the double block number by 50% instead of using the complete elimination cycle time to eliminate 50% of the block. Obviously Engineering considerations can be used, and the total time to prioritize the elimination of the program can be used to set the duration of the interrupt cancellation period to between 〇% and 1〇〇% of the nominal complete elimination period. The use of flash memory (for NOR and NAND type flash memory), although it does not "go to many commands, respond to the special" abort" command during the elimination cycle, for example: (1) NOR type flash The "reset" command in memory, for example, as described in http://www.samsung.eom/Products/Semiconductor/M CP/NOR_based/K5L5628JBM/K5L5628JBM.htm; (2) NOR-type flash memory The "suspend elimination" command, as described in http://www.electronicstalk.com/news/sor/sorlOO.html; and 124523.doc -15- 200822124 (3) NAND-type flash memory Set the command, for example, as described in the Samsung K9FIG08U0A data sheet: http://wwwesamsung·com/Produets/Semiconductor/NANDFlash/SLC-Large Block/lGbit/K9FIG08U0A/ds-k9flg08x0a-revl0.pdf.
Samsung K9FIG08U0A之資料表格聲明：，，該裝置提供重 設特徵，其係藉由將FFh寫入命令暫存器來執行。當裝置 在奴機項取、程式化或消除模式期間處於忙線狀態，重設 操作將中止該等操作”。 ί、The data sheet of Samsung K9FIG08U0A states: that the device provides a reset feature that is executed by writing FFh to the command register. When the device is busy during the slave entry, stylization or elimination mode, the reset operation will abort the operation.” ί,
忒等〒7遠短於完整消除週期（NAND型快閃記憶體中， 重設命令耗費0.5 ms之最A值，^整消除週期耗費Μ )田中止疋整消除週期時，記憶體留在隨機狀態内， /、對任何目的均無用。較佳的係使用5,間隔以開始五個 完整消除週期並在每〇·5咖後中止週期（使用各消耗0.5 ms ::個重叹命令)’而非執行兩個完全完整消除週期。兩 種替代方案消耗完整5_ms間隔。 本發明之較伟且_ . 示），可以任音方;執實^例中（如表1内具體實施例3所 較古、、肖pi土μ 快閃單元之寫入，記錄接收 第:=元::7 常，將隨後快閃單元與:―::序:二:_元。通 對準，以#犬 、八〗早兀之阿消除優先權區塊 塊接收具有相閃單元内具有相同(或相關)位址之區 列消除具=優先權之資料。此致能系統以藉由並 必經過邏輯、方 區塊'肖除鬲消除優先權資料，而不 除片段之構造（如上所述，且如圖2所示）。 124523.doc 200822124 主w對南'肖除優先權資料使用快速消除區塊並對準 共同實體消除片段内之高消除優先權資料並非衝突協定， 而可較佳地-起實施。儘管將高消除優先權區塊儲存於快 閃單元之’’較快部分，，内’以隨機順序將區塊儲存於第一快 閃單元内。此隨機順序規定用於所有其他快閃單元之順 序，從而產生駐留於共同實體消除片段内之高消除優 資料。 Ο 應注意，雖然邏輯消除片段内之消除及實體消除片段内 =^可導致相同消除順序（且因此導致相同最佳化層 消除Λ體=片段：⑴更易於實施，以及（2)比使用邏輯 因此又之施方案内需要更少管理及管理資料儲存器。 口此、’較佳的係使用實體消除片段之實施方案。 應注意，硬碟機係本發明涵蓋之館存 本發明並非僅以任何方式限於_ 的，、型乾例。 適用於並涵蓋具有以下特徵之至少—些的任:::二疋 ⑴儲存裝置係分成許多子單元，各 ’、、、’. 除； 早兀了早獨加以消 (2)子單元之消除時間係較長程序； (::子單元之完全消除比中止消除耗費更長. ()館存裝置控制器具有將資料储存 ’以及 活性。 丁早兀内之靈 儘f已闕於有限數目的且俨 明白可對本…-列來說明本發明，㈣ 了對本發明進仃許多改變、修改及 仁應 【圖式簡單說明J ^ 124523.doc -17- 200822124 本文參考附圖而僅以範 圖1係使用優先消除程序’呪明本發明’其中： 性方塊圖，其依據本發明之如快閃記憶體系統之簡化示意 片段進行消除； λ佳具體實施例使用實體消除 圖2係使用優先消除程成 化示意 輯消除 牙序之快閃記憶體系統之食 性方塊圖’其依據本發明 知月之較佳具體實施例使用超 片段進行消除； 圖3係依據本發明之較佳具體實施例的優先消忒等〒7 is much shorter than the complete elimination period (in NAND-type flash memory, the reset command consumes the most A value of 0.5 ms, and the entire elimination cycle consumes Μ). When the field stops the elimination cycle, the memory remains in random. Within the status, / is useless for any purpose. Preferably, 5 is used to start the five complete elimination periods and to suspend the period (using each of the consumed 0.5 ms :: sigh commands) instead of performing two complete elimination cycles. Both alternatives consume a full 5_ms interval. The invention is more advanced and can be used as the sound side; in the example of the implementation (as in the case of the specific embodiment 3 in Table 1, the writing of the Xiao pi soil flash unit, the recording reception: = Yuan::7 Normally, the flash unit will be followed by: -:: Preface: 2: _ yuan. Alignment, with #犬,八〗 A zone with the same (or associated) address eliminates the material with priority = the priority. This enables the system to eliminate the priority data by means of logical and square blocks, without the construction of the segment (as above Said, and as shown in Figure 2.) 124523.doc 200822124 The main w is to use the fast elimination block and align the common entity to eliminate the priority information in the fragment. It is not a conflict agreement. Preferably, the implementation is performed. Although the high cancellation priority block is stored in the 'faster portion of the flash cell, the inner block is stored in the first flash cell in a random order. This random order is specified. The order of all other flash units, resulting in a high elimination in the common entity elimination segment资料 资料 Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο Ο 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑 逻辑It is less than the use of logic and therefore requires less management and management of data storage. The preferred embodiment is to use an entity to eliminate fragment implementation. It should be noted that the hard disk drive is covered by the present invention. It is not limited to any of the following, and is applicable to and covers at least some of the following features::: Two (1) storage devices are divided into a number of subunits, each ',,, '. As early as possible, the elimination time of the subunit is longer (2). The complete elimination of the subunit is longer than the elimination of the suspension. () The storage device controller has the data storage and activity. The spirit of Ding Zaoqi has been limited to a limited number and can be understood from the present invention. (4) Many changes, modifications and benevolences have been made to the present invention. [Simple description of the figure J ^ 124523.doc -17- 20 0822124 herein, with reference to the accompanying drawings, only the priority elimination procedure is used to illustrate the present invention, wherein: a block diagram of the present invention is eliminated according to the simplified schematic segment of the flash memory system according to the present invention; Example using entity elimination FIG. 2 is a food-saving block diagram of a flash memory system using a priority elimination process to eliminate the tooth sequence. The preferred embodiment of the invention according to the present invention uses a super-segment to eliminate; FIG. 3 is based on Priority of a preferred embodiment of the invention
4h. ^ ^ ^ _ 、& 序之 【主要元件符號說明】 20 主機系統 22 快閃記憶體裝置 24 快閃控制器 26 快閃單元 28 區塊 30 實體消除片段 32 邏輯消除片段 34 邏輯消除片段 36 邏輯消除片段 38 邏輯消除片段 E 區塊 Η 區塊 L 區塊 Μ 區塊 124523.doc -18 -4h. ^ ^ ^ _, & [Main component symbol description] 20 Host system 22 Flash memory device 24 Flash controller 26 Flash unit 28 Block 30 Entity elimination segment 32 Logic elimination segment 34 Logic elimination segment 36 Logic Elimination Fragment 38 Logic Elimination Fragment E Block Η Block L Block Μ Block 124523.doc -18 -