JP5486047B2 - Device and method for prioritized erase of flash memory - Google Patents

Description

  The present invention relates to a device for managing the storage and erasure of data in a storage device such that high critical data is erased before low critical data is erased.

In computer engineering, it is well known that data in a storage device needs to be erased,
(1) the need to clear space for new data, and
(2) The need to destroy confidential information for storage devices with secure areas
Two alternative needs are motivated.

  The first reason is not urgent, but the second reason is essential in an important aspect. The “time window” between the decision to erase data and the loss of control over the storage device can be very short. Often, the time available to erase the storage device is less than the time required to completely erase the entire storage device. Unfortunately, the prior art does not disclose how to organize the erase procedure such that high critical data is erased before low critical data is erased.

  It is therefore desirable to have a device that ensures that the most critical data is erased first when critical erasure is required. Such prioritized erasure procedures provide an optimal solution in time critical aspects.

  It is an object of the present invention to provide a device for managing the storage and erasure of data in a storage device such that high critical data is erased before low critical data is erased. .

  For purposes of clarity, the following terms are specifically defined for use in the text. The term “erase procedure” as used herein uses the contents of a block by (1) setting all cells in the block to the same logical value, or (2) randomizing the contents of all cells in the block. Mention an electronic process that renders it impossible. As used herein, the term “priority erase” refers to an erase procedure that erases a portion of memory according to an erase priority protocol. As used herein, the term “block” refers to the physical portion of a flash memory storage device. As used herein, the term “sanitize erasure” refers to an erasure procedure in which the contents of digital memory are destroyed such that the contents cannot be recovered by forensic means. Such sanitized erase is in contrast to normal erase procedures that disable the use of content for normal read commands, but may not prevent recovery by advanced technical means. As used herein, the term “flash unit” refers to a portion of flash memory within a flash memory device.

  The present invention is applicable to both single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory. Subsequent discussion will concentrate primarily on SLC cells, but it will be apparent to those skilled in the art that the present invention is applicable to MLC cells (and generally other non-volatile storage devices). As used herein, the terms “erase” and “write” refer to setting the threshold voltage of a memory cell. For SLC cells, erasing typically sets a voltage corresponding to one logic value, and writing typically sets a voltage corresponding to zero logic value. In the text, the terms “write” and “programming” are used interchangeably. The present invention is particularly applicable to NAND type flash memories that read and program one page at a time.

  Table 1 shows three alternative embodiments of the present invention.

  In the preferred embodiment according to the present invention, data is stored in flash memory in any manner that does not impose any restrictions on write allocation, as shown in Table 1, Example 1 and described below. . Therefore, the location of the write block containing important data is recorded, and erasure is performed according to these records.

  In another preferred embodiment of the present invention, data is stored in the flash unit in a manner that ensures fastest erasure of high erase priority data, as shown in Table 1, Example 2 and described below. Remembered. A specific area of the flash unit is reserved for the high erase priority block. In the emergency phase, the reserved area is erased before any other part of the flash unit. The location of the blocks available for writing data is predetermined according to the erase priority of each block.

  In another preferred embodiment of the present invention (described in Table 1, Example 3 and described below), data is stored in the flash unit in a manner that combines the advantages of Examples 1 and 2. In Example 3, writing is performed as fast as Example 1, and erasing is performed as fast as Example 2. In Example 3, the writing of the first flash unit is performed in a random order (similar to Example 1), and then the location of the high erase priority area in the remaining flash units is Aligned according to one flash unit. In Example 3, writing to the first flash unit is as fast as Example 1, and emergency erasure is as fast as Example 2.

Prioritized erase of flash memory can be performed using at least three different procedures.
(1) Normal erase command as described in the technical data sheet of K9F1G08U0A flash memory available from Samsung Electronics of Suwon, Korea.
(2) Sanitization elimination as disclosed, for example, in US Patent Application No. 20040188710 to Koren et al. And
(3) Interrupt erasure as described in detail below.

  The prioritized erase procedure described in the present invention includes selection of an erase procedure and an erase order.

  Therefore, according to the present invention, a nonvolatile storage device having an erase function with priority order is provided for the first time. The device includes (a) a storage memory for storing data in the storage device, and (b) a storage device controller. The storage memory has at least one flash unit, and each flash unit has a plurality of blocks. The storage device controller (i) writes data into multiple blocks, (ii) assigns an erase priority to each block, and (iii) erases each block as soon as an emergency erase command is received. It is configured to erase data in each block according to priority. Note that the erase priority assigned to each block correlates with the data erase priority.

  The controller is preferably configured to perform a write on an arbitrarily selected block, and the designation is preferably performed according to data erasure priority.

  The controller is configured to perform an erase priority designation prior to writing data, and the write is preferably performed according to the erase priority of each block.

  The controller is configured to perform data writes to the blocks in any order within the first flash unit, and subsequent writes to the flash unit are in order in the first flash unit. It is preferable to execute with correlation.

  Most preferably, the controller is further configured to (iv) assign a common erase priority to blocks having a common relative position within each flash unit.

  The controller further (iv) stores an erasure priority log for each block, and (v) erases the data in each block according to the erasure priority stored in the log as soon as an emergency erase command is received. It is preferable to be configured to do so.

  The erasure by the controller preferably includes aborting the erasure for at least some of the plurality of blocks before completing the erasure.

  According to the present invention, a hard disk drive having an erase function with priority order is provided for the first time. The drive includes: (a) a storage memory having at least two sectors for storing data in the hard disk drive; (b) a mechanism for assigning an erase priority to each sector; and (c) each sector. Includes a mechanism for erasing the sector according to the erasure priority. Note that the erase priority assigned to each sector is correlated with the data erase priority.

  These and other embodiments are described in detail below.

  The present invention will now be described with reference to the accompanying drawings by way of illustration.

1 is a simplified block diagram illustrating a flash memory system using a prioritized erase procedure that erases utilizing a physical erase slice, in accordance with a preferred embodiment of the present invention. FIG. 1 is a simplified block diagram illustrating a flash memory system using a prioritized erase procedure that uses a logical erase slice to erase according to a preferred embodiment of the present invention. FIG. 6 is a simplified flowchart representing a prioritized erase procedure according to a preferred embodiment of the present invention.

  The present invention relates to a device for managing the storage and erasure of data in a storage device such that high critical data is erased before low critical data is erased. The principles and operation for managing the storage and erasure of data in a storage device according to the present invention may be better understood with reference to the accompanying description and drawings.

  In Example 1 of Table 1 above, the writing process is arbitrary, the log details the allocation of blocks to various erase priorities, and the erase is performed according to the log.

  In Example 2 of Table 1 above, the writing process is performed according to the preliminary allocation of blocks to a high erase priority, and the erasure is performed according to that allocation.

  In Example 3 of Table 1 above, the writing of the first flash unit is arbitrarily performed as in Example 1. Such any allocation then defines the allocation within the remaining flash units. The erasure is executed as in the second embodiment.

  Reference is now made to the drawings. FIG. 1 is a simplified block diagram illustrating a flash memory system using a prioritized erase procedure that erases utilizing a physical erase slice in accordance with a preferred embodiment of the present invention. The host system 20 is shown connected to a flash memory device 22 having a flash controller 24 and a plurality of flash units 26.

  Each flash unit 26 has a number of blocks 28 that are individually addressable for erasure. Such a structure for a flash memory disk drive is well known in the art and is a component such as FFD-25-UATA-8192-A available from SanDisk IL in Kufa Sabah, Israel. Seen in.

  Some blocks 28 of the flash unit 26 have been selected to accommodate high erase priority data (shown as block H in FIG. 1). The location of block H is communicated to the write mechanism of host system 20. The write mechanism is typically the flash controller 24 but may be the host system 20. The write mechanism then assigns high erase priority data to block H. The other blocks 28 of the flash unit 26 are selected to accommodate medium and low erase priority data (shown as blocks M and L, respectively, in FIG. 1). The location of blocks M and L is also notified to the write mechanism of host system 20. The write mechanism then assigns lower erase priority data to blocks M and L. There may be many erasure priorities for selective allocation of data to block 28.

  In the preferred embodiment according to the present invention, some blocks 28 are designated with an exclusion erase priority that excludes the designated block from the priority erase procedure (shown as block E in FIG. 1). Data can be assigned to block E that does not need to be erased during the emergency erase phase. If there is an urgent need to erase data in the flash memory device 22, the erase mechanism erases the blocks 28 according to their designated erase priority and also ensures that the data is erased in the correct order. To do.

  A “physical erase slice” is a collection of several blocks from several flash units, with each selected block having the same address in each flash unit. If the blocks are assigned at the time of writing such that each of the selective erase priority blocks in each flash unit share the same address, it is possible to perform an optimized prioritized erase with a physical erase slice.

  The physical erase slice 30 shown in FIG. 1 represents a set of blocks 28 that traverse the flash unit 26. Although block H is shown in FIG. 1 as part of physical erase slice 30, physical erase slice 30 may include any “slice” of block 28. In the preferred embodiment according to the present invention, erasure of block 28 in physical erase slice 30 is performed simultaneously.

  In some flash memory architectures, erasure of some blocks is faster than erasure for other blocks due to the heterogeneous structure of flash memory. In the present embodiment illustrated in FIG. 1, since blocks are pre-assigned to high erase priority, it is preferable to use essentially fast erase blocks for allocation to high erase priority data. If the high erase priority data belongs to a fast erase block, the protocol can be applied. In such a system, the fast erase block is selected to accommodate higher erase priority data. By doing so, the high erasure priority data will be erased faster.

  It should be noted that in this embodiment, high erase priority blocks are randomly assigned to flash units. The erase procedure erases one block in each flash unit during one erase cycle, so that in other flash units, all flash unit priority blocks have already been erased, but some flash units In some cases, there may still be a situation in which there are still blocks to be erased. Such a situation results in a loss of efficiency. The erase procedure continues to erase fewer blocks during each cycle until the last high erase priority block in the last flash unit is erased.

  FIG. 2 is a simplified block diagram illustrating a flash memory system using a prioritized erase procedure that uses a logical erase slice to erase according to a preferred embodiment of the present invention. In this embodiment, the write process is optimized by engineering considerations disclosed in the prior art of flash memory device configurations that are not relevant to the present invention, eg, US Pat. No. 6,898,662, Gorobets et al. Is done.

  Typically, writing is not performed on the flash units 26 one after the other in a contiguous set of blocks 28, but rather “cross the whole surface” on several parallel flash units 26. Data is written to Simultaneously with writing, a record is created in the erase priority log table (not shown) of each written block 28 or at least block H (ie, the block into which high erase priority data is written). For the purposes of this disclosure, it is assumed that there are three levels of erase priority and that most blocks have no erase priority (ie, block E). Therefore, there is no danger if the data in block E is left unerased.

  As is known in flash memory engineering, erasing a multi-unit flash memory device is most efficient when one block of each flash unit is erased simultaneously during one erase cycle. However, a physical erase slice cannot be performed if the blocks are not pre-arranged according to their erase priority. In such a case, a “logical erase slice” can be performed.

  A “logical erase slice” is a collection of any representative block 28 from each flash unit 26 (eg, block H, M or L in FIG. 2). This embodiment takes advantage of the fact that a single erase cycle can erase blocks at different locations within each flash unit 26 in a single operation. The logical erase slice can be erased at the same time by providing the address of the select block 28 in each flash unit 26 and then applying the erase command to all the flash units 26. Is erased. Such a procedure provides a way to erase the blocks 28 in each flash unit 26 according to their relative erase priority.

  The flash memory device 22 can erase one physical erase slice or one logical erase slice in a single erase cycle. In FIG. 1, the data is organized into an architecture that is optimal for erasing blocks in physical erase slices. In FIG. 2, the data is arbitrarily organized. Therefore, a mechanism for erasing a block by a logical erase slice must be implemented.

  If the flash memory device 22 needs to be erased urgently, the flash controller 24 checks the log table to find the highest erase priority block for each flash unit 26. A set of blocks H from each flash unit 26 becomes a logical erase slice 32 as shown in FIG. The logical erase slice 32 is erased and the log table is updated to reflect that these blocks have been erased. It should be noted that not all blocks H in the logical erase slice 32 are erased, only one block H from each flash unit 26 is erased. The flash controller 24 then selects the next highest erase priority block (eg, block M) within each flash unit 26. A set of blocks M from each flash unit 26 becomes the logical erase slice 34 to be erased, and the log table is updated again. This process continues until there are no high erase priority blocks in the flash unit 26 (eg, logical erase slices 36 and 38). In practice, even after the logical erase slice 32 is erased, the next selected logical erase slice may contain only block H. Such a procedure continues until there is no more block H in the log table, and then the logical erase slice 34 (ie, block M) will be erased. Alternatively, it continues until the erase process is stopped externally.

  FIG. 3 is a simplified flowchart representing a prioritized erase procedure according to a preferred embodiment of the present invention. Upon receiving an emergency erase command from the host system, the flash memory device controller initiates a prioritized erase procedure (step 40). The controller checks whether there is an erase priority block to be erased (step 42). If there are no erase priority blocks to be erased, the prioritized erase procedure ends (step 44). If there is an erase priority block to be erased, the controller checks whether there are any flash units remaining to be examined (step 46). If there are more flash units to examine, the controller searches for the highest erase priority block in the next flash unit (step 48) and proceeds to add the block to the current logical erase slice. (Step 50). The controller then checks again whether there are any remaining flash units to be tested (step 46). When all flash units have been examined, the current logical erase slice is erased (step 52). At this time, all the blocks included in the logical erase slice are erased in parallel. Accordingly, the log table is updated accordingly (step 54).

  In the preferred embodiment of the present invention, instead of a “full erase” cycle, an “interrupt erase” cycle is used. A full erase cycle is an erase procedure that spends a relatively long time, typically 2.5 milliseconds, and the erase is “clean” in that all bits of the memory block are set to one logic. Make sure. If the erase procedure is shortened, there is a risk that some bits will not be set to one logic. If a flash memory with thousands of blocks is erased and each block is erased in a full erase cycle, the total erase time can be tens of seconds. In an emergency situation, there is a risk that the erase procedure will be interrupted briefly before all the blocks are erased.

  The emergency erase time can be used more effectively by allocating a portion of the 2.5 ms cycle to erase one block, and more blocks can be erased within 2.5 ms. Typically, after less than 50% of the full erase cycle is performed, most bits lose their original logic state. The remaining total number of bits that have not been completely erased is small enough to make the information substantially unavailable. Therefore, it is preferable to erase twice the number of blocks using 50% of the full erase cycle time rather than erasing 50% of the blocks using the full erase cycle time. Determination of interrupt erase cycle duration can be set between 0% and 100% of the nominal full erase cycle based on engineering considerations and an estimate of the total time available for the prioritized erase procedure Obviously.

One possible way to perform an interrupt erase cycle is that flash memory (for both NOR and NAND type flash memory) is “blind” for many commands during the erase cycle, for example To take advantage of the fact that it reacts to a special "abort" command:
(1) “Reset” command in NOR type flash memory as described in “http://www.samsung.com/Products/Semiconductor/MCP/NORbased/K5L5628JBM/K5L5628JBM.htm”.
(2) “Suspend erase” command in NOR type flash memory as described in “http://www.electronicstalk.com/news/sor/sor100.html”. And
(3) For example, a NAND type as described in the Samsung K9F1G08U0A data sheet of “http://www.samsung.com/Products/Semiconductor/NANDFlash/SLC_LargeBlock/1Gbit/K9F1G08U0A/ds_k9flg08x0a_rev10.pdf” “Reset” command in flash memory.

  The Samsung K9F1G08U0A data sheet states, “The device provides a reset function that is performed by writing FFh to the command register. When the device is busy during random read, program or erase mode, The reset operation aborts these operations. "

  These commands are much shorter than a full erase cycle. (In NAND type flash memory, a full erase cycle takes 2.5 ms, but a reset command takes up to 0.5 ms.) When a full erase cycle is aborted, the memory can be used for any purpose. It remains in a random state that is not useful. Rather than performing two complete full erase cycles, start five full erase cycles and abort them after 0.5 ms each (using five reset commands each consuming 0.5 ms) It is preferable to use a time of 5 ms. Both options consume a full 5ms of time.

  In the preferred embodiment of the present invention (shown in Table 1, Example 3), the writing of the first flash unit can be performed in any manner while recording the blocks that receive the higher erasure priority data. . After writing to the first flash unit, subsequent flash units are written in an order that is interrelated with the order of the first flash unit. Typically, subsequent flash units are aligned with the high erase priority block of the first flash unit, so blocks with the same (or correlated) address in all flash units are Receive data with the same erasure priority. This eliminates the need for the system to go through the structure of the logical erase slice (described above and shown in FIG. 2), and by erasing blocks with the same address in parallel, Allows erasing data.

  It should be noted that using a fast erase block for high erase priority data and aligning the high erase priority data to a common physical erase slice is not a conflicting protocol, but can be performed well together. is there. The high erase priority block is stored in the “faster part” of the flash unit, but the blocks are stored in random order in the first flash unit. Since this random order defines the order for all other flash units, high erase priority data will be present in the common physical erase slice.

  Although erasing logical erase slices and erasing physical erase slices can lead to the same order of erasures (and thus to the same level of optimization), physical erase slices can be performed more simply than (1) It should be noted that (2) management data need not be managed and stored as compared to the embodiment using the logical erase slice. Therefore, an embodiment using a physical erase slice is preferred.

It should be noted that the hard disk drive is a typical example of the storage device covered by the present invention. The present invention is not limited to flash memory storage devices but is applicable to and covers storage systems featuring at least some of the following functions.
(1) The storage device is divided into a number of subunits, each erasable individually.
(2) The subunit erasing time is a relatively long process.
(3) Complete erasure of subunits takes much longer than aborted erasure. And
(4) The storage device controller has the flexibility to store data in any subunit.

  Although the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention are possible.

Claims (10)

(A) a storage memory for storing data provided in a non-volatile storage device having a plurality of flash units each composed of a plurality of blocks;
(B)
(I) giving data erasing priority and operating data to be written to any block of the plurality of blocks constituting the plurality of flash units;
(Ii) For each of the blocks in which the data is written, an operation is performed so as to designate a block erase priority correlated with the data erase priority given to the written data;
(Iii) An operation is performed to designate a logical erase slice priority that designates a block in which the same block erase priority is designated among the plurality of flash units.
(Iv) upon receiving an emergency erase command, a controller that operates to erase the data in each block of all of the plurality of flash units according to the logical erase slice priority;
A non-volatile storage device having a prioritized erase function. The controller is
(V) operate to store a log of the logical erase slice priority for each block;
(Vi) upon receiving the emergency erase command, operative to erase the data in a block of all of the plurality of units according to the logical erase slice priority stored in the log. device.   The device according to claim 1 or 2, wherein the erasure by the controller is performed by erasing at least some data in the block for at least some of the plurality of blocks. (A) a storage memory for storing data provided in a non-volatile storage device having a plurality of flash units each composed of a plurality of blocks;
(B)
(I) The block constituting the plurality of flash units operates to execute designation of block erase priority in a predetermined order between the plurality of flash units;
(Ii) An operation is performed such that data erasure priority is assigned and data is written to a block having a block erasure priority designated with a correlation with the data erasure priority,
(Iii) upon receipt of an emergency erase command, a controller that operates to erase the data in each block of all of the plurality of flash units according to the block erase priority;
A non-volatile storage device having a prioritized erase function.   The device of claim 4, wherein the erasure by the controller is operative to erase at least some data in the block for at least some of the plurality of blocks. A non-volatile storage device having a plurality of flash units each composed of a plurality of blocks and a controller , wherein the controller erases data stored in the non-volatile storage device with priority.
Writing data to an arbitrary block of the plurality of blocks constituting the plurality of flash units by giving a data erasing priority; and
Designating a block erase priority having a correlation with a data erase priority assigned to the written data for each of the blocks in which the data is written;
Designating a logical erase slice priority for designating a block having the same block erase priority designated among the plurality of flash units;
Erasing the data in each block of all of the plurality of flash units according to the logical erase slice priority upon receipt of an emergency erase command;
A method comprising: The controller is
Operative to store a log of said logical erase slice priority for each block;
The step of erasing the data, when receiving the emergency erase command, operates to erase the data in each block of all the plurality of flash units according to the logical erase slice priority stored in the log The method of claim 6 including the step of:   The method of claim 6 or 7, wherein erasing the data comprises erasing at least some data in the block for at least some of the plurality of blocks. A non-volatile storage device having a plurality of flash units each composed of a plurality of blocks and a controller , wherein the controller erases data stored in the non-volatile storage device with priority.
Designating block erasure priority in a predetermined order among the plurality of flash units to the plurality of blocks constituting the plurality of flash units;
A step of assigning a data erasing priority and writing the data to a block designated with a block erasing priority correlated with the data erasing priority;
Receiving an emergency erase command, erasing the data in each block of all of the plurality of flash units according to the block erase priority;
A method comprising:   The method of claim 9, wherein the erasing comprises erasing at least some data in the block for at least some of the plurality of blocks.

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