JP2006053950A - Nonvolatile semiconductor memory device and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of performing writing, and elongating its service life. <P>SOLUTION: This nonvolatile semiconductor memory device has a memory cell array having a plurality of writable and erasable blocks, a management means having erasing flags indicating whether the plurality of blocks are respectively erased or not, a control means for determining an unused block among the plurality of blocks, and writing a new data into the unused block, a means for setting the erasing flag corresponding to the block in which old data to be rewritten is recorded as an erased one, a means for selectively erasing the blocks on which the erasing flags are set, and a means for making a logical address corresponded to a physical address of the block having the old data, correspond with a physical address of the block in which new data is written. Each of the plurality of blocks is an erasing unit as a unit smaller than a nonvolatile semiconductor memory chip of the memory cell array. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device using a NAND type EEPROM in an electrically rewritable nonvolatile semiconductor memory element (EEPROM) and a control method thereof.

  In general, a rewritable storage device (storage element) in a computer system has a physical limit in capacity, and therefore, new information is overwritten on unnecessary information. The rewritable storage device (storage element) can be roughly divided into two types according to the method of overwriting. For example, new information can be overwritten as it is on old information, such as random access memory (RAM), hard disk, floppy disk, or magnetic tape. The other is that new information cannot be written unless old information to be overwritten is erased once, as in some types of optical storage devices and EEPROMs.

  There are two methods for erasing a NAND type EEPROM, one of which is a method of erasing information on the entire chip at once, such as a flash EEPROM manufactured by Intel. The other is a method of selectively erasing only information on a part of the chip.

  In the NAND type EEPROM, a plurality of structurally continuous memory cells for reading data continuously or writing data are called in units of pages. For example, in a 4M-bit EEPROM, one page is composed of 4096-bit storage cells. Also, a plurality of structurally continuous pages are called in units called blocks. For example, in a 4M-bit EEPROM, one block is composed of storage cells for 8 pages (4 kbytes). In the NAND type EEPROM, the unit for selectively erasing only a part of the information on the chip is the same as this block.

  Since the NAND-type EEPROM can erase only a part of the data as described above, it is a nonvolatile memory element that can be relatively easily rewritten only for one sector of data as in a magnetic disk device. Therefore, it has been used for applications such as replacing conventional magnetic disk devices by taking advantage of the features of semiconductor memory such as reliability related to mechanical strength, low power consumption, and high speed reading time.

  However, the EEPROM requires a long time to write data, although the access time for reading the data is high. For example, in the case of a 4Mbit NAND type EEPROM, the time required to read one block of data is about 490 μsoc. On the other hand, to erase and rewrite one block, it takes about 10 msec for erasing and about 4 msec for writing data. Cost.

  Furthermore, the current technology has a limit on the number of times data can be rewritten, and the lifetime is reached by rewriting 10 4 to 105 times. Therefore, there is a problem that if the overwriting of data concentrates on the same block, the life of the chip itself is shortened.

  As described above, the conventional nonvolatile semiconductor memory device using the NAND type EEPROM requires a longer time for writing than the data reading time, and the number of times of rewriting is limited. There was a problem of shrinking.

  An object of the present invention is to solve such problems, and to provide a nonvolatile semiconductor memory device and a control method therefor that can perform writing at a high speed and can extend the lifetime.

  In order to solve the above problems, the first feature of the present invention is that (a) a memory cell array having a plurality of blocks that can be selectively written and erased, and (b) a plurality of blocks, respectively. A management means having an erasure flag indicating whether or not it has been erased; (c) a control means for determining an unused block among a plurality of blocks and writing new data to the unused block; and (d) an old data to be rewritten. Means for setting the erase flag corresponding to the block in which the data is recorded to erased; (e) means for selectively erasing the block in which the erase flag is set; and (f) a block having old data. Means for associating the logical address associated with the physical address of the block with the physical address of the block in which new data has been written. Each is summarized in that a non-volatile semiconductor memory device which is a unit of erasing a unit smaller than the non-volatile semiconductor memory chip in which the memory cell array is realized.

According to a second aspect of the present invention, there is provided a data rewrite control method for a nonvolatile semiconductor memory device having a plurality of blocks that can be selectively written and erased. (A) Each of the plurality of blocks includes a memory cell array. An erasing unit as a unit smaller than the realized non-volatile semiconductor memory chip. (B) A step of determining an unused block among a plurality of blocks and (c) erasing a block having old data to be rewritten. Without writing the new data to the unused block, (d) selectively erasing the block in which the old data was recorded, and (e) the physical address of the block having the old data. Associating the associated logical address with the physical address of the block in which the new data is written; And summarized in that a control method for a nonvolatile semiconductor memory device which comprises.
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  According to the first feature of the present invention, new data is written to an unused block area that has been erased in advance as much as possible. As a result, the nonvolatile semiconductor memory device originally needs to be performed prior to writing, and the erasing operation that inevitably increases the access time is omitted, thereby enabling high-speed writing. Even when the same data is updated / changed, the physical writing position changes with each writing, so that an increase in the number of times of writing with respect to a specific block can be avoided and a longer life can be achieved.

  According to the second feature of the present invention, new data is written to an unused block area that has been erased in advance as much as possible. As a result, the nonvolatile semiconductor memory device originally needs to be performed prior to writing, and the erasing operation that inevitably increases the access time is omitted, thereby enabling high-speed writing. Even when the same data is updated / changed, the physical writing position changes with each writing, so that an increase in the number of times of writing with respect to a specific block can be avoided and a longer life can be achieved.

  As described above, according to the present invention, new data is written to an unused block that has been erased in advance as much as possible. An erasing operation that necessitates an increase is omitted, and writing can be performed at high speed. Further, even when the same data is updated / changed, the physical writing position changes with each writing, so that the increase in the number of times of writing with respect to a specific block can be avoided and the non-volatile semiconductor memory capable of extending the life An apparatus and a control method thereof can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device. In the figure, reference numeral 1 denotes a NAND type EEPROM module as a memory means, which is composed of a memory cell array divided into blocks each composed of a plurality of pages. The EEPROM module 1 is connected to a host system (not shown) via a host interface 2 connected by a data line. A multiplexer 9 and a data buffer 10 are provided on the data line. In the host interface 2, a data register 3, an address register 4, a count register 5, a command register 6, a status register 7 and an error register 8 are provided. Reference numeral 11 is a control logic, 12 is an ECC (error correction code) generator / checker, 13 is an address generator, 14 is a CPU having functions as an erasing means and a control means, 15 is a working RAM, and 16 is a control program ROM. The control program ROM 16 stores a series of control programs for writing data.

  The memory device of this embodiment uses a management table to assign and manage the position of data recorded in the EEPROM module 1 which is a nonvolatile memory area. This table is recorded in the EEPROM module 1 together with other user data, but is automatically read into the work RAM 15 when the apparatus is activated. The contents of this table are updated each time data is written to the EEPROM module 1, but this updated table is written back to the EEPROM module 1 each time or when the use of the apparatus is finished. Suppose that

  One of the tables is a table (management table) for managing unused blocks whose configuration is shown in FIG. The other is a comparison table of addresses designated by the host system shown in FIG. 4 and physical addresses on the memory module.

  First, an example of a table for managing unused blocks in FIG. 3 will be described. The first 210 of the table is used to manage unused data blocks in a chain, and is a pointer to the first block in the chain. The second 211 of the table is a pointer to the same purpose but to the end of the chain. The third to n + 2th in the table correspond to the first to nth physical blocks of the NAND type EEPROM module 1. These contents are further composed of a pointer 213 to the next unused block and an erasure flag 214, as exemplified in 212. When the content is “−1” like the pointer in the m-th 218 of the table, it indicates that it is the end of the chain. Therefore, in this example, since the last pointer 211 points to the mth 218 of the table, the content is set to m. The erase flag 214 indicates whether or not the corresponding block has been erased. Here, “0” represents erased, and “1” represents unerased.

  An outline of the operation when data is recorded will be described using a specific example. Assume that the chain of unused blocks is as shown in FIG. To record data, first, the contents of the head pointer 101 are examined. In FIG. 2A, since the 53rd table is pointed, the physical block address on the writable NAND type EEPROM module 1 is 51 obtained by subtracting the offset 2. After writing to the block 51, the value of the head pointer 101 is reset to the point destination 33 of 102, and the table 102 corresponding to the block 51 is removed from this chain. The results are shown in FIG.

  When the data of the existing block becomes unnecessary along with this writing, an operation for updating the table is further performed as shown in FIG. If it is the block 45 that has recorded unnecessary data, the pointer in the 151st 104 of the table pointed to by the end pointer 105 and the value of the end pointer 105 correspond to the block 45. Reset to table number 47. The pointer in the 47th 107 of the table is set to “−1”, and the erase flag is set to “−1”.

  Since the block immediately after being added to the chain of the unused block is not erased, when the read / write access is interrupted, the chain is sequentially erased and the erase flag of the table corresponding to the block is set to “0”. Set to "".

  Next, the comparison table of FIG. 4 will be described. The length n of the table is equal to or less than the block of the NAND type EEPROM module 1. For example, for the sake of simplicity, assuming that the EEPROM module 1 is composed of one 4-Mbit EEPROM, the capacity of one block is 4 kbytes, so the total number of blocks is 128, and the number of items in the comparison table n is also 128 or less.

  In this apparatus, the physical position on the EEPROM module 1 is allocated in units of data amount corresponding to the block capacity of the EEPROM module 1. That is, the first item in the table indicates the physical position where the first 4 kbytes of data designated by the host system are actually recorded. In the example of FIG. 4, since 203 is the third item in the table, 4 kbytes from the 8 kbyte of the address designated by the host system (hereinafter referred to as a logical address) is actually the EEPROM module 1. Assigned to the 101st block. In addition, since the table in which “−1” is written as in 201 and 202 has not yet been written to the logical address corresponding to the position, the physical area is not allocated. Show.

  Next, the operation of this apparatus will be described. The host system sets an access start address in the address register 4 in the host interface 2 of FIG. 1, sets the sector length of data to be accessed in the count register 5, and finally sets an instruction such as read / write in the command register 6. . When an access command is written in the command register 6 of the host interface 2, the CPU 14 in the controller reads the command in the command register 6 and executes a series of control programs for command execution stored in the control program ROM 16. In the following description, for the sake of simplicity, it is assumed that the sector length designated by the host system and the page length in the EEPROM module 1 match.

  FIG. 5 is a flowchart showing a procedure for reading data from the EEPROM module 1. First, the CPU 14 in FIG. 1 determines a physical address on the EEPROM module 1 to be read with reference to the start address set in the host interface 2 and the address conversion table in the management table (step 301). Next, data is read from the EEPROM module 1 to the data buffer 10 (step 302). Next, error processing and data transfer from the data buffer 10 to the host system, which will be described in detail later, are executed (steps 303 to 305).

  FIG. 6 is a flowchart showing a procedure for reading data from the EEPROM module 1 to the data buffer 10. The CPU 14 accesses the EEPROM module 1 through the multiplexer 9 to set the read mode, and sets the data buffer 10 to the read mode (steps 401 and 402). A physical address of the EEPROM module 1 to be read is set in the address generator 13 (step 403). Then, an area in which the read data is to be stored is determined in the data buffer 10, and the head address is set as a write address to the data buffer 10 (step 404). Thereafter, the control logic 11 is instructed to execute a predetermined sequence for reading data.

  The control logic 11 sets the multiplexer 9 so that the read data from the EEPROM module 1 flows to the data buffer 10, and reads the data for one sector while incrementing the contents of the address generator 13 (step 405). Further, the EEC generator / checker 12 is controlled so as to detect an error by using these data and the ECC code read accompanying therewith. When the data for one sector is read, the CPU 14 checks the ECC generator / checker 12 for data errors (step 406). If no error is detected, or if correction is possible even if it is detected, data is transferred from the data buffer 10 to the host system. If an uncorrectable error is detected, the CPU 14 does not transfer data to the host system, and the CPU 14 stores a code indicating that an error has occurred in the status register 7 in the host interface 2 in the error register 8. Is set to a code indicating the content of the error, the host system is notified that the execution of the instruction has been terminated abnormally, and the process is terminated (steps 407 to 410).

  FIG. 7 is a flowchart showing a procedure for transferring data from the data buffer to the host system. The CPU 14 sets the start address of the area where the data read in the data buffer 10 is stored as a read address from the buffer (steps 501 and 502), and the control logic 11 stores data for one sector in the host system. Command to transfer. The control logic 11 controls the data buffer 10 and the host interface 2 to transfer data for one sector to the host system (step 503). When this is completed, the address register 4 is advanced by one sector, and the count register 5 1 is subtracted and the CPU 14 is notified that the transfer has been completed. As long as there is data to be transferred to the host system, the CPU 14 repeats this control. When all the read data has been transferred, the CPU 14 sets a code indicating that there is no error in the status register 7 in the host interface 2, notifies the host system that the execution of the instruction has ended, and ends the processing. .

  8 and 9 are flowcharts showing a procedure for writing data into the EEPROM module 1. The CPU 14 refers to the start address set in the host interface 2 and the address conversion table in the management table, and determines the block on the EEPROM module 1 allocated to the address to which the host system intends to write (step 601). ). If the block on the EEPROM module 1 corresponding to the address designated by the host system has already been allocated and the request from the host system does not rewrite all of the data in the block, the data that cannot be rewritten in the block Are read into the data buffer 10 (steps 602 to 604). The procedure for reading data from the EEPROM module 1 to the data buffer 10 has been described with reference to the flowchart of FIG. The process of FIG. 6 is repeated until all the data in the block that is not overwritten is read into the data buffer 10. Next, the transfer of write data from the host system to the data buffer 10, the data write process from the data buffer 10 to the EEPROM module 1, the error process, and the like as described in detail later are executed (steps 605 to 611).

  FIG. 10 shows a procedure for transferring write data from the host system to the data buffer 10. The CPU 14 sets the data buffer 10 to the write mode (step 701), and sets an address on the data buffer 10 in which data transferred from the host system is stored as a write address to the buffer (step 702). Thereafter, the control logic 11 is instructed to transfer data for one sector from the host system. The control logic 11 controls the data buffer 10 and the host interface 2 to receive one sector of data from the host system, and when this is completed, notifies the CPU 14 that the transfer has been completed (step 703). The process of FIG. 10 is continued as long as data to be transferred from the host system remains and data for the block to be written to the EEPROM module 1 in the data buffer 10 is insufficient. When the transfer from the host system is completed, the CPU 14 refers to the start address set in the host interface 2 and the table for managing the unused block, and as described above, handles the unused block chain to process the data. An unused block on the EEPROM module 1 to which one block of data stored in the buffer 10 is to be written is determined, and writing is performed on the EEPROM module 1.

  FIG. 11 is a flowchart showing a procedure for writing one page of data in the data buffer 10 to the EEPROM module. The CPU 14 initializes the EEPROM module 1 and the data buffer 10 if necessary (steps 801 and 802), and then sets the top address of the page to be written in the address generator 13 (step 803). Sets the start address of the data to be written as the read address of the buffer (step 804). Then, the control logic 11 is instructed to execute a predetermined sequence for writing data. The control logic 11 sets the multiplexer 9 so that the write data from the data buffer 10 flows to the EEPROM module 1, and writes the data while incrementing the contents of the address generator 13 (step 805). Further, the ECC generator / checker 12 is controlled to generate an ECC code from these data, and this code is recorded together with the data (step 806). The processing in FIG. 11 is continued until a writing error occurs or data for one block is completely written (step 807). If data writing cannot be performed normally, error processing is performed, blocks on the EEPROM module 1 to which data for one block is to be written are reassigned, and writing is performed again. When writing is completed normally, the contents of the management table are updated.

  When all the data requested by the host system has been recorded, or when the process is interrupted because recovery from an error is impossible, the CPU 14 sets a predetermined code in the status register 7 in the host interface 2 and stores it in the host system. Notify that the execution of the instruction is complete. At an appropriate timing when an access command is not written to the command register 6 of the host interface 2, the CPU 14 in the controller sequentially erases the unerased blocks while chaining the unused block management table as described above. Go.

  In the above embodiment, the EEPROM module 1 is controlled by the controller operable in parallel with the host system via the host interface 2, but is directly controlled by the CPU of the host system. It may take a form. In addition, the present invention can be variously modified and used without departing from the gist thereof.

1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG. 6 is a diagram (part 1) for explaining the operation of a table for managing unused blocks in the embodiment. It is FIG. (2) for demonstrating operation of the table which manages an unused block in a present Example. It is a figure which shows the structure of the comparison table for address conversion in a present Example. 4 is a flowchart for explaining a process of reading data from the EEPROM module 1 in the present embodiment. 4 is a flowchart for explaining a process of reading data from the EEPROM module 1 to the data buffer 10 in the present embodiment. 6 is a flowchart for explaining read data transfer processing from the data buffer 10 to the host system in the present embodiment. 5 is a flowchart (part 1) for explaining a data writing process to the EEPROM module 1 in the present embodiment. 4 is a flowchart (part 2) for describing a data writing process to the EEPROM module 1 in the present embodiment. 4 is a flowchart for explaining write data transfer processing from the host system to the data buffer in the present embodiment. 4 is a flowchart for explaining a process of writing data in a data buffer 10 to the EEPROM module 1 in the present embodiment.

Explanation of symbols

1 EEPROM module (memory means)
2 ... Host interface 3 ... Data register 4 ... Address register 5 ... Count register 6 ... Command register 7 ... Status register 8 ... Error register 9 ... Multiplexer 10 ... Data buffer 11 ... Control logic 12 ... EEC generator / checker 13 ... Address generator 14 ... CPU that executes erasure processing, write processing, copy processing, etc. of unerased blocks
15 ... Working RAM
16 ... Control program ROM

Claims (2)

A memory cell array having a plurality of blocks each of which can be selectively written and erased;
Management means having an erasure flag indicating whether each of the plurality of blocks has been erased;
Control means for determining an unused block among the plurality of blocks and writing new data to the unused block;
Means for setting the erase flag corresponding to a block in which old data to be rewritten is recorded;
Means for selectively erasing the block in which the erasure flag is set;
Means for associating a logical address associated with a physical address of a block having the old data with a physical address of a block in which the new data is written;
Each of the plurality of blocks is an erase unit as a unit smaller than a nonvolatile semiconductor memory chip in which the memory cell array is realized. In a data rewrite control method of a nonvolatile semiconductor memory device including a memory cell array each having a plurality of blocks that can be selectively written and erased,
Each of the plurality of blocks is an erase unit as a unit smaller than the nonvolatile semiconductor memory chip in which the memory cell array is realized,
Of the plurality of blocks, determining an unused block;
Writing new data to the unused block without erasing the block having the old data to be rewritten;
Associating a logical address associated with a physical address of a block having the old data with a physical address of a block in which the new data is written;
Notifying the host system that writing to the unused block has ended;
And a step of selectively erasing the block in which the old data has been recorded after the notifying step.

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