TW200822123A - Flash memory device and method for controlling erase operation of the same - Google Patents

Abstract

A non-volatile memory device includes first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines. A block selection unit connects given local word lines to global word line, respectively, in response to a block selection signal. A first bias voltage generator is configured to apply at least first and second erase voltages to the global word lines during an erase operation, the first erase voltage being applied to the global word lines during a first erase attempt of the erase operation, the second erase voltage being applied to the global word lines during a second erase attempt, where the second erase attempt is performed if the first erase attempt did not successfully perform the erase operation. The first and second erase voltages being positive voltages. A bulk voltage generator applies a bulk voltage to a bulk of the memory cells during the erase operation.

Description

200822123 IX. Description of the Invention: [Technical Field] The present invention relates to semiconductor memory elements, and more particularly to a flash memory element in which a cause can be prevented The reliability of the erase operation is reduced by a leakage current in a block-based erase operation, and a method of controlling the erase operation of the flash memory device. [Prior Art] Generally, a flash memory component can be classified into an N 0 R type and a NAND type, wherein the NOR type is generally used to store a small amount of information at a high speed, and the NAND type is generally used. To store a lot of information. The flash memory component performs a read operation, a program operation, and an erase operation. The terms "pr gram 〇perati ο η" and "erase operation" refer to the use of electrons to be injected into the floating gate and to remove electrons from the floating gate in one or The operation of storing data in a plurality of memory cells. For example, in the stylized operation, only selected memory cells of a plurality of memory cells included in a memory cell block are programmed. The erase operation of the flash memory component is performed when the electrons present in the floating gate of the memory cell are released toward the P-well region by FN tunneling. In the erasing operation, the data stored in all the memory cells included in the memory cell block are simultaneously erased. That is, the erase operation is performed on the basis of a memory unit block. Fig. 1 is a circuit diagram for explaining a memory unit and a transfer gate of an erase operation of a conventional flash memory device. In an erasing operation, the application 200822123 adds a bias voltage Vb of ον to an overall word line GWL, and applies a bulk voltage VBK1 of 20V to the P-well region of the memory cells CA1 to CAn and CB1 to CBn ( Where η is an integer). The sources and drains of the memory cells CA1 to CAn and CB1 to CBn are floated. In addition, a gate having a voltage (Vcc) level, a gate select signal BKSEL1 to a NM0S transistor NM1, is applied, wherein the NMOS transistor NM1 is connected to a selected (ie, erased) memory. A local word line WL1 of the body unit block A is between the whole word line GWL. A body voltage VBK2 having a voltage of 0 V is applied to a substrate (not shown) of the NMOS transistor NM1. The NMOS transistor NM1 is turned on to return to the block select signal BKSELI, and the local word line WL1 is connected to the overall word line GWL. As a result, the voltage of the local word line WL1 becomes 0V, and the control gates (not shown) connected to the local word lines WL1 of the memory cells CA1 to CAn and the memory cells CA1 to CAn The P-well interval produces a voltage difference of 20V. Thus, when the electrons of the floating gates of the memory cells CA1 to CAn are released toward the P-well regions, the erase operation of the memory cell blocks A is performed. At the same time, the gate of an NMOS transistor NM2 is applied with a block select signal BKSEL2 of 0V, wherein the NMOS transistor NM2 is connected to a memory cell block that is not selected (ie, will not be erased). A local word line WL2 of B is between the overall word line GWL. Further, a body voltage VBK2 of 0 V is applied to the substrate of the NMOS transistor NM2. The NMOS transistor NM2 is turned off to return to the block select signal BKSEL2, and the local word line WL2 is separated from the overall word line GWL. This floats the local word line WL2. Thereafter, a body voltage VBK1 applied to the P-well region of the memory cells CB1 to CBn is applied to the local word line WL2 by a capacitive coupling 200822123 phenomenon, and thus the local word line is applied The voltage level of WL2 is raised to approximately 19V. This results in a voltage difference between the local word line WL2 and the P-well section of the memory cells CB 1 to CBn, the voltage difference of the IV being insufficient for floating gates from the memory cells CB1 to CBn. Release the electrons. As a result, when the erase operation is performed on the memory cell block A, the erase operation is not performed on the memory cell block B. Although the NMOS transistor NM2 is turned off, a leakage current is generated in the NMOS transistor NM2. Thus, the voltage level of the local word line WL2 is raised to a voltage level close to the body voltage VBK1, which is gradually reduced. This results in an increase in the voltage difference between the control gates of the memory cells CB 1 through CBn and the P-well regions. Therefore, a shallow erase may be caused, i.e., a small amount of electrons may be unintentionally released from the floating gates of the memory cells CB1 to CBn. When the number of memory cell blocks included in a flash memory element is increased, the erase interference like a light erase becomes more significant. For example, each time the memory cell blocks are subjected to an erase operation one by one, a shallow erase phenomenon is repeatedly generated in the memory cells of the memory cell block which should not be erased. Therefore, when the threshold voltage of the corresponding memory cell is gradually reduced, it is highly likely that the read operation fails. Furthermore, a rapid stylization phenomenon occurs in which, when the number of erasing operations increases, the threshold voltage rises above a target voltage during a stylized operation, or a slow erase phenomenon occurs, wherein an erase operation occurs. The threshold voltage cannot be sufficiently reduced to a target voltage. Next, 200822123 will be described in more detail with reference to Fig. 2. Fig. 2 is a graph showing a slow erase characteristic and a fast stylized characteristic depending on the number of times of an erase operation in the prior art. Although the stylization or erasing operation is performed in the same state, when the stylization or erasing operation is performed, the threshold voltage of a memory cell increases, and finally becomes higher than a target voltage. This increase in threshold voltage results in a fast implementation of the stylized operation or a slow implementation of the erase operation. This phenomenon occurs when the voltage difference between the word lines and the body is high during the erasing operation. In other words, the higher the voltage difference between the word lines and the body during the erasing operation, the more severe the fast stylization and slow erasing. Figure 3 is a graph showing the characteristics of a slow erase characteristic and a fast stylized characteristic depending on the level of a erase voltage in the prior art. It can be seen that if the voltage difference between the word lines and the body is high (high potential erasing), the erasing operation is performed, and the rapid stylization phenomenon and the slow erasing phenomenon are suddenly generated. However, if the voltage difference between the word lines and the body is low (low potential erase), the erase operation is performed, and the fast stylization phenomenon and the slow erase phenomenon are gradually generated. To prevent the rapid stylization and slow erasing described above, the erase operation should be performed when there is a low voltage difference between the temple line and the body. In this case, it is possible to extend an erasing operation time and possibly improperly implement the erasing operation. If the erase operation is not implemented properly, the corresponding block is marked as an invalid block that is not used. This reduces the number of available blocks and reduces data storage capacity. SUMMARY OF THE INVENTION Thus, embodiments of the present invention are directed to an operation in which electrons are released from the floating gates of the memory cells, e.g., an erase operation. The erase operation of this embodiment is implemented to reduce the leakage current of the memory cells that are not selected for the erase operation. In one embodiment, a first positive voltage is applied to the overall word line during a erase operation (first attempt). If the erase operation is not properly performed, the erase operation (second attempt) is performed again by applying a second voltage less than the first voltage to the overall word line. The erase attempt is repeated a predetermined number of times or until the erase operation has been successfully performed, whichever occurs first. The voltage applied to the overall word line is reduced after each failed attempt to increase the voltage difference of the erase operation. In one embodiment, a non-volatile memory component includes first and second memory cell blocks, each memory cell block includes a plurality of memory cells and includes a local drain selection line and a local source. The pole selection line and the plurality of local word lines. A block selection unit respectively connects a given local word line to the overall word line in response to a block selection signal. a first bias generator configured to apply at least first and second erase voltages to the overall word line during an erase operation, the first erase voltage being erased at the first erase operation The trial period is applied to the overall word line 'the second erase voltage is applied to the overall sub-wires during the second erase attempt' if the first erase attempt does not successfully perform the erase In operation, the second erase attempt is performed. The first and second erase voltages are positive voltages. A body voltage generator applies a body voltage to one of the body of the memory cells during the erase operation. In this embodiment, each time a new erase attempt is performed, the erase voltage applied to the overall word line is reduced by a given voltage -10- 200822123, wherein a predetermined number of failed wipes After a try, stop a given erase operation. In one embodiment, a flash memory component includes a plurality of memory cell blocks, each memory cell block including a local drain select line, a local source select line, and a plurality of local word lines. And a plurality of billion element units are connected to the local drain selection line, the local source selection line, and the plurality of local word lines. A block selection unit respectively connects the local word lines to the overall word line in response to a block selection signal. A first bias generator applies a positive erase voltage to the overall word line during an erase operation. A body voltage generator is configured to apply a first body voltage to one of the memory cells during a first erase attempt of the erase operation and to perform the first erase if not properly implemented Attempts to apply a second body voltage to the body during the second erase attempt. If the first erase attempt does not erase all of the memory cells selected for the erase operation, then the first erase attempt is considered not properly implemented. In one embodiment, a method of erasing a non-volatile memory element includes connecting a local word line of a selected block and an overall word line to respond to a block select signal. Applying a first erase voltage to the overall word line and a first body voltage higher than the first erase voltage to a body such that a voltage difference between the local word lines and the body is A first potential difference is used to perform a first erase attempt of an erase operation. The method further includes determining if the first erase attempt has been properly performed. A second erase attempt of the erase operation is performed if it is determined that the first erase attempt is not properly performed. The second erase attempt includes applying a second erase -11-200822123 voltage to the overall word line and a second body voltage to the body to increase a voltage difference between the local word lines and the body To a second potential difference. The second erase voltage may be less than the first erase voltage. The second body voltage may be greater than the first body voltage. The first erase voltage and the second erase voltage may be different, and the first body voltage and the second body voltage may be different. A flash memory device in accordance with a first embodiment of the present invention includes a plurality of memory cell blocks, a block selection unit, a first bias generator, and a body voltage generator. Each memory cell block includes a partial drain select line, a local source select line, and a plurality of local word lines, and a plurality of memory cells are connected to the local drain select line, the local source select Line and the plurality of local word lines. The block selection unit respectively connects the local word lines to the overall word lines in response to a block selection signal. The first bias generator applies a positive erase voltage to the overall word line during an erase operation, and if there is a memory cell that is not erased, reducing the erase voltage and applying a decrease The voltage is erased to the overall word line to perform the erase operation again. The body voltage generator applies a body voltage to one of the body of the memory unit during the erasing operation. The first bias generator can generate the erase voltage such that the voltage difference between the local word lines and the body becomes 1 5 V during an initial erase operation, and the erase voltage is reduced to When the erase operation is performed, the voltage difference between the local word lines and the body becomes higher than 15 V. At this time, the first bias generator can have a linear function, a quadratic function or an exponential function at 0. 1 to 0. This erase voltage is reduced under the 5V reference. -12- 200822123 The flash memory component can further include a page buffer for reading data stored in the memory cells, and a Y-decoder for outputting in the page buffer The stored data is to a data I/O buffer and the first bias generator. If the 尙 not erased material of the data output from the Y-decoder is detected, the first bias generator can reduce the erase voltage to perform the erase operation again. A flash memory device in accordance with a second embodiment of the present invention includes a plurality of memory cell blocks, a block selection unit, a first bias generator, and a body voltage generator. Each memory cell block includes a partial drain select line, a local source select line, and a plurality of local word lines, and a plurality of memory cells are connected to the local drain select line, the local source select Line and the plurality of local word lines. The block selection unit respectively connects the local word lines to the overall word lines in response to a block selection signal. The first bias generator applies a positive erase voltage to the overall word line during an erase operation. The body voltage generator applies a body voltage to one of the body of the memory unit during the erasing operation, and if there is a memory unit that is not erased, for the re-execution of the erasing operation, increasing The body voltage and an applied body voltage are applied to the body. The body voltage generator can generate the body voltage such that a voltage difference between the local word lines and the body becomes 1 5 V during an initial erasing operation, and the body voltage is reduced to perform the erasing again In operation, the voltage difference between the local word lines and the body becomes higher than 15 V. At this time, the body voltage generator can increase the body mjE by a linear function, a quadratic function -13-200822123 number or an exponential function under the scale of 0.5 to IV. The flash memory component can further include a page, a buffer, and a data stored in the memory cells, for outputting data stored in the page buffer. To _ I _ Ι / 〇 buffer and the body voltage generator. If the remaining data of the data output from the Υ-decoder is detected, the body voltage generator can increase the body power; |g, & ^ stomach performs the erase operation. According to a third embodiment of the present invention, a flash memory cell yak package has a plurality of memory cell blocks, a block selection unit, a _{flat g generator, and a body voltage generator. Each memory cell block includes a partial drain select line, a local source select line, and a plurality of local word lines, and a plurality of memory cells are connected to the local drain select line, the local source select Line and the plurality of local word lines. The block selection unit respectively connects the local word lines to the overall word lines in response to a block selection signal. The first bias generator applies a positive erase voltage to the overall word line during an erase operation, and if there is a memory cell that is not erased, reducing the erase voltage and applying a decrease The voltage is erased to the overall word line to perform the erase operation again. The body voltage generator applies a body voltage to one of the body of the memory unit during the erasing operation, and if there is a memory unit that is not erased, for the re-execution of the erasing operation, increasing The body voltage and an applied body voltage are applied to the body. In the above, during an initial erasing operation, the first bias generator and the body voltage generator can respectively generate the erase voltage and the voltage of the body-14-200822123, so that the local word lines and the The voltage difference between the bodies becomes 15V. When the erase operation is performed again, the body voltage generator can increase the body voltage and the first bias generator can reduce the erase voltage so that a voltage difference between the local word lines and the body becomes high. At 1 5 V. At this time, the first bias generator can be a linear function, a second order function or an exponential function at 0. 1 to 0. This erase voltage is reduced by the 5V reference. The body voltage generator can be a linear function, a quadratic function or an exponential function at 0. The erase voltage is increased under the 5 to IV reference. The flash memory component can further include a page buffer for reading data stored in the memory cells, and a Y-decoder for outputting data stored in the page buffer a data I/O buffer, the body voltage generator, and the first bias generator. Meanwhile, if the data of the data output from the Y-decoder is not erased, the first bias generator reduces the erase voltage and the body voltage generator increases the body voltage to implement again This erase operation. The flash memory component can further include an X-decoder for decoding a column of address signals and outputting the block select signal to the high voltage generating unit. Furthermore, the flash memory component can further include a second bias voltage generator for applying a predetermined operating voltage according to any one of the programming, reading and erasing operations. To the local drain selection line and the local source selection line. The first bias generator may include a first 杲 circuit (pUmp ciiruit) for generating a read voltage required for a read operation in response to a read -15-200822123 command; a second pump circuit for Generating a stylized voltage required for a stylized operation in response to a stylized command; a third pump circuit for generating the erase voltage in response to an erase command and if the output of the Y-decoder is detected The data is not erased, the erase voltage is reduced and the output is reduced by a subtraction voltage; and a bias selection unit is configured to select the read voltage, the programmed voltage or the erase voltage to respond An operation command signal and a selection voltage are respectively output to the overall word line. At this time, the bias selection unit may include a selection signal generator for generating a selection signal according to the operation instruction signal, and a plurality of selection circuits respectively connected to the overall word line for respectively outputting the signals Reading one of the voltage, the stylized voltage, and the erase voltage to the overall sub-line of the temple to return to the selection signal. According to a first embodiment of the present invention, there is provided a method of controlling an erase operation of a flash memory device, the method comprising the steps of: (a) electrically connecting a local word line and an overall word of a selected block, respectively The line responds to a block selection signal; (b) applying a positive erase voltage to the overall word line and a body voltage higher than the erase voltage to one of the memory cells according to an erase command The body is configured to perform an erase operation; (c) determining whether the erase operation has been properly performed; and (d) if it is determined that the erase operation is not properly performed, by reducing the erase voltage to make the portions The erase operation is performed again by the voltage difference between the word line and the body becoming larger. The steps (c) and (d) may be repeated a plurality of times while reducing the erase voltage as far as possible to a predetermined level, and including if the erase operation is not properly performed until the predetermined number of times, A corresponding block -16 - 200822123 is treated as an invalid block. According to a second embodiment of the present invention, there is provided a method of controlling an erase operation of a flash memory device, the method comprising: (a) electrically connecting a local word line and an overall word line of a selected block, respectively. Responding to a block selection signal; (b) applying a positive erase voltage to the overall word line and a body voltage higher than the erase voltage to a body of a memory cell according to an erase command a erase operation; (c) determining whether the erase operation has been properly performed; and (d) if it is determined that the erase operation is not properly performed, by adding the erase voltage to cause the local word lines The erase operation is performed again by the voltage difference between the body and the body becoming larger. The steps (c) and (d) may be repeated a plurality of times while increasing the erase voltage as far as possible to a predetermined level, and including if the erase operation is not properly performed until the predetermined number of times, A corresponding block is treated as an invalid block. According to a third embodiment of the present invention, there is provided a method of controlling an erase operation of a flash memory device, the method comprising the steps of: (a) electrically connecting a local word line and an overall word of a selected block, respectively The line responds to a block selection signal; (b) applying a positive erase voltage to the overall word line and a body voltage higher than the erase voltage to one of the memory cells according to an erase command The body performs an erase operation; (C) determines whether the erase operation has been properly performed; and (d) if it is determined that the erase operation is not properly performed, by simultaneously controlling the erase voltage and the body voltage The erasing operation is performed again to increase the voltage difference between the local word lines and the body. The steps (C) and (d) may be repeated multiple times while reducing the voltage of the wipe -17-200822123 as far as possible to a predetermined level and increasing the body voltage as far as possible to a predetermined level, and if Until the erase operation is not properly performed until the predetermined number of times, a corresponding block is regarded as an invalid block. Furthermore, the erase voltage and the body voltage can be set such that the voltage difference between the local word lines and the body is 15V or higher. Can be 0. 1 to 0. The 5V reference reduces the erase voltage to increase the voltage difference between the local word lines and the body in a range that causes the voltage difference to become at least 1 5 V, or can reduce the erase voltage by an exponential function so that The voltage difference between the local word lines and the body is increased within a range that causes the voltage difference to become at least 1 5 V. Can be 0. The erase voltage is increased by a 5 to IV reference to increase the voltage difference between the local word lines and the body in a range in which the voltage difference becomes at least 1 5 V, or the erase voltage can be increased by an exponential function And increasing the voltage difference between the local word lines and the body in a range that causes the voltage difference to become at least 1 5 V. [Embodiment] Various embodiments in accordance with the present invention will now be described with reference to the accompanying drawings. Since various embodiments have been proposed in order to enable those skilled in the art to understand the invention, the various embodiments of the invention are not limited to the scope of the invention. Figure 4 is a block diagram of a flash memory component in accordance with an embodiment of the present invention. A flash memory component 100 includes a memory cell array 110, an input buffer 120, a control logic circuit 130, a high voltage generator 140, an X-decoder 150, and a block. The selection unit 160, the page buffer 170, a Y-decoder 180, and a data I/O buffer -18-200822123 1 90. The memory cell array 110 includes memory cell blocks MB 1 to Μ BK (where K is an integer), and each memory cell block has a plurality of memory cells (not shown). The input buffer 120 receives an instruction signal CMD or an address signal ADD and outputs them to the control logic 130. The control logic circuit 130 receives the command signal CMD or the address signal ADD in response to the external control signals /WE, /RE, ALE, and CLE. The control logic circuit 130 generates one of a read command READ, a program command PGM and an erase command ERS to respond to the command signal CMD. The control logic circuit 130 generates a column address signal RADD and a row address signal CADD to echo the address signal ADD. The high voltage generator 140 includes a body voltage generator 40, a first bias generator 50 and a second bias generator 60. The body voltage generator 40 generates a body voltage VCB to return the read command READ, the program command PGM and the erase command ERS, and supply the body voltage VCB to the P-well region of the memory cells. More specifically, the body voltage generator 40 generates a low voltage level (e.g., 0V) body voltage VCB to return the read command READ or the stylized command PGM. The body voltage generator 40 also generates a body voltage VcB of a high voltage level (e.g., 20V) to echo the command ERS. Meanwhile, if the cell having the erase operation is not properly implemented according to the data output from the Y-decoder 180 after the erase operation, the level of the body voltage V C B can be controlled. For example, if the erase operation is not properly performed, the level of the body voltage Vcb can be increased by 〇 5 or 1 V reference, and if appropriate, the increased width of the body voltage VeB can be changed. The first bias generator 50 generates a drain bias voltage Vc3D and a source bias -19-200822123 voltage Vu to return one of the read command READ, the stylized command PGM, and the erase command ERS, and The drain bias voltage Vcd is supplied to an overall drain select line GDSL and the source bias voltage Vm to an overall source select line GSSL. More specifically, the first bias generator 50 produces a high voltage level (e.g., 4. 5 V) bucker bias V. d and source bias voltage V. s back should read the instruction READ. The first bias generator 50 also generates a drain bias VCD of internal voltage level (VCC, not shown) and a source bias VCS of low voltage level to respond to the programmed command PGM. Furthermore, the first bias generator 50 generates a low voltage level of the drain bias V (3D and the source bias V (3S in response to the erase command ERS. The second bias generator 60 generates the word) The line bias voltages VwF1 to VWFJ (where: ί is an integer), the word line bias voltages Vwsl to VwsJ (where J is an integer) or the word line bias voltages VWT1 to VwtH (where J is an integer) to return the read command READ And one of the stylized instruction PGM and the erase command ERS and a decode signal DEC, and supply the generated word line bias to the overall word line GWL1 to GWLJ (where J is an integer). More specifically The second bias generator 60 generates the word line bias voltages VWF1 to VWFJ to return the read command READ. The second bias generator 60 generates the word line bias voltages Vws1 to VwSJ to respond. Stylized instruction PGM. The first 'bias generator 60 generates a sub-wire bias voltage VwtI to VwtI to echo the instruction ERS. In this case, when the erase command ERS is input, the second bias The generator 60 generates a positive voltage higher than 0 V. After the erase operation, if there is a 尙 not output according to the Y-decoder 1 800 The data suitably implements the unit of the erasing operation, and the second bias generator 60 controls the level of the word line bias voltages Vwt 1 to VwtJ of -20-200822123. For example, if the 尙 is not properly implemented In addition to the operation, the second bias generator 60 can be 0. 1 v to 0. The 5V reference reduces the word line bias voltages VwTi to VwT; [the level and output of the reduced word line bias. The reduced width of the word line bias voltages Vwt 1 to VwtJ can be changed if necessary. If the erase operation is not properly performed, the body voltage generator 40 and the second word line voltage generator 60 control the output voltage. This will perform the erase operation again (i.e., perform a double erase operation). The re-wiping operation is performed by increasing the voltage difference between the word lines and the body. In order to increase the voltage difference between the word lines and the body, the body voltage generator 40 and the second word line voltage generator 60 have only one voltage generator or the body voltage generator 40 and the second word. Both of the line voltage generators 60 can control the level of the output voltage. This will be described in detail later. The X-decoder 150 decodes the column address signal R A D D and outputs a decoded signal DEC. The block selecting unit 160 selects one or more of the memory cell blocks MB1 to MBK to echo the decoded signal DEC, and respectively connects a selected memory cell block (or a memory cell block). Local word lines WL11 through WL1 (see Figure 5) to the general word lines GWL1 through GWL. The block selecting unit 160 is connected to one of the drain select lines DSL1 to DSLK (see FIG. 5) of the selected memory cell block to the overall drain select line GDSL, and a source connecting the selected memory cell block. One of the pole selection lines SSL1 to SSLK (see Figure 5) to the overall source selection line GSSL. The construction and operation of the page buffer 170, the Y-decoder 180, and the data I/O buffer 190 are known to those skilled in the art, and thus the description thereof will be omitted. Fig. 5 is a detailed circuit diagram of the memory cell array, the block selecting unit, the second bias generator, the body voltage generator, and the X-decoder shown in Fig. 4. The memory cell block MB 1 of the memory cell array 110 includes memory cells M1 1 1 to M1]T (in which J and T are integers), a drain selective transistor DST1, and a source selective transistor. SST1. The memory cells M1 1 1 to M1 JT share the bit lines BL1 to BLT (in which the integer is), the local word lines WL11 to WL1 (wherein J is an integer), and a common source line C S L 1 . That is, the memory cells Μ 1 1 1 to Μ 1 1 T are respectively connected to the bit lines BL1 to BLT via the (odd) drain selection transistor DST1, and the memory cells Μ1Π to M1 JT The source selection transistor SST 1 is connected to the common source line CSL 1 via the (etc.) source. Further, the gates of the memory cells Μ 1 1 1 to M 1JT are connected to the local word lines WL1 1 to WL1]. The gate of the (odd) drain select transistor DST1 is coupled to the local drain select line DSL1, and the gate of the (etc.) source select transistor SST1 is coupled to a local source select line SSL1. The memory cell block Μ B 2 to Μ B K of the memory cell array 110 is of the same construction as the memory cell block MB 1 . The block selecting unit 160 includes a block switching unit 161 and a plurality of switching units PG1 to PGK (where K is an integer). The block switching unit 161 outputs the block selection signals BSEL1 to BSELK (where K is an integer) in response to the decoded signal DEC received from the X-decoder 150. The plurality of switching units PG1 to PGK are respectively configured in a manner corresponding to the memory cell blocks MB1 to MBK and are enabled or disabled to return to the equal block selection signals BSEL1 to BSELK. -22- 200822123 Each of the switching units PG1 to PGK includes a plurality of switching elements. For example, the switching unit PG 1 has switching elements GD 1 , G 1 1 to G1 and GS1. The construction and operation of the switching units PG2 to PGK are similar to the configuration and operation of the switching unit PG1. Therefore, it will be described in accordance with the operation of the switching unit PG1. Preferably, the switching elements GDI, Gl 1 to G1J and GS1 can be implemented using NMOS transistors. Hereinafter, the switching elements GDI, G11 to GH, and GS1 will be referred to as "NMOS transistors" for convenience of description. The block selection signal BSEL1 is input to the gates of the NMOS transistors GDI, G11 to G1J, and GS1. The NMOS transistor GDI has a source connected to the overall drain select line GDSL and a drain connected to the local drain select line DSL1. The NMOS transistors G11 to G1J have sources respectively connected to the general word lines GWL1 to GWL, and are respectively connected to the local word lines WL11 to WL1: [the drain. The NMOS transistor GS1 has a source connected to the global source select line GSSL and a drain connected to the local source select line SSL1. The NMOS transistors GDI, G11 to G1J and GS1 are turned on or off at the same time to return to the block selection signal BSEL1. More specifically, when the block selection signal BSEL1 is enabled, the NMOS transistors GDI, G11 to G1 are turned on: [and GS1, and when the block selection signal BSEL1 is disabled, the NMOS transistors are turned off. GDI, G11 to G1 and GS1. When the NMOS transistors GDI, G11 to G1 are turned on; [and GS1, the overall drain select line GDSL is connected to the local drain select line DSL1, and the global source select line GSSL is connected to the local source select line SSL1, and the general word line lines GWL1 to GWL are respectively connected to the local word lines WL1 1 to WL1 J. -23- 200822123 The second bias generator 60 includes first to third pump circuits 61, 62 and 63 and a bias selection unit 64. The first pump circuit 61 generates the read voltages VRD1 and VRD2 to return the read command READ. Preferably, the read voltage VrdI has a high voltage level (for example: 4. 5V), and the read voltage VRD2 has a low voltage level (for example: 0V). In a read operation of the memory cell array 110, the read voltage V rd 1 is applied to the local word line, wherein the memory cell is not selected (ie, the memory cell that will not be read) a gate is connected to the local word lines, and the read voltage VRD2 is applied to the local word line, wherein the gate of the memory cell (ie, the memory cell to be read) is selected Connect to the local word lines. The second pump circuit 62 generates a programmed voltage Vp. And the VPS to respond to the stylized instruction PGM. Preferably, the stylized voltages Vp. And the VPS has a high voltage level (for example: VPC = 18V, VPS = 10V). The stylized voltage Vp is programmed in one of the memory cell arrays 110. Applied to a local word line, wherein a gate of the memory cell to be programmed is connected to the local word line, and the stylized (or pass) voltage VPS is applied to the local word line, The gates of the memory cells that are not programmed are connected to the local word lines. Furthermore, the third pump circuit 63 generates a positive erase voltage Vers which is higher than 0 V to echo the command ERS. In other words, the third pump circuit 63 generates the erase voltage Vers to apply a voltage higher than 0 V to the word line of one of the selected blocks during the erase operation. At the same time, in the block in which the erase operation is performed according to the positive erase voltage Vers, the voltage difference between the word line and a body is lowered. Preferably, the erase voltage Vers is generated in a level in which the voltage difference between the word lines and the body is about 15 to 20 V in the block in which the erase operation is performed. Meanwhile, if the Y-decoder (refer to the component symbol 180 in FIG. 4) detects the non-erased state in the operation of determining whether the erase operation has been properly performed (for example, 〇 The data (that is, the erase operation has failed), then the third pump circuit 63 can be 0. 1 to 〇.  The 5 V reference reduces the erase voltage VERS2 level and outputs a reduced erase voltage Vers. If appropriate, the reduced width of the erase voltage Vers can be changed. [What does it mean to reduce the width? The erase voltage Vers can be reduced by a linear function, a quadratic function or an exponential function. Thus, the voltage difference between the word lines and the body is increased and the erase operation is performed again in accordance with the increased voltage difference. The bias selection unit 64 selects the read voltages VRD1 and Vrd2 in response to the decoded signal DEC received from the X-decoder 150 and then outputs the selected read voltages VRD1 and VRD2 to the overall word lines, respectively. GWL1 to GWLJ are biased as the word line lines VWF1 to VwF; [, the program voltage Vp is selected. And VPS and then respectively outputting the selected programming voltages Vp6 and VPS to the overall word lines GWL1 to GWLJ as word line bias voltages Vwsl and Vws (where J is an integer), or selecting the erase voltage乂^5 and then the selection erase voltage VERS is output to the overall word line lines GWL1 to GWU as the word line bias voltages VwtI to VwTJ. The body voltage generator 40 generates a high body voltage VCB to be applied to a body (eg, a P well region) during an erase operation to echo the instruction ERS, wherein the memory is formed in the body Body unit-25- 200822123

Mill to MUTU and T series integer). The body voltage VcB may be generated in a voltage level range of 丨5 to 2 〇ν between the word lines and the body in a block in which the erase operation is performed. At the same time 'if the non-erase state in the data output by the Y-decoder (refer to the component symbol 1 8 第 in FIG. 4) is detected in the operation of determining whether the erase operation has been properly performed (for example, The data of the device (ie, the erase operation has failed), the body voltage generator 40 can increase the level of the body voltage VCB and output an increase of the body voltage VCB from .5 to IV. The width of the bulk voltage V C B can be varied, if appropriate. The body voltage V C : B can be increased by a linear function, a quadratic function or an exponential function. Thus, the voltage difference between the word lines and the body is increased and the erase operation is performed again in accordance with the increased voltage difference. As described above, the erase operation is performed in a state where a positive voltage is applied to the overall word line. If the erase operation is not properly performed, the voltage difference between the word line and the body is increased by controlling the output voltage of one or both of the third pump circuit 63 and the body voltage generator 40. This erase operation is performed again. The output voltage of the third pump circuit 63 or the body voltage generator 40 can be controlled so that the voltage difference between the word lines and the body is 15V or higher. Fig. 6 is a detailed circuit diagram of the memory unit, the transfer gate, the body voltage generator, and the bias selection unit shown in Fig. 5. Referring to Fig. 6, the bias selection unit 64 includes a selection signal generator 65 and selection circuits S1 to S (where J is an integer). The selection signal generator 65 generates selection signals SL1 to SLJ based on the decoded signal DEC. Each of the selection circuits S1 to SJ includes switches SW11 to -26-200822123 SW15........ SWJ1 to SWJ5 which are respectively connected to the overall word lines GWL1 to GWL: [. Each of the selection circuits S1 to SJ receives the read voltages VRD1 and VRD2, the programmed voltages Vpc and Vps and the erase voltage Vers, and the output word line bias voltages VwfI to VwfJ, Vws1 to VwsJ or VwtI to VwtJ to the overall word line GWL1 to GWL to return the selection signals SL1 to SLJ. This will be described in more detail later. For example, the switches SW11 to SW15 of the selection circuit S1 are connected to the read voltages VRD1 and VRD2, respectively, and the stylized voltages Vp. And V P s and the erase voltage V E R s and the overall word line G W L 1 . The switches SW11 to SW15 are turned on or off in accordance with the logic 位 of the bits B1 to B5 of the selection signal S L 1 . In this case, in the case where the switches SW1 1 to SW15 are implemented using an NMOS transistor, when the logic turns of the bits B1 to B5 are 1, the switches SW11 to SW15 are turned on. Meanwhile, when the logical turns of the bits B1 to B5 are 0, the switches S W 1 1 to S W 1 5 are turned off. For example, when one of the switches SW1 1 and SW12 is turned on, one of the read voltages VRD1 and VRD2 is input to the overall word line GWL1 as the word line bias VWF1. Furthermore, when one of the switches SW13 and SW14 is turned on, the voltage Vp is programmed. And one of the VPSs is input to the overall word line GWL 1 as the word line bias voltage Vwsl. Further, when the switch Swi5 is turned on, the erase voltage VERS is input to the overall word line GWL1 as the word line bias voltage VwtI. In this case, since the selection signal generator 65 causes one of the bits B1 to B5 to generate a logical 値1 and causes the remaining bits to generate a logical 値〇, one of the switches SW1 1 to SW15 is turned on. , and turn off the remaining switches of -27-200822123. As a result, one of the read voltages Vrd1 and Vrd2, the programmed voltages Vp (3 and Vps, and the erase voltage Vers) is applied to the overall word line GWL1. The construction of the selection circuits S2 to SJ and The operation is similar to the configuration and operation of the above-described selection circuit S 1. It is shown in Fig. 6 that each of the selection circuits si to ST has five switches. However, it is noted that the selection circuits S1 can be changed or modified. The construction of SJ. As is known to those skilled in the art, 'there are a number of methods for causing the selection circuits S1 to S to output the word line bias voltages Vwf1 to VwfJ, Vwsl to VwsJ or VwtI to VwtJ. Simplification of the figure, FIG. 6 only shows connections to the global word lines GWL1 and GWL, the local word lines WL1 1 , WL1], WLK1 and WLKJ and the memory units Μ111, Μητ, M1J1 NMOS transistors G1 1, GK1, G1J, and GKJ of M1JT, ΜΚ11, ΜΚ1Τ, MKJ1, and MKJT. The gates of the memory cells M1 1 1 to Μ 1 1 T are connected to the local word line WL 1 1, And the gates of the memory cells Μ 1 Π to Μ 1] The word line WL U is further connected to the local word line WLK1, and the gates of the memory cells ΜΚΠ to MKJT are connected to the local word line WLKJ. The source and the drain of the NMOS transistor G11 are respectively connected to the overall word line GWL 1 and the local word line WL1 1. The source and the drain of the NMOS transistor GK1 are respectively connected to the overall word line. GWL1 and the local word line WLK1. In addition, the source and the drain of the NMOS transistor G1J are respectively connected to the overall word line GWLJ and the local word line WL 1 J. The source of the NMOS transistor GKJ and The drain is connected to the overall word line GWL) and the local character -28-200822123 line WLKJ, respectively. Figure 7 is a flow chart depicting a method of controlling the erase operation of the flash memory device in accordance with an embodiment of the present invention. The erase voltage VwtJ and the body voltage vCB are set so that the erase voltage VwtJ has a positive voltage level and the difference between the erase voltage VWT] and the body voltage Vc:B is 15V (S701). Once the erase voltage VWTJ and the body voltage VCB have been set, the erase voltage VwT is immediately used according to a block selection signal BLKWL to perform an erase operation on the memory cell of a selected block with the body voltage VCB (S702). . After the erase operation is performed, it is determined whether the erase operation has been properly performed (S73). If all of the memory cells in the selected block have been erased, it is determined that the erase operation has been properly performed, in which case the erase operation is ended. On the other hand, if there is one or more memory cells that are not erased, it is determined that the erase operation is not properly performed and the erase voltage VWTJ and the body voltage VCB are reset to implement the wipe again. In addition to the operation. This will be described in more detail below. The number of erasing operations performed is increased by one (S 704). Then, it is determined whether or not the number of erasing operations performed is less than a predetermined number of times (S 7 0 5). If the number of erase operations performed is less than the predetermined number of times, the erase voltage VwtJ and the body voltage VCB are changed (S706). At this time, the erase voltage VwT and the body voltage VCB are changed so that the difference between the erase voltage VWTI and the body voltage Vu gradually becomes greater than 15V. A detailed method of changing the erase voltage VwT and the body voltage Vcb will be described later. If the erase voltage VwtJ and the body voltage VCB have been changed, then -29-200822123 is used to perform an erase operation (or erase operation HS702). The above steps are performed again (S703 to S705). If the erase operation is not completed within a given period, the selected memory block is marked as an invalid block (S707). In this embodiment, when the number of times of the erase operation is equal to the predetermined number of times, the selected memory block is marked. The erase operation of the flash memory device 100 which has been described in Fig. 7 will now be described in more detail with reference to Figs. 4 through 6. The control logic circuit 130 generates the erase command ERS to echo the external control signals /WE, /RE, ALE, and CLE and the command signal CMD, and generates the column address signal RADD based on the address signal ADD. The body voltage generator 40 of the high voltage generator 140 generates a high voltage level (eg, 17V) body voltage Vu to echo the command ERS, and supplies the generated body voltage VCB to the body material (P well region) The memory cell blocks MB1 to MBK are formed in the body material. Furthermore, the first bias generator 50 of the high voltage generator 140 generates a low voltage (e.g., 〇V) drain bias VC3D and a source bias VC3S to echo the command ERS. Thus, the drain bias voltage V6D is applied to the overall drain select line GDSL, and the source bias voltage V (3s is applied to the overall source select line GSSL. At the same time, the X-decoder 150 decodes the column Address signal RADD, and outputting the decoded signal DEC. The second bias generator 60 of the high voltage generator 140 generates the word line bias voltages VwtI to VWTJ to echo the erase command ERS and the decoded signal DEC, and Supplying the generated voltages to the overall word lines GWL1 to GWLI °, respectively, more particularly, the third pump circuit 63 of the second bias generator 60 generates an erase voltage VERS having a positive turn to respond In addition to the command ERS °, for example: the -30-200822123 erase voltage vERS is lower than the body voltage VeB supplied to the P-well region of the memory cell in the erase operation, and has a positive 値. Preferably, The difference between the body voltage Vu supplied to one of the P-well regions of a memory cell and the erase voltage Vers in the erase operation may be set to be higher than or equal to 5 V. The second bias generator 60 The bias selection unit 64 selects the erase voltage VERS to return the decoded signal. DEC, and outputting the selection voltage as the word line bias voltages VwtI to Vwt; [more specifically, the selection signal generator 65 of the bias selection unit 64 outputs the selection signals SL1 to SL The number of bits B1 to B5 is "00001" to return the decoded signal DEC. The switches SW15 to SWJ5 of the selection circuits S1 to SJ of the bias selection unit 64 are turned on, and the switches SW11 to SWJ1, SW12 to SWJ2 are turned on. SW13 to SWJ3 and SW14 to SWJ4 are turned off to wait for the selection signals SL1 to SLJ, and then the erase voltage VERS is input to the overall word lines GWL1 to GWL via the switches SW15 to SWJ5 as the The word line line is biased from VWT1 to VWTJ. Further, the block selecting unit 160 selects one of the memory cell blocks MB1 to MBK to return the decoded signal DEC, and respectively connects a selected memory cell block. The local word line is connected to the whole word line GWL1 to GWLJ. For example, if the memory unit block MB1 is selected, the block switching unit 161 of the block selecting unit 160 enables the block selection signal BSEL1 to be enabled. In return, the signal DEC should be decoded. And disabling all of the block selection signals BSEL2 to BSELK. As a result, only the switching unit PG1 of the block selection unit 160 is enabled, and all of the switching units PG2 to PGK are disabled. More specifically, at the same time, Turning on the switching elements GD1, G11 to G1 and GS1 of the switching unit PG1, and -31-200822123, switching elements GD2 to GDK, G21 to G2J.....GK1 of the switching units PG2 to PGK to GKJ, GS2 to GSK are all closed. Thus, the drain select line DSL1 of the memory cell block MB1 is connected to the overall drain select line GD S L , and the source select line S S L 1 is connected to the overall source select line GSSL. Therefore, when the low voltage level gate bias VC3D and the source bias voltage Vos are respectively applied to the drain select line DSL1 and the source select line SSL1, the drain select transistor DST1 and the source are turned off. Select transistor SST1. Thus, the drain and source of the memory cells Μ 1 1 1 to Μ 1 JT of the memory cell block MB 1 are floated. Further, the local word lines WL1 1 to WL1 of the memory cell block ΜΒ 1 are made [connected to the overall word lines GWL1 to GWLJ, respectively. As a result, the word line bias voltages VwtI to Vwt of the entire word line lines GWL1 to GWLJf are transferred to the local word lines WL11 to WL1, respectively. Therefore, a voltage difference (for example, 15 V or higher) is generated between the gate of the memory cell Μ 1 1 1 to Μ 1 JT of the memory cell block Μ B 1 and the body, and the voltage difference is caused by the voltage difference Electrons are released from the floating gates of the memory cells Μ 1 1 1 to Μ 1 Τ 1 to perform the erase operation of the memory cells Μ 1 1 1 to Μ 1 Τ. At the same time, the drain select lines DSL2 to DSLJ of the memory cell blocks ΜΒ2 to 隔离 are isolated from the overall drain select line GDSL, and the source select lines SSL2 to SSLJ and the overall source select line are also made. GSSL isolation. Further, the local word lines WL21 to WL2J........ WLK1 to WLKJ of the memory cell blocks MB 2 to MB 全部 are all isolated from the overall word lines GWL1 to GWU. Thus, the local word lines -32-200822123 WL21 to WL2J..... WLK1 to WLKJ are boosted by the body voltage VcB of a high voltage level (eg, 20V), wherein the body voltage VCB is applied to Memory cells of the memory cell blocks MB 2 to MBK. Therefore, a boost voltage V BST close to the body voltage Vc: B is generated in the local word lines WL21 to WL2J..... WLK1 to WLK: [. In this case, the operation of the NMOS transistors G21 to G2J.....GK1 to GKJ will be described in more detail with reference to FIGS. 8A and 8B, wherein the NMOS transistors G21 to G2J... ..... GK1 to GKJ are connected to the local word lines WL21 to WL2J........ WLK1 to WLKJ of the memory cell blocks MB2 to MBK and the overall word lines GWL1 to GWLJ between. Figures 8A and 8B show a cross-sectional view of the NMOS transistor GK1 and the potential of the NMOS transistor GK1, respectively. The NMOS

The operation of the crystals G21 to G2J.....GK2 to GKJ is similar to the operation of the NMOS transistor GK1. Therefore, the detailed description thereof is omitted for the sake of simplicity. Fig. 8A is a cross-sectional view of the NMOS transistor GK1 (-switching element) connected to the local word line WLK1 of the memory cell block MBK. The source 72 of the NMOS transistor GK1 is applied with a positive word line bias voltage VwtI, and the gate 74 of the NMOS transistor GK1 is applied with a block selection having a low voltage level (for example, 0V). Signal BSELK. The boosting voltage VBST is applied to the drain 73 of the NMOS transistor GK1. When the block selection signal BSELK is at a low level, the NMOS transistor GK1 is turned off. Furthermore, since the word line bias VwtI has the positive sign, the bit position of the source 72 region can be reduced to about Ev2 as shown in Fig. 8B. Thus, the amount of electrons introduced from the source 72 into a substrate 71 is reduced, and the amount of electrons introduced into the local word line -33 - 200822123 WLK1 is reduced, wherein the local word line WLK1 is connected to the drain 73. As a result, when the leakage current generated in the NMOS transistor GK is reduced, the local word line WLK1 is maintained at the boost voltage VBST level. Therefore, the material of the memory cell connected to the local word line WLK 1 is not erased. On the other hand, in the case where a 0V word line bias voltage VwtI is applied to the source 72, the bit position of the source 72 region can be increased to about Evl as shown in Fig. 8B. Thus, the amount of electrons introduced from the source 72 to the substrate 71 increases, and the amount of leakage current of the NMOS transistor GK1 increases. In this relationship, in order to reduce the leakage current of the NMOS transistor GK1, it is necessary to reduce the potential energy of the source region. After the erase operation is performed in the above state, it is determined whether all the memory cells of a block have been properly erased, and the erase operation has been performed on the block. This can be confirmed using the data output from the Y-decoder 180 via the page buffer 170. For example, if the data output by the Y-decoder 180 is "1", it can be determined that the erasing operation has been properly performed, wherein one of the strings is implemented in a state where 0V is applied to all the word lines. Read operation. If the data output by the Y-decoder 180 is "〇", it can be determined that the erase operation is not properly performed. In this prior art, after the determination of the erase operation failure, the units are marked as "invalid units". These units are not used afterwards, which results in a reduction in data storage capacity. However, in the present embodiment, 'the erase operation is performed again by increasing the voltage difference between the word lines and the body, so that the unit that does not pass the first erase operation can be implemented appropriately-34·200822123 A subsequent erase operation. This minimizes the premature marking of a memory block as an invalid block. A procedure for controlling the above-described voltage difference to perform the erase operation again will now be described in more detail. Figures 9A through 9C are waveforms associated with the circuit diagram of Figure 5, wherein a voltage is applied to the overall word line and a P-well region during an erase operation in accordance with one embodiment. 10A through 10C are waveforms associated with the circuit diagram of Fig. 5, wherein a voltage is applied to the overall word line and a P well region in accordance with one of the erase operations of another embodiment. Referring to FIG. 9A, an erase operation is performed by applying a positive erase voltage VWTJ to the overall word line GWL and a body voltage Vcb to the body PWELL. The body voltage VCB is substantially greater than the erase voltage VWT, for example, 15V or more. After the first erase attempt is performed, a wipe verification procedure is performed to determine if the erase operation has been properly performed. If all of the memory cells in the selected memory block have been erased, it is determined that the erase operation has been properly performed. If one or more of the memory cells in the selected memory block are not erased, it is determined that the erase operation is not properly performed. The erase verification process includes checking the data output by the Y-decoder 180. The data output from the Y-decoder 180 is input to the second bias generator 60 and the body voltage generator 40, wherein the second bias generator 60 generates the erase voltage VwTJ. A second erase attempt is performed if it is determined that the erase operation is not properly performed. The second erase attempt includes causing the second bias generator 60 to lower the erase voltage VwT by a given amount (for example, 0.1 to 55V) and applying a lower erase voltage VwT to the overall word. Yuan line GWL. Therefore, the voltage between the overall word line GWL and the body PWELL is increased by -35-200822123. Another erase verification procedure is implemented to determine if all of the memory cells in the memory block have been erased, i.e., whether the second erase attempt has been applied. If it is determined that the attempt is not properly performed, the second bias generator 60 is lowered by a given amount (for example, 0.1 to 0.5 V) to increase the voltage difference and apply a reduced erase voltage to the VWTJ level. The overall character line is subjected to a third erase attempt. This erasing method is called an "Incremental Stepping Pulse Erase (ISPE) method. The IS PE method increases the voltage difference and performs the erasing operation again to repeat the erasing attempts until all the menus are properly erased. The number of times or the number of such erase attempts is equal to a predetermined number of times, after all the selection elements are not properly erased after the predetermined number of attempts, the memory block is marked as an invalid block. The application sets the predetermined number of times. It has been described that when the erase operation is performed, the erase voltage VwT of the donor word line GWL is lowered to increase the voltage difference between the body and the body. However, as shown in Fig. 8B, the pressure generator 40 The body voltage VCB can be increased by 0.5 to increase the voltage difference between the word lines and the body. In FIG. 8C, the body voltage generator 40 can have a body voltage VCB, and the second bias The pressure generator 60 lowers the pressure VwtJ to increase between the word lines and the body

It has been described above that reducing the erase voltage V\ linear function by a linear function boosts the body voltage Vu. However, as in the case of the first 该A, it is appropriate to implement the second erroneous voltage step to increase the GWL to implement the pulse glitch. According to the work. Selective memory. If the unit is billed, the body can be charged 1 V according to the total word line, so that another case can be added to increase the erased power difference. VTJ may reduce the erase voltage VWT] by an exponential function as shown in Fig. -36 - 200822123. Alternatively, the body voltage VCB may be boosted by an index function. In another case, the erase voltage Vwt may be lowered by a quadratic function or the body voltage V C B may be boosted by a quadratic function. According to the above method, the present invention can minimize the occurrence of invalid blocks and can also prevent the threshold voltage from being reduced by the shallow erase phenomenon in the unselected block in which an erase operation is not performed, or when the erase is repeatedly performed. This quick stylization or the slow erase phenomenon is prevented during operation. Figure 11 is a graph comparing the changes in the threshold voltage of unselected blocks during an erase operation. In this prior art, a leakage current is generated in a switching element (e.g., G1 J in Fig. 5, where is an integer). Thus, the shallow erase phenomenon is produced, and the shallow erase phenomenon is performed by gradually performing a erase operation in a state where the voltage applied to the word line is gradually lowered. For this reason, the following problem arises: lowering the threshold voltage of one of the memory cells in the unselected block. However, in the present invention, an erasing operation is performed in a state where the entire word line is applied with a positive erase voltage in order to prevent a switching element (for example, G 1 J in Fig. 5, where J is an integer) The occurrence of leakage current in the middle. Thus, the shallow erase phenomenon is rarely generated in the unselected block. Therefore, the amount of change in the threshold voltage can be minimized. Figure 12 is a graph depicting the characteristics of a slow erase characteristic and a fast stylized characteristic depending on the number of erase operations in accordance with one embodiment of the present invention. In the first erasing operation, the voltage difference between the word lines and the body is maintained in a range in which the erasing operation can be appropriately performed. If the erase operation is properly performed, the erase operation is performed again by increasing the voltage difference again -37-200822123. Therefore, although the erasing operation is repeatedly performed, the rapid stylization phenomenon and the low-speed erasing phenomenon are generated in the range of about 0. 5 V. Considering that at least 2V or more produces the fast stylization phenomenon and the slow erase phenomenon shown in Fig. 2 of the prior art, it can be seen from Fig. 2 that the rapid stylization is rarely produced in the present invention. Phenomenon or this low speed erase phenomenon. As described above, the present invention includes one or more of the following advantages. First, during the erase operation, a voltage higher than 0 V is applied to the overall word line. Accordingly, the occurrence of leakage current can be prevented in the switching elements that are coupled between the global word lines and the local word lines. Therefore, it is possible to prevent the voltage of the word line of the unselected block which is not subjected to the erase operation from being reduced, and the occurrence of the shallow erase phenomenon can be prevented in an unselected block. Secondly, in the prior art, in the procedure of verifying whether the erase operation has been properly performed after the erase operation is performed, if there is a memory unit that does not properly perform the erase operation, it will correspond Blocks are considered invalid blocks and thus do not use such corresponding blocks. This results in a reduction in data storage capacity. However, in the present invention, if there is a memory cell in which the erase operation is not properly performed, the erase operation is performed again by increasing the voltage difference between the word lines and the body. Therefore, it is allowed to minimize the occurrence of invalid blocks and thus minimize the reduction of the data storage capacity. Third, if the erase operation is performed in a state where the word line has a high voltage difference from the first time from the first time, the electrons are trapped on the tunnel oxide layer or stress is supplied thereto. Tunneling oxide layer 'so-38 - 200822123 may reduce the electrical characteristics of a memory cell. However, in the present invention, only the minimum voltage difference is used for the erasing operation to carry out the erasing operation. If the erasing operation fails, the erasing operation is performed again by increasing the voltage difference. Thus, the amount of electrons trapped on the tunnel oxide layer or the stress provided on the tunnel oxide layer can be minimized, which results in an extended life of the memory cell. Fourth, in the present invention, the erasing operation is performed using a minimum voltage difference at an initial erasing operation. If a failure occurs, the erase operation is performed again by increasing the voltage difference. Therefore, although the read/erase operation is repeatedly performed, the rapid stylization or the slow erase phenomenon can be prevented from occurring to the maximum extent. According to the above operation, the reliability of the erasing operation can be improved, the occurrence of failure can be minimized, and the life of the component can be increased. While the various embodiments have been described in the foregoing, it is understood that the modifications and modifications of the invention may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a memory unit and a transfer gate of a conventional flash memory device erase operation; FIG. 2 shows the number of times in a conventional technique that depends on an erase operation. A slow erase characteristic and a characteristic curve of a fast stylized characteristic; Fig. 3 shows a slow erase characteristic and a fast stylized characteristic depending on the level of a erase voltage in the prior art. 4 is a block diagram of a memory device in accordance with an embodiment of the present invention; -39- 200822123 Figure 5 is a memory cell array, a block selection shown in FIG. Detailed circuit diagram of the unit, a second bias generator, a body voltage generator and an X-decoder; FIG. 6 is a memory unit, a transmission gate, a body voltage generator and a bias shown in FIG. Detailed circuit diagram of the pressure selection unit; FIG. 7 is a flow chart showing a method of controlling the erase operation of the flash memory element according to an embodiment of the present invention; FIG. 8A is not shown in FIG. An example of a switching element Figure 8B is a diagram depicting the displacement of the bit energy dependent on the bias of the word line in the switching element shown in Figure 6; Figures 9A to 9C depicting one of the patterns in Figure 5 In addition to the operation, a voltage is applied to the waveform of the first embodiment of the overall word line and a P-well; the 10A to 10C diagrams describe applying a voltage to the overall character during one of the erase operations in FIG. The waveform of the second embodiment of the line and the P well region; the first graph is for comparing the characteristic curve of the change of the threshold voltage of the unselected block during an erasing operation; and the second graph is based on the description A characteristic of a slow erase characteristic and a fast stylized characteristic depending on the number of erase operations of an embodiment of the invention. [Main component symbol description] 40 body voltage generator 50 first bias generator 60 second bias generator-40-200822123 61-63 first - to second pump power 64 bias 々 BB selection unit 65 Signal Generator 71 Substrate 72 Source 73 Drain 74 Gate 100 Flash Memory Element 1 10 Memory Cell Array 120 Input Buffer 130 Control Logic Circuit 140 Local Pressure Generator 150 X- Decoder 160 Block CBB Select Unit 161 Block Switching Unit 170 Page Buffer 180 Y-Decoder-41 -

Claims (1)

200822123 X. Patent application scope: '1 · A non-volatile memory component, comprising: - first and second memory cell blocks, each memory cell block comprising a plurality of memory cells and including a partial defect a pole selection line, a partial source selection line and a plurality of local word lines; a block selection unit respectively connecting a given local word line to the overall word line in response to a block selection signal; a voltage generator configured to apply at least first and second erase voltages to the overall word line during an erase operation, the first erase voltage being during a first erase attempt of the erase operation Applied to the overall word line, the second erase voltage being applied to the overall word line during a second erase attempt, wherein if the first erase attempt does not successfully perform the erase operation, Performing the second erasing attempt, the first and second erasing voltages are positive voltages; and a body voltage generator applying a body voltage to one of the memory cells during the erasing operation. 2. The memory component of claim 1, wherein each time a new erase attempt is performed, a erase voltage applied to the overall word line is reduced by a given voltage, wherein After a predetermined number of failed erase attempts, a given erase operation is stopped. 3. The memory component of claim 1, wherein the first bias generator generates the erase voltage such that a voltage difference between the local word lines and the body is at the first erase attempt It becomes 15V, and a well area of the system is formed with the first memory unit block in the well area. -42- 200822123 4. The memory component of claim 3, wherein each time a new erase attempt is performed, a erase voltage applied to the overall word line is reduced by a given voltage Where the given voltage is no greater than 0.5V. 5) The memory component of claim 1, further comprising: a page buffer for reading data stored in the memory cells; and a Y-decoder for outputting The data stored in the page buffer is to a data I/O buffer and the first bias generator. 6. The memory component of claim 5, wherein the first bias generator reduces the first erase voltage to the second erase voltage according to data output by the Y-decoder, wherein the memory The body element is a NAND flash memory element. 7. A flash memory component, comprising: a plurality of memory cell blocks, each memory cell block comprising a partial drain select line, a local source select line, and a plurality of local word lines, respectively And a plurality of memory cells are connected to the local drain selection line, the local source selection line and the plurality of local word lines; a block selection unit connecting the local word lines to the overall word lines respectively Responding to a block selection signal; a first bias generator applying a positive erase voltage to the overall word line during an erase operation; and a body voltage generator configured to be erased Applying a first body voltage to one of the memory cells during the first erase attempt, and if the first erase test is not properly performed - 43-200822123 test, then the second erase attempt A second body voltage is applied to the body during the period. 8. The flash memory component of claim 7, wherein if the first erase attempt 尙 does not erase all of the memory cells selected for the erase operation, then the 尙 is not properly implemented The first erase attempt. 9. The flash memory component of claim 7, wherein the body voltage generator generates the first body voltage such that a voltage difference between the local word lines and the body is during an initial erase operation A flash memory component according to claim 9 wherein the body voltage generator increases the first body voltage by no more than IV to generate the second body voltage. 1 1 - The flash memory component of claim 7 further comprising: a page buffer for reading data stored in the memory cells; and a Y-decoder for The data stored in the page buffer is output to a data I/O buffer and the body voltage generator. 12. The flash memory component of claim 11, wherein the body voltage generator generates the second body voltage according to data output by the Y-decoder to implement a second wipe of the erase operation. Except try. 1 3 - A flash memory component, comprising: a plurality of memory cells, each memory cell block - 44 - 200822123 includes a partial drain selection line, a local source selection line, and a plurality a local word line, and a plurality of memory cells are connected to the local drain selection line, the local source selection line, and the plurality of local word lines; a block selection unit for respectively connecting the local lines a word line to the overall word line in response to a block select signal; a first bias generator for applying a positive erase voltage to the overall word line during an erase operation, and if present a memory cell that is not erased, reducing the erase voltage and applying a reduced erase voltage to the overall word line to perform the erase operation again; and a body voltage generator for the wipe In addition to applying a body voltage to one of the body of the memory unit, and if there is a memory unit that is not erased, increasing the body voltage and applying an increased body voltage to the body, It will then execute the erase operation. 1 . The flash memory component of claim 13 wherein: the first bias generator and the body voltage generator respectively generate the erase voltage and the body during an initial erase operation a voltage such that a voltage difference between the local word lines and the body becomes 15V; and when the erase operation is performed again, the body voltage generator increases the body voltage and the first bias generator reduces the erase The voltage is such that the voltage difference between the local word lines and the body becomes higher than 15V.丄5. A flash memory component as claimed in claim 13 wherein: -45- 200822123 the first bias generator has a linear function, a quadratic function or an exponential function at a reference of 0.1 to 0.5V The erase voltage is reduced; and the body voltage generator increases the body voltage by a linear function, a quadratic function, or an exponential function at a scale of 0.5 to IV. 16. The flash memory component of claim 13 further comprising: a page buffer for reading data stored in the memory cells; and a Y-decoder for outputting The data stored in the page buffer is to a data I/O buffer, the body voltage generator and the first bias generator. 17. The flash memory component of claim 16, wherein the first bias generator reduces the erase voltage if the data of the data output by the Y-decoder is detected to be unerased. And the body voltage generator increases the body voltage to perform the erase operation again. 18. The flash memory component of claim 13 further comprising an X-decoder for decoding a column of address signals and outputting the block selection signal to the high voltage generating unit. 19. The flash memory component of claim 11, further comprising a second bias generator for performing any one of programming, reading and erasing operations A predetermined operating voltage is applied to the local drain select line and the local source select line. 20. The flash memory component of claim 17, wherein the first bias generator comprises: -46- 200822123 a first pump circuit for generating a read voltage required for a read operation Responding to a read command; a second pump circuit for generating a stylized voltage required for a stylized operation in response to a stylized command; a third pump circuit for generating the erase voltage in response to an erase command And if the data of the data output by the γ-decoder is not erased, the erase voltage is reduced and the output is reduced by a subtraction voltage; and a bias selection unit is configured to select the read The voltage, the programmed voltages or the erase voltages are responsive to an operational command signal and respectively output a select voltage to the overall word line. 2. The flash memory component of claim 20, wherein the bias selection unit comprises: a selection signal generator for generating a selection signal according to the operation command signal; and a plurality of selection circuits respectively connected Up to the overall word line, the selection circuits are configured to respectively output the read voltages, the programmed voltages, the erase voltages, or a combination thereof to the overall word lines for selection signal. 2 2. A method of erasing a non-volatile memory component', the method comprising: respectively connecting a local word line and a global word line of a selected block in response to a block selection signal; And erasing a voltage to the overall word line and a first body voltage higher than the first erase voltage to a body such that a voltage difference between the -47-200822123 local word line and the body is a first potential difference Performing a first erase attempt of one of the erase operations; determining whether the first erase attempt has been properly performed; and applying a second erase if it is determined that the first erase attempt is not properly performed A second erase attempt of the erase operation is performed by applying a voltage to the overall word line and a second body voltage to the body to increase a voltage difference between the local word line and the body to a second potential difference. The method of claim 2, wherein the second erase voltage is less than the first erase voltage. 24. The method of claim 22, wherein the second body voltage is greater than the first body voltage. 25. The method of claim 22, wherein the first erase voltage is different from the second erase voltage and the first body voltage is different from the second body voltage. 2 6. The method of claim 22, wherein the erasing operation is stopped after the predetermined number of erasure attempts are not successfully performed, wherein after the predetermined number of erasure attempts are not successfully performed, The selected block is marked as an invalid block. 27. A method of controlling an erase operation of a flash memory component, the method comprising: respectively connecting a local word line and a global word line of a selected block in response to a block selection signal; Except that the command applies a positive erase voltage to the overall word line and a body voltage higher than the erase voltage to a body of one hundred-48-200822123 body unit to perform an erase operation; determining whether it has been properly Performing the erase operation; and if it is determined that the erase operation is not properly performed, the voltage difference between the local word lines and the body is increased by simultaneously controlling the erase voltage and the body voltage. This erase operation is performed. 2 8. The method of claim 24, wherein the step of determining whether the erase operation has been properly performed is performed repeatedly, while reducing the erase voltage at a predetermined level and increasing the body voltage A predetermined level, and including if the erase operation is not properly performed until the predetermined number of times, a corresponding block is regarded as an invalid block. The method of claim 27, wherein the erase voltage and the body voltage are set such that a voltage difference between the local word lines and the body is 15V or higher. 30. The method of claim 27, wherein the erase voltage is reduced by 〇. 1 to 〇. 5 V, such that the voltage difference between the local word lines and the body increases within a range Where the voltage difference becomes at least 15V. 3. The method of claim 27, wherein the erase voltage is reduced by an exponential function such that a voltage difference between the local word lines and the body increases within a range, wherein the voltage difference becomes At least 15V. 32. The method of claim 27, wherein the erase voltage is increased by a factor of 至5 to IV such that a voltage difference between the local word lines and the body increases within a range, wherein This voltage difference becomes at least 15V. -49-200822123 3 3. The method of claim 27, wherein the erase voltage is increased by an exponential function such that a voltage difference between the local word lines and the body increases within a range, wherein The voltage difference becomes at least 15V. -50-