CN101178937B - Flash memory device and method for controlling erased operation - Google Patents

Flash memory device and method for controlling erased operation Download PDF

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Publication number
CN101178937B
CN101178937B CN2007101101758A CN200710110175A CN101178937B CN 101178937 B CN101178937 B CN 101178937B CN 2007101101758 A CN2007101101758 A CN 2007101101758A CN 200710110175 A CN200710110175 A CN 200710110175A CN 101178937 B CN101178937 B CN 101178937B
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voltage
erasing
erase operation
memory cell
bulk
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CN101178937A (en
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李熙烈
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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Abstract

The present invention provides a flash memory device and a method used for controlling erasing operation of the flash memory device.A non-volatile memory mechanism includes a first and a second memory cell blocks, wherein each memory cell block includes a plurality of memory cells, a local drain selection wire, a local source pole selection wire and a plurality of local character wires.A block selection unit respectively connects the set local character wires and an integral character wire to respond to block selective signals.A first voltage bias generator is allocated to be used for applying at least a first and a second erasing voltages which are positive ones to the integral character wire during the erasing manipulation period, wherein, the first erasing voltage is applied to the integral character wire during a first erasing try period of the erasing operation, the second erasing voltage is applied to the integral character wire during the second erasing try period, and a second erasing try is executed if a first erasing try does not make good erasing manipulation.A body voltage generator applies a body electric voltage to a body of the memory cell during the erasing manipulation period.

Description

Flash memory device reaches in order to control the method for its erase operation
Technical field
The present invention relates to semiconductor memory system, and more particularly, relate to flash memory device, in flash memory device, can prevent because of reducing the reliability of erase operation based on the leakage current in the erase operation of piece, and the method that relates to the erase operation of controlling flash memory device.
Background technology
Usually, flash memory device can be categorized into NOR type and NAND type, wherein the NOR type generally is to store low-volume information in order to high speed, and the NAND type generally is in order to store bulk information.Flash memory device is implemented read operation, programming operation and erase operation.Term " programming operation (program operation) " and " erase operation (erase operation) " refer to by electronics being injected floating grid and removing electronics with the operation at one or more memory cell storage datas from floating grid.For example, in programming operation, only be programmed in the selected memory cell of a plurality of memory cells included in the memory cell block.When wear tunnel (tunneling) is released in memory cell towards the P-wellblock floating grid by FN in, during existing electronics, carry out the erase operation of flash memory device.In erase operation, wipe stored data in whole memory cells included in memory cell block simultaneously.That is, be that erase operation is implemented on the basis with the memory cell block.
Fig. 1 is in order to the memory cell of the erase operation of explanation conventional flash memory device and the circuit diagram of transmission grid.In erase operation, the bias voltage Vb that applies 0V is to global character line GWL, and applies the P-wellblock (wherein n be integer) of bulk voltage (bulk voltage) VBK1 of 20V to memory cell CA1 to CAn and CB1 to CBn.Source electrode and the drain electrode of memory cell CA1 to CAn and CB 1 to CBn are floated.In addition, apply the grid of the block selection signal BKSEL1 of (Vcc) level that has voltage to nmos pass transistor NM1, wherein nmos pass transistor NM1 is connected between the local word line WL1 and global character line GWL of memory cell block A of selected (that is, will be wiped free of).The bulk voltage VBK2 that will have 0V is applied to the substrate (not shown) of nmos pass transistor NM1.Make nmos pass transistor NM1 conducting with response block selection signal BKSEL1, and make local word line WL1 be connected to global character line GWL.As a result, the voltage of local word line WL1 becomes 0V, and the voltage difference that produces 20V between the P-wellblock of the control grid (not shown) that is connected to local word line WL1 of memory cell CA1 to CAn and memory cell CA1 to CAn.So, when present dynasty P-wellblock discharges the electronics of floating grid of memory cell CA1 to CAn, implement the erase operation of memory cell block A.
Simultaneously, the grid of nmos pass transistor NM2 is applied in the block selection signal BKSEL2 of 0V, and wherein nmos pass transistor NM2 is connected between the local word line WL2 and global character line GWL of memory cell block B of not selected (that is, will not be wiped free of).In addition, apply the substrate of the bulk voltage VBK2 of 0V to nmos pass transistor NM2.Make nmos pass transistor NM2 by with response block selection signal BKSEL2, and local word line WL2 is separated with global character line GWL.This local word line WL2 that floats.After, the bulk voltage VBK1 of 20V that will be applied to the P-wellblock of memory cell CB1 to CBn by a capacitive coupling phenomenon is applied to local word line WL2, and thereby the voltage level of local word line WL2 is promoted to about 19V.This causes the voltage difference of the 1V between the P-wellblock of local word line WL2 and memory cell CB1 to CBn, and the voltage difference of 1V is not enough to discharge electronics from the floating grid of memory cell CB 1 to CBn.As a result, when memory cell block A is implemented erase operation, memory cell block B is not implemented erase operation.
Though, can in nmos pass transistor NM2, produce leakage current by nmos pass transistor NM2.So the voltage level that the voltage level of local word line WL2 is promoted near bulk voltage VBK1 can little by little reduce.This causes in the control grid of memory cell CB1 to CBn and the increase of the voltage difference between the P-wellblock.Therefore, may cause shallow wiping (shallow erase), that is, may be non-painstakingly discharge electronics in a small amount from the floating grid of memory cell CB 1 to CBn.When the number of memory cell block included in flash memory device increases, become more remarkable as the shallow interference of wiping of wiping.For example, whenever memory cell block is one by one implemented erase operation, in the memory cell of the memory cell block that should not be wiped free of, repeatedly produce the shallow phenomenon of wiping.Therefore, when the threshold voltage of corresponding stored device unit reduces gradually, increase the read operation failure probably.
Moreover, the fast programming phenomenon takes place, and wherein when the number of times of erase operation increased, threshold voltage rose to more than the target voltage when programming operation, perhaps take place to wipe phenomenon at a slow speed, wherein when erase operation, can't make threshold voltage be reduced to target voltage fully.Do more detailed description below with reference to Fig. 2
Fig. 2 shows the erasing characteristic at a slow speed of the number of times that depends on erase operation in the prior art and the performance diagram of fast programming characteristic.Though under equal state, implement programming or erase operation, when implementing to programme or during erase operation, the threshold voltage increase of memory cell, and become at last and be higher than target voltage.The increase of threshold voltage causes the quick enforcement of programming operation or the enforcement at a slow speed of erase operation.When the voltage difference when at erase operation between character line and body was higher, this phenomenon can take place.In other words, the voltage difference when erase operation between character line and body is high more, fast programming and to wipe phenomenon at a slow speed serious more.
Fig. 3 shows the erasing characteristic at a slow speed of the level that depends on erasing voltage in the prior art and the performance diagram of fast programming characteristic.Can find out if when the voltage difference between character line and body higher (noble potential is wiped), implement erase operation, then suddenly produce the fast programming phenomenon and wipe phenomenon at a slow speed, if yet when the voltage difference between character line and body lower (electronegative potential is wiped), implement erase operation, then little by little produce the fast programming phenomenon and wipe phenomenon at a slow speed.
Prevent fast programming phenomenon recited above and wipe the generation of phenomenon at a slow speed, implement erase operation in the time of should between character line and body, having the low-voltage difference.In this case, the erase operation time may be prolonged and erase operation may be implemented inadequately.If implement erase operation inadequately, then the corresponding blocks mark can be become the invalid block that is not used.This reduces the number of available block and reduces the data storing capacity.
Summary of the invention
So embodiments of the invention relate to the operation that discharges electronics from the floating grid of memory cell, for example, erase operation.The erase operation of implementing present embodiment is to reduce the leakage current of the memory cell that is not selected for erase operation.In one embodiment, during erase operation, apply first positive voltage to global character line (first attempts).If suitably do not implement erase operation as yet, then by apply less than second voltage of first voltage to the global character line to implement erase operation (second attempts) once more.Repeat to wipe and attempt pre-determined number or till successfully implementing erase operation, and whichever takes place earlier.Attempt the back minimizing in each failure and be applied to the voltage of global character line to increase the voltage difference of erase operation.
In one embodiment, non-volatile memory device comprises first and second memory cell block, and each memory cell block comprises a plurality of memory cells and comprises local drain electrode selection wire, local source electrode selection wire and many local word lines.The piece selected cell connect respectively given local word line to the global character line with the response block selection signal.First bias generator is configured in order to apply at least first and second erasing voltage to the global character line during erase operation, first erasing voltage is wiped at first of erase operation and is applied to the global character line between trial period, second erasing voltage is wiped second and is applied to the global character line between trial period, if wherein first wipe trial and successfully do not implement erase operation, then implement second and wipe trial.First and second erasing voltage is a positive voltage.The bulk voltage generator applies the body of bulk voltage to memory cell during erase operation.In this embodiment, each enforcement is newly wiped when attempting, and reduces the erasing voltage that is applied to the global character line by given voltage, wherein after trial is wiped in the failure of pre-determined number, stops given erase operation.
In one embodiment, flash memory device comprises a plurality of memory cell block, each memory cell block comprises local drain electrode selection wire, local source electrode selection wire and many local word lines respectively, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines.The piece selected cell connect respectively local word line to the global character line with the response block selection signal.First bias generator applies positive erasing voltage to the global character line when erase operation.The bulk voltage generator is configured to apply the body of first bulk voltage to memory cell between trial period in order to wipe at first of erase operation, if and suitably do not implement first as yet and wipe trial, then wipe and apply second bulk voltage between trial period to body second.Do not wipe as yet at selected all memory cells of erase operation if first wipes trial, think that then suitably not implementing first as yet wipes trial.
In one embodiment, the method for wiping a non-volatile memory device comprises and connects the local word line of selecting piece and global character line with the response block selection signal.By apply first erasing voltage to global character line and first bulk voltage that is higher than first erasing voltage to body so that the voltage difference between local word line and body is first potential difference (PD) implements first of erase operation and wipe trial.Method comprises that further determining whether suitably to implement first wipes trial.If determine that suitably not implementing first as yet wipes trial, then implements second of erase operation and wipes trial.Second wipe attempt comprising apply second erasing voltage to global character line and second bulk voltage to body to be increased in voltage difference to the second potential difference (PD) between local word line and body.Second erasing voltage may be less than first erasing voltage.Second bulk voltage may be greater than first bulk voltage.First erasing voltage and second erasing voltage may be different, and first bulk voltage and second bulk voltage may be different.
Flash memory device according to the first embodiment of the present invention comprises a plurality of memory cell block, piece selected cell, first bias generator and bulk voltage generator.Each memory cell block comprises local drain electrode selection wire, local source electrode selection wire and many local word lines, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines.The piece selected cell connect respectively local word line to the global character line with the response block selection signal.First bias generator applies positive erasing voltage to the global character line when erase operation, and if have the memory cell be not wiped free of as yet, then reduce erasing voltage and apply erasing voltage to the global character line, so that implement erase operation once more through reducing.The bulk voltage generator applies the body of bulk voltage to memory cell when erase operation.
First bias generator can produce erasing voltage, so that the voltage difference between local word line and body becomes 15V when initial erase is operated, and the minimizing erasing voltage, when implementing erase operation once more with box lunch, the voltage difference between local word line and body becomes and is higher than 15V.At this moment, first bias generator can linear function, quadratic function or exponential function reduce erasing voltage under 0.1 to 0.5V benchmark.
Flash memory device may further include page buffer, in order to reading in data stored in the memory cell, and the Y-code translator, in order to output stored data to a data I/O impact damper and first bias generator in page buffer.
If detect the obliterated data not as yet of the data exported from the Y-code translator, then first bias generator can reduce erasing voltage, so that implement erase operation once more.
Flash memory device according to the second embodiment of the present invention comprises a plurality of memory cell block, piece selected cell, first bias generator and bulk voltage generator.Each memory cell block comprises local drain electrode selection wire, local source electrode selection wire and many local word lines, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines.The piece selected cell connect respectively local word line to the global character line with the response block selection signal.First bias generator applies positive erasing voltage to the global character line when erase operation.The bulk voltage generator applies the body of bulk voltage to memory cell when erase operation, and if have the memory cell be not wiped free of as yet, then for the execution again of erase operation, increase bulk voltage and apply bulk voltage to body through increasing.
The bulk voltage generator can produce bulk voltage, so that the voltage difference between local word line and body becomes 15V when initial erase is operated, and the minimizing bulk voltage, when implementing erase operation once more with box lunch, the voltage difference between local word line and body becomes and is higher than 15V.At this moment, the bulk voltage generator can linear function, quadratic function or exponential function increase bulk voltage under 0.5 to 1V benchmark.
Flash memory device may further include page buffer, in order to reading in data stored in the memory cell, and the Y-code translator, in order to output in page buffer stored data to data I/O impact damper and bulk voltage generator.
If detect the obliterated data not as yet of the data exported from the Y-code translator, then the bulk voltage generator can increase bulk voltage, so that implement erase operation once more.
Flash memory device according to the third embodiment of the present invention comprises a plurality of memory cell block, piece selected cell, first bias generator and bulk voltage generator.Each memory cell block comprises local drain electrode selection wire, local source electrode selection wire and many local word lines, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines.The piece selected cell connect respectively local word line to the global character line with the response block selection signal.First bias generator applies positive erasing voltage to the global character line when erase operation, and if have the memory cell be not wiped free of as yet, then reduce erasing voltage and apply and reduce erasing voltage to the global character line, so that implement erase operation once more.The bulk voltage generator applies the body of bulk voltage to memory cell when erase operation, and if have the memory cell be not wiped free of as yet, then for the execution again of erase operation, increase bulk voltage and apply bulk voltage to body through increasing.
In above-mentioned, when initial erase was operated, first bias generator and bulk voltage generator can produce erasing voltage and bulk voltage respectively, so that the voltage difference between local word line and body becomes 15V.When implementing erase operation once more, the bulk voltage generator can increase bulk voltage and first bias generator can reduce erasing voltage, is higher than 15V so that the voltage difference between local word line and body becomes.At this moment, first bias generator can linear function, quadratic function or exponential function reduce erasing voltage under 0.1 to 0.5V benchmark.The bulk voltage generator can linear function, quadratic function or exponential function increase erasing voltage under 0.5 to 1V benchmark.
Flash memory device may further include page buffer, in order to read in data stored in the memory cell, and the Y-code translator, in order to export data stored in page buffer to data I/O impact damper, bulk voltage generator and first bias generator.
Simultaneously, if detect the obliterated data not as yet of the data exported from the Y-code translator, then first bias generator reduces erasing voltage and the bulk voltage generator increases bulk voltage, so that implement erase operation once more.
Flash memory device may further include the X-code translator, and the X-code translator is in order to the decoding column address signal and export block selection signal to high-voltage generating unit.Moreover flash memory device may further include the second bias voltage generator, the second bias voltage generator in order to according to programming, read and erase operation in any operation apply scheduled operation voltage to local drain electrode selection wire and local source electrode selection wire.
First bias generator can comprise first pump circuit (pump ciruit), in order to produce read operation required read voltage with the response reading command; Second pump circuit is in order to produce the required program voltage of programming operation with the response programming instruction; The 3rd pump circuit, in order to producing erasing voltage with the response erasing instruction, and if the obliterated data not as yet that detects data that the Y-code translator exported, then reduce erasing voltage and output reduces erasing voltage; And biasing selected unit, in order to select to read voltage, program voltage or erasing voltage with the operation response command signal and respectively output select voltage to the global character line.At this moment, biasing selected unit can comprise the selection signal generator, select signal in order to produce according to operation instruction signal, and a plurality of selection circuit, be connected to the global character line respectively, one of read in voltage, program voltage and the erasing voltage to the global character line in order to output respectively and select signal with response.
According to the first embodiment of the present invention, the method for erase operation of control flash memory device is provided, method comprises the following steps: that (a) electrically connects the local word line of selecting piece and global character line respectively to respond block selection signal; (b) apply the body of positive erasing voltage to implement erase operation by the foundation erasing instruction to global character line and the bulk voltage that is higher than erasing voltage to memory cell; (c) determine whether suitably to implement erase operation; And if (d) determine suitably not implement as yet erase operation, then come to implement once more erase operation greatly so that the voltage difference between local word line and body becomes by reducing erasing voltage.
Step (c) reaches and (d) can repeatedly be repeated to implement, and reduces erasing voltage simultaneously and arrives predetermined level as far as possible, and comprise if suitably do not implement erase operation as yet till pre-determined number, then corresponding blocks is considered as invalid block.
According to the second embodiment of the present invention, the method for erase operation of control flash memory device is provided, method comprises that (a) electrically connects the local word line of selecting piece and global character line respectively to respond block selection signal; (b) apply the body of positive erasing voltage to implement erase operation by the foundation erasing instruction to global character line and the bulk voltage that is higher than erasing voltage to memory cell; (c) determine whether suitably to implement erase operation; And if (d) determine suitably not implement as yet erase operation, then come to implement once more erase operation greatly so that the voltage difference between local word line and body becomes by increasing erasing voltage.
Step (c) reaches and (d) can repeatedly be repeated to implement, and increases erasing voltage simultaneously and arrives predetermined level as far as possible, and comprise if suitably do not implement erase operation as yet till pre-determined number, then corresponding blocks is considered as invalid block.
According to the third embodiment of the present invention, the method for erase operation of control flash memory device is provided, method comprises the following steps: that (a) electrically connects the local word line of selecting piece and global character line respectively to respond block selection signal; (b) apply the body of positive erasing voltage to implement erase operation by the foundation erasing instruction to global character line and the bulk voltage that is higher than erasing voltage to memory cell; (c) determine whether suitably to implement erase operation; And if (d) determine suitably not implement as yet erase operation, then come to implement once more erase operation greatly so that the voltage difference between local word line and body becomes by controlling erasing voltage and bulk voltage simultaneously.
Step (c) reaches and (d) can repeatedly be repeated to implement, reducing erasing voltage simultaneously arrives predetermined level as far as possible and increases bulk voltage as far as possible in predetermined level, and comprise if till pre-determined number, suitably do not implement erase operation as yet, then corresponding blocks is considered as invalid block.
Moreover, can set erasing voltage and bulk voltage, so that the voltage difference between local word line and body is 15V or higher.
Can reduce erasing voltage by 0.1 to 0.5V benchmark, so that make the voltage difference that voltage difference becomes to be increased in the scope of 15V at least between local word line and body, perhaps can exponential function reduce erasing voltage, so that make the voltage difference that voltage difference becomes to be increased in the scope of 15V at least between local word line and body.
Can increase erasing voltage by 0.5 to 1V benchmark, so that make the voltage difference that voltage difference becomes to be increased in the scope of 15V at least between local word line and body, perhaps can exponential function increase erasing voltage, so that make the voltage difference that voltage difference becomes to be increased in the scope of 15V at least between local word line and body.
Description of drawings
Fig. 1 describes the memory cell of erase operation of conventional flash memory device and the circuit diagram of transmission grid;
Fig. 2 shows the erasing characteristic at a slow speed of the number of times that depends on erase operation in the prior art and the performance diagram of fast programming characteristic;
Fig. 3 shows the erasing characteristic at a slow speed of the level that depends on erasing voltage in the prior art and the performance diagram of fast programming characteristic;
Fig. 4 is the calcspar according to the flash memory device of embodiments of the invention;
Fig. 5 is the detailed circuit diagram of memory cell array, piece selected cell, second bias generator, bulk voltage generator and X-code translator shown in Figure 4;
Fig. 6 is memory cell shown in Figure 5, the detailed circuit diagram of transmission grid, bulk voltage generator and biasing selected unit;
Fig. 7 is the process flow diagram of description according to the method for the erase operation of the control flash memory device of embodiments of the invention;
Fig. 8 A is the sectional view that shows the example of switching device shifter shown in Figure 6;
Fig. 8 B is potential energy displacement graphic that is described in the bias variations that depends on character line in the switching device shifter shown in Figure 6;
When Fig. 9 A to 9C is the erase operation that is described among Fig. 5 voltage is applied to the waveform of first embodiment of global character line and P wellblock;
When Figure 10 A to 10C is the erase operation that is described among Fig. 5 voltage is applied to the waveform of second embodiment of global character line and P wellblock;
Figure 11 is in order to the performance diagram of non-selected variations in threshold voltage when the erase operation relatively; And
Figure 12 is that description is according to the erasing characteristic at a slow speed of the number of times that depends on erase operation of embodiments of the invention and the performance diagram of fast programming characteristic.
Embodiment
Now, will be with reference to appended graphic the description according to various embodiment of the present invention.Because propose various embodiment for those skilled in the art can understand the present invention, so it can be revised in every way and described after a while various embodiment do not limit to scope of the present invention.
Fig. 4 is the calcspar according to the flash memory device of embodiments of the invention.Flash memory device 100 comprises memory cell array 110, input buffer 120, control logic circuit 130, high-pressure generator 140, X-code translator 150, piece selected cell 160, page buffer 170, Y-code translator 180 and data I/O impact damper 190.Memory cell array 110 comprises memory cell block MB1 to MBK (wherein K is an integer), and each memory cell block has a plurality of memory cell (not shown)s.Input buffer 120 receives command signal CMD or address signal ADD, and exports them to control logic circuit 130.Control logic circuit 130 receive command signal CMD or address signal ADD with response external control signal/WE ,/RE, ALE and CLE.Control logic circuit 130 one of produces among reading command READ, programming instruction PGM and the erasing instruction ERS with response instruction signal CMD.Control logic circuit 130 generation column address signal RADD and row address signal CADD are with response address signal ADD.
High-pressure generator 140 comprises bulk voltage generator 40, first bias generator 50 and second bias generator 60.Bulk voltage generator 40 produces bulk voltage V CBWith response reading command READ, programming instruction PGM and erasing instruction ERS, and supply bulk voltage V CBP-wellblock to memory cell.More particularly, bulk voltage generator 40 produces low voltage level (for example, bulk voltage V 0V) CBWith response reading command READ or programming instruction PGM.Bulk voltage generator 40 also produces high-voltage level, and (for example, bulk voltage VCB 20V) is with response erasing instruction ERS.Simultaneously, if behind erase operation, have as yet the unit that the data of suitably not exported according to Y-code translator 180 are implemented erase operation, level that then can control body voltage VCB.For example, if suitably do not implement erase operation as yet, then can 0.5 or the 1V benchmark increase the level of bulk voltage VCB, and if suitably, can change bulk voltage V CBThe increase width.
First bias generator 50 produces drain bias V GDAnd source electrode bias voltage V GSWith one of among response reading command READ, programming instruction PGM and the erasing instruction ERS, and supply drain bias V GDTo overall situation drain electrode selection wire GDSL and source electrode bias voltage V GSTo overall source electrode selection wire GSSL.More particularly, first bias generator 50 produces high-voltage level (for example, drain bias V 4.5V) GDAnd source electrode bias voltage V GSWith response reading command READ.First bias generator 50 also produces the builtin voltage level drain bias V of (VCC does not show) GDAnd the source electrode bias voltage V of low voltage level GSWith response programming instruction PGM.Moreover first bias generator 50 produces the drain bias V of low voltage level GDAnd source electrode bias voltage V GSWith response erasing instruction ERS.
Second bias generator 60 produces character line bias voltage V WF1 to V WFJ (wherein J is an integer), character line bias voltage V WS1 to V WSJ (wherein J is an integer) or character line bias voltage V WT1 to V WTJ (wherein J is an integer) is with one of among response reading command READ, programming instruction PGM and the erasing instruction ERS and decoded signal DEC, and supply produces character line and is biased into global character line GWL1 to GWLJ (wherein J is an integer).More detailed, second bias generator 60 produces character line bias voltage V WF1 to V WFJ is with response reading command READ.Second bias generator 60 produces character line bias voltage V WS1 to V WSJ is with response programming instruction PGM.Second bias generator 60 produces character line bias voltage V WT1 to V WTJ is with response erasing instruction ERS.
In this case, when input erasing instruction ERS, second bias generator 60 produces the positive voltage that is higher than 0V.Behind erase operation, if having the unit that the data of not exported according to Y-code translator 180 are as yet suitably implemented erase operation, second bias generator, 60 control character line bias voltage V then WT1 to V WTThe level of J.For example, if suitably do not implement erase operation as yet, then second bias generator 60 can reduce character line bias voltage V by 0.1V to 0.5V benchmark WT1 to V WTThe level of J and output reduce the character line bias voltage.If necessary, can change character line bias voltage V WT1 to V WTThe minimizing width of J.
If suitably do not implement erase operation as yet, then bulk voltage generator 40 and the second word line voltages generator, 60 control output voltage.This will implement erase operation (that is, implement erase operation again) once more.By increasing voltage difference between character line and body to implement erase operation again.In order to increase the voltage difference between character line and body, have only in the bulk voltage generator 40 and the second word line voltages generator 60 voltage generator or bulk voltage generator 40 and the second word line voltages generator 60 both can control output voltage level.After this will be described in detail in.
X-code translator 150 decoding column address signal RADD, and output decoded signal DEC.One or more among the piece selected cell 160 selection memory cell block MB1 to MBK with response decoded signal DEC, and the local word line WL11 to WL1J (seeing the 5th figure) that connects selection memory cell block (or memory cell block) respectively is to global character line GWL1 to GWLJ.Piece selected cell 160 one of connects among the drain electrode selection wire DSL1 to DSLK (seeing the 5th figure) of selection memory cell blocks to overall situation drain electrode selection wire GDSL, and one of connects among the drain selection line SSL1 to SSLK (seeing the 5th figure) of selection memory cell block to overall source electrode selection wire GSSL.The structure of page buffer 170, Y-code translator 180 and data I/O impact damper 190 and operation are that skilled persons will is known, thereby the descriptions thereof are omitted.
Fig. 5 is the detailed circuit diagram of memory cell array, piece selected cell, second bias generator, bulk voltage generator and X-code translator shown in Figure 4.The memory cell block MB1 of memory cell array 110 comprises memory cell M111 to M1JT (wherein J and T are integers), drain electrode selection transistor DST1 and drain selection transistor SST1.Memory cell M111 to M1JT share bit lines BL1 to BLT (wherein T is an integer), local word line WL11 to WL1J (wherein J is an integer) and shared source electrode line CSL1.That is, memory cell M111 to M11T via (etc.) drain electrode selects transistor DST1 to be connected to bit line BL1 to BLT respectively, and memory cell M1J1 to M1JT via (etc.) drain selection transistor SST1 is connected to and shares source electrode line CSL1.In addition, the grid of memory cell M111 to M1JT is connected to local word line WL11 to WL1J.(etc.) drain electrode selects the grid of transistor DST1 to be connected to local drain electrode selection wire DSL1, and (etc.) grid of drain selection transistor SST1 is connected to local source electrode selection wire SSL1.
The structure of the memory cell block MB2 to MBK of memory cell array 110 is same as the structure of memory cell block MB1.Piece selected cell 160 comprises piece switch unit 161 and a plurality of switch unit PG1 to PGK (wherein K is an integer).Piece switch unit 161 output block selection signal BSEL1 to BSELK (wherein K is an integer) are to respond the decoded signal DEC that is received from X-code translator 150.A plurality of switch unit PG1 to PGK respectively with dispose corresponding to memory cell block MB 1 to MBK mode and be enabled or anergy to respond block selection signal BSEL1 to BSELK.
Each switch unit of switch unit PG1 to PGK comprises a plurality of switching device shifters.For example, switch unit PG1 has switching device shifter GD1, G11 to G1J and GS1.The structure of switch unit PG2 to PGK and operation are similar in appearance to structure and the operation of switch unit PG1.Therefore, will describe according to the operation of switch unit PG1.Best, can use nmos pass transistor to implement switching device shifter GD1, G11 to G1J and GS1.After, switching device shifter GD 1, G11 to G1J and GS 1 will be called " nmos pass transistor " for convenience of description.Block selection signal BSEL1 is inputed to the grid of nmos pass transistor GD1, G11 to G1J and GS 1.Nmos pass transistor GD1 has source electrode that is connected to overall situation drain electrode selection wire GDSL and the drain electrode that is connected to local drain electrode selection wire DSL1.Nmos pass transistor G11 to G1J has source electrode that is connected to global character line GWL1 to GWLJ respectively and the drain electrode that is connected to local word line WL11 to WL1J respectively.Nmos pass transistor GS1 has the source electrode that is connected to overall source electrode selection wire GSSL and is connected to the drain electrode of local source electrode selection wire SSL1.Conducting simultaneously or by nmos pass transistor GD1, G11 to G1J and GS 1 with response block selection signal BSEL1.
More particularly, when making block selection signal BSEL1 activation, conducting nmos pass transistor GD1, G11 to G1J and GS1, and when block selection signal BSEL1 anergy, by nmos pass transistor GD1, G11 to G1J and GS1.When conducting nmos pass transistor GD1, G11 to G1J and GS1, overall situation drain electrode selection wire GDSL is connected to local drain electrode selection wire DSL1, overall situation source electrode selection wire GSSL is connected to local source electrode selection wire SSL1, and global character line GWL1 to GWLJ is connected to local word line WL11 to WL1J respectively.
Second bias generator 60 comprises first to the 3rd pump circuit 61,62 and 63 and biasing selected unit 64.First pump circuit 61 produces and reads voltage V RD1 and V RD2 with response reading command READ.Best, read voltage V RD1 has high voltage level (for example, 4.5V), and reads voltage V RD2 have low voltage level (for example, 0V).In the read operation of memory cell array 110, will read voltage V RD1 is applied to local word line, and the grid of wherein non-selected memory cell (that is, with the memory cell that is not read) is connected to local word line, and will read voltage V RD2 are applied to local word line, and wherein the grid of selection memory unit (that is, with the memory cell that is read) is connected to local word line.
Second pump circuit 62 produces program voltage V PGAnd V PSWith response programming instruction PGM.Best, program voltage V PGAnd V PSHas high voltage level (for example, V respectively PG=18V, V PS=10V).In the programming operation of memory cell array 110, with program voltage V PGBe applied to local word line, wherein the grid with the memory cell that is programmed is connected to local word line, and (or transmission (pass)) the voltage V that will programme PSBe applied to local word line, wherein the grid of the memory cell that will not be programmed is connected to local word line.
Moreover the 3rd pump circuit 63 produces positive erasing voltage V ERS, positive erasing voltage V ERSBe higher than 0V with response erasing instruction ERS.In other words, the 3rd pump circuit 63 produces erasing voltage V ERS, so that selected character line will be higher than the voltage of 0V and be applied to erase operation the time.Simultaneously, according to positive erasing voltage V ERSImplement to be reduced in the voltage difference between character line and body in the piece of erase operation.Being preferably in the voltage difference that makes in the piece of implementing erase operation between character line and body is about in 15 to 20V the level range and produces erasing voltage V ERS
Simultaneously, if in the operation that determines whether suitably to implement erase operation, detect in the data that Y-code translator (with reference to the symbolic device 180 among the 4th figure) exported non-erase status (for example, data 0) (that is, erase operation is failed), then the 3rd pump circuit 63 can reduce erasing voltage V by 0.1 to 0.5V benchmark ERSLevel and output reduce erasing voltage V ERSIf suitably, then can change erasing voltage V ERSThe minimizing width.Can linear function, quadratic function or exponential function reduce erasing voltage V ERSSo the voltage difference and the foundation increase voltage difference that increase between character line and body are implemented erase operation once more.
Voltage V is selected to read in biasing selected unit 64 RD1 and V RD2 with respond the decoded signal DEC that received from X-code translator 150 and then respectively output select to read voltage V RD1 and V RD2 to global character line GWL1 to GWLJ with as character line bias voltage V WF1 to V WFJ selects program voltage V PGAnd V PSAnd export respectively then and select program voltage V PGAnd V PSTo global character line GWL1 to GWLJ with as character line bias voltage V WS1 and V WSJ (wherein J is an integer), perhaps selective erasing voltage V ERSReach selective erasing voltage V then ERSExport global character line GWL1 to GWLJ to as character line bias voltage V WT1 to V WTJ.
Bulk voltage generator 40 produces the high bulk voltage V that will be applied to body (for example, P wellblock) when erase operation CBWith response erasing instruction ERS, wherein in body, be formed with memory cell M111 to M1JT (J and T are integers).Can make voltage difference between character line and body in implementing the piece of erase operation is to produce bulk voltage V in 15 to 20V the voltage level range CB
Simultaneously, if in the operation that determines whether suitably to implement erase operation, detect in the data that Y-code translator (with reference to the symbolic device 180 among the 4th figure) exported non-erase status (for example, data 0) (that is, erase operation is failed), then bulk voltage generator 40 can increase bulk voltage V by 0.5 to 1V benchmark CBLevel and output increase bulk voltage V CBIf suitably, can change bulk voltage V CBThe increase width.Can linear function, quadratic function or exponential function increase bulk voltage V CBSo the voltage difference and the foundation increase voltage difference that increase between character line and body are implemented erase operation once more.
As previously discussed, in being applied with the state of positive voltage, the global character line implements erase operation.If suitably do not implement erase operation, then by one of in control the 3rd pump circuit 63 and the bulk voltage generator 40 or both output voltages implement erase operation once more with the voltage difference that increases between character line and body.Can control the output voltage of the 3rd pump circuit 63 or bulk voltage generator 40, so that the voltage difference between character line and body is 15V or higher.
Fig. 6 is memory cell shown in Figure 5, the detailed circuit diagram of transmission grid, bulk voltage generator and biasing selected unit.
With reference to figure 6, biasing selected unit 64 comprises to be selected signal generator 65 and selects circuit S1 to SJ (wherein J is an integer).Select signal generator 65 to produce and select signal SL1 to SLJ according to decoded signal DEC.Each that select circuit S1 to SJ select circuit comprise switch SW 11 to SW15 ..., SWJ1 to SWJ5, it is connected to global character line GWL1 to GWLJ respectively.Select each selection circuit reception of circuit S1 to SJ to read voltage V RD1 and V RD2, program voltage V PGAnd V PSAnd erasing voltage V ERS, and output character line bias voltage V WF1 to V WFJ, V WS1 to V WSJ or V WT1 to V WTJ selects signal SL1 to SLJ with response to global character line GWL1 to GWLJ.After this will be described in more detail in.For example, the switch SW 11 to SW15 of selection circuit S1 is connected to and reads voltage V RD1 and V RD2, program voltage V PGAnd V PSAnd erasing voltage V ERSAnd between the global character line GWL1.According to the logical value conducting of the position B1 to B5 that selects signal SL1 or by switch SW 11 to SW15.In this case, using nmos pass transistor to implement in the situation of switch SW 11 to SW15, when the logical value of position B1 to B5 is 1, actuating switch SW11 to SW15.Simultaneously, when the logical value of position B1 to B5 is 0, by switch SW 11 to SW15.
For example, when one of among switch SW 11 and the SW12 during conducting, will read voltage V RD1 and V RDInput to global character line GWL1 one of in 2 with as character line bias voltage VWF1.Moreover, when one of among switch SW 13 and the SW14 during conducting, with program voltage V PGAnd V PSIn one of input to global character line GWL1 with as character line bias voltage V WS1.In addition, when switch SW 15 conductings, with erasing voltage V ERSInput to global character line GWL1 with as character line bias voltage V WT1.One of in this case, produce logical value 1 and make remaining bit produce logical value 0 because select signal generator 65 one of to make among the B1 to B5, so among the actuating switch SW11 to SW15, and by the residue switch.As a result, will read voltage V RD1 and V RD2, program voltage V PGAnd V PSAnd erasing voltage V ERSIn one of be applied to global character line GWL1.The structure of selection circuit S2 to SJ and operation are similar in appearance to structure and the operation of above-mentioned selection circuit S1.
Show that in Fig. 6 each selection circuit of selecting circuit S1 to SJ has 5 switches.Yet, notice to change or to revise the structure of selecting circuit S1 to SJ.As have the knack of a skill person and understand, have many making and select circuit S1 to SJ output character line bias voltage V WF1 to V WFJ, V WS1 to V WSJ or V WT1 to V WTThe method of J.
Moreover, for graphic simplification, Fig. 6 only shows nmos pass transistor G11, GK1, G1J and the GKJ that is connected to global character line GWL1 and GWLJ, local word line WL11, WL1J, WLK1 and WLKJ and memory cell M111, M11T, M1J1, M1JT, MK11, MK1T, MKJ1 and MKJT.The grid of memory cell M111 to M11T is connected to local word line WL11, and the grid of memory cell M1J1 to M1JT is connected to local word line WL1J.In addition, the grid of memory cell MK11 to MK1T is connected to local word line WLK1, and the grid of memory cell MKJ1 to MKJT is connected to local word line WLKJ.The source electrode of nmos pass transistor G11 and drain electrode are connected to global character line GWL1 and local word line WL11 respectively.The source electrode of nmos pass transistor GK1 and drain electrode are connected to global character line GWL1 and local word line WLK1 respectively.In addition, the source electrode of nmos pass transistor G1J and drain electrode are connected to global character line GWLJ and local word line WL1J respectively.The source electrode of nmos pass transistor GKJ and drain electrode are connected to global character line GWLJ and local word line WLKJ respectively.
Fig. 7 is the process flow diagram of description according to the method for the erase operation of the control flash memory device of embodiments of the invention.Set erasing voltage V WTJ and bulk voltage V CBLevel so that erasing voltage V WTJ has positive voltage level and erasing voltage V WTJ and bulk voltage V CBBetween difference be 15V (S701).In case set erasing voltage V WTJ and bulk voltage V CB, use erasing voltage V according to block selection signal BLKWL immediately WTJ and bulk voltage V CBThe memory cell of selecting piece is implemented erase operation (S702).After implementing erase operation, determine whether suitably to implement erase operation (S703).If wiped all memory cells of selecting in the piece, then determine suitably to implement erase operation, in this case, finish erase operation.On the other hand, if having one or more memory cells of not wiping as yet, determine that then suitably not implementing erase operation as yet reaches by reseting erasing voltage V WTJ and bulk voltage V CBTo implement erase operation once more.This will do more detailed description below.
Make the number of times of the erase operation of being implemented increase by 1 (S704).Then, determine whether that the number of times of the erase operation implemented is less than pre-determined number (S705).If the number of times of the erase operation of being implemented less than pre-determined number, then changes erasing voltage V WTJ and bulk voltage V CB(S706).At this moment, change erasing voltage V WTJ and bulk voltage V CB, so that erasing voltage V WTJ and bulk voltage V CBBetween difference little by little become greater than 15V.To describe after a while and change erasing voltage V WTJ and bulk voltage V CBDetailed method.
If changed erasing voltage V WTJ and bulk voltage V CB, then use to change voltage to implement erase operation (or erase operation) again (S702).Implement above-mentioned steps (S703 to S705) once more.If in period demand, do not finish erase operation, selection memory piece mark is become invalid block (S707).In the present embodiment, when the number of times of erase operation equals pre-determined number, mark selection memory piece.
Referring now to the erase operation of Fig. 4 to 6 with the flash memory device 100 that is described in more detail in the 7th figure and described.Control logic circuit 130 produce erasing instruction ERS with response external control signal/WE ,/RE, ALE and CLE and command signal CMD, and produce column address signal RADD according to address signal ADD.The bulk voltage generator 40 of high-pressure generator 140 produces high voltage level (for example, bulk voltage V 17V) CBWith response erasing instruction ERS, and supply the bulk voltage V that is produced CBTo bulk material (P wellblock), and be formed with memory cell block MB1 to MBK at bulk material.
Moreover first bias generator 50 of high-pressure generator 140 produces low pressure (for example, drain bias V 0V) GDAnd source electrode bias voltage V GSWith response erasing instruction ERS.So, drain bias VGD is applied to overall situation drain electrode selection wire GDSL, and with source electrode bias voltage V GSBe applied to overall source electrode selection wire GSSL.Simultaneously, X-code translator 150 decoding column address signal RADD, and output decoded signal DEC.Second bias generator 60 of high-pressure generator 140 produces character line bias voltage V WT1 to V WTJ is with response erasing instruction ERS and decoded signal DEC, and respectively the voltage that produced of supply to global character line GWL1 to GWLJ.More particularly, the 3rd pump circuit 63 of second bias generator 60 produce have on the occasion of erasing voltage V ERSWith response erasing instruction ERS.For example, erasing voltage V ERSBe lower than the bulk voltage V of the P-wellblock that in erase operation, is provided to memory cell CB, and have on the occasion of.Be preferably, can will in erase operation, be provided to the bulk voltage V of the P-wellblock of memory cell CBWith erasing voltage V ERSBetween difference set for and be greater than or equal to 5V.The biasing selected unit 64 selective erasing voltage VERS of second bias generator 60 are with response decoded signal DEC, and output selects voltage as character line bias voltage V WT1 to V WTJ.More detailed, the numerical value " 00001 " of the position B 1 to B5 of the selection signal generator 65 output selection signal SL1 to SLJ of biasing selected unit 64 is with response decoded signal DEC.The switch SW 15 of the selection circuit S1 to SJ of the biasing selected unit 64 of conducting is to SWJ5, and with switch SW 11 to SWJ1, SW12 to SWJ2, SW13 to SWJ3 and SW14 to SWJ4 by, select signal SL1 to SLJ with response.So, erasing voltage VERS is inputed to global character line GWL1 to GWLJ with as character line bias voltage V via switch SW 15 to SWJ5 WT1 to V WTJ.
Moreover with response decoded signal DEC, and the local word line that connects the selection memory cell block respectively is to global character line GWL1 to GWLJ one of among the piece selected cell 160 selection memory cell block MB1 to MBK.For example, if selection memory cell block MB1, then the piece switch unit 161 of piece selected cell 160 makes block selection signal BSEL1 activation with response decoded signal DEC, and makes all block selection signal BSEL2 to BSELK anergies.As a result, only make the switch unit PG1 activation of piece selected cell 160, and make the whole anergies of switch unit PG2 to PGK.More detailed, switching device shifter GD1, G11 to G1J and the GS1 of the switch unit of conducting simultaneously PG1, and with switching device shifter GD2 to GDK, the G21 to G2J of switch unit PG2 to PGK ..., GK1 to GKJ, GS2 to GSK all by.So, make the drain electrode selection wire DSL1 of memory cell block MB1 be connected to overall situation drain electrode selection wire GDSL, and make drain selection line SSL1 be connected to overall source electrode selection wire GSSL.Therefore, as drain bias V with low voltage level GDAnd source electrode bias voltage V GSWhen being applied to drain electrode selection wire DSL1 and drain selection line SSL1 respectively, select transistor DST1 and drain selection transistor SST1 by drain electrode.So, drain electrode and the source electrode of the memory cell M111 to M1JT of memory cell block MB1 are floated.
In addition, make the local word line WL11 to WL1J of memory cell block MB1 be connected to global character line GWL1 to GWLJ respectively.As a result, with the character line bias voltage V of global character line GWL1 to GWLJ WT1 to V WTJ is sent to local word line WL11 to WL1J respectively.Therefore, between the grid of the memory cell M111 to M1JT of memory cell block MB1 and body, (for example produce voltage difference, 15V or higher), and, use the erase operation of implementing memory cell M111 to M1JT by the floating grid release electronics of voltage difference from memory cell M111 to M1JT.
Simultaneously, the drain electrode selection wire DSL2 to DSLJ of memory cell block MB2 to MBK and overall situation drain electrode selection wire GDSL are isolated, and drain selection line SSL2 to SSLJ and overall source electrode selection wire GSSL are isolated.Moreover, make memory cell block MB2 to MBK local word line WL21 to WL2J ..., WLK1 to WLKJ and global character line GWL1 to GWLJ all isolate.So, by high voltage level (for example, bulk voltage V 20V) CBLifting local word line WL21 to WL2J ..., WLK1 to WLKJ, wherein bulk voltage V CBBe applied to the memory cell of memory cell block MB2 to MBK.Therefore, local word line WL21 to WL2J ..., produce near bulk voltage V among the WLK1 to WLKJ CBBooster voltage V BSTIn this case, will with reference to 8A and 8B figure more detailed description nmos pass transistor G21 to G2J ..., GK1 to GKJ operation, wherein nmos pass transistor G21 to G2J ..., GK1 to GKJ be connected in memory cell block MB2 to MBK local word line WL21 to WL2J ..., between WLK1 to WLKJ and global character line GWL1 to GWLJ.8A and 8B figure show the sectional view of nmos pass transistor GK1 and the potential energy of nmos pass transistor GK1 respectively.Nmos pass transistor G21 to G2J ..., GK2 to GKJ operation similar in appearance to the operation of nmos pass transistor GK1.Therefore, omit its detailed description for simplicity.
Fig. 8 A is the sectional view of nmos pass transistor GK1 (switching device shifter), and nmos pass transistor GK1 is connected to the local word line WLK1 of memory cell block MBK.The source electrode 72 of nmos pass transistor GK1 be applied in have on the occasion of character line bias voltage V WT1, and the grid 74 of nmos pass transistor GK1 is applied in (for example, block selection signal BSELK 0V) that has low voltage level.The drain electrode 73 of nmos pass transistor GK1 has been applied in booster voltage V BSTWhen block selection signal BSELK is in a low level, by nmos pass transistor GK1.In addition, because character line bias voltage V WT1 have on the occasion of, so the potential energy in source electrode 72 zones is reduced to about Ev2 shown in 8B figure.So, reduce the amount of electrons that is introduced into substrate 71 from source electrode 72, and reduce the amount of electrons that is introduced into local word line WLK1, wherein local word line WLK1 is connected to drain electrode 73.As a result, when reducing the leakage current that in nmos pass transistor GK, is produced, make local word line WLK1 keep booster voltage V BSTLevel.Therefore, do not wipe the data of the memory cell that is connected to local word line WLK1.
On the other hand, at character line bias voltage V with 0V WT1 is applied in the situation of source electrode 72, and the potential energy in source electrode 72 zones increases to about Ev1 shown in 8B figure.So the amount of electrons that is introduced into substrate 71 from source electrode 72 increases, the magnitude of leakage current of nmos pass transistor GK1 increases.In this relation, reduce the leakage current of nmos pass transistor GK1, need to reduce the potential energy in source electrode 72 zones.
After implementing erase operation under the above-mentioned state, determine whether suitably all memory cells of erase block, wherein piece has been implemented erase operation.This can use the data of being exported from Y-code translator 180 via page buffer 170 to confirm.
For example, if the data that Y-code translator 180 is exported are " 1 ", then can determine suitably to implement erase operation, wherein in the state that 0V is applied to all character lines be that read operation is implemented on the basis with the string.If the data that Y-code translator 180 is exported are " 0 ", then can determine suitably not implement as yet erase operation.
In the prior art, behind the determining of erase operation failure, the unit is labeled as " invalid unit ".After do not use these unit, this causes the minimizing of data storing capacity.Yet, in the present embodiment, by being increased in voltage difference between character line and body implementing erase operation once more, so that can suitably implement erase operation subsequently by the unit of first erase operation.This minimizes the situation that too early memory block is marked as invalid block.Now with more detailed description by the above-mentioned voltage difference of control to implement the program of erase operation once more.
9A to 9C figure is the waveform that is associated in the circuit diagram of the 5th figure, wherein when the erase operation of foundation one embodiment voltage is applied to global character line and P wellblock.10A to 10C figure is the waveform that is associated in the circuit diagram of the 5th figure, wherein according to the erase operation of another embodiment the time voltage is applied to global character line and P wellblock.
With reference to 9A figure, by apply have on the occasion of erasing voltage V WTJ is to global character line GWL and bulk voltage V CBTo body PWELL to implement erase operation.Bulk voltage V CBIn fact greater than erasing voltage V WTJ has for example 15V or more.After trial is wiped in enforcement first, implement the erase verification program to determine whether suitably to implement erase operation.If wiped all memory cells in the selection memory piece, then determine suitably to implement erase operation.If do not wipe the one or more memory cells in the selection memory piece as yet, then determine suitably not implement as yet erase operation.The erase verification program comprises the data of checking that Y-code translator 180 is exported.The data that Y-code translator 180 is exported input to second bias generator 60 and bulk voltage generator 40, and wherein second bias generator 60 produces erasing voltage V WTJ.
If determine suitably not implement erase operation as yet, then implement second and wipe trial.Second wipes and attempts comprising and make second bias generator 60 reduce erasing voltage V WTThe level of J has specified rate (for example 0.1 to 0.5V) and applies erasing voltage V through reducing WTJ is to global character line GWL.So, be increased in the voltage difference between global character line GWL and body PWELL.
Implement another erase verification program determining whether to wipe all memory cells in the selection memory piece, that is, whether suitably implement second and wipe trial.If determine that suitably not implementing second as yet wipes trial, then by making second bias generator 60 reduce erasing voltage V WTThe level of J has specified rate (for example 0.1 to 0.5V) with further increase voltage difference and apply and implement the 3rd once the erasing voltage that reduces to global character line GWL and wipe trial.This method for deleting is called " increment stepping pulsed erase (IncrementalStepping Pulse Erase, ISPE) method ".Increase voltage difference and implement erase operation once more according to the ISPE method.
Repeat to wipe trial, till the number of times of suitably wiping all selection memory unit or wiping trial equals pre-determined number.If after predetermined number of attempts, suitably do not wipe all selection memory unit as yet, then the memory block mark become invalid block.Can be according to the application settings pre-determined number.
The above-mentioned description when implementing erase operation reduced the erasing voltage V that is applied to global character line GWL WTJ is so that be increased in voltage difference between character line and body.Yet shown in 8B figure, bulk voltage generator 40 can promote bulk voltage V CBHave 0.5 to 1V, so that be increased in the voltage difference between character line and body.In another situation, shown in 8C figure, bulk voltage generator 40 can increase bulk voltage V CB, second bias generator 60 reduces erasing voltage V simultaneously WTJ is so that be increased in voltage difference between character line and body.
Described above with linear function and reduced erasing voltage V WTJ or promote bulk voltage V with linear function CBYet, shown in 10A to 10C figure, can reduce erasing voltage V by exponential function WTJ or can exponential function promote bulk voltage V CBIn another situation, can reduce erasing voltage V by quadratic function WTJ or can quadratic function promote bulk voltage V CB
According to said method, the reducing to minimum and also can not prevent that threshold voltage from reducing because of the shallow phenomenon of wiping in implementing non-selected of erase operation as yet of voidable piece of the present invention perhaps prevents fast programming or wipes the generation of phenomenon at a slow speed when repeating to implement erase operation.
The 11st figure is in order to the performance diagram of non-selected variations in threshold voltage when the erase operation relatively.In the prior art, in switching device shifter, produce leakage current (for example, the G1J among the 5th figure, wherein J is an integer).So, produce the shallow phenomenon of wiping, and the shallow phenomenon of wiping is to implement erase operation in the state that reduces the voltage that is applied to character line gradually.Based on this reason, produce following point: the threshold voltage that is reduced in the memory cell in non-selected.
Yet, in the present invention, in the global character line is applied in the state of positive erasing voltage, implement erase operation, so that prevent the generation of the leakage current in switching device shifter (for example, the G1J among the 5th figure, wherein J is an integer).So, in non-selected, seldom produce the shallow phenomenon of wiping.Therefore, can make the variations in threshold voltage amount reduce to minimum.
The 12nd figure describes according to embodiments of the invention to depend on the erasing characteristic at a slow speed of number of times of erase operation and the performance diagram of fast programming characteristic.In first erase operation, make the voltage difference between character line and body maintain and suitably to implement in the scope of erase operation.If suitably implement erase operation, then by increasing voltage difference to implement erase operation once more.Therefore, though repeatedly implement erase operation, generation fast programming phenomenon and low speed are wiped phenomenon in about 0.5V scope.Consider producing the fast programming phenomenon shown in the 2nd figure of the prior art at least more than the 2V and wiping at a slow speed under the phenomenon, can find out that from the 12nd figure seldom producing fast programming phenomenon or low speed in the present invention wipes phenomenon.
As previously discussed, the present invention includes one or more advantages in the following advantage.At first, when erase operation, apply be higher than 0V voltage to the global character line.Therefore, can allow to prevent the generation of leakage current in switching device shifter, wherein switching device shifter is connected between global character line and the local word line.Therefore, can prevent from not implement as yet the minimizing of voltage of non-selected character line of erase operation, and can in non-selected, prevent shallow generation of wiping phenomenon.
The second, in the prior art, after implementing erase operation, verify whether suitably implement in the program of erase operation, if having the memory cell of suitably not implementing erase operation as yet, then corresponding blocks is considered as invalid block and reaches thereby do not use corresponding blocks.This causes the minimizing of data storing capacity.Yet, in the present invention, if there is the memory cell suitably do not implement erase operation as yet, by being increased in voltage difference between character line and body to implement erase operation once more.Therefore, can allow to make the minimum minimum that is reduced to that reaches thereby make the data storing capacity of reducing to of invalid block.
The 3rd, if from the state that just has for the first time high voltage differential between character line and body, implementing erase operation, then because of making electron trapping on tunnel oxide or provide stress, so may reduce the electrical specification of memory cell to tunnel oxide.Yet, in the present invention, only use minimum voltage difference to implement erase operation for erase operation.If the erase operation failure is then by increasing voltage difference to implement erase operation once more.So, can make in amount of electrons of being subside on the tunnel oxide or the stress that on tunnel oxide, provided and reduce to minimum, this causes the life-span of memory cell to prolong.
The 4th, in the present invention, when initial erase is operated, use minimum voltage difference to implement erase operation.If fail, then by increasing voltage difference to implement erase operation once more.Therefore, though repeatedly implement to read/erase operation, can prevent fast programming or wipe the taking place of phenomenon at a slow speed to maximum magnitude.
According to aforesaid operations, can improve the reliability of erase operation, can make reducing to of failure minimum, and the life-span that can increase device.
Though before described various embodiment, recognized that haveing the knack of a skill person can implement change of the present invention and modification in spirit that does not break away from the present invention and appended request item and scope.

Claims (33)

1. non-volatile memory device comprises:
First memory cell block and second memory cell block, each memory cell block comprise a plurality of memory cells and comprise local drain electrode selection wire, local source electrode selection wire and many local word lines;
The piece selected cell, connect respectively given local word line to the global character line with the response block selection signal;
First bias generator, be configured in order to during erase operation, to apply at least the first erasing voltage and second erasing voltage to the global character line, first erasing voltage is wiped at first of erase operation and is applied to the global character line between trial period, second erasing voltage is wiped second and is applied to the global character line between trial period, if wherein first wipe trial and successfully do not implement erase operation, then implement second and wipe trial, first erasing voltage and second erasing voltage are positive voltages; And
The bulk voltage generator applies the body of bulk voltage to memory cell during erase operation.
2. storage arrangement as claimed in claim 1, wherein each enforcement is newly wiped when attempting, and reduces the erasing voltage that is applied to the global character line by given voltage, wherein after trial is wiped in the failure of pre-determined number, stops given erase operation.
3. storage arrangement as claimed in claim 1, wherein first bias generator produces erasing voltage, becomes 15V so that the voltage difference between local word line and body is wiped when attempting first, and body is the wellblock, is formed with the first memory cell block in the wellblock.
4. storage arrangement as claimed in claim 3, wherein each enforcement is newly wiped when attempting, and reduces the erasing voltage that is applied to the global character line by given voltage, and wherein given voltage is not more than 0.5V.
5. storage arrangement as claimed in claim 1 further comprises:
Page buffer is in order to read in data stored in the memory cell; And
The Y-code translator is in order to export data stored in page buffer to the data I/O impact damper and first bias generator.
6. storage arrangement as claimed in claim 5, wherein the data exported according to the Y-code translator of first bias generator reduce by first erasing voltage to the second erasing voltage,
Wherein storage arrangement is the nand flash memory device.
7. flash memory device comprises:
A plurality of memory cell block, each memory cell block comprise local drain electrode selection wire, local source electrode selection wire and many local word lines respectively, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines;
The piece selected cell, connect respectively local word line to the global character line with the response block selection signal;
First bias generator applies positive erasing voltage to the global character line when erase operation; And
The bulk voltage generator, be configured to apply the body of first bulk voltage between trial period to memory cell in order to wipe at first of erase operation, if and suitably do not implement first as yet and wipe trial, then wipe and apply second bulk voltage between trial period to body second.
8. flash memory device as claimed in claim 7 if wherein first wipe trial and do not wipe as yet at selected all memory cells of erase operation, thinks that then suitably not implementing first as yet wipes trial.
9. flash memory device as claimed in claim 7, wherein the bulk voltage generator produces first bulk voltage, is 15V at least so that the voltage difference between local word line and body is wiped when attempting first.
10. flash memory device as claimed in claim 9, wherein the bulk voltage generator increases by first bulk voltage and is no more than 1V to produce second bulk voltage.
11. flash memory device as claimed in claim 7 further comprises:
Page buffer is in order to read in data stored in the memory cell; And
The Y-code translator is in order to export data stored in page buffer to data I/O impact damper and bulk voltage generator.
12. flash memory device as claimed in claim 11, wherein the data exported according to the Y-code translator of bulk voltage generator produce second bulk voltage, wipe trial so that implement second of erase operation.
13. a flash memory device comprises:
A plurality of memory cell block, each memory cell block comprise local drain electrode selection wire, local source electrode selection wire and many local word lines respectively, and a plurality of memory cell is connected to local drain electrode selection wire, local source electrode selection wire and many local word lines;
The piece selected cell, in order to connect respectively local word line to the global character line with the response block selection signal;
First bias generator, in order to apply positive erasing voltage to the global character line when the erase operation, if and have the memory cell be not wiped free of as yet, then reduce erasing voltage and apply erasing voltage to the global character line, so that implement erase operation once more through reducing; And
The bulk voltage generator, in order to apply the body of bulk voltage when the erase operation to memory cell, if and have the memory cell be not wiped free of as yet, then increase bulk voltage and apply bulk voltage to body, so that carry out erase operation again through increasing.
14. flash memory device as claimed in claim 13, wherein:
When described erase operation, first bias generator and bulk voltage generator produce erasing voltage and bulk voltage respectively, so that the voltage difference between local word line and body becomes 15V; And
When implementing erase operation once more, the bulk voltage generator increases bulk voltage and first bias generator reduces erasing voltage, is higher than 15V so that the voltage difference between local word line and body becomes.
15. flash memory device as claimed in claim 13, wherein:
First bias generator reduces erasing voltage with linear function, quadratic function or exponential function under 0.1 to 0.5V benchmark; And
The bulk voltage generator increases bulk voltage with linear function, quadratic function or exponential function under 0.5 to 1V benchmark.
16. flash memory device as claimed in claim 13 further comprises:
Page buffer is in order to read in data stored in the memory cell; And
The Y-code translator is in order to export data stored in page buffer to data I/O impact damper, bulk voltage generator and first bias generator.
17. flash memory device as claimed in claim 16, if wherein detect the obliterated data not as yet of data that the Y-code translator exported, then first bias generator reduces erasing voltage and the bulk voltage generator increases bulk voltage, so that implement erase operation once more.
18. flash memory device as claimed in claim 13 further comprises the X-code translator, the X-code translator is in order to the decoding column address signal and export block selection signal to high-voltage generating unit.
19. flash memory device as claimed in claim 11 further comprises second bias generator, second bias generator in order to according to programming, read and erase operation in any operation apply scheduled operation voltage to local drain electrode selection wire and local source electrode selection wire.
20. flash memory device as claimed in claim 17, wherein first bias generator comprises:
First pump circuit, in order to produce read operation required read voltage with the response reading command;
Second pump circuit is in order to produce the required program voltage of programming operation with the response programming instruction;
The 3rd pump circuit, in order to producing erasing voltage with the response erasing instruction, and if detect the data of being exported based on the Y-code translator and determine as yet not obliterated data, then reduce erasing voltage and output reduces erasing voltage; And
Biasing selected unit, in order to select to read voltage, program voltage or erasing voltage with the operation response command signal and respectively output select voltage to the global character line.
21. flash memory device as claimed in claim 20, wherein biasing selected unit comprises:
Select signal generator, select signal in order to produce according to operation instruction signal; And
A plurality of selection circuit are connected to the global character line respectively, select circuit arrangement to become to read voltage, program voltage, erasing voltage or its in order to output respectively to be incorporated into the global character line and to select signal with response.
22. the method for an erasable nonvolatile memory device, method comprises:
The local word line of connection selection piece and global character line are with the response block selection signal respectively;
Make that by applying first erasing voltage to global character line and first bulk voltage to the body that is higher than first erasing voltage voltage difference between local word line and body is that first potential difference (PD) is implemented first of erase operation and wiped trial;
Determine whether suitably to implement first and wipe trial; And
If determine that suitably do not implement first as yet wipes trial, then implement second of erase operation and wipe trial to increase voltage difference to the second potential difference (PD) between local word line and body to global character line and second bulk voltage to body by applying second erasing voltage.
23. method as claimed in claim 22, wherein second erasing voltage is less than first erasing voltage.
24. method as claimed in claim 22, wherein second bulk voltage is greater than first bulk voltage.
25. method as claimed in claim 22, wherein first erasing voltage is different with second erasing voltage, and first bulk voltage is different with second bulk voltage.
26. method as claimed in claim 22, wherein as yet not the successful implementation pre-determined number wipe trial after, stop erase operation, wherein as yet not the successful implementation pre-determined number wipe trial after, will select the piece mark to become invalid block.
27. a method of controlling the erase operation of flash memory device, method comprises:
The local word line of connection selection piece and global character line are with the response block selection signal respectively;
Apply the body of positive erasing voltage to implement erase operation by the foundation erasing instruction to global character line and the bulk voltage that is higher than erasing voltage to memory cell;
Determine whether suitably to implement erase operation; And
If determine suitably not implement as yet erase operation, then make the voltage difference change between local word line and body come to implement once more erase operation greatly by controlling erasing voltage and bulk voltage simultaneously.
28. method as claimed in claim 24, wherein repeatedly implement to determine whether suitably to implement the step of erase operation, carry out simultaneously with the execution number of times identical and to reduce erasing voltage in predetermined level and increase bulk voltage in predetermined level with this step, and comprise if till pre-determined number, suitably do not implement erase operation as yet, then corresponding blocks is considered as invalid block.
29. method as claimed in claim 27 is wherein set erasing voltage and bulk voltage, makes that the voltage difference between local word line and body is 15V or higher.
30. method as claimed in claim 27 wherein reduces erasing voltage with 0.1 to 0.5V benchmark, makes that the voltage between local word line and body is worse than increase in the scope, wherein voltage difference becomes 15V at least.
31. method as claimed in claim 27 wherein reduces erasing voltage with exponential function, makes that the voltage between local word line and body is worse than increase in the scope, wherein voltage difference becomes 15V at least.
32. method as claimed in claim 27 wherein increases erasing voltage with 0.5 to 1V benchmark, makes that the voltage between local word line and body is worse than increase in the scope, wherein voltage difference becomes 15V at least.
33. method as claimed in claim 27 wherein increases erasing voltage with exponential function, makes that the voltage between local word line and body is worse than increase in the scope, wherein voltage difference becomes 15V at least.
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