CN106205706B - The relative erasing method of memory device - Google Patents
The relative erasing method of memory device Download PDFInfo
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- CN106205706B CN106205706B CN201510214671.2A CN201510214671A CN106205706B CN 106205706 B CN106205706 B CN 106205706B CN 201510214671 A CN201510214671 A CN 201510214671A CN 106205706 B CN106205706 B CN 106205706B
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Abstract
The present invention is a kind of relative erasing method of memory device.The memory device includes multiple memory blocks and a controller.The memory blocks such as this include: at least one first memory block and at least one second memory block.Erasing method performed by controller comprises the steps of: sequentially carries out that a first stage erases operation and a second stage is erased operation in a first period and a second phase at least one first memory block in the memory blocks such as this；And sequentially carry out that the first stage erases operation and the second stage is erased operation at least one second memory block in the memory blocks such as this during the second phase and a third.
Description
Technical field
The invention relates to a kind of relative erasing methods of memory device, and in particular to a kind of use
The relative erasing method of memory device of pipeline architecture (pipeline configuration).
Background technique
Flash memory (flash memory) is a kind of fairly common non-volatility memorizer (non-volatile
memory).Flash chip includes multiple storage units.
Referring to Figure 1, be a non-volatile formula memory storage unit side view.In simple terms, the control of flash memory
Between end C and substrate 13 processed, it can be used for storing charge.The operation of flash memory can be roughly divided into: write operation, read operation, erase behaviour
Make.Write operation and operation of erasing all are the control terminals changed in transistor cell (transistor memory cell)
Between C and base stage (substrate), stored charge (charge) amount number.
As the stored quantity of electric charge changes, critical voltage (the threshold voltage, referred to as V of transistorth)
With change.Wherein, write operation is changing critical voltage (V in such a way that control terminal C applies positive voltageth), critical electricity
Press (Vth) size can change with the data content that is written.On the other hand, operation of erasing is then by applying in control terminal C
The mode of negative voltage changes critical voltage (Vth).Read operation is then to apply voltage between drain D and source S, when being exerted by
The voltage of control terminal C reaches critical voltage (Vth) when, thus it will make memory cell conducts (turn on).Thereafter, further according to making to deposit
Critical voltage (the V of storage unit conductingth) value judge the data content that the storage unit is stored.
Fig. 2 is referred to, is when erase to storage unit operating, storage unit number is relative to threshold voltage variations
Schematic diagram.Wherein curve location is higher, indicates that storage unit number corresponding with the critical voltage is more.One is represented herein
After single-layer memory cell (single-level cell, referred to as SLC) is written into data, critical voltage is original level (V0).
In order to reuse this storage unit, just need to apply negative voltage to storage unit, and then make facing for storage unit
Boundary voltage (Vth) mobile to the left side of Fig. 2.
Each flash chip is made of multiple memory blocks (block), and each block then further includes many pagings
(page).Erase flash memory when, need to be as unit of memory block.When write-in or reading flash memory, then as unit of paging.It is grasped with reading
Work, write operation are compared, and the operation of erasing of flash memory needs to spend longer time.It is, in general, that write operation and read operation
The required time is about microsecond (μ s) grade, and erasing and operating the required time is about millisecond (ms) grade.Memory block is carried out
Erasing, it is comparable time-consuming to operate, it is also desirable to a large amount of electric power.
Control circuit to memory block sending erase instruct when, be not only the simple storage unit in memory block and apply
Add negative voltage, it is also necessary to further confirm the critical voltage (V of all storage units in memory blockth) really all low
In the verifying voltage V that eraseserase.Herein by the critical voltage (V of all storage units in memory blockth) be lower than and erased
Verifying voltage VeraseIt is known as meeting verification condition.If verification condition is unsatisfactory for, control circuit will control voltage to memory block again
It is secondary to erase, until the critical voltage (V of all storage unitsth) be below and meet the verifying voltage V that eraseseraseUntil.Herein
By the critical voltage (V of the storage unit after erasingth) it is known as target level Vtarget.Herein and memory block will be issued
It erases after instruction, the timing definition of required cost is the period T that erases of memory blockerase。
Fig. 3 is referred to, is after erasing instruction to a memory block sending, what the mode of operation of memory block changed shows
It is intended to.Memory block 15a before erasing is known as using rear memory block, and the memory block 15b after erasing is known as idle memory block
Block (free block).As previously mentioned, each storage unit in memory block is required to be erased and be verified.With depositing
The factors such as the storage unit number increase for being included in the increase for the number of pages that storage area block is included or each paging, are deposited
The storage unit number that storage area block is included also and then increases.Related, cost needed for instructing of erasing to memory block sending
The period T that erases of memory blockeraseAlso increasingly longer.
The period T that erases of memory blockeraseThe elongated use experience that not only will affect user, it is also possible to because of such
Flash memory control chip is set to be mistaken for damaging by flash chip.Because flash memory control chip can be for the sending for instruction of erasing
And one section of waiting time is preset, if after waiting time passes through, still can not be successfully and receive the verifying item that memory chip is returned
When the information that part passes through, the instruction that will will erase writes off.It may is that however, waiting time is elongated because memory block is wrapped
The increase of the storage unit number contained, and then the time erased to memory block is caused also to follow elongated reason.Also because
This, flash chip may thus be mistaken for damaging by flash memory control chip.Therefore, how quickly to erase to generate idle deposit
Storage area block (free blocks) has become an important issue.
Summary of the invention
According to the first aspect of the invention, a kind of erasing method is proposed, applied to the storage comprising multiple memory blocks
Device device, the erasing method comprise the steps of: sequentially in a first period and a second phase in the memory blocks such as this
At least one first memory block carries out that a first stage erases operation and a second stage is erased operation；And sequentially in this second
During period and a third at least one second memory block in the memory blocks such as this carry out the first stage erase operation and
The second stage is erased operation.
According to the second aspect of the invention, propose a kind of memory device, include: multiple memory blocks include: at least one
First memory block；And at least one second memory block；And a controller, the memory blocks such as this are electrically connected to, sequentially
A first stage is carried out at least one first memory block in a first period and a second phase to erase operation and one second
Stage erases operation, and sequentially during the second phase and a third at least one second memory block carry out this first
Stage erase operation and the second stage erase.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates institute
Attached drawing is described in detail below:
Detailed description of the invention
Fig. 1 is the side view of the storage unit of a non-volatile formula memory.
Fig. 2 is signal of the storage unit number relative to threshold voltage variations when erase to storage unit operating
Figure.
Fig. 3 is the schematic diagram that the mode of operation of memory block changes after erasing instruction to a memory block sending.
Fig. 4 A is the schematic diagram that solid-state storage device includes multiple flash chips.
Fig. 4 B is the schematic diagram that quick flashing note memory chip includes multiple flash blocks.
Fig. 5 is the schematic diagram erased by three second part and instruct the critical voltage for changing memory block.
Fig. 6 is the signal that instruction erase to memory block during the erasing of operation of being erased by three second part
Figure.
Fig. 7 is issued multi-tiling part to multiple memory blocks and is erased the signal of instruction using three pipeline stages
Figure.
Fig. 8, be using three pipeline stages, and in each pipeline stage simultaneously to multiple memory blocks execute it is multiple-
The schematic diagram that part is erased.
It includes to fulfil the schematic diagram of the memory block for operation of erasing ahead of schedule that Fig. 9, which is in pipeline stage,.
Figure 10 is to instruct the schematic diagram erased to memory block by block erasure.
Figure 11 and is issued multiple-sub-block in each pipeline stage and erased the showing of instruction using three pipeline stages
It is intended to.
Figure 12, be using three pipeline stages, and in each pipeline stage simultaneously to multiple memory blocks execute it is multiple-
Sub-block is erased the schematic diagram of instruction.
Figure 13 A~Figure 13 F is when erasing to instruct the practice to memory block sending sub-block, to back up memory block in advance
The schematic diagram of the data stored.
Figure 14 A~Figure 14 E is when erasing to instruct to memory block sending sub-block, elastic to select point being erased
The schematic diagram of page.
Figure 15 is the schematic diagram using each functional layer of the data processing system of memory device.
[symbol description]
Substrate 13 erase before memory block 15a
Memory block 15b solid-state storage device 20 after erasing
Controller 23
Flash chip 251,252,253,254,30
Memory block 251a, 251b, 251c, 251d, 252a, 252b, 252c, 252d, 253a, 253b, 253c, 253d,
254a、254b、254c、254d、35、37、39、40a、40b、40c、40d、41a、41b、41c、41d、42a、42b、42c、42d、
43a、43b、43c、61、63、71
First memory block 41,51 second memory blocks 42,52
Third memory block 43,53 the 4th memory blocks 44,54
5th memory block 45,55 the 6th memory blocks 46,56
7th memory block 47,57 the 8th memory blocks 48,58
9th memory block 49,59 the tenth memory blocks 410,60
Paging 50a, 50b, 50c, 50d, 50e, 50f, 51a, 51b, 51c, 51d, 51f, 52a, 52b, 52c, 52d, 52e,
52f、53a、53b、53c、53d、53e、53f、61a、61b、61c、61d、61e、61f、63a、63b、63c、63d、63e、63f、
71a、71b、71c、71d、71e、71f
80 application program 81 of system
The original file system 88 of block file system 83
85 distributor 851 of flash translation layer (FTL)
Averager 855 is lost in cleaner 853
Memory technology device 87 reads driver 871
Part 873 multiple partial of driver of erasing is erased driver 874
Write driver program 875 is erased driver 876
The sub-block multiple sub-block of driver 877 of erasing is erased driver 878
Specific embodiment
In order to improve to memory block sending erase instruct when, spend overlong time the phenomenon that.The present invention proposes a kind of benefit
With pipeline architecture multiple memory blocks are synchronized with the practice erased.The block that is used alternatingly below, memory block represent
Flash block.In addition, in the following figures, with the shading of trellis represent via selected by Algorithms of Selecting, need by with
In the memory block erased.
Flash memory devices or solid-state storage device (Solid State Drive, referred to as SSD) may include multiple sudden strains of a muscle
Chip is deposited, these memory chips each the memory block of some may need to be erased.Alternatively, being deposited for single
Inside memory chip, it is also possible to there are multiple memory blocks to erase.After all elements of solid state hard disk are completed, packet
It is used to manage the flash memory storage processor (FSP) of numerous nand flash memory particles containing one.Solid state hard disk manufacturer can be tough in progress
When body programming, additionally retain a part of hard disc storage capacity as over capacity cache (over-provisioning, abbreviation
For OP).Over capacity cache is generally used for junk data recycling function (garbage collector) and loss average function
(wear leveller).In an embodiment of the present invention, over capacity cache is also further utilized, as progress pipeline stage
(pipeline erase stages) required cushion space of erasing, and the memory capacity for maintaining user that can use.
Fig. 4 A is referred to, is the schematic diagram that solid-state storage device includes multiple flash chips.Positioned at external host 21
(such as: solid-state storage device 20 CPU of laptop) is connected to by external bus, and inside solid-state storage device 20
Multiple flash chips 251,252,253,254 are controlled by controller 23.For purposes of illustration only, it is assumed herein that each flash chip
251,252,253,254 four flash blocks are respectively contained.Memory chip 251 include memory block 251a, 251b,
251c,251d；Memory chip 252 includes memory block 252a, 252b, 252c, 252d；Memory chip 253 includes storage
Block 253a, 253b, 253c, 253d；Memory chip 254 includes memory block 254a, 254b, 254c, 254d.Controller 23
The state of each memory block on different flash chips 251,252,253,254 can be rested in.Such as: memory block
251a, 252a, 254a are in the state for needing to be erased；Memory block 251b, 252c, 252d, 253b, 253c, 253d,
254b, 254c, 254d are in idle (free) state；Memory block 251c, 251d, 252b, 253a are storage valid data
State.
Fig. 4 B is referred to, is the schematic diagram that flash chip includes multiple flash blocks.Flash chip 30 includes more
A memory block, and controller 31 can grasp the use state of each memory block.For example, in figure 4b, with trellis shading
Square represents the memory block 37 in the state that is erased；To indicate the memory block that the square of data represents storage valid data
35, and represent with the square of blank the memory block 39 of not stored any data.
In an embodiment of the present invention, the selection of memory block to be erased can be obtained by all types of selection algorithms
Out.For example, least recently used (Least Recently Used, referred to as LRU) Algorithms of Selecting, greediness (Greedy) are chosen
Preferential (the Young Block first) Algorithms of Selecting of algorithm, most young memory block, the Algorithms of Selecting based on minimum effectively paging
(least valid page based selection) etc..Certainly, the mode of memory block that selection need to be erased not with
This is limited.
The mode of erasing of pipeline stage proposed by the invention, can in each pipeline stage, to it is multiple need by
The synchronous progress of the memory block erased is multiple-instruction of partially erasing (multiple partial erase command) or more
Weight-sub-block erases instruction (multiple subblock erase command).In pipeline stage, while it be used to smear
The multiple memory blocks removed, physical location do not need to be defined.In other words, the memory block for needing to be erased may be such as
It is located at the same chip shown in Fig. 4 B, or is located at different memory chips as shown in Figure 4 A.Even, part need by
The memory block erased is located on the same storage chip, remaining memory block that need to be erased then is dispersed in other storage chips
On.
It include the situation of multiple memory blocks for needing to be erased for memory device, erasing method of the invention proposes
It is synchronous to M group memory block to carry out instruction (the partial erase that partially erases with the practice that M pipeline stage carries out
Command) or sub-block erases instruction (subblock erase command).Wherein, M is positive integer.For purposes of illustration only, with
Under embodiment assume M=3, but be not limited thereto when practical application.During what if memory block of erasing needed erases
For Terase, after applying the present invention, at interval of Terase/ M can provide one group of idle memory block.Therefore, when the numerical value of M is got over
Greatly, to the wear leveling time of memory block also with shortening.
As previously mentioned, (erasing period) during the execution needed as T after issuing instruction of erasing to a memory blockerase。
M pipeline stage is divided into erasing for each memory block.It is erased instruction according to a kind of pipeline, is T in lengtherase/M
Each pipeline stage in, execute multiple pipelines and erase operation.First memory block can erasing the phase in memory block
Between TeraseIt completes to erase afterwards, thereafter, at interval of Terase/ M can provide a workable idle memory block after erasing
Block (free block).Conception according to the present invention can be divided into two classes with the instruction of erasing of the pipeline that uses of pipeline stage collocation, more
It weigh-partially erases instruction (multiple-partial erase command) and multiple-sub-block is erased instruction
(multiple-subblock erase command)。
Fig. 5 is referred to, is the schematic diagram erased by three second part and instruct the critical voltage for changing memory block.?
In this embodiment, the entire process of erasing is divided into three phases (M=3).It is erased instruction by the first second part, by memory block
The critical voltage of internal storage unit is moved to the first level V1 by original level V0.It executes the first second part and erases and instruct institute
The time that need to be spent is known as the period T1 that erases of first stage.It is erased instruction by the second second part, inside memory block
The critical voltage of storage unit is moved to second electrical level V2 by the first level V1.It executes the second second part and erases and instruct required cost
Time be known as the period T2 that erases of second stage.It is erased instruction by third second part, by the storage list inside memory block
The critical voltage of member is moved to target level V by second electrical level V2target.Execution third second part, which is erased, instructs required cost
Time is known as the period T3 that erases of phase III.Wherein, the period T1 that erases of first stage, second stage erase period T2 with
The length of the period T3 that erases of phase III is equal to each other.In addition, the voltage difference between original level V0 and the first level V1, greatly
Voltage difference between the first level V1 and second electrical level V2；And the first voltage difference between level V1 and second electrical level V2, greatly
In second electrical level V2 and target level VtargetBetween voltage difference.
Fig. 6 is referred to, is that instruction of being erased by three second part erase during the erasing of operation to memory block
Schematic diagram.For memory block 40a wait erase after the first second part erases instruction, the critical voltage of internal storage unit is equal
Become the first level V1 via original level V0.This shading for sentencing rectilinear direction is represented erases instruction by the first second part
Afterwards, critical voltage is the memory block 40b of the first level V1.
Then, second part is executed to the memory block 40b that critical voltage is the first bit level V1 to erase instruction, and then make
The critical voltage of internal storage unit becomes second electrical level V2 by the first level V1.This shading for sentencing crossline direction, which represents, to be passed through
Second second part is erased after instruction, and critical voltage is the memory block 40c of second electrical level V2.
Thereafter, Part III is executed to the memory block 40c that critical voltage is second electrical level V2 to erase instruction, and then make interior
The critical voltage of portion's storage unit becomes target level V by second electrical level V2target.This square for sentencing blank is represented by the
Three second part are erased after instruction, and critical voltage is target level VtargetMemory block 40d.
According to an embodiment of the invention, erase period T2 and the third rank of the period T1 that erases of first stage, second stage
The summation of the period T3 that erases of section is substantially equal to the period T that erases of single a memory blockerase, alternatively, the first stage erases
Period T1, second stage erase period T2 and phase III the period T3 that erases summation slightly larger than single a memory block
Erase period Terase。
Fig. 7 is referred to, is that instruction of partially erasing is simultaneously emitted by multiple memory blocks and is shown using three pipeline stages
It is intended to.The present invention for erasing the situation of instruction to multiple block issued section simultaneously, further define it is one multiple-partially erase
It instructs (multiple partial erase command).This attached drawing also assumes that M=3, that is, each memory block is individual
It completes to erase after three pipeline stages.The first row of Fig. 7 represent controller to storage chip issued it is multiple-partially smear
Except the sequencing of instruction.
The secondary series of Fig. 7 represents the process of erasing to the first memory block 41.First memory block 41 first it is multiple-
It partially erases during the execution of instruction, carries out first pipeline stage (T1).That is, making the storage unit in the first memory block 41
Critical voltage, the first level V1 is reduced to by original level V0.First memory block 41 is in second multiple-finger of partially erasing
During the execution of order, second pipeline stage (T2) is carried out.That is, making the critical electricity of the storage unit in the first memory block 41
Pressure, is reduced to second electrical level V2 by the first level V1.First memory block 41 third it is multiple-execution phase of instruction of partially erasing
Between, it carries out third pipeline stage (T3).That is, making the critical voltage of the storage unit in the first memory block 41, by the second electricity
Flat V2 is reduced to target level Vtarget.Third it is multiple-partially erase instruction after, the first memory block 41 is just completed
It erases.In other words, when executing since the 4th multiple-instruction of partially erasing, the first memory block 41 can be used for
Storing data.
The third column of Fig. 7 represent the process of erasing to the second memory block 42.Second memory block 42 second it is multiple-
Part erase instruction execution during (T1), carry out first pipeline stage (T1).That is, making the storage in the second memory block 42
The critical voltage of unit is reduced to the first level V1 by original level V0.Second memory block third it is multiple-partially erase
During the execution of instruction, second pipeline stage (T2) is carried out.That is, making the critical electricity of the storage unit in the second memory block 42
Pressure, is reduced to second electrical level V2 by the first level V1.Execution phase of second memory block in the 4th multiple-instruction of partially erasing
Between, it carries out third pipeline stage (T3).That is, making the critical voltage of the storage unit in the second memory block 42, by the second electricity
Flat V2 is reduced to target level Vtarget.The 4th it is multiple-partially erase instruction after, the second memory block 42 is just completed
It erases.In other words, when executing since the 5th multiple-instruction of partially erasing, the second memory block 42 can be used for
Storing data.
The 4th column of Fig. 7 represent the process of erasing to third memory block 43.Third memory block 43 third it is multiple-
It partially erases during the execution of instruction, carries out first pipeline stage (T1).That is, making the storage unit in third memory block 43
Critical voltage, the first level V1 is reduced to by original level V0.Third memory block 43 is in the 4th multiple-finger of partially erasing
During the execution of order, second pipeline stage (T2) is carried out.That is, making the critical electricity of the storage unit in third memory block 43
Pressure, is reduced to second electrical level V2 by the first level V1.Execution of the third memory block 43 in the 5th multiple-instruction of partially erasing
Period carries out third pipeline stage (T3).That is, making the critical voltage of the storage unit in third memory block 43, by second
Level V2 is reduced to target level Vtarget.The 5th it is multiple-partially erase instruction after, third memory block 43 is just complete
At erasing, and it can be used for storing data.
Accordingly, every by during the erasing of stage after third multiple-instruction execution of partially erasing, just
A memory block completion is had to erase and can be used for storing data.Since the period of erasing in each stage is approximately equal to (1/3)
×Terase, the speed of erasing of block entirety is allowed to be substantially improved.
Further, in each multiple-instruction execution of partially erasing, can also to simultaneously to multiple memory blocks into
It erases the part in row same line stage.Fig. 8 is referred to, is using three pipeline stages, and simultaneously in each pipeline stage
Multiple-schematic diagram for partially erasing is executed to multiple memory blocks.In this embodiment, multiple memory blocks are simultaneously emitted by more
It weigh-partially erases instruction.It also assumes that herein and three pipeline stage (M is divided into the operation of erasing of each memory block
=3).
The first row of Fig. 8 represents the sequencing for multiple-instruction of partially erasing that controller issues storage chip.Figure
8 secondary series is represented via selected by selection algorithm, starts carry out portion as during next multiple-instruction execution of partially erasing
Divide the memory block erased.Each column of remaining of Fig. 8 correspond to the state of memory block.
During the execution of first multiple-instruction of partially erasing, the first memory block 41 and the second memory block 42 are same
When be in the first pipeline stage (T1), and for carry out the first second part erase.That is, by the first memory block 41 and the second storage
The critical voltage V of the storage unit of block 42th, the first level V1 is moved to by original level V0.In addition, third memory block 43
Then it is selected as block to be erased with the 4th memory block 44.
During the execution of second multiple-instruction of partially erasing, the first memory block 41 and the second memory block 42 are same
When be in the second pipeline stage (T2), and for carry out the second second part erase.That is, by the first memory block 41 and the second storage
The critical voltage V of the storage unit of block 42th, second electrical level V2 is moved to by the first level V1.At the same time, third memory block
Block 43 and the 4th memory block 44 are then in the first pipeline stage (T1) simultaneously, and erase for carrying out the first second part.That is, will
The critical voltage V of the storage unit of third memory block 43 and the 4th memory block 44th, the first electricity is moved to by original level V0
Flat V1.In addition, the 5th memory block 45 and the 6th memory block 46 are then selected as block to be erased.
During the execution of the multiple-instruction of partially erasing of third, the first memory block 41 and the second memory block 42 are same
When be in third pipeline stage (T3), and erase for carrying out third second part.That is, by the first memory block 41 and the second storage
The critical voltage V of the storage unit of block 42th, target level V is moved to by second electrical level V2target.At the same time, third is deposited
Storage area block 43 and the 4th memory block 44 are then in the second pipeline stage (T2) simultaneously, and erase for carrying out the second second part.
That is, by the critical voltage V of third memory block 43 and the storage unit of the 4th memory block 44th, it is moved to by the first level V1
Second electrical level V2.And the 5th memory block 45 and the 6th memory block 46 be then in the first pipeline stage (T1) simultaneously, be used in combination
It erases in carrying out the first second part.That is, by the critical voltage of the 5th memory block 45 and the storage unit of the 6th memory block 46
Vth, the first level V1 is moved to by original level V0.In addition, the 7th memory block 47 is then selected as with the 8th memory block 48
Block to be erased.
After the multiple-instruction of partially erasing of third, the first memory block 41 has been erased with the second memory block 42
It completes.During the execution of the 4th multiple-instruction of partially erasing, third memory block 43 is located simultaneously with the 4th memory block 44
It erases in third pipeline stage (T3), and for carrying out third second part.That is, by third memory block 43 and the 4th memory block
The critical voltage V of 44 storage unitth, target level V is moved to by second electrical level V2target.At the same time, the 5th memory block
Block 45 and the 6th memory block 46 are then in the second pipeline stage (T2) simultaneously, and erase for carrying out the second second part.That is, will
The critical voltage V of the storage unit of 5th memory block 45 and the 6th memory block 46th, the second electricity is moved to by the first level V1
Flat V2.And the 7th memory block 47 and the 8th memory block 48 be then in the first pipeline stage (T1) simultaneously, and for carrying out
First second part is erased.That is, by the critical voltage V of the 7th memory block 47 and the storage unit of the 8th memory block 48th, by original
Beginning level V0 is moved to the first level V1.In addition, the 9th memory block 49 is then selected as with the tenth memory block 410 wait erase
Block.
Two embodiments for comparing Fig. 7 and Fig. 8 can be seen that deposits what each pipeline stage carried out partially erasing simultaneously
When the number of storage area block is more, whole speed also Synchronous lifting of erasing.For example, in Fig. 7, in erasing period for phase III
After T3, the completion of only the first memory block 41 is erased.On the other hand, in fig. 8, in the period T3 knot of erasing of phase III
Shu Hou, the first memory block 41 are completed to erase with the second memory block 42.Similarly, in M pipeline stage, if each is managed
The line stage can carry out part to N number of memory block and erase, then the speed for being integrally used to generate memory block after erasing can be further
It is promoted.That is, average at interval of TeraseMemory block after just generation one is erased during/(M*N).
In some cases, the storage unit in some memory blocks, the movement of critical voltage are relatively easy to.For this
Kind situation, it may occur however that memory block is completed before all pipeline stages are completed and erases.That is, critical voltage Vth
Level become target level V in more previous pipeline stagetarget.Management consistency consideration based on pipeline stage, needle
To such situation, after still waiting pipeline stage, which is just provided together and is deposited with other memory blocks as idle
Storage area block.
Fig. 9 is referred to, is the schematic diagram of the memory block in pipeline stage comprising fulfiling operation of erasing ahead of schedule.This attached drawing
Each memory block it is similar to Fig. 8 relative to the execution sequence of each pipeline stage and multiple-instruction of partially erasing.With Fig. 8
Unlike, in Fig. 9, after second multiple-instruction execution of partially erasing, although the second memory block 42 is just passed through
Second pipeline stage, but has reached the state for completion of erasing.Nonetheless, controller still can be by 42 row of the second memory block
Enter next pipeline stage.That is, controller can still issue third it is multiple-instruction of partially erasing is to the second memory block
42。
In general, instruction of erasing can be regarded as erasing circuit application voltage appropriate in memory block by one.Then, needle
The situation erased is fulfiled ahead of schedule to the second memory block 42, specially treated can be carried out by circuit of erasing.For example, circuit of erasing
During the execution of the multiple-instruction of partially erasing of third, part is carried out to the second memory block 42 again and is erased.Alternatively,
During the execution of the multiple-instruction of partially erasing of third, circuit of erasing, which can suspend, carries out part to the second memory block 42 again
It erases.Accordingly, there are the memory blocks of identical quantity by each pipeline stage of the whole process of erasing of maintenance for controller, and every
It maintains to generate N number of (in Fig. 9, N=2) idle memory block after the period of erasing in one stage.
Pipeline stage of the present invention can also be realized by the sub-block mode of erasing.Each memory block includes
Multiple pagings (for example, O paging).These pagings can be further classified as M group (M sub-block).Wherein, it is located in same group
Paging might not be adjacent to each other.After assuming that sub-block is erased, instruction is issued, circuit of erasing can be to the paging (O/ in same group
M paging) it erases.Sub-block, which erases to instruct, can make the critical voltage of specific one or the storage unit in multiple pagings
Vth is directly reduced to target level V by original level V0target。
Referring to Figure 10, it is the schematic diagram that instruction erases to memory block of being erased by sub-block.It is false herein
If each memory block includes 6 pagings 50a, 50b, 50c, 50d, 50e, 50f.That is, O=6.This six pagings are divided into three
Group.That is, M=3.Wherein each group includes two pagings.Instruct meeting every time right simultaneously in this embodiment, it is assumed that sub-block is erased
2 pagings therein are erased.
Before when pipeline stage starts, 6 pagings 50a, 50b, 50c, 50d, 50e, 50f in memory block are wait smear
Except state.After the period T1 that erases of first stage, paging 50e, 50f completion are erased.By erasing period for second stage
After T2, paging 50c, 50d completion are erased.After the period T3 that erases of phase III, paging 50a, 50b completion are erased.This hair
Bright embodiment can allow pipeline architecture and accelerate the speed integrally erased on the basis of Figure 10.
Referring to Figure 11, it is that multiple memory blocks are sent out simultaneously using three pipeline stages, and in each pipeline stage
Multiple out-sub-block is erased the schematic diagram of instruction.The process of erasing of memory block is divided into three pipeline stages by this embodiment
(M=3).In other words, after sub-block three times erases operation, the operation of erasing to memory block is completed.The first of Figure 11
Column represent multiple-sub-block that controller issues storage chip and erase the sequencing of instruction.
The secondary series of Figure 11 represents the process of erasing to the first memory block.First memory block is in first multiple-son
During the execution of block erasure instruction, it is in first pipeline stage (T1).At this point, controller control is erased, circuit is deposited to first
First group of paging 51e, 51f of storage area block erase.First memory block is erased the holding of instruction in second multiple-sub-block
Between the departure date, it is in second pipeline stage (T2).Second component of the circuit to the first memory block at this point, controller control is erased
Page 51c, 51d erase.First memory block third multiple-sub-block erase instruction execution during, be in third
A pipeline stage (T3).At this point, controller control is erased, circuit smears third component page 51a, 51b of the first memory block
It removes.After multiple-the sub-block of third erases the execution of instruction, the first memory block is just completed to erase.In other words, certainly
The instruction of erasing of 4th multiple-sub-block starts, and the first memory block can be used for storing data.
The third column of Figure 11 represent the process of erasing to the second memory block.Second memory block is in second multiple-son
During the execution of block erasure instruction, it is in first pipeline stage (T1).At this point, controller control is erased, circuit is deposited to second
Paging 52e, 52f in first sub-block of storage area block erase.Second memory block is smeared in the multiple-sub-block of third
Except instruction execution during, be in second pipeline stage (T2).At this point, controller control erases circuit to the second memory block
Second sub-block in paging 52c, 52d erase.Second memory block is erased instruction in the 4th multiple-sub-block
Execution during, be in third pipeline stage (T3).Third of the circuit to first memory block at this point, controller control is erased
Paging 52a, 52b in sub-block erase.After the 4th multiple-sub-block erases instruction, the second memory block
Just it completes to erase.In other words, since the 5th multiple-sub-block erases instruction, the second memory block can be used for
Storing data.
The 4th column of Figure 11 represent the process of erasing of third memory block.Third memory block is in the multiple-sub-district of third
Block erase instruction execution during, be in first pipeline stage (T1).At this point, controller control is erased, circuit stores third
First group of paging 53e, 53f of block erase.Third memory block is erased the execution of instruction in the 4th multiple-sub-block
Period is in second pipeline stage (T2).Second group paging of the circuit to third memory block at this point, controller control is erased
53c, 53d erase.Third memory block the 5th multiple-sub-block erase instruction execution during, in third
Pipeline stage (T3).At this point, controller control is erased, circuit erases to third component page 53a, 53b of third memory block.
After the 5th multiple-sub-block erases instruction, third memory block is just completed to erase.In other words, from more than the 6th
The instruction of erasing of weight-sub-block starts, and third memory block can be used for storing data.It holds, from the multiple-sub-district of third
Block is erased after being finished of instruction, every by that during the erasing of stage, will have a memory block completion to erase behaviour
Make and can be used for storing data.
Based on Figure 11, the erase execution of instruction of multiple-sub-block can also further arrange in pairs or groups in each pipeline stage
In, while multiple memory blocks are carried out simultaneously.Referring to Figure 12, it is using three pipeline stages, and in each pipeline rank
Section executes multiple-sub-block to multiple memory blocks simultaneously and erases the schematic diagram of instruction.This embodiment is same to multiple memory blocks
When issue multiple-sub-block and erase instruction.Also assume that erasing for a memory block is divided into three pipeline stages herein
(M=3).
First multiple-sub-block erase instruction execution during, the first memory block 51 and the second memory block 52
It is in the first pipeline stage (T1) simultaneously, and for erasing to respective first group of paging.In addition, third memory block 53
Then it is selected as block to be erased with the 4th memory block 54.
Before second multiple-sub-block erases instruction execution, the of the first memory block 51 and the second memory block 52
One group of paging has been completed to erase.During second multiple-sub-block erases instruction execution, the first memory block 51 and second
Memory block 52 is in the second pipeline stage (T2).At this point, controller control erases circuit to the first memory block 51 and second
Second group of paging of memory block 52 is erased.At the same time, third memory block 53 is then in the 4th memory block 54
First pipeline stage (T1), circuit of erasing smear third memory block 53 and first group of paging of the 4th memory block 54
It removes.In addition, the 5th memory block 55 and the 6th memory block 56 are then selected as block to be erased.
Before third multiple-sub-block erases instruction execution, the of the first memory block 51 and the second memory block 52
Two groups of pagings have been completed to erase, and third memory block 53 and first group of paging of the 4th memory block 54 have been completed to smear
It removes.Third multiple-sub-block erase instruction execution during, the first memory block 51 and the second memory block 52 are in the
Three pipeline stages (T3), circuit of erasing erase to the third component page of the first memory block 51 and the second memory block 52.
At the same time, third memory block 53 and the 4th memory block 54 are then in the second pipeline stage (T2), and circuit of erasing is to third
Memory block 53 and second group of paging of the 4th memory block 54 are erased.And the 5th memory block 55 and the 6th storage
Block 56 is then in the first pipeline stage (T1), and circuit of erasing is to first group of the 5th memory block 55 and the 6th memory block 56
Paging is erased.In addition, the 7th memory block 57 and the 8th memory block 58 are then selected as block to be erased.
Multiple-the sub-block of third is erased after instruction, and the first memory block 51 has been smeared with the second memory block 52
Except completion.Before the 4th multiple-sub-block erases instruction execution, the second of third memory block 53 and the 4th memory block 54
Group paging has been completed to erase, and first group of paging of the 5th memory block 55 and the 6th memory block 56 has been completed to erase.
The 4th multiple-sub-block erase instruction execution during, third memory block 53 and the 4th memory block 54 are in third
Pipeline stage (T3), circuit of erasing erase to third memory block 53 and the third component page of the 4th memory block 54.?
This simultaneously, the 5th memory block 55 and the 6th memory block 56 are then in the second pipeline stage (T2), and circuit of erasing is deposited to the 5th
Storage area block 55 is erased with the second group of paging of the 6th memory block 56 then.And the 7th memory block 57 and the 8th storage
Block 58 is then in the first pipeline stage (T1), and circuit of erasing is to first group of the 7th memory block 57 and the 8th memory block 58
Paging is erased.In addition, the 9th memory block 59 and the tenth memory block 510 are then selected as block to be erased.
Comparing Figure 11 and Figure 12 can be seen that in the case where also assuming that M=3, each pipeline stage is for applying
Multiple-sub-block erase instruction memory block number it is more when, to the speed also Synchronous lifting of erasing of memory block.For example,
In Figure 11, after the multiple-sub-block of third erases instruction, the completion of only the first memory block is erased.On the other hand,
In Figure 12, after the multiple-sub-block of third erases instruction, the first memory block 51 and the second memory block 52 are complete
At erasing.Similarly, it in M pipeline stage, erases if each pipeline stage can carry out part to N number of memory block, it is whole
Body is used to generate erase after the speed of memory block can further be promoted.
3A~Figure 13 F referring to Figure 1 is when erasing to instruct the practice to memory block sending sub-block, and backup is deposited in advance
The schematic diagram for the data that storage area block is stored.This attached drawing hypothesis selects memory block 61 as block to be erased, memory block 61
Include paging 61a, 61b, 61c, 61d, 61e, 61f.Wherein, paging 61a, 61e, 61f is in the state for needing to be erased；Paging
61c is blank paging；And paging 61b, 61d have newest data.
As shown in FIG. 13A, make corrupted data in order to avoid the newest data stored in paging 61b, 61d are erased
The phenomenon that, it, can be first by a storage to another backup of data duplication in paging 61b, 61d before carrying out pipeline and erasing
Block 63.Likewise, memory block 63 includes six pagings 63a, 63b, 63c, 63d, 63e, 61f.Memory block 63 it is each
The size of paging is identical as the size of each paging of memory block 61.Subsidiary one is mentioned that, for storing point of block to be erased
The backup memory block of data in page, might not whole pagings be idle idle memory block.
In other words, the data in paging 61b, 61d can also be copied to the storage that part paging is in idle state
Block.Even, data data1, data2 that paging 61b, 61d is stored, it is also possible to copied in the block of different memory areas respectively
Paging.The variation of this part can freely be applied by this case person of an ordinary skill in the technical field, and details are not described herein again.
Since data data1, data2 of paging 61b, 61d have already passed through backup it can be seen from Figure 13 B, paging is represented
The content of 61b, 61d belong to the data that can be erased.This is in the top mark cross of data data1, data2.
In Figure 13 C, 13D, 13E, it is selected using thick dark squares representative as the paging for erase in pipeline stage.?
In Figure 13 C, erase to first group of paging 61e, 61f of memory block 61.That is, memory block 61 enters the first pipeline rank
Section.In Figure 13 D, erase to second group of paging 61c, 61d of memory block 61.That is, memory block 61 enters the second pipe
The line stage.In Figure 13 E, erase to third component page 61a, 61b of memory block 61.That is, memory block 61 enters the
Three pipeline stages.Figure 13 F is represented after three pipeline stages, all paging 63a, 63b of memory block 61,63c, 63d,
63e, 61f are completed and erase.That is, the completion of memory block 61 erases and becomes idle block.
The present invention can be realized by different modes and improvement.Such as: if controller can be grasped in memory block respectively
The step of use state of a paging, the then aforementioned content for being stored paging is copied to other memory blocks, can omit.
4A~Figure 14 E referring to Figure 1 is when erasing to instruct to memory block sending sub-block, elastic to select to be smeared
The schematic diagram of the paging removed.The memory block 71 of Figure 14 A has the composition similar with the memory block 61 of Figure 13 A.That is, memory block
Paging 71a, 71e, 71f of block 71 are in the state for needing to be erased；Paging 71c is blank paging；And paging 71b, 71d are deposited
There is newest data.In Figure 14 B, Figure 14 C, Figure 14 D, it is selected using thick dark squares representative as in pipeline stage and carries out use of erasing
Paging.
In fig. 14b, it erases to paging 71e, 71f.That is, memory block 71 enters the first pipeline stage.In Figure 14 C
In, although memory block 71c, 71d, into the second pipeline stage, control is erased circuit only to paging 71c progress by controller
It erases.That is, controller, which is known, is stored with effect data data1 in paging 71d, and then the circuit that avoids erasing smears paging 71d
It removes.In some applications, although paging 71c, 71d is discharged into the second pipeline stage, but controller can further judge paging 71c
For blank paging, and after having valid data data1 in paging 71d, smeared in the second pipeline stage pause control circuit of erasing
Except operation.
In Figure 14 D, although memory block 71, into third pipeline stage, controller is only right by control circuit of erasing
Paging 71a erases.That is, controller, which is known, is stored with effect data data2 in paging 71b, so avoid erasing circuit to point
Page 71b erases.Figure 14 E represents result of the memory block after the erasing of third pipeline stage.
Further, if the function that sub-block is erased can be more elastic and can rest in actual needs in memory block and erase
Paging, then even can only using two pipeline stages i.e. complete erase.For example, first pipeline stage to paging 71e,
71f erases.And it erases in second pipeline stage to paging 71a.About the content for judging that paging is stored
Afterwards, the number for the paging being erased in response to actual needs and the position in memory block, then determine to divide used in pipeline stage
The mode of page (group), the those of ordinary skill of the technical field as described in this case voluntarily apply, and and will not be described here in detail.
To sum up, the present invention proposes the memory device and erasing method in the way of pipeline architecture, and it is idle to promote generation
The speed of block.Pipeline architecture proposed by the invention, can allow it is multiple-partially erase instruction or multiple-sub-block erase
Instruction uses.No matter pipeline architecture be collocation it is multiple-partially erase instruction or multiple-sub-block is erased instruction, can be with
Runing time is erased the process of instruction (stage erase during), and different memory blocks is made to be in corresponding pipeline rank
Section.Pipeline architecture of the invention is erased using the over capacity cache of memory device as part, the memory block of sub-block makes
With.Therefore, user do not feel as it is whole can memory space be affected.
Referring to Figure 15, it is the schematic diagram using each functional layer of the data processing system of memory device.The present invention
Erasing method performed by controller can use firmware or software realization.System 80 is deposited according to the operation of application program 81
It stores up, capture and update storage the data in NAND gate (NAND) flash memory 89.
In this embodiment, block file system 83 and original file system 88 are with memory technology device
(Memory Technology Device, the referred to as MTD) access interface of layer 87 as NAND gate flash memory 89.System 80 is also wrapped
Flash translation layer (FTL) (Flash containing one as the interface between block file system 83 and memory technology device layers 87
Translation Layer, referred to as FTL) 85.Flash translation layer (FTL) 85 includes distributor 851, cleaner 853, loss averager
855。
For using flash memory as the purposes of storage device, using block file system 83, flash translation layer (FTL) 85 and memory
The combination of technique device.Wherein, block file system 83 can for file allocation table (File Allocation Table, referred to as
FAT) file system, third generation extended function file system (Third Extended File System, referred to as EXT3) or
New technique file system (New Technology File System, referred to as NTFS).
In addition, the present invention is also using original (native) file system 88 for being directed to flash memory design.Original file system
System 88 can for journaling flash file system version 2 (Journaling Flash File System Version 2, referred to as
JFFS2), no sequence block image file system (Unsorted Block Image File System, referred to as UBIFS) or
Another flash memory file system (Yet Another Flash File System, referred to as YAFFS) again.
Memory technology device layers 87 include: to read driver 871, partially erase driver 873, multiple partial to smear
Except driver 874, write driver program 875, erase driver 876, sub-block are erased driver 877, multiple sub-district
Block is erased driver 878.
Present invention can apply to safe digital card (Secure Digital Memory Card, referred to as SD), solid-states to deposit
The storage system of the types such as storage device or embedded multi-media card (Embedded Multi Media Card, referred to as eMMC),
The flash translation layer (FTL) and memory technology device that collocation is controlled in a manner of firmware.Conception according to the present invention passes through firmware mode
The pipeline erasing method realized and provided does not need again to modify to the file system for being located at upper layer.
The present invention can be realized in flash translation layer (FTL) 85 or original file system 88, for controlling the management of memory block
(block management).Wherein, memory technology device 87 need to be comprising that can support erase with part instruction, multiple-part
Instruction, the multiple-sub-block of erasing erase instruction, multi-tiling multiple-sub-block erase and instruct corresponding driver.This hair
The bright general design (common designs) for applying also for flash translation layer (FTL), for example, block level image (Block
Level Mapping, referred to as BL), the sections of block associations translate (Block Associative Sector
Translation, referred to as BAST) and fully associative property section translation (Fully Associative Sector
Translation, referred to as FAST).
The practice of flash memory storage charge can be divided into floating grid (floating gate) frame using tool conductive material
Structure, and with floating grid or nitride (Silicon-Oxide-Nitride-Oxide-Silicon, referred to as SONOS)
Charge limits to (trap) framework.The feature of SONOS framework is that the characteristic mobile in oxygen nitrogen oxygen (ONO) interlayer is not easy using charge,
By charge limitation (trap) in fixed position.Since the speed that charge moves between ONO layer is slower, to the flash memory of SONOS framework
Erase when operating, the time spent needed for operating of erasing is again longer.Therefore, if applying the present invention to SONOS framework
Flash memory when, effect is also more significant.
It need to be noted that, only pipe is previously with regard to the level of critical voltage with single-step form storage unit (Single-Level
Cell, referred to as SLC) for.But conception of the invention is equally applicable to multi-level cell memory (Multi-Level
Cell, referred to as MLC) or three rank storage units (Triple-Level Cell, referred to as TLC) type storage unit.Again
Person, memory chip belong to NAND gate (NAND) or when nor gate (NOR) mode are realized, there may be overlong times of erasing
Phenomenon.Therefore, the practice that pipeline proposed by the invention is erased can be applied to the storage of all types of devices that erase
Device device.
According to preceding description, it is apparent that the present invention proposes in a manner of pipeline stage, rank is carried out to memory block
The operation of erasing of section can be shortened the waiting time for generating idle block really.It is related, controller also than less easily because etc.
It waits overlong time and is mistaken for having damaged by memory block.Wherein, the operation of erasing in stage can be by multiple-finger of partially erasing
It enables or multiple-sub-block erases and instructs and carry out to memory block.
In conclusion although the present invention has been disclosed above in the preferred embodiment, however, it is not to limit the invention.This hair
Those of ordinary skill in bright technical field, without departing from the spirit and scope of the present invention, when can make various change with
Modification.Therefore, protection scope of the present invention is subject to view as defined in claim.
Claims (8)
1. a kind of erasing method, which is characterized in that applied to the memory device comprising multiple memory blocks, the erasing method
It comprises the steps of:
One sequentially is carried out at least one first memory block in multiple memory block in a first period and a second phase
First stage erases operation and a second stage is erased operation；And
Sequentially at least one second memory block in multiple memory block is somebody's turn to do during the second phase and a third
First stage erases operation and the second stage is erased operation；Wherein:
After the first stage erases operation, one first critical voltage corresponding at least first memory block and with this extremely
Few corresponding one second critical voltage of second memory block is reduced to one first level by an original level, and
After the second stage erases operation, first critical voltage and second critical voltage are reduced to by first level
One second electrical level.
2. erasing method according to claim 1, wherein all phase during the first period, the second phase and the third
Deng.
3. erasing method according to claim 1, wherein at least one first memory block includes multiple first pagings,
In at least 1 the one the first paging in multiple first paging be to be erased in the first period, and in multiple first paging
At least 1 the two the first paging be to be erased in the second phase.
4. erasing method according to claim 1, wherein at least one second memory block includes multiple second pagings,
In at least 1 the one the second paging in multiple second paging be the controller by the memory device in the second phase quilt
It erases, and the two the second paging of at least 1 in multiple second paging is erased during the third by the controller.
5. a kind of memory device, characterized by comprising:
Multiple memory blocks include:
At least one first memory block；And
At least one second memory block；And
One controller is electrically connected to multiple memory block, sequentially in a first period and a second phase to this at least one
First memory block carries out that a first stage erases operation and a second stage is erased operation, and sequentially in the second phase and
During one third at least one second memory block carry out the first stage erase operation and the second stage erase；Wherein:
After the first stage erases operation, which makes one first critical electricity corresponding at least first memory block
Pressure and one second critical voltage corresponding at least second memory block by an original level are reduced to one first level, and
After the second stage erases operation, the controller make first critical voltage and second critical voltage by this first
Level is reduced to a second electrical level.
6. memory device according to claim 5, wherein all phase during the first period, the second phase and the third
Deng.
7. memory device according to claim 5, wherein at least one first memory block includes multiple first pagings,
Wherein the one the first paging of at least 1 in multiple first paging is erased by the controller in the first period, and multiple
At least 1 the two the first paging in first paging is erased by the controller in the second phase.
8. memory device according to claim 5, wherein at least one second memory block includes multiple second pagings,
Wherein the one the second paging of at least 1 in multiple second paging is to be erased by the controller in the second phase, and this is more
At least 1 the two the second paging in a second paging is erased during the third by the controller.
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| CN110970076B (en) * | 2019-12-02 | 2022-03-18 | 武汉新芯集成电路制造有限公司 | Memory structure and erasing method thereof |
| CN113311992B (en) * | 2020-08-31 | 2024-01-23 | 阿里巴巴集团控股有限公司 | Dynamic adjustment method and device for reserved space of solid state disk |
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