JP4977703B2 - Non-volatile memory with scheduled playback operation - Google Patents

Description

  This application relates to the operation of reprogrammable non-volatile memory systems, such as semiconductor flash memory, and more particularly to the management of available space in such memory. Any patents, patent applications, articles, other publications, documents, or matters referred to herein are hereby incorporated by reference in their entirety for all purposes.

  In early generation commercial flash memory systems, a rectangular array of memory cells was divided into a number of cell groups each storing the amount of data in a standard disk drive sector, ie 512 bytes. More usually, an error correction code (ECC) is stored, possibly a certain amount, such as 16 bytes, to store user data and / or other overhead data related to the memory cell group storing it. Data will be added to each group. The memory cells in each such group are the minimum number of memory cells that can be erased together. That is, the erase unit is effectively the number of memory cells that store one data sector and, if overhead data is included, the overhead data. U.S. Pat. Nos. 5,602,987 and 6,426,893 describe examples of this type of memory system. As a feature of flash memory, it is necessary to erase the memory cell before reprogramming the data into the memory cell.

  Flash memory systems are often provided in the form of memory cards or flash drives that are detachably connected to various hosts, such as personal computers and cameras, but can also be embedded in such host systems. is there. When a host normally writes data to memory, it assigns a unique logical address to a sector, cluster or other data unit within the contiguous virtual address space of the memory system. The host, like a disk operating system (DOS), writes data to and reads data from addresses in the logical address space of the memory system. The controller in the memory system translates the logical address received from the host into a physical address where the data in the memory array is actually stored, and grasps the history of the address translation. The data storage capacity of the memory system corresponds at least to the amount of data addressed over the entire logical address space set for the memory system.

  In subsequent generation flash memory systems, the size of the erase unit has been expanded to a memory cell block that can sufficiently store data of a plurality of sectors. Even if the host system, which is the connection destination of the memory system, programs and reads data in a small minimum unit such as a sector, a large number of sectors are stored in one erase unit of the flash memory. When the host updates or replaces logical sector data, several data sectors in a block are often used up. Since the entire block must be erased before the data stored in the block can be overwritten, new or updated data is usually stored in a separate block that has been previously erased and has room for data. The In this process, the used data remains in the original block and takes up valuable space in the memory. However, this block cannot be erased if valid data remains in it.

  Therefore, in order to effectively use the memory storage capacity, it is common to arrange or collect the data amount of the effective incomplete block by copying it to the erased block, and this is equivalent to the data copy source. Blocks can be erased and their entire storage capacity can be reused. It is also desirable to copy the data to group the data sectors in the block in the order of their logical blocks, which increases the speed at which the data is read and transferred to the host. If such data copying is performed too frequently, the operating performance of the memory system may be degraded. This particularly affects the operation of the memory system if the storage capacity of the memory is not very different from the amount of data that can be addressed by the host through the logical address space of the system. In this case, the data needs to be organized or retrieved before the host programming command is executed. This will prolong the programming time.

  In order to increase the number of bits of data that can be stored in a given semiconductor area, the size of the block has increased through generational changes in memory systems. Blocks that store more than 256 data sectors are becoming common. In addition, two, four, or more blocks of arrays or subarrays are often logically linked together as metablocks to increase parallelism in programming and reading data. Such large capacity operation units have the problem of operating them efficiently.

Accordingly, there is a need for improved management of data stored in non-volatile memories. There is also a need for a system that does not contain valid data and that efficiently reclaims memory space that is not currently available for storing new valid data. There is also a need for a system that performs playback operations so that there is little or no impact on other memory operations, such as programming host data.
US Pat. No. 5,602,987 US Pat. No. 6,426,893 US patent application Ser. No. 10 / 915,039 US Pat. No. 5,570,315 US Pat. No. 5,774,397 US Pat. No. 6,046,935 US Pat. No. 6,373,746 US Pat. No. 6,456,528 US Pat. No. 6,522,580 US Pat. No. 6,771,536 US Pat. No. 6,781,877 US Published Patent Application No. 2003/0147278 US Published Patent Application No. 2003/0109093 US patent application Ser. No. 10 / 749,189 US patent application Ser. No. 10 / 841,118 US patent application Ser. No. 11 / 016,271 US Pat. No. 6,763,424 US patent application Ser. No. 10 / 750,155 US patent application Ser. No. 10 / 749,831 US patent application Ser. No. 10 / 917,888 US patent application Ser. No. 10 / 917,867 US patent application Ser. No. 10 / 917,889 US patent application Ser. No. 10 / 917,725 US patent application Ser. No. 10 / 897,049 US Patent Application No. 11 / 022,369 US patent application Ser. No. 11 / 040,325 US patent application Ser. No. 11 / 060,249 US Patent Application No. 11 / 060,174 US Patent Application No. 11 / 060,248 US Provisional Patent Application No. 60 / 705,388

  If the memory array is reclaimed before the memory runs out of erased blocks, the risk of host data programming being severely delayed and exceeding the time limit can be avoided. As the host data enters the memory, the memory array space is reclaimed so that the erased blocks are not used up until the memory is full. Replay can be performed according to a schedule where playback begins long before the number of erased blocks runs short. Since the reproduction operation is alternately performed with the writing of the host data in accordance with the alternating ratio, the reproduction operation is dispersed over a long period of time instead of being performed at a stretch over a long time. This alternating ratio is calculated to be the ratio of the remaining all host writes to the remaining all playback writes.

  When a file-oriented host interface connects memory to the host, the memory controller can get accurate and up-to-date information about the data stored in the memory array and can be written to the memory before it is full From this amount of host data and the amount of playback required before the memory is full, an appropriate alternating ratio can be estimated. A constant rate of host data programming is achieved by distributing the replay operations uniformly throughout the remaining time. In the case of a memory having a sector-oriented interface and other interfaces, information for performing such an estimation is provided from the host, so that the alternating ratio can be calculated in the same manner.

  The alternating ratio can be calculated at intervals, or it can be calculated when there is a triggering event, such as deletion of some stored data by the host. In this way, the alternating ratio is appropriately updated to adapt to changes in the situation.

  Playback can be managed differently in different modes. In addition to adaptive playback based on estimates of host data to be written and playback operations performed, there may be a minimum playback mode that plays back space at some low (or zero) rate. The minimum playback mode is usually applied when there are enough erased blocks compared to the reproducible space. There may also be a maximum playback mode in which space is played back alternately at a certain maximum rate. Maximum playback mode usually applies to situations where there are few erased blocks, that is, when the memory is almost full. In addition, playback can be performed continuously in response to host commands (not alternately). Playback can also be prohibited in response to host commands.

Overview of Flash Memory Typical operations with current flash memory systems and host devices are described in relation to FIGS. Various aspects of the present invention can be implemented in such a system. The host system 1 in FIG. 1 stores data in the flash memory 2 and extracts data from the flash memory 2. The flash memory can also be embedded in the host, but the memory 2 is shown in the figure in the form of a more general card, which is inserted and removed through mating parts 3 and 4 of mechanical and electrical connectors. Connected to the host in a possible state. For example, various flash memory cards such as a compact flash (CF), a multimedia card (MMC), a secure digital (SD), a mini SD, a memory stick, a smart media, and a trans flash card are currently on the market. Although each of these cards has a unique mechanical and / or electrical interface according to their respective standardized specifications, the flash memory system built into each is similar. Both of these cards are available from SanDisk Corporation, the assignee of the present application. SanDisk Corporation also offers a series of flash drives under the trademark Cruzer, which connect to the host by plugging into the host's Universal Serial Bus (USB) receptacle. A small handheld memory system having a USB plug. Each of these memory cards and flash drives incorporates a controller that controls the operation of the built-in flash memory in conjunction with the host.

  There are many host systems that use such memory cards and flash drives. These include personal computers (PCs), laptops and other portable computers, mobile phones, personal digital assistants (PDAs), digital still cameras, digital video cameras, portable audio players, and the like. While hosts usually incorporate an integrated slot for one or more types of memory cards or flash drives, some hosts require an adapter to plug in a memory card.

  As long as the memory 2 is connected, the host system 1 in FIG. 1 can be regarded as having two main parts consisting of a combination of a circuit and software. They are an application unit 5 and a driver unit 6 that works in conjunction with the memory 2. For example, in the case of a personal computer, the application unit 5 may include a processor that executes a word processor, graphics, control, or other general application software. In the case of a camera, mobile phone, or other host system dedicated to performing a set of functions, the application unit 5 operates the camera to make and store pictures, to make and receive calls. Including software to operate the phone.

  The memory system 2 in FIG. 1 includes a flash memory 7 and a circuit 8, both of which are linked with a host that is a connection destination of a card in order to exchange data and control the memory 7. The controller 8 usually converts between the logical address of the data used by the host 1 and the physical address of the memory 7 when programming and reading data.

  With reference to FIG. 2, a circuit of a typical flash memory system that can be used as the non-volatile memory 2 of FIG. 1 is described. The system controller is typically implemented on a single integrated circuit chip 11 connected in parallel with one or more integrated circuit memory chips along the system bus 13, and only one such memory chip 15 is shown in FIG. Has been. The particular bus 13 shown in the figure includes a set of conductors 17 that carry data, a set 19 for memory addresses, and a set 21 for control and status signals. Alternatively, one set of conductors can be shared in time division among these three functions. Furthermore, US patent application Ser. No. 10 / 915,039, filed Aug. 9, 2004, “Ring Bus Structure and It's Use in Flash Memory Systems” (Patent Document 3). Other system bus configurations can be used, such as the ring bus described in).

  The typical controller chip 11 has its own internal bus 23 that works with the system bus 13 through an interface circuit 25. The main functions normally connected to this bus include a processor 27 (eg, a microprocessor or microcontroller), a read only memory (ROM) 29 that contains code for initializing ("booting") the system, and Random access memory (RAM) 31 used mainly to buffer data transferred between the memory and the host, and error correction code (ECC) for data going back and forth between the memory and the host through the controller And a circuit 33 for calculating and inspecting. The controller bus 23 is linked to the host system through a circuit 35, which is accomplished through an external contact 37 of the card that forms part of the connector 4 in the case of the system of FIG. The clock 39 is connected to each of the other components of the controller 11 and is used by each of the other components.

  The memory chip 15 and other memory chips connected to the system bus 13 typically contain a memory cell array organized into a plurality of subarrays or planes, and two such planes 41 and 43 are shown for simplicity. More planes, for example four or eight, can be used instead. Alternatively, the memory cell array of the chip 15 may not be divided into planes. However, if divided, each plane has its own column control circuits 45 and 47 that can operate independently of each other. Circuits 45 and 47 receive the addresses of the respective memory cell arrays from the address section 19 of the system bus 13 and address them to address one or more specific bit lines of the respective bit lines 49 and 51. Decrypt. The word line 53 is addressed through the row control circuit 55 according to the address received by the address bus 19. Source voltage control circuits 57 and 59 are also connected to the respective planes, as are p-well voltage control circuits 61 and 63. If the memory chip 15 has only one memory cell array and more than one such chip is present in the system, the array of each chip should be operated in the same way as the plane or sub-array in the multi-plane chip described above. Can do.

  Data enters and exits the planes 41 and 43 through the respective data input / output circuits 65 and 67 connected to the data section 17 of the system bus 13. Circuits 65 and 67 are for programming data into the memory cells and reading data from the memory cells in the respective planes through lines 69 and 71 that connect to the planes through the respective column control circuits 45 and 47.

  The controller 11 programs, reads, erases data, and controls the operation of the memory chip 15 to accommodate various housekeeping operations, but each memory chip also performs such functions. A certain control circuit for executing a command from the controller 11 is accommodated. The interface circuit 73 is connected to the control and status unit 21 of the system bus 13. Commands from the controller are provided to state machine 75, which also provides specific control of other circuits to execute these commands. Control lines 77-81 connect the state machine 75 to the other circuits shown in FIG. The state information from the state machine 75 is transmitted along the line 83 to the interface 73 for transmission to the controller 11 along the bus unit 21.

  Currently, the NAND architecture of memory cell arrays 41 and 43 is preferred, but other architectures such as NOR can be used instead. Examples of this operation as part of a NAND flash memory and memory system are disclosed in US Pat. Nos. 5,570,315, 5,774,397, 6,046. , 935 (patent document 6), 6,373,746 (patent document 7), 6,456,528 (patent document 8), 6,522,580 (patent document 9), , 771,536 (Patent Document 10), and 6,781,877 (Patent Document 11) and US Published Patent Application No. 2003/0147278 (Patent Document 12).

  An example of a NAND array is shown in the circuit diagram of FIG. 3 corresponding to a part of the memory cell array 41 of the memory system of FIG. A number of global bit lines are provided, but only four such lines 91-94 are shown in FIG. 3 for simplicity of illustration. Several series-connected memory cell strings 97 to 104 are connected between one bit line of these bit lines and a reference potential. A memory cell string 99 is used as a representative, and a plurality of charge storage memory cells 107 to 110 are connected in series to select transistors 111 and 112 at both ends of the string. When a selection transistor of one string is energized, the string is connected between the bit line and the reference potential. Then, one memory cell in the string is programmed or read at a time.

  3 extend individually across the charge storage elements of one memory cell in each of a number of memory cell strings, and gates 119 and 120 indicate the state of the select transistor at each end of the string. Control. Memory cell strings sharing a common word and control gate lines 115-120 form a block 123 of memory cells that are erased together. This block of cells contains the minimum number of cells that can be physically erased at one time. One row of memory cells along one word line of word lines 115 to 118 is programmed at a time. Normally, the rows of the NAND array are programmed in a defined order, starting with the row along the word line 118 closest to the end of the string connected to ground or common potential. Next, a memory cell row along word line 117 is programmed and proceeds similarly throughout block 123, and so forth. Finally, the row along word line 115 is programmed.

  The second block 125 is similar and its memory cell string is connected to the same global bit line as the string of the first block 123 but has a different set of word lines and control gate lines. The word line and the control gate line are driven to an appropriate operating voltage by the row control circuit 55. If two or more planes or subarrays, such as planes 1 and 2 in FIG. 2, are in the system, a common word line extending between them is used in one memory architecture. Alternatively, there may be more than two planes or subarrays sharing a common word line. In another memory architecture, individual planes or sub-array word lines are driven separately.

  Operating the memory system to store more than two detectable charge levels in each charge storage element or region, as described in some of the previously referenced NAND patents and published patent applications. In this way, data of 2 bits or more is stored in each. The charge storage element of a memory cell is generally a conductive floating gate, but instead is a non-conductive dielectric charge trapping material described in US Published Patent Application No. 2003/0109093. Also good.

  FIG. 4 conceptually illustrates the organization of the flash memory cell array 7 (FIG. 1) used as an example in the further description below. There may be four planes or subarrays 131-134 of memory cells on one integrated memory cell chip, two chips (two of the planes on each chip), or four separate chips. The specific arrangement is not important for the following description. Of course, there may be other numbers of planes in the system, such as 1, 2, 8, 16 or more. The planes are each divided into memory cell blocks shown in FIG. 4 by rectangles of blocks 137, 138, 139, and 140 located in the respective planes 131-134. Each plane can have dozens or hundreds of blocks. As described above, a block of memory cells is an erasing unit, that is, the minimum number of memory cells that can be physically erased together. However, in order to increase parallelism, the block is operated in units of larger metablocks. One block from each plane is logically linked to form a metablock. The figure shows how one metablock 141 is formed by four blocks 137-140. Normally, all cells in one metablock are erased together. As seen in the second metablock 143 consisting of blocks 145-148, the blocks used to form the metablock need not be constrained to the same relative position in each plane. It is usually preferable to extend metablocks across all planes, but for high system performance, move metablocks that consist of any or all of one, two, or three blocks in different planes. The memory system can be manipulated using the ability to create automatically. This makes it possible to make the size of the metablock closer to the amount of data that can be used for storage in a single programming operation.

  The individual blocks are further divided into pages of memory cells for operational purposes as shown in FIG. For example, each memory cell of the blocks 131 to 134 is divided into eight pages P0 to P7. Alternatively, 16, 32, or more memory cell pages may be in each block. A page is a unit in which data is programmed and read in a block, and contains a minimum amount of data that is programmed or read at a time. In the NAND architecture of FIG. 3, a page is formed from memory cells along a word line in a block. However, such pages that are in more than one block can be logically linked into metapages to increase the operational parallelism of the memory system. FIG. 5 shows a metapage 151 formed from one physical page in each of the four blocks 131 to 134. The metapage 151 includes, for example, a page P2 in each of the four blocks, but the metapage pages may not be in the same relative position in each of the blocks. It is desirable to program and read the maximum amount of data across all four planes in parallel, but for high system performance, either one, two, or three pages of separate blocks in different planes Alternatively, the memory system can be operated to form a metapage from everything. This makes it possible to adapt the programming and reading operations to a data amount that can be easily handled in parallel, and further reduces the chance that a portion where data is not programmed remains in the metapage.

  A metapage composed of physical pages of a plurality of planes shown in FIG. 5 accommodates memory cells along word line rows of the plurality of planes. Rather than programming all the cells in a word line row simultaneously, it is more common to program them alternately in two or more interleaved groups, each group (within a single block) One page of data or one metapage of data (across multiple blocks) is stored. By programming alternating memory cells at a time, it is not necessary to provide a group of peripheral circuits including data registers and sense amplifiers for each bit line, but rather are time-shared between adjacent bit lines. . This saves the amount of substrate space required for the peripheral circuitry and can increase the implementation density along the row of memory cells. Otherwise, it is desirable to program all cells along a row simultaneously in order to derive maximum parallelism from a given memory system. For most data management purposes, metablocks and metapages can be treated like blocks and pages. The examples presented herein with respect to metablocks and metapages also generally apply to memories that use blocks and pages, respectively, as erase and programming units. Similarly, the examples presented for blocks and pages generally apply to memory using metablocks and metapages.

  One challenge in efficiently controlling the operation of a memory array with very large erase blocks is to match the number of data sectors stored during a given write operation to the capacity of the block of memory. And align with that boundary. Because one approach is required to store a certain amount of data that does not fill the entire metablock, the metablocks used to store new data from the host are configured appropriately below the maximum number of blocks. To do. The use of adaptive metablocks is described in US patent application Ser. No. 10 / 749,189, “Adaptive Metablocks” filed Dec. 30, 2003 (Patent Document 14). The alignment of the boundaries between data blocks and the physical boundaries between metablocks is described in US patent application Ser. No. 10 / 841,118, filed on May 7, 2004, on December 16, 2004. This is described in filed US patent application Ser. No. 11 / 016,271, “Data Run Programming”.

  Referring to FIG. 3, for the most convenient simultaneous programming of data into alternating memory cells along a row, two rows of select transistors (not shown) are shown in the figure along at least one end of the NAND string. Is to provide instead of one line. In this case, the select transistors in one row connect the staggered strings in the block to the respective bit lines in response to one control signal, and the select transistors in the other row intervene in response to another control signal. Connect alternate strings to each bit line. Accordingly, two pages of data are written in each row of memory cells.

  The amount of data in each logical page is usually an integer number of one or more data sectors, and each sector conventionally accommodates 512 bytes of data. FIG. 6 shows a logical data page consisting of two data sectors 153 and 155 of one page or metapage. Each sector typically contains a portion 157 where 512 bytes of user data or system data is stored, and another number of bytes 159 for overhead data associated with the data in the portion 157 or the physical page or block storing it. To do. The number of bytes of overhead data is normally 16 bytes, for a total of 528 bytes for each of sectors 153 and 155. The overhead portion 159 includes the ECC calculated from the data portion 157 during programming, its logical address, the experience count of the number of times the block is erased and reprogrammed, one or more control flags, the operating voltage level, etc. ECC calculated from the overhead data 159 can be accommodated. Alternatively, overhead data 159 or a portion of overhead data 159 can be stored on another page of another block.

  As memory parallelism increases, the data storage capacity of the metablock increases and, as a result, the size of the data pages and metapages also increase. The data page can contain data of 3 sectors or more. There are four sectors in one metapage, with two sectors in one data page and two data pages for each metapage. Therefore, each metapage stores 2,048 bytes of data. This is a high degree of parallelism and can be further increased as the number of memory cells in a row increases. For this reason, the width of the flash memory is being expanded in order to increase the amount of data in the page and metapage. The physically small reprogrammable non-volatile memory cards and flash drives described above are commercially available, with data storage capacities of 512 megabytes (MB), 1 gigabyte (GB), 2 GB, 4 GB or more.

  FIG. 7 shows a typical interface between a host and such a mass memory system. The host processes data files generated or used by application software or firmware programs executed by the host. A word processor data file is an example, and a computer aided design (CAD) software drawing file corresponds to this, and is mainly found in general computer hosts such as PCs and laptop computers. A document in the pdf format is also such a file. The still picture digital video camera generates a data file for each photograph, and the data file is stored in a memory card. A cellular phone uses data from a file on a built-in memory card such as a telephone directory. The PDA stores and uses several types of files such as address files and calendar files. In such applications, the memory card may contain software that operates the host.

  In FIG. 7, the contiguous logical address space 161 is large enough to provide an address for all data stored in the memory system. Usually, the logical address space is somewhat smaller than the physical address space of the memory array, so there is some extra space in the memory array. The host logical address space is usually divided into data cluster units. In a given host system, each cluster can be designed to accommodate several data sectors, typically around 4 to 64 sectors. A standard sector contains 512 bytes of data.

  In the example of FIG. 7, three files 1, 2, and 3 are shown as created. An application program running on the host system creates each file as an ordered set of data and identifies it by a unique name or other reference. File 1 is allocated by the host a fully usable logical address space that has not yet been allocated to other files. File 1 is shown with a series of available logical address ranges assigned. In addition to this, address ranges are usually allocated for specific purposes, such as specific ranges for host operating software, and these address ranges are used even when the host attempts to assign logical addresses to the data. Even if these addresses are not yet used, they are avoided when storing data.

  Similarly, when the file 2 is created later by the host, the host assigns two different consecutive address ranges in the logical address space 161 as shown in FIG. There is no need to assign consecutive logical addresses to a file, and it may be a fragment of an address that is between address ranges already assigned to other files. This example further shows that another file 3 created by the host is allocated another portion of the host address space that has not yet been allocated to files 1 and 2 and other data. In this example, file 1, file 2, and file 3 are all assigned a part of the common logical address space (logical address space 161).

  The host keeps track of the memory logical address space by maintaining a file allocation table (FAT), in which the logical addresses that the host assigns to the various host files are maintained. The FAT table is usually stored in non-volatile memory similar to the host memory and is frequently updated by the host when new files are stored, when other files are deleted, when files are modified, etc. . Obviously, when a host file is deleted, the host can release the logical addresses previously allocated to the deleted file by updating the FAT table and use those logical addresses for another data file. To.

  The host does not care about the physical location that the memory system controller chooses to store the file. A typical host recognizes only its logical address space and the logical addresses it has assigned to its various files. On the other hand, the memory system recognizes only the portion of the logical address space where data is written, through a typical host / card interface, not the logical address allocated to a particular host file, and not even the number of host files. . The memory system controller converts a logical address provided from a host for storing and retrieving data into a unique physical address in a flash memory cell array in which the host data is stored. Block 163 represents a logical-physical address translation work table maintained by the memory system controller.

  The memory system controller is programmed to store data files in the blocks and metablocks of the memory array 165 while maintaining high system performance. In this illustration, four planes or subarrays are used. The data is preferably programmed and read with the maximum degree of parallelism allowed by the system over the entire metablock formed from the blocks in each plane. Typically, at least one metablock 167 is allocated as a reserved block for storing operating firmware and data used by the memory controller. Then, another metablock 169 or a plurality of metablocks can be allocated for storing the host operating software, the host FAT table, and the like. Most of the physical storage space remains for storage of data files. However, the memory controller does not recognize how the received data is allocated by the host among the various file objects. Normally, all that the memory controller knows through interaction with the host is that the data written by the host to a specific logical address is stored at the corresponding physical address, which is the controller's logical-physical address table. Maintained by H.163.

  In a typical memory system, an extra storage capacity for several blocks is prepared separately from the need to store data in the address space 161. One or more of these extra blocks can be prepared as redundant blocks to be substituted when other blocks become defective during the lifetime of the memory. The logical grouping of blocks contained within individual metablocks is typically changed for various reasons, such as substituting redundant blocks for defective blocks that were originally assigned to metablocks. In a pool of erased blocks, one or more auxiliary blocks such as metablock 171 are typically maintained. When the host writes data to the memory system, the controller translates the logical address assigned by the host into a physical address in a metablock in the erased block pool. Then, other metablocks that are not used to store data in the logical address space 161 are erased and designated as erased pool blocks for use in subsequent data write operations.

  Data stored at a specific host logical address is frequently overwritten with new data, and the original stored data is used up. In response, the memory system controller writes new data to the erased block and modifies the logical-physical address table for those logical addresses to reveal the new physical block that stores the data at the logical address. The block containing the original data at those logical addresses is then erased and can be used to store new data. Typically, if the pre-erased block in the erase block pool does not have sufficient storage capacity when writing begins, this erase must be done before the ongoing data write operation is completed. This can compromise the data programming speed of the system. A memory controller typically knows that data at a particular logical address is obsolete only when the host writes new data to that same logical address. Therefore, many blocks of memory may store such invalid data for some time.

  In order to efficiently operate the area of the integrated circuit memory chip, the sizes of blocks and metablocks have been increased. As a result, the amount of data stored in most individual data writes is less than the storage capacity of the metablock, and in many cases even less than the storage capacity of the block. Since the memory system controller normally directs new data to the metablock of the erased pool, some parts of the metablock are not filled. If the new data is an update of data stored in another metablock, the remaining valid data metapages in another metablock with logical addresses that are contiguous with the logical address of the new data metapage are also , Preferably copied to a new metablock in logical address order. Old metablocks may hold other valid data metapages. As a result, the metapage data of each specific metablock will eventually be used and invalidated, replaced with new data, and the same logical address will be written to different metablocks.

  In order to maintain enough physical memory space to store data throughout the logical address space 161, the portion of memory occupied by the used data can be reclaimed with a garbage collection operation. If there is an erased space in a block that contains valid data, the erased space can also be recovered by consolidation, and the valid data can be reconstituted into a smaller block by organizing and consolidating the valid data into a smaller number of blocks. Blocks can be added. Thus, the block is subject to garbage collection or consolidation as it reclaims the memory space for reuse. It is also desirable to keep the data sectors in the metablock in the same order as the logical addresses as much as possible. This is because data can be read more efficiently at successive logical addresses. Therefore, data consolidation and garbage collection are usually performed for this further purpose. US Pat. No. 6,763,424 describes several aspects of memory management and metablock usage when receiving incomplete block data updates. In the present application, garbage collection and consolidation are collectively referred to as “playback”, and operations performed as part of garbage collection or consolidation are referred to as “playback operations”.

Reproduction Example During garbage collection, pages of valid data whose logical address range is contiguous or nearly contiguous are retrieved from one or more copy source blocks containing used data and re-entered to the copy destination block. Written. This copy destination block may be in the erased block pool or may contain some valid data. Once all valid data metapages have been copied from one or more source blocks, they can be erased for future use. Figures 8A and 8B illustrate a typical garbage collection operation. FIG. 8A shows how valid data X, X + 1, and X + 2 on pages 0-2 of block 1 are copied from block 1 to block 3, and valid data X + 3 from page 1 of block 2 is copied to block 3. ing. After the data X, X + 1, X + 2, and X + 3 are copied to block 3, blocks 1 and 2 can be added to a pool of blocks that can be erased immediately, usually soon thereafter. FIG. 8B shows the situation after this garbage collection, where blocks 1 and 2 are erased and block 3 contains data. As a result of this garbage collection operation, blocks 1 and 2 join the erased block pool, but since block 3 is no longer in the erased block pool, the erased block pool is increased by one block. To accomplish this, data X, X + 1, X + 2, and X + 3 are copied. The data unit in this example is equal to the content of the page and can contain one or more data sectors. Alternatively, the data may not be in logical sector units, in which case the contents of the page may not have uniformly sized individually addressable units. Similarly, other examples of playback operations apply to data in logically addressable sector units, or in some other form. In this example, data X, X + 1, X + 2, and X + 3 are copied so that they are stored sequentially in block 3. In another example, data is not sequentially stored in a block corresponding to a data copy destination.

  9A and 9B show another example of garbage collection. Here, valid data Y is copied from block 2 that contains used data in pages 0 and 2 to block 1 that contains only valid data. After Y is copied, only used data remains in block 2, so block 2 is erased. FIG. 9B shows the situation after garbage collection, where data Y is stored on page 3 of block 1 previously erased in block 1 and block 2 is erased. Thus, in this example, no blocks from the erased block pool are required. If the data Y is the amount of data that fills one page of the memory array, only one page is copied by this operation, one block is erased, and as a result, one additional erase block is added to the erased block pool. In this example, there is no logical relationship between data Y and data X, X + 1, and X + 2. In other examples, data can be copied to a block that contains logically related data.

  Data compression is a specific form of garbage collection that normally reads all valid data pages from a block and writes them to a new block, ignoring pages that contain invalid data in the process. Also, pages containing valid data are preferably arranged in physical address order that matches the logical address order of the data stored therein. Since data compression is performed on blocks that store data in a nonsequential (disordered) format, the data can be stored in a sequential format after compression. Since the page containing the used data is not copied to the new block, the number of pages in the new block is less than the number of pages in the old block. The old block is then erased and made available for storing new data. The additional page capacity gained by this consolidation can be used to store other data.

  10A and 10B show an example of data compression. FIG. 10A shows block 1 filled with data, some of the data has been used and some is valid. The data stored in block 1 is not arranged in order. Block 1 is typical of chaotic update blocks used in some memory designs, such as those described in US patent application Ser. No. 10 / 750,155. Pages 2 and 3 of block 1 contain valid data copies Z + 1 and Z + 2, and pages 0 and 1 contain used data copies. When a chaotic update block is mapped to a limited logical address range, the block is compressed when full, allowing further updates within the block's logical address range. FIG. 10B shows the situation after compression. Valid data Z + 1 and Z + 2 of pages 2 and 3 of block 1 are copied to block 2 and arranged to be stored sequentially. One advantage of storing data sequentially is that there is no need to maintain indexes at different sector locations, and the overhead associated with maintaining such indexes is reduced. Block 2 contains erased space in pages 2 and 3 that can be used to store additional data. Block 1 is shown in the figure after all valid data has been copied to block 2 and erased. As a result of the compression, there is no change in the number of erased blocks in the erased block pool, but a space that did not exist before is in block 2 and can be used for writing data. Data is copied from two pages to achieve this compression.

  Data consolidation can be used to provide data storage space. In some memory systems, the erased space of the memory may not be fully usable because it is finely distributed in blocks that also contain valid data. If the new data to be received does not have a logical relationship with the stored data of the block that has sufficient space to program the data, program this into the erased block instead of the partially filled block It is desirable to do. Such new data that has no logical relationship with the stored data is typically stored in erased blocks in the erased block pool. After some time, multiple blocks with erased space that cannot be used for new logically unrelated data may occur. This leads to wasted space. The valid data of such partially written blocks can be merged. For example, since the effective data of two blocks having erased spaces can be merged, erased blocks are formed from the merged erased spaces.

  FIG. 11A shows block 1 that contains data X, X + 1, and X + 2 on pages 0-2, and block 2 contains data Y on page 0. Data Y has no logical relationship to data X, X + 1, and X + 2. Blocks 1 and 2 keep the erased space for some time to see if more data is received that is continuous with data X + 2 of block 1 or continuous with data Y of block 2 be able to. Blocks 1 and 2 can be marked for consolidation when some threshold time has passed without any further consecutive data being received, or when some other condition is met. Since the list of blocks to be consolidated can be maintained and blocks can be selected from the list according to the amount of valid data contained in those blocks, one block is filled or filled by merging those valid data. Approaches the state. FIG. 11B shows blocks 1 and 2 after consolidation. Data Y is copied to block 1 and block 2 is erased. In this consolidation, in order to add a block to the erased block pool, it is only necessary to copy one page of data (data Y on page 0 of block 2). Normally, it is desirable to perform consolidation in a form that suppresses the number of copies, so instead of copying data X, X + 1, and X + 2 to block 2, data Y is copied to block 1.

  Data consolidation and garbage collection are time consuming and affect the performance of the memory system, especially if data consolidation or garbage collection must be done before executing a command from the host. Memory system controllers usually schedule such operations in the background as much as possible, but the need to perform these operations causes the controller to send a busy signal to the host until such operations are complete. Must be provided. For example, if there are not enough pre-erased metablocks in the erased block pool to store all of the data that the host wants to write to memory, host command execution will be postponed, so the data is organized first. One or more valid data metablocks need to be cleaned up by integration or garbage collection, and then those metablocks can be erased. Therefore, care must be taken in managing memory control to minimize such confusion. The following US patent applications describe many such techniques. These US patent applications include US Patent Application No. 10 / 749,831, filed December 30, 2003, "Management of Non-Volatile Memory Systems Having Large Erase Blocks) ", US Patent Application No. 10 / 750,155, filed December 30, 2003," Non-Volatile Memory and Method with Block Management System ". Management System) ", U.S. Patent Application Serial No. 10 / 917,888, filed August 13, 2004," Non-Volatile Memory and Method with Memory " Planes Alignment) ”(patent document 20), US patent application Ser. No. 10 / 917,867 filed Aug. 13, 2004 (patent) 21), US patent application Ser. No. 10 / 917,889, filed Aug. 13, 2004, “Non-Volatile Memory and Method with Phased Program Failure Handling” (U.S. Pat. No. 6,057,028) and US patent application Ser. No. 10 / 917,725, filed Aug. 13, 2004, “Non-Volatile Memory and Method with Control Data Management”. ] (Patent Document 23).

  The memory controller can also use the FAT table data stored in the non-volatile memory by the host for efficient operation of the memory system. For example, it is useful for knowing that data has been identified as being used by the host by releasing the logical address. Normally, the memory controller can know in advance that the data has been identified as being used by writing new data to its logical address, and the memory controller can schedule the erasure of blocks containing such invalid data. Can stand. No. 10 / 897,049 filed Jul. 21, 2004 “Method and Apparatus for Maintaining Data on Non-Volatile Memory Systems”. (Patent Document 24). Another approach is to monitor the pattern of the host writing new data to the memory to determine whether a given write operation is a single file, or if there are multiple files, where the boundaries between files Estimate if there is. US patent application Ser. No. 11 / 022,369, “FAT Analysis for Optimized Sequential Cluster Management” (Patent Document 25), filed on December 23, 2004, The use of the technique is described.

  In order to operate the memory system efficiently, it is desirable for the controller to know as much as possible about the logical addresses assigned to the data of individual files by the host. Thus, a data file can be stored in a metablock or group of metablocks by a controller where the file boundaries are not known. As a result, the number and complexity of data consolidation and garbage collection operations is reduced. As a result, the performance of the memory system is improved. However, as described above, if the host / memory interface includes the logical address space 161 (FIG. 7), it is difficult for the memory controller to know much about the host data file structure.

Playback with Logical Address Standard Interface FIG. 12 illustrates the operation of the host / memory interface of FIG. 7 when a file is deleted. The application 201 executed in the host system determines that the file 2 should be deleted in the memory. For example, the application 201 running on the PC determines that the file 2 is no longer needed based on user input or for other reasons. As a result, the application transmits an instruction to delete the file 2 to the driver unit of the host. In this case, data storage is managed using FAT to indicate the logical address used for each file stored in memory. For example, file 2 is shown in the figure as having two separate logical address ranges 203 and 205. Each logical address range 203 and 205 may include a plurality of consecutive clusters. File 2 is shown in the figure as having two separate logical address ranges 203 and 205, but the file is fragmented into multiple logical address ranges, and other files are mapped to intervening logical addresses There are many. Since the FAT is corrected as a result of the instruction to delete the file 2, the clusters of the logical address ranges 203 and 205 allocated to the file 2 are released and can be used for subsequent allocation by the host. However, usually, with the release of these clusters in the host FAT, the memory management structure used by the memory controller is not changed. The logical-physical address translation 163 includes a table maintained by the memory controller, and a physical address for storing the data cluster is recorded in the table. Address ranges 203 and 205 are mapped to physical address ranges 209 and 211, respectively. This record is not changed as a result of the “Delete File 2” command from the application. Thus, the table maintains entries for logical address ranges 203 and 205. Also, the corresponding physical locations 209 and 207 remain filled with data, but this data is no longer needed by the application. The memory controller typically changes the logical-physical address translation of logical address ranges 203 and 205 only when new data with these addresses is sent by the host. Since the memory controller does not know the release of the cluster, it normally maintains at least one entry for each logical address, and therefore considers the entire logical address range occupied. Usually there is more physical space than the memory's logical address range, so even if the entire logical address range is filled with apparently valid data, the space occupied by erased or used data is extra It is in.

  FIG. 13 illustrates how the physical space of the memory array is managed as host data is written to the memory. The physical space is treated as being almost filled with valid data, which corresponds to the entire logical address range. The space left in the memory consists of erased space and space occupied by used data. As host data is programmed into the memory array, the amount of space occupied by used data increases as shown in the figure. This is because a new sector received with a particular logical address is stored in a new physical location and recorded in the logical-physical address translation 163. This replaces the stored sector with the same logical address. The stored sector is then used, and the physical location of the stored sector is recorded as containing used data. As the amount of used data increases, the erased space decreases. At some point, there will not be enough erased space to continue programming the host data. FIG. 13 shows a state in which no erased space remains in the memory at time t1. Thus, no more host data can be programmed into the memory array at time t1. In another example, programming stops when the erased space remaining in the memory array reaches a certain minimum amount. At time t1, a garbage collection operation starts to reclaim the space occupied by the used data. This operation ends when all the used spaces are reproduced and become erased spaces at time t2. In another example, the garbage collection operation ends before all possible space is reclaimed, eg, when enough space is reclaimed to continue programming host data. At the time t2, the programming of the host data starts again. At the time t3, the writing of the host data stops, and the garbage collection operation starts again. The viewpoint shown in FIG. 13 is the state of data in the memory viewed from the memory controller viewpoint, and is not necessarily the same as the host viewpoint. Even if the memory controller sees the logical space as full, the host may see the same space as largely free.

  As a disadvantage of managing the memory as shown in FIG. 13, the memory is unavailable to the host between times t1 and t2. Therefore, the host data is not written during the period from t1 to t2. Since a large number of pages have to be copied, the time from t1 to t2 can be quite long. In some cases this time is so long that the host times out. This means that the host has a maximum time to write a portion of the data, and the garbage collection required to allow new data to be written when the erased space is insufficient will exceed this maximum time. Sometimes.

  FIG. 14 shows an alternative memory management method in which garbage collection is performed in a state where sufficient erased space remains for writing host data. In this example, garbage collection is performed before this is absolutely necessary. Garbage collection can be alternated between host data writes, as described in US patent application Ser. No. 11 / 040,325. It may be a trigger for starting such alternate garbage collection when the number of erased blocks reaches a certain threshold value. Alternate garbage collection operations slow down host data programming to memory. However, this garbage collection operation can prevent the number of erased blocks from decreasing to the extent that host data cannot be written. Thus, the risk of the host timing out or interrupting programming is reduced or eliminated. Alternate garbage collection can be stopped when enough erased blocks are available so that programming speed is not unnecessarily compromised. Thus, the amount of erased space changes as alternating garbage collection switches on / off or as the rate of alternating garbage collection changes.

  FIG. 15 shows a timing diagram of garbage collection performed alternately with writing of host data. After N3 pages of host data have been written, N4 pages of data are written or x blocks are erased as part of the garbage collection operation. This cycle is repeated. Thus, the overhead associated with garbage collection is distributed over time instead of being concentrated all at once and incurring timeouts. Consolidation, other replay operations, or other housekeeping operations can also be alternated in this manner. Housekeeping operations in this context refer to operations that the memory controller undertakes to maintain data in the memory array. Such operations may include wear leveling operations and data scrub operations.

Playback with a file-oriented interface Some memory interfaces allow the memory controller to obtain more information to enable more efficient playback. No. 11 / 060,249, “Direct Data File Storage in Flash Memories” (Patent Document 27), US Patent Application No. 11 / 060,249 filed on Feb. 16, 2005. 11 / 060,174 “Direct File Data Programming and Deletion in Flash Memories” (Patent Document 28), US Patent Application No. 11 / 060,248 “Direct Data in Flash Memory” “Direct Data File Storage Implementation Techniques in Flash Memories” (Patent Document 29), and provisional patent application No. 60 / 705,388 filed Aug. 3, 2005 “Direct Data in Flash Memory” “Direct Data File Storage in Flash Memories” (Patent Document 30) Now, an example of such a memory interface is described. The file is sent from the host to the memory without being mapped to a logical address in the logical address range defined for the memory. Such a memory can be regarded as having a file-oriented interface. Files are mainly stored in memory in a metablock dedicated to that file. The storage location of the file is recorded using the file identifier and the offset. FIG. 16 shows a memory interface that uses such direct data file storage, where the file is sent to memory, where file / offset-physical address translation 173 is performed. Such memory can maintain files in a manner that reduces fragmentation, and thus most metablocks contain data from a single file. The memory controller of such a memory gets more information about the stored data. Specifically, a memory controller that identifies data by file can store the file in a file-oriented manner.

  FIG. 17 illustrates what happens when an application deletes a file stored in a memory system using the interface of FIG. The application 225 transmits a command instructing that the file 2 should be deleted. This command is sent from the host to the memory, in which case it is not necessary to identify the file by the logical sector address. The host can identify the file using the file identifier. File 2 is mapped to blocks a, b, and c, and the mapping is recorded by file / offset-physical translation 173. This command causes file / offset-physical translation 173 to be updated to reflect the deletion of file 2. As a result, blocks a, b, and c are incorporated into a garbage collection schedule so that they can be reused for new data. Thus, instead of waiting for alternative data to be stored in the memory array as in the case of memory using logical sector addresses, garbage collection can be initiated by deleting files by the application. In this case, the memory controller does not always see the entire logical address space. Instead, the memory controller gets accurate information about the validity of the data stored in the memory. At some point, the memory controller may recognize that there is little or no valid data in the memory array. At other times, the memory controller may recognize that the memory array is full or nearly full with valid data. With such information about valid and used data in the memory array, playback can be managed more efficiently than ever.

  FIG. 18 shows an example of a memory playback system that operates on a memory that uses a direct data file interface. FIG. 18 shows the state of the memory array as the host data is written. The viewpoint shown in the figure represents the viewpoint of the controller, and the viewpoint in this case matches the viewpoint of the host. Here, it can be seen that the memory portion that accommodates the valid data is relatively small, and the remaining portion of the memory consists of erased blocks and reproducible space. The reproducible space includes erased space that is not in the erased block in addition to the space occupied by the used data. Some memories use erased space scattered in that way to store additional data, but some systems use this erased space to store data after consolidating them into erased blocks. is there. FIG. 18 shows how the amount of valid data steadily increases until time t5. During this time, since the reproduction operation is not performed, the amount of reproducible space is kept constant. During this period, the space of the erased block decreases as valid data is written to the erased block. At time t5, one or more files are deleted and the data in those files stored in the memory array is obsolete. Thus, the amount of space occupied by valid data decreases and the amount of reproducible space increases correspondingly. Then, from time t5 to t6, more data is programmed into the memory array, the amount of valid data increases again, and the erased block space decreases. The memory reaches a point at time t6 where a replay operation is deemed necessary for further data programming. This point may be reached when the erased block space reaches some threshold or may depend on some other criteria. From time t6 to t7, a reproduction operation is performed to convert a part of the reproducible space into an erased block. Since new data is not written to the memory array during these reproduction operations, the amount of space occupied by valid data is kept constant. At time t7, the playback operation ends and new data programming starts again. This system is similar to the system described above that performs replay operations only when needed. One disadvantage of such a system is that the time from t6 to t7 exceeds the time limit, which may cause the host to interrupt the write operation. Instead of performing the replay operation only when necessary, it is possible to perform it in a manner that does not significantly affect the host write operation before it is required. Skillfully schedule the replay operation so that it has little impact on the host write operation, especially with memory that gets more information about the amount of used data stored in the memory array, such as memory that uses a direct data file storage system It is possible to assemble.

  FIG. 19 shows an example of how space can be managed in a memory array. Valid data increases at a constant rate until the memory array is filled with valid data. At the same time, the reproducible space decreases as the reproducible space is converted into erased blocks by the replay operation. Since the system for managing the space of the memory array in this way performs the replay operation according to the schedule, the individual replay operations are distributed between the individual host write operations to provide a constant rate of host data write. The To accomplish this, the controller can estimate the amount of such additional valid data to fill the memory array, and can estimate the number of playback operations that are required before the memory is full. The replay operations are then scheduled at a rate that uniformly distributes the replay operations over the remaining time. This prevents the memory from running out of erased blocks prematurely. The replay operation can be sandwiched between operations to program new data into the memory array as before. The reproduction operation includes copying a part of data from one block to another and erasing a block that does not contain valid data. The rate of reclaiming space can be determined by the alternating ratio, that is, by the ratio of the number of replay operations to the number of host write operations. In some cases, there are far more copy operations than erase operations, so block erase operations are ignored in calculating this ratio. The ratio in this case is the ratio of the write operation for reproduction to the write operation for new data.

  FIG. 20 shows what happens when one or more files are deleted at time t10 in such a system. Until time t10, the space occupied by valid data increases, and both the reproducible space and the erased block space decrease as the effective data amount increases. As indicated by the dashed line, the reproducible space is replayed at a rate that guarantees replay of all reproducible space when the memory is full. Since one or more files are deleted at time t10, the space once occupied by valid data is occupied by used data, and thus becomes a reproducible space. After t10, the memory array can store more valid data, but this requires additional playback operations. Therefore, the controller recalculates the rate at which the playback operation should be performed. This provides an adaptive scheduling system that responds to changes in the state of data stored in the memory array. As a result, the playback rate is modified, and the playback rate affects the rate at which valid data is programmed, so the rate at which valid data is programmed is also changed. The adaptive playback scheduling system can recalculate the alternating ratio periodically, when triggered by a host command, or when triggered by some other event.

  FIG. 21 shows another example of memory management with three playback modes. In the first mode, the playback operation is not performed during the host data writing before t12. The amount of valid data increases at the same rate as the amount of space in the erased block decreases. During this time, since there is no data to be used, the amount of reproducible space is kept substantially the same. Some blocks may store valid data while leaving portions of the blocks that are erased and unused. These erased portions can be reproduced by consolidating the valid data in such a way that the erased space is integrated into one or more erased blocks. Therefore, in this mode, the reproducible space may increase to some extent even if there is no data to be used. In some examples, the minimum playback rate can be maintained in this first mode to ensure that the playback rate never goes to zero. Since the playback rate is low or zero, the rate at which host data is programmed in this first mode is high.

  In the second mode, the reproduction operation is performed from t12 to t13 according to the adaptive schedule shown in FIGS. In this case, the replay rate is calculated and the replay operation is sandwiched between the programming of new data, so the reproducible space decreases as the memory is full. Because of this alternate playback operation, the rate at which new data is programmed in the second mode is slightly lower than in the first mode. The second mode can be initiated when valid data in memory exceeds a threshold, when the space of erased blocks falls below the threshold, or based on some other criteria.

  In the third mode, the reproduction operation is performed at the maximum rate after t13 in order to prepare an erased block in which new data can be written. Increasing the rate of playback operations reduces the rate at which host data is programmed. The third mode can be initiated when the amount of valid data exceeds the threshold, when the amount of space in the erased block is below the threshold, or based on some other criteria.

Adaptive Scheduling-Detailed Example The non-volatile memory management for performing playback operations according to the adaptive scheduling system while keeping the host data programming rate constant will now be described in detail using the example of a memory with a direct data file storage interface. To do. This example demonstrates how to calculate the appropriate alternating ratio from parameters monitored by the memory controller. FIG. 22 shows in detail various states of pages in the memory space over time in such a memory. A number of possible transitions in a page or block of the memory array are also shown. The memory array consists of blocks, each block containing a plurality of pages. In this example, the terms “block” and “page” are used, but this example also applies to memories having metablocks and metapages as erase and programming units, respectively. A block is treated as any one of three states at any time, and pages in these blocks are treated as any one of five states. FIG. 22 shows the page numbers that take each of these five states over time.
Block classification for data storage
File block : The file block is filled with host data and does not contain used data. Actually, there may be a case where the minimum unprogrammed page, for example, two pages can be accommodated in the file block.
Incomplete block : An incomplete block contains some host data and some erased and / or used pages.
Erased block : A completely erased block in the erased block pool.

  In addition to these three categories, some blocks may be filled with obsolete data. For example, immediately after a file to be deleted or deleted is indicated by the host, a block containing the file is included in the garbage collection schedule. Some of these blocks are filled with data. However, such blocks are not considered for the purposes of this calculation because they are quickly erased without requiring significant resources.

Page Classification for Data Storage Terms for classifying pages in the memory array according to the state of the page and other pages in the same block are listed below. FIG. 22 shows the page numbers in each state.
File block page (FBP) : This is the number of valid host data pages contained in the file block.
Data pages (DP) : This is the number of valid host data pages contained in an incomplete block.
Used pages (OP) : This is the number of used host data pages contained in incomplete blocks.
Erased pages (EP) : This is the number of erased pages contained in an incomplete block. It can be considered that a reusable space is formed in the memory array by the used page (OP) and the erased page (EP).
Erased block page (EBP) : This is the number of erased pages contained in the erased block.
Pages that exist in blocks that contain only used data are ignored in this list because they do not exist for a long time and do not place a heavy burden on the garbage collection they need to regenerate.

In addition to the five mutually exclusive categories described above, there are two numbers related to pages in the memory array: total page number and total data page number. These terms represent pages that fall into the categories described above. These numbers are tracked by the memory controller.
Total pages (TP) : This is the total number of pages in the device that can be used for data storage and corresponds to the data capacity of the device.
Total data pages (TDP) : This is the number of pages that contain valid host data at any given time. Data pages are in either file blocks or incomplete blocks.
Stages of data copy operation: There are two stages in the data copy operation, but they do not need to be considered separately in the following adaptive scheduling analysis.
(1) Garbage collection stage: There are used pages in the device, and a garbage collection operation is performed to eliminate them.
(2) Block consolidation / integration stage: A block consolidation / integration operation is performed to recover an erased capacity constrained in an incomplete block.

  If the host writes data to the same file as valid data, blocks that contain only valid and erased space can continue to be used without consolidation, so typically, garbage collection is performed first and block consolidation is performed. You should turn around. Even where the file is closed, the file is reopened and the data is written to the program block. Since garbage collection must be performed before the block containing the obsolete data can be used again, there is no advantage in deferring such garbage collection.

Page Transition Caused by Device Operation FIG. 22 shows the following page transition.
Used page to erased block page (1) : Occurs when a block is erased after a valid data page is copied from the block containing the used page.
Data page to data page (2) : related to the data page copied from the copy source block to the copy destination block.
Erased page to erased block page (3) : When the copy source block is erased after all valid data pages have been copied from the copy source block to the copy destination block, the erased page programmed in the copy destination block Is effectively an erased block page in the source block.
Erased block page to erased page (4) : After the valid data page is copied from the copy source block to the erased block, the remaining erased block pages in the erased block become erased pages.
Data page to file block page (5) : A valid data page in an incomplete block becomes a file block page when the block is full.
Erased block page to file block page (6) : An erased block page becomes a file block page when the block is filled with data written by the host.

  FIG. 23 illustrates how these transitions occur in a block of the memory array. FIG. 23A shows four blocks A to D in the memory array, and the amount and state of data differ from block to block. Since pages 0-3 of block A each contain valid data (indicated by shading), block A is filled with valid data. Therefore, block A is regarded as a file block. Block B includes page 0 containing valid data (data X), pages 1 and 2 containing used data (indicated by diagonal lines), and page 3 in an erased state. Block B contains some valid data, but is not filled with valid data and is therefore considered an incomplete block. Block C has pages 0 and 1 filled with valid data and pages 2 and 3 in an erased state. Block C also contains some valid data, but is not filled with valid data and is therefore considered an incomplete block. Since block D is completely erased and contains no data, it is considered an erased block.

  Since block A in FIG. 23A is the only file block, the number of file block pages (FBP) is equal to the number of pages in block A, ie four. The number of data pages (DP) is the number of valid pages in blocks B and C and is therefore equal to 3. The number of used pages (OP) is the number of pages filled with used data in blocks B and C, and is equal to two. The number of erased pages (EP) is the number of pages in the erased state in blocks B and C and is equal to 3. Since block D is the only erased block, the number of erased block pages (EBP) is the number of pages in block D and is equal to four. In this example, the total page (TP) is, in short, the total number of pages of all blocks, and here is 16 pages. The total data page (TDP) is the number of pages containing valid data, and is 7 pages here.

  FIG. 23A shows how valid data X is copied from page 0 of block B to page 2 of block C. This is an example of a type (2) transition from DP to DP. Thereafter, since only the used data remains in the block B of FIG. 23B, the block B can be queued for erasure at this point. New valid data Y is written in block D of FIG. 23B, and page 0 of block D thus becomes a data page. Pages 1 to 3 of block D change from an erased block page to an erased page with a type (4) transition. FIG. 23C shows the blocks A to D after the block B is erased. Pages 0-2 change from a used page to an erased block page with a type (1) transition. Page 3 of block B changes from the erased page in the incomplete block to the erased block page in the erased block of FIG. 23C. This is an example of a type (3) transition. Also in FIG. 23C, valid data Y is copied from page 0 of block D to page 3 of block C, so that block C is full of valid data as shown in FIG. 23D. Therefore, the block C in FIG. 23D is regarded as a file block. Pages 0-2 of block C, which was once a data page, become file block pages when block C becomes a file block with a type (5) transition. In FIG. 23D, block B is also filled with valid data to fill block B. The page of block B changes from an erased block page to a file block page at type (6) transition.

  One purpose of this adaptive scheduling scheme is to alternately perform host write and replay operations to provide constant rate host data programming. Thus, the rate at which the total data page (TDP) increases is constant until the total data page (TDP) is equal to the total page (TP), that is, until the memory is full. In this example, a certain amount of rough estimation is performed when calculating various parameters. However, other examples may be based on other assumptions or may be performed in other ways. This calculation ignores the data group structure of the copied data. Therefore, the data group may be divided when copying. Once the data page is copied from the source block and the available erased page of the destination block is filled, the remaining data page can be copied to another destination block.

  The controller maintains specific parameter values that are used in calculating the appropriate alternating ratio between the playback operation and the new data write. In the calculation introduced in the present specification, a page is used as a basic data unit of calculation, but another unit such as a block or a metablock may be used. The alternating ratio is as follows using only the parameter values maintained by the controller: only total page (TP), total data page (TDP), incomplete block page (PBP), and erased block page (EBP). Can be calculated as shown.

(Host Data): (Copy Data) Derivation of Interleave Ratio The number of additional host data pages that can be written to the device before the device is full is determined by the following equation:
Host data to be written = TP-TDP

The number of erased pages (EP) and data pages (DP) can also be written as follows using parameters monitored by the controller:
Erased page (EP) = TP-TDP-OP-EBP
Data page (DP) = PBP-EP-OP
= PBP- (TP-TDP-OP-EBP) -OP
= TDP + PBP + EBP-TP

  The amount of valid data that must be copied is determined based on an approximation that all incomplete blocks contain the same number of valid data pages. When the total number of pages in one block is N, the average number of effective pages in the incomplete block is N * DP / PBP.

  Only a small portion of the data page in the incomplete block needs to be copied. There is a residue in an incomplete block that becomes a copy destination block to which data is copied. It is assumed that incomplete blocks are used as copy destination blocks in all copies, and it is not necessary to use erased blocks. Since valid data in each incomplete block to be erased is copied prior to erasure, the number of blocks corresponding to the data copy source is equal to the number of erased blocks to be created. Number of erased blocks created = (PBP-DP) / N.

Thus, by multiplying the number of blocks to be erased by the average number of effective pages per block, an approximation of the amount of data copied to reproduce the entire reproducible space in the memory array can be obtained.
Data to be copied = {N * DP / PDP} * {(PBP-DP) / N}
= DP * (PBP-DP) / PBP
= (TDP + PBP + EBP-TP) * (PBP-TDP-PBP-EBT + TP) / PBP
= (TDP + PBP + EBP-TP) * (TP-TDP-EBP) / PBP
Note that this actually overestimates the amount of data to be copied because the block with the least amount of valid data to be copied is selected as the source block for the copy operation. Thus, the rate of data copy based on simplification, where all incomplete blocks contain data pages at the same rate, is somewhat higher than the required rate.
(Host data): (Copy data) Interchange ratio = (Host data to be written) / (Data to be copied)
= (TP-TDP) * PBP / (TDP + PBP + EBP-TP) / (TP-TDP-EBP)

  This provides an alternating ratio that allows programming of host data to continue at a constant rate until the memory is full. This ratio can be updated periodically or in response to some triggering event. This ratio is an example of an equation that can be used to schedule a playback operation to allow constant rate host data programming. Other formulas can be used. The formula for calculating the alternating ratio may be based on the above-described calculation or the like, or may be based on experience in actual memory. The formula can be simplified by making assumptions about factors that should be ignored in the calculation. Instead, more complex formulas can take into account additional factors such as the time to erase a block, or the possibility that an erased block may be required as a garbage collection destination block.

  Although the example memory described above has a file-oriented host interface, aspects of the invention can also be applied to memory using a sector-oriented host interface or some other host interface. Some memories with a sector-oriented interface lack sufficient information to greatly benefit from the application of the described technique, but some performance improvement can be achieved. In addition, some memories with sector oriented interfaces parse the FAT or otherwise obtain more information about the state of stored data. Some hosts use additional commands to provide information about stored data to the controller. Such information can be used to set up a reproduction schedule early.

Host operation In some examples, playback operations in non-volatile memory can be managed in various modes. As described above, the playback operation can operate at a certain minimum rate (including zero in some examples) in the first mode, can operate adaptively in the second mode, and can operate at the maximum rate in the third mode. Can work. The playback mode can be selected by the memory controller according to a predetermined standard. In some examples, the host can control the playback mode. The host can determine which of the three modes described above is selected. In addition, the host may have a command to select an appropriate playback mode based on current host activity or expected host activity. The host system may be physically separated from the memory system as shown in FIG. Alternatively, the processor in the memory card that executes the on-card application can be considered as the host. US Provisional Patent Application No. 60 / 705,388 (Patent Document 30) describes such a configuration.

  The first host command relating to the memory playback mode is a “playback on (Reclaim_on)” command that allows continuous playback operations instead of alternating operations. The playback operation performed in this way is regarded as a background operation because it does not cause a delay in the execution of the host command and is transparent to the host. “Playback On” corresponds to an “idle” command that tells the memory that the host will not send an additional command for a while. In some systems, these are the same commands. The play-on mode that this results in ends when another host command is received.

  The “replay normal (Reclaim_normal)” command enables operation in the default playback mode of the memory. This can mean playing according to an adaptive schedule, or it can mean giving the memory controller control over playback mode selection and the memory controller selecting the playback mode based on some predetermined criteria. . The memory can enter this mode by default upon receipt of a host command that terminates the playback on mode.

  The “playback off (Reclaim_off)” command prohibits the playback operation and performs only the host operation. This mode can be selected to provide maximum host data write performance. This mode is terminated by a playback on command or a playback normal command.

Possible playback mode hierarchies according to the descending order of playback rates are as follows.
Play On : The device performs a continuous playback operation until another command is received.
Maximum alternation : The replay operation is performed alternately with the host data write operation at a constant maximum alternation ratio. This is the upper limit of the adaptive alternating ratio.
Adaptive alternation : The replay operation is performed alternately with the host data write operation according to the adaptive alternation ratio.
Minimum alternation : The replay operation is performed alternately with the host data write operation at a certain minimum alternation ratio. This is the lower limit of the adaptive alternating ratio.
Playback off : Playback operation is prohibited, and only host data write operation is performed.

  It should be noted that the above description refers to constant rate host data writes. The constant rate provided by alternate regeneration is observed over multiple cycles. When viewed at the level of individual cycles, host data is written in a periodic host write operation with a replay operation. However, the host data write rate per cycle or over many cycles can be kept constant at the estimated rate and can be maintained until the memory array is full.

  In the above description, it can be seen that the rate at which the reproducible space in the memory array is converted to erased blocks is constant. However, even if the number of reproduction operations per cycle or unit time is constant, the rate at which erased blocks are created by the reproduction operation is not always constant. This is because the block to be reproduced is selected so that the block that is easy to reproduce is reproduced first. Therefore, when adaptive reproduction starts, if there are valid data for R pages in the block to be reproduced, the blocks are reproduced for each R page of the copied data. Thereafter, to reproduce a block having valid data for 2R pages, 2R copy operations are required every time an erased block is created. Therefore, the rate at which erased blocks are created by playback is reduced to half of the previous rate. In another example, the rate at which erased blocks are created varies differently depending on the playback order of the blocks. If a block is played back regardless of the amount of valid data contained therein, the rate at which the erased blocks are created by playback is reasonably constant.

  While various aspects of the present invention have been described with respect to exemplary embodiments thereof, it will be understood that the rights should be protected within the full scope of the appended claims.

1 schematically illustrates a currently implemented non-volatile memory system connected to a host. FIG. 2 is a block diagram of an example of a flash memory system used as the nonvolatile memory of FIG. 1. FIG. 3 is a typical circuit diagram of a memory cell array that can be used in the system of FIG. An example of the physical memory organization of the system of FIG. FIG. 5 shows an enlarged view of a portion of the physical memory of FIG. 4. Figure 6 shows a further enlarged view of a portion of the physical memory of Figures 4 and 5; 1 illustrates a general prior art logical address interface between a host and a reprogrammable memory system. An example of the garbage collection in a non-volatile memory is shown. An example of the garbage collection in a non-volatile memory is shown. Another example of garbage collection in non-volatile memory is shown. Another example of garbage collection in non-volatile memory is shown. An example of compression in a non-volatile memory is shown. An example of compression in a non-volatile memory is shown. An example of consolidation in a nonvolatile memory is shown. An example of consolidation in a nonvolatile memory is shown. FIG. 8 illustrates file deletion by a host application of a file stored in non-volatile memory using the interface of FIG. An example of how the space of a non-volatile memory is managed is shown. Another example of how non-volatile memory space is managed is shown. Shows alternate host write operations and garbage collection operations. Fig. 2 illustrates a non-volatile memory having a file oriented interface to a host. FIG. 17 illustrates file deletion by a host application of a file stored in non-volatile memory using the interface of FIG. An example of space management in a non-volatile memory having a file-oriented interface is shown. FIG. 4 shows another example of space management in a non-volatile memory with a file-oriented interface that provides a constant rate of host data programming until the memory array is full. Fig. 4 shows another example of space management in a non-volatile memory with a file-oriented interface with adaptive playback scheduling adapted to file deletion. Spatial management in a non-volatile memory with a file-oriented interface in three modes: an initial mode with a minimum playback rate, an adaptive mode with an adaptively scheduled playback rate, and a final mode with a maximum playback rate Here is another example. FIG. 5 shows a detailed view of space management in a non-volatile memory with a file oriented interface, including memory array portions in various states and possible data transitions between those states. FIG. 23 shows a block of a memory array in which the stored data follows a transition that matches the transition of FIG. FIG. 23 shows a block of a memory array in which the stored data follows a transition that matches the transition of FIG. FIG. 23 shows a block of a memory array in which the stored data follows a transition that matches the transition of FIG. FIG. 23 shows a block of a memory array in which the stored data follows a transition that matches the transition of FIG.

Claims (21)

A method of managing space in a non-volatile memory array of a memory system that is detachably connected to a host, the non-volatile memory array having a block erase unit and partially filled with valid data In a method having blocks,
Operations and for storing host data in the nonvolatile memory array for receiving from (a) a host, the (b) the stored valid data toward another block of the nonvolatile memory array of one block of the nonvolatile memory array Copying and alternately forming an erase block for storing host data in the non-volatile memory array,
The altering step includes changing the amount of valid data copied to reproduce the erase block of the nonvolatile memory array so that the erase block storing the host data in the nonvolatile memory array is not used up. A method based on an adaptive ratio that relies on an estimate of . The method of claim 1, wherein
Performing the alternating method provides for storing host data in a constant rate in the nonvolatile memory array. The method of claim 2, wherein
The alternation ratio is further calculated such that the erase block is not exhausted and continues to store host data at a constant rate until the non-volatile memory array is filled with valid data. The method of claim 1, wherein
The alternating ratio is recalculated in response to a host command received from the host to store host data in the non-volatile memory array . The method of claim 1, wherein
The alternating ratio is further based on an estimate of the amount of change in additional host data that can be stored in the non-volatile memory array. The method of claim 5, wherein
The estimated value of the amount of change in the non-volatile memory additional host data may be stored in array further method based on the host or we received the information indicating that the host file is obsolete. The method of claim 1, wherein
Performing the alternating reproduction on mode to allow the reproduction-off mode to prohibit copying the already stored valid data, copying the already stored valid data in the nonvolatile memory array without storing host data A method that occurs in response to a host command that selects an alternate mode from a plurality of modes including: A method of reclaiming space in a non-volatile memory array of a memory system that is detachably connected to a host, the non- volatile memory array having a page programming unit and a block erasing unit, In a method of accommodating more than one page, the non-volatile memory array also accommodates a plurality of blocks each partially filled with valid data, but not completely ,
Valid data stored in a plurality of blocks is stored in the non-volatile memory so as to form a plurality of blocks in the non-volatile memory array that stores host data received from a host connected in a detachable manner with the memory system. Copying to another block of the array, said copy at a rate that relies on adaptively changing the amount of valid data stored in the plurality of blocks so that the erase block storing host data is not exhausted Steps to be performed, and
The individual blocks of the multiple blocks, after the entire effective data is copied in the block of the individual, and the step of erasing,
Including methods. The method of claim 8, wherein
The copying is performed alternately with a host write operation, and the rate is set according to a change amount of valid data copied within a time allowed for the host write operation. The method of claim 9, wherein
The rate is set by a ratio of the number of pages of valid data copied to the number of pages of host data written in one cycle of the repetition cycle. The method of claim 10, wherein:
The ratio is calculated adaptively from the equation r = x / y;
Here, x is the estimated value of the variation of the effective data contained in the block of numbers Ifuku shall be copied to play space in multiple blocks,
y is an estimate of the amount of change in additional host data that can be stored in the non-volatile memory array before the non-volatile memory array is full. The method of claim 9, wherein
The rate is the hand as the gradually filled with the non-volatile memory array Gaho strike write operation, a method of the step of said copy, is calculated to uniformly distribute in between host write operation. The method of claim 8, wherein
Block of multiple effective data is copied, the method also accommodates Data for the obsolete Ru identified by the host command. A method of managing space in a nonvolatile memory array of a memory system connected in a detachable manner with a host , wherein the nonvolatile memory array has a block erase unit,
Operations and for storing host data in the nonvolatile memory array for receiving from (a) a host, the (b) the stored valid data toward another block of the nonvolatile memory array of one block of the nonvolatile memory array the operations that copy, in accordance with alternate ratio at repeated cycles, is performed alternately, hands the non-volatile memory array without block is used up by the host data may be stored is as the filling in the host data, constant over a plurality of cycles A method comprising the step of storing host data at a rate of. The method of claim 14, wherein
The alternate ratio is the estimated value of the total amount of additional host data may be stored in non-volatile memory array, in order to reproduce all the playable space in the nonvolatile memory array, separate from one single block method is calculated from the estimated value of the total amount of the stored valid data toward the block must be copied. The method of claim 15, wherein
The method estimates of the total amount of the copied the stored valid data must is obtained by assuming that the effective data across all the blocks partially filled with valid data are uniformly dispersed. A memory system that is detachably connected to a host ,
A non-volatile memory array including a plurality of blocks, wherein one block is a minimum erase unit;
A memory controller that maintains a record of logical-to-physical mapping for host data received from the host and stored in the non-volatile memory array, the record having a plurality of items, each item being the logical address indicates the unique file identifiers and offsets, the memory controller includes: the host to determine obsolete therefore whether the stored data is valid or information supplied by, and the amount of change in the effective data to be copied such that said non-volatile memory array is to form the non-volatile total change amount and a plurality of erase blocks in relying rate to adapt to the additional host data may be stored in the memory array before the full, the non further to copy the valid data toward another block from one block of sexually memory array When configured memory controller,
A memory system comprising: The memory system of claim 17, wherein
The rate is recalculated in response to a host command. The memory system of claim 17, wherein
The memory system is calculated to provide for storing host data at a constant rate until the non-volatile memory array is filled with valid host data. The memory system of claim 17, wherein
The memory system is embodied as a removable memory card that communicates with the host through a standard interface. The memory system of claim 17, wherein
The host memory system to provide information about the host file using a unique file identifier to refer to the host file.

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