WO2023082252A1

WO2023082252A1 - Garbage collection method, and memory and memory management apparatus

Info

Publication number: WO2023082252A1
Application number: PCT/CN2021/130653
Authority: WO
Inventors: 黄恩走
Original assignee: 华为技术有限公司
Priority date: 2021-11-15
Filing date: 2021-11-15
Publication date: 2023-05-19

Abstract

A garbage collection method, and a memory and a memory management apparatus. In the method, a memory controller can receive first garbage collection (GC) information from a processor by means of an information management interface, and map a first logic storage area in the first GC information into a first physical storage area; and the memory controller determines a plurality of second physical storage areas, on which the memory controller needs to execute a second GC operation, and when the first physical storage area has intersections with a plurality of second physical storage areas, selects a first target physical storage area from among the second physical storage areas, which have intersections with the first physical storage area. In this way, the influence, on the execution of the second GC operation by the memory controller, of the execution of the first GC operation on the first logic storage area by the processor is reduced, that is, the workload of the memory controller ineffectively transferring valid data when the second GC operation is subsequently executed can be reduced, thereby improving the efficiency of the memory controller executing the second GC operation, and ensuring the performance of the memory.

Description

A garbage collection method, memory and memory management device

technical field

The present application relates to the technical field of storage, and in particular to a garbage collection method, a memory and a memory management device.

Background technique

The memory is mainly composed of a memory controller and a storage unit that provides physical storage space. In order to ensure the storage efficiency of the physical storage space, the physical storage space is generally mapped to the virtual storage space. Among them, the physical storage space can be divided into multiple physical blocks (physical block), and the virtual storage space can also be divided into many logical blocks (logical block).

The following uses a solid state disk (SSD) as an example for illustration. The memory controller in the SSD can perform space management on the physical storage space in the storage unit. For example, the memory controller can not only use the flash translation layer (flash translation layer, FTL) to perform logical block address (logical block address, LBA) in the logical storage space and physical block address (physical block address, PBA) in the physical storage space The mapping and conversion between them can also perform garbage collection GC (garbage collection, GC) operations.

Applying storage (continuing to use SSD as an example) in a distributed storage system (distributed storage system, DSS) is a common application mode at present. DSS can write data to SSD through append write mode, so as to realize the purposes of snapshot and exception handling, and also improve the performance of SSD. Similar to SSD, DSS can also use FTL technology or other technologies similar to FTL technology to map and convert between DSS effective storage space and SSD LBA. Of course, the DSS is also designed with a GC function for the logical storage space of the SSD, which is executed by the storage management device.

However, when the GC functions of SSD and DSS are superimposed, it may have a negative impact on the performance of SSD. Among them, the basic unit of GC operation is a storage block.

When SSD performs GC operation, it will move valid data in one physical block to other physical blocks, that is, every time GC operation is performed, SSD will transfer valid data in the physical storage area corresponding to GC operation to other physical blocks in the Flash medium. Re-persistent writing on the physical storage area consumes the P/E times in the Flash medium, thereby reducing the write performance presented by the SSD to the storage management device. The industry uses the write amplification factor (WAF) to measure the impact of the same valid data being persistently stored multiple times on the Flash medium. WAF is a numerical value, which is a ratio obtained by dividing the amount of data written into the Flash medium by the memory controller in the SSD by the amount of data written into the SSD by the memory management device. Generally, the more times valid data is persistently stored on the Flash medium, the greater the WAF of the SSD; that is, the greater the amount of valid data moved by GC operations inside the SSD, the greater the WAF of the SSD, and the lower the efficiency of SSD GC operations. As a result, the performance presented by SSD to DSS, especially the write performance, is also lower.

Moreover, when the DSS performs GC operations, the DSS itself also has a WAF value; the WAF value of the DSS will reduce the write performance presented to the upper-layer application. Apparently, when both the DSS and the SSD perform GC operations, the WAF values of the SSD and the DSS will reduce the write performance presented by the SSD to the storage management device.

Contents of the invention

The present application provides a garbage collection method, a memory and a memory management device, which are used to improve the efficiency of the memory controller to perform GC operations to ensure the performance of the memory when the memory management device and the GC function of the memory are superimposed.

In a first aspect, a garbage collection method is provided, which is applied to a memory controller, and the method includes:

Receive the first GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation on the logical storage space; the logical storage The space is obtained by mapping the physical storage space managed by the memory controller; then, mapping the first logical storage area to at least one first physical storage area in the physical storage space; in the physical storage space, determining A plurality of second physical storage areas that need to perform a second GC operation; when it is determined that there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas, from the plurality of second physical storage areas Determine at least one second physical storage area to be selected; there is no intersection between the at least one second physical storage area to be selected and the at least one first physical storage area; and in the at least one second physical storage area to be selected Determine the first target physical storage area where the memory controller performs the second GC operation.

In this method, after the memory controller receives the first GC information, it determines the first logical storage area where the processor needs to perform the first GC operation according to the received first GC information; then, the memory controller sets the first The logical storage area is mapped to at least one first physical storage area, wherein the first valid data located in the first logical storage area is stored in the at least one first physical storage area in the physical storage space. After determining the plurality of second physical storage areas, the memory controller determines whether the second physical storage area stores the second physical storage area by judging whether there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas. A valid data, and then it can be determined whether the second physical storage area is affected by the processor's first GC operation. When at least one first physical storage area intersects with multiple second physical storage areas, it means that the second GC operation of the memory controller is affected by the first GC operation. Select at least one candidate second physical storage area that does not overlap with the first physical storage area in the area, and determine the first target physical storage area for the memory controller to perform the second GC operation from the at least one candidate second physical storage area Storage area, to reduce the impact of the first GC operation on the second GC operation performed by the memory controller; and, when the processor performs the first GC operation on the first logical storage area, the processor moves the first valid data so that the physical The storage area of the corresponding first valid data stored in the storage space changes, so as to reduce the first valid data stored in the second physical storage area, and reduce the number of valid data that is invalidly moved by the memory controller in subsequent second GC operations. workload, improving the efficiency with which the memory controller performs the second GC operation.

In a possible design, the memory controller selects from the plurality of second physical storage areas to affect the At least one candidate second physical storage area whose factor is smaller than the set threshold; wherein, the impact factor of each second physical storage area is used to characterize the first valid data and the second valid data in the second physical storage area The storage space occupied by the intersection of in the second physical storage area. In addition, the impact factor represents the influence of the processor executing the first GC operation on the memory controller executing the second GC operation on the second physical storage area.

Through this design, the memory controller determines the impact factor of the processor performing the first GC operation on the first logical storage area on each second physical storage area according to the first valid data and the second valid data, and the memory controller can Determine the degree of influence of the first GC operation on the second physical storage area according to the determined impact factor; the memory controller selects at least one candidate second physical storage area whose impact factor is less than the set threshold from the plurality of second physical storage areas ; Then, the memory controller is made to select the first target physical storage area from at least one second physical storage area to be selected, and at the same time, the second physical storage area whose impact factor is greater than or equal to the set threshold is put behind for processing, On the basis of minimizing the workload of invalidly moving valid data when the memory controller performs the second GC operation, the workload of the memory controller for subsequently executing the second GC operation for invalidly moving valid data can be reduced, thereby improving the subsequent performance of the memory controller. The efficiency of the second GC operation.

In a possible design, the memory controller determines at least one third physical storage area that needs to perform the third GC operation in the physical storage space, and maps at least one third physical storage area to the logical storage space at least one second logical storage area; then, sending second GC information to the processor through an information management interface, wherein the second GC information is used to indicate at least one logical storage area that needs to perform a third GC operation.

With this design, the memory controller sends the second GC information to the processor, so that the processor can determine at least one second logical storage area where the memory controller needs to perform the third GC operation according to the received second GC information, and Applying the determined at least one second logical storage area to the process of the processor determining the first target logical storage area for performing the fourth GC operation, so that when the processor performs the fourth GC operation on the first target logical storage area, it can Reduce the valid data stored in the third physical storage area by processing the valid data located in the first target logical storage area, and reduce the workload of invalidly moving valid data when the memory controller performs the third GC operation on the third physical storage area , improving the efficiency of the subsequent third GC operation on the third physical storage area, so as to achieve the purpose of ensuring memory performance.

In a second aspect, a garbage collection method is provided, which is applied to a processor, and the method includes:

In the logical storage space, determine the first logical storage area that needs to perform the first GC operation; wherein, the logical storage space is obtained by mapping the physical storage space managed by the memory controller; then, report to the memory controller through the information management interface Sending first GC information; wherein, the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation.

In this method, since the processor sends the first GC information to the memory controller after determining the first logical storage area that needs to perform the first GC operation, the memory controller makes the first GC information from the memory controller according to the received first GC information. In the second physical storage area where there is no intersection of the first logical storage area, determine the first target physical storage area for performing the second GC operation, so as to reduce the memory control of the processor when performing the first GC operation on the first logical storage area The impact of the memory controller performing the second GC operation on the first target physical storage area, and reducing the workload of invalidly moving valid data when the memory controller performs the second GC operation on the first target physical storage area, and improving the memory controller's execution of the second GC operation The efficiency of GC operation, so as to achieve the purpose of guaranteeing memory performance.

In a possible design, the processor receives the second GC information sent by the memory controller through the information management interface; where the second GC information is used to indicate that the memory controller needs to perform the first GC on the physical storage space At least one second logical storage area obtained by mapping the third physical storage area of the three GC operations in the logical storage space; and, in the logical storage space, the processor determines that a plurality of second logical storage areas that need to perform the fourth GC operation Three logical storage areas; then, when there is an intersection between the at least one second logical storage area and the plurality of third logical storage areas, the third logical storage area to be selected from at least one of the plurality of third logical storage areas In the storage area, select the first target logical storage area where the processor performs the fourth GC operation; wherein, the at least one third logical storage area to be selected has an intersection with the at least one second logical storage area.

Through this design, according to the received second GC information, the processor determines at least one second logical storage area mapped in the logical storage space by the third physical storage area where the memory controller performs the third GC operation, and determines that it needs to execute A plurality of third logical storage areas operated by the fourth GC, and by judging whether there is an intersection between at least one second logical storage area and a plurality of third logical storage areas, it is determined whether the processor performs a fourth GC operation on the third logical storage area It will affect the execution of the third GC operation on the third physical storage area by the memory controller. When at least one second logical storage area intersects with multiple third logical storage areas, from at least one candidate third logical storage area intersecting with at least one second logical storage area, the selection processor executes a fourth GC The first target logical storage area of the operation can enable the processor to reduce the amount stored in the third physical storage area by processing the valid data in the first target logical storage area when performing the fourth GC operation on the first target logical storage area. valid data, thereby reducing the workload of the memory controller for invalidly moving valid data when performing the third GC operation on the third physical storage area, improving the execution efficiency of the memory controller performing the third GC operation, and achieving the purpose of ensuring memory performance.

In a possible design, the processor selects the first target logical storage area with the largest invalid ratio among the at least one third logical storage area to be selected; wherein, each third logical storage area to be selected The invalid ratio is a ratio of invalid data in the third logical storage area to be selected to the storage space of the third logical storage area to be selected.

Through this design, the processor selects the first target logical storage area with the largest invalid ratio among at least one third logical storage area to be selected, which can ensure the execution efficiency of the processor when executing the fourth GC operation.

In a third aspect, a memory is provided, and the memory includes: a memory controller and a storage unit; the memory controller is used for:

Receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation on the logical storage space; the said The logical storage space is obtained by mapping the physical storage space managed by the memory controller;

mapping the first logical storage area to at least one first physical storage area in the physical storage space;

In the physical storage space, determine a plurality of second physical storage areas that need to perform the second GC operation;

When there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas, at least one candidate second physical storage area is determined from the plurality of second physical storage areas; the at least one There is no intersection between the second physical storage area to be selected and the at least one first physical storage area;

A first target physical storage area for the memory controller to perform the second GC operation is determined in the at least one second physical storage area to be selected.

In a possible design, the memory controller is also used for:

In the physical storage space, determine at least one third physical storage area that needs to perform a third GC operation;

mapping the at least one third physical storage area to at least one second logical storage area in the logical storage space;

Sending second GC information to the processor through the information management interface; wherein the second GC information is used to indicate the at least one second logical storage area that needs to perform the third GC operation.

In a fourth aspect, a memory management device is provided, the memory management device includes: a processor and an information management interface; the processor is used for:

In the logical storage space, determine the first logical storage area that needs to perform the first GC operation; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

Sending first GC information to the memory controller through the information management interface; wherein the first GC information is used to indicate a first logical storage area where the processor needs to perform a first GC operation.

In a possible design, the processor is also used for:

Receive second GC information from the memory controller through the information management interface; wherein the second GC information is used to indicate that the memory controller needs to perform a third GC operation on the physical storage space for the third physical storage At least one second logical storage area obtained by mapping the area in the logical storage space;

In the logical storage space, determine a plurality of third logical storage areas that need to perform the fourth GC operation;

When there is an intersection between the at least one second logical storage area and the plurality of third logical storage areas, selecting the at least one candidate third logical storage area among the plurality of third logical storage areas The processor executes the first target logical storage area of the fourth GC operation; wherein, the at least one third logical storage area to be selected has an intersection with the at least one second logical storage area.

In a fifth aspect, a garbage collection device is provided, and the garbage collection device is applied to a memory controller in a memory; the device includes:

The transmission module is configured to receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate that the processor needs to perform the first logic of the first GC operation on the logical storage space storage area; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

a mapping module, configured to map the first logical storage area to at least one first physical storage area in the physical storage space;

A determining module, configured to determine a plurality of second physical storage areas that need to perform a second GC operation in the physical storage space; when there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas , determining at least one second physical storage area to be selected from the plurality of second physical storage areas; there is no intersection between the at least one second physical storage area to be selected and the at least one first physical storage area; Determine the first target physical storage area where the memory controller executes the second GC operation in the at least one second physical storage area to be selected.

In a possible design, the determining module is specifically configured to: in the physical storage space, determine at least one third physical storage area that needs to perform a third GC operation;

The mapping module is specifically configured to: map the at least one third physical storage area to at least one second logical storage area in the logical storage space;

The transmission module is specifically configured to: send second GC information to the processor through the information management interface; wherein the second GC information is used to indicate the at least one first GC that needs to perform the third GC operation. Two logical storage areas.

In a sixth aspect, a garbage collection device is provided, the garbage collection device is applied to a processor; the device includes:

The processing module is configured to determine the first logical storage area that needs to perform the first GC operation in the logical storage space; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

A transmission module, configured to send first GC information to the memory controller through the information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation .

In a possible design, the transmission module is specifically configured to: receive second GC information from the memory controller through the information management interface; where the second GC information is used to indicate that the memory controller At least one second logical storage area obtained by mapping the third physical storage area in the logical storage space where the controller needs to perform the third GC operation on the physical storage space;

The processing module is specifically configured to: in the logical storage space, determine a plurality of third logical storage areas that need to perform the fourth GC operation; when the at least one second logical storage area and the plurality of third logical storage areas When there is an intersection of the storage areas, selecting the first target logical storage area for the processor to perform the fourth GC operation from at least one candidate third logical storage area among the plurality of third logical storage areas; wherein , there is an intersection between the at least one candidate third logical storage area and the at least one second logical storage area.

In the seventh aspect, the present application provides a computer-readable storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed, the computer can execute any one of the above-mentioned first aspect or the first aspect. The method in the implementation manner of the above-mentioned second aspect or the method in any possible implementation manner of the second aspect.

In an eighth aspect, the present application provides a computer program product. When the computer executes the computer program product, the computer is made to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect, or the computer is made to execute the above-mentioned first aspect. The method in the second aspect or any possible implementation of the second aspect.

For the above-mentioned beneficial effects of the third aspect and the fifth aspect, please refer to the description of the above-mentioned beneficial effects of the first aspect, and for the above-mentioned beneficial effects of the fourth and sixth aspects, please refer to the description of the above-mentioned beneficial effects of the second aspect. Repeat it again.

Description of drawings

FIG. 1 is a schematic structural diagram of a possible storage system of the solution provided by the embodiment of the present application;

FIG. 2 is a schematic structural diagram of another possible storage system of the solution provided by the embodiment of the present application;

FIG. 3 is a schematic structural diagram of another possible storage system of the solution provided by the embodiment of the present application;

FIG. 4 is a schematic diagram of a possible garbage collection method of the solution provided by the embodiment of the present application;

FIG. 5 is a schematic diagram of a possible garbage collection method of the solution provided by the embodiment of the present application;

FIG. 6 is a schematic diagram of a possible memory controller management queue of the solution provided by the embodiment of the present application;

FIG. 7 is a schematic diagram of a possible storage space of the solution provided by the embodiment of the present application;

FIG. 8 is a schematic diagram of another possible storage space of the solution provided by the embodiment of the present application;

FIG. 9 is a schematic flowchart of a possible garbage collection method of the solution provided by the embodiment of the present application;

FIG. 10 is a schematic diagram of another possible management queue of the solution provided by the embodiment of the present application;

FIG. 11 is a schematic flowchart of another possible garbage collection method of the solution provided by the embodiment of the present application;

FIG. 12 is a schematic diagram of an interaction process of a possible garbage collection method of the solution provided by the embodiment of the present application;

FIG. 13 is a schematic structural diagram of a memory management device according to the solution provided by the embodiment of the present application;

Fig. 14 is a schematic structural diagram of a garbage collection device according to the solution provided by the embodiment of the present application;

Fig. 15 is a schematic structural diagram of another garbage collection device according to the solution provided by the embodiment of the present application.

Detailed ways

Embodiments of the present application provide a garbage collection method, a memory, and a memory management device. Wherein, the method, the memory, and the memory management device are based on the same idea. Since the method, the memory, and the memory management device have similar problem-solving principles, the implementation of the memory, the memory management device, and the method can be referred to each other, and repeated descriptions will not be repeated.

In order to make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings. Among them, in the description of the embodiments of the present application, the terms "first" and "second" are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features . Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of these features.

In order to facilitate understanding, descriptions of concepts related to the present application are provided as examples for reference.

1) The memory is composed of a memory controller and a storage unit of non-volatile medium particles such as Flash. Wherein, the storage unit provides physical storage space for the memory, and the storage unit includes many storage blocks (block), and the block includes many storage pages (page). The current storage includes: SSD, shingled magnetic recording hard disk drive (SMR HDD) and other storage devices with GC functions similar to SSD.

The following uses SSD as an example for description.

SSD is a hard disk made of solid-state electronic memory chip arrays, also known as solid-state drives. An SSD generally includes at least two parts, a memory controller and a storage array, and the memory controller can be used to control the storage array. The storage array is composed of storage units that provide physical storage space, and are used to provide the storage area of the SSD and can store data. A storage unit consists of multiple blocks. Wherein, the block may be a flash memory (flash), and the following uses a flash memory as an example for description.

When SSD uses flash memory as the storage medium, the storage array usually includes dozens, hundreds or even thousands of flash memories, each flash memory can include hundreds to thousands of flash memory blocks, and each flash memory block can include thousands of flash memory pages . Flash memory has three basic operations: read, write, and erase. Among them, the operation granularity of read operation and write operation is a flash memory page, and the operation granularity of erase operation is a flash memory block. Therefore, flash memory has remote update and asymmetric read/write erase. Latency characteristics.

In order to better use blocks, the memory controller in the SSD can perform space management on the physical storage space in the storage unit. For example, the memory controller can not only use the FTL mapping table in the FTL to map and convert between the LBA in the logical storage space and the PBA in the physical storage space, but also perform GC operations to ensure the performance of the SSD.

The FTL mapping table is an address translation table, which is used to indicate the mapping relationship between the LBA in the logical storage space and the PBA in the physical storage space. Among them, LBA is the logical block address generated by the system for data before writing to the block, and PBA is the physical block address after writing to the block. After the data processing request (or user request) is sent to the SSD, the SSD can determine the PBA in the block corresponding to the data processing request through the FTL mapping table. If the data processing request is a read request (for requesting a read operation), the data of the corresponding PBA in the block is read out; if the data processing request is a write request (for requesting to perform a write operation), and the write operation If it is the first time to write a certain data, then write the data into the blank PBA in the storage block; The PBA corresponding to the data in the storage block is invalid, and the updated data corresponding to the data is written into the blank PBA in the storage block, and then the corresponding address mapping relationship in the FTL mapping table is updated to complete the operation. If the data processing request is an erase request (for requesting to perform an erase operation), delete the data of the corresponding physical address in the storage block, and delete the corresponding address mapping relationship in the FTL mapping table.

2) GC operation is the operation of reclaiming the used space when the available storage space (blank storage space or free storage space) in the storage space is small, and its specific operation includes: reading the valid data in the selected storage block to be reclaimed And migrate it into the target storage block in the available storage space, and then erase all the data in the storage block to be reclaimed, so as to reclaim the storage space corresponding to the storage block through GC operation.

3) The storage system is mainly composed of a memory and a processor, wherein the number of the memory and the processor is not limited. Optionally, the storage system is a detachable storage system, for example, DSS.

The DSS consists of a management device and multiple storage servers; the storage server is used to store data, and the management device is used to manage the storage servers. The management device in the DSS is equivalent to the processor in the storage system, and any storage server is equivalent to the memory.

4) Data processing request, which may be referred to as input/output (IO) request, IO, hereinafter referred to as IO request, refers to other devices (such as processors) issued to the memory to instruct the memory controller to perform data processing Action request. Exemplarily, the IO request may include at least one of a read request, a write request, and an erase request.

Taking the storage as an SSD as an example, the IO operation refers to the process in which the SSD executes the corresponding operation according to the received IO request, which is the operation performed by the SSD when responding to the IO request. For example, the IO operation may include at least one of a read operation, a write operation, and an erase operation.

5) The information management interface refers to the interface located in the memory and the processor, and is used to transmit GC information. Wherein, the information management interface may be an interface in a physical sense, or an interface in a logical sense.

6) The I/O interface refers to the interface located in the memory and the processor, and is used to transmit IO requests.

7) The storage space is divided into physical storage space and logical storage space.

The physical storage space refers to the space in which the data provided by the storage unit in the memory is actually stored.

The logical storage space refers to the storage space mapped to the outside of the physical storage space, which is controlled by the processor. The processor can manage the physical storage space by managing the logical storage space.

8) The storage area refers to the basic unit for performing GC operations in the storage space, that is, the storage block.

9) The invalid ratio refers to the ratio of invalid data in the storage area to the storage space of the storage area.

Since the storage space is divided into physical storage space and logical storage space, for the convenience of distinction, in the embodiment of the present application, the storage blocks in the physical storage space may be called physical blocks, and the storage blocks in the logical storage space may be called logical blocks .

In the description of the embodiments of the present application, "and/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which may mean: A exists alone, A and B exist simultaneously, and There are three cases of B. The character "/" generally indicates that the contextual objects are an "or" relationship. The at least one involved in this application refers to one or more; a plurality refers to two or more than two. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or imply order. Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

Usually, when the memory and the memory management device execute the GC operation, the valid data in the storage block corresponding to the GC operation will be moved to other storage blocks. In the following, description will be made by taking the storage as an SSD and the storage management device as a DSS as an example. When an SSD performs a GC operation, it moves the valid data in the physical storage area corresponding to the GC operation to other physical storage areas. When the GC operation moves more valid data, the WAF of the SSD is larger, and the efficiency of the SSD to perform GC operations is higher. If the value is low, the write performance presented by the SSD is poor; and, when the DSS also performs GC operations, the WAF value of the DSS itself will reduce the write performance presented by the SSD to the upper-layer application. Obviously, when the GC functions of the memory and the processor are superimposed, the performance of the memory may be affected.

In order to improve the efficiency of the GC operation performed by the memory controller and ensure the write performance of the memory, an embodiment of the present application provides a garbage collection method, which is applied to a memory management device and a memory, and the memory is capable of performing GC operations and IO operations. In this method, the processor in the memory management device and the first device in the memory can transmit GC information to the second device through an information management interface, wherein the GC information is used to indicate the storage area where the first device performs GC operations; the second The second device determines the storage area for the next GC operation according to the received GC information, thereby reducing the amount of invalid data transfer when the memory controller performs GC operations, thereby improving the efficiency of the memory controller to perform GC operations, and finally ensuring that the memory performance.

Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a possible storage system to which the solution provided by the embodiment of the present application is applicable. As shown in Figure 1, the system includes at least a memory, a processor and an information management interface.

Wherein, the memory includes a memory controller and a storage unit, the memory controller is used to control the memory, and the storage unit is used to provide a physical storage space of the memory. Optionally, the storage may be SSD or other storage devices.

This application does not limit the deployment form of the storage system. In an implementation manner, the storage system may be an inseparable storage system. In this case, the processor and the memory are located in the same electronic device, and the entire storage system is located in the electronic device. In another embodiment, the storage system may also be a detachable storage system, for example, DSS. In this case, the processor may be a host, and the storage may be an SSD, that is, the processor and the storage may be located in different devices.

In this storage system, the processor and the memory can communicate through the information management interface and transmit GC information. The processor can send GC information to the memory through the information management interface to perform some control on the memory. The memory can also pass information The management interface responds to GC messages from the processor.

In one embodiment, the memory controller in the memory may further include an information parsing module, an information management interface and an FTL module, as shown in FIG. 1 . Wherein, the FTL module may further include an address conversion module and a GC module. The information management interface can be used to transfer GC information. The information analysis module can be used to analyze GC information, and can also be used to send the analysis result to the address translation module in the FTL module; the address translation module can be used to perform address translation on LBA and PBA. The GC module is used to determine the target physical storage area for performing GC operation next time according to the received GC information, and perform GC operation on the target physical storage area.

In the memory, the storage unit is the physical carrier for the final storage of data. Exemplarily, the storage unit may be non-volatile medium particles such as Flash, and the Flash includes many blocks.

In an implementation manner, the processor may further include a GC module. Wherein, the GC module can be used to determine the logical storage area to perform GC operation next time, perform GC operation on the logical storage area, and generate GC information for indicating the logical storage area to perform GC operation.

In one embodiment, the logical storage space controlled by the processor is obtained by externally mapping the physical storage space controlled by the memory controller. The processor controls the physical storage space by controlling the logical storage space. Wherein, after the memory controller receives the GC information through the information management interface, the LBA of the logical storage area is determined through the information parsing module. The memory controller converts the LBA into the PBA through the address translation table in the address translation module. Wherein, the address translation table is used to represent the mapping relationship between the LBA in the logical storage space and the PBA in the physical storage space.

In one embodiment, the processor determines the first logical storage area that needs to perform the first GC operation through the GC module, and obtains the first GC information; the processor sends the first GC information to the memory controller through the information management interface.

After the memory controller receives the first GC information through the information management interface, it can analyze the first GC information through the information analysis module to obtain the first physical storage area. Then, the memory controller determines the first target physical storage area where the memory controller performs the second GC operation next time according to the first physical storage area through the GC module.

In an implementation manner, the information management interface may exist in a logical form or in a physical form. For example, the information management interface may be a transmission line between the processor and the memory, connecting the memory and the processor so that the memory and the processor can communicate through the information management interface.

FIG. 2 is a schematic structural diagram of another possible storage system to which the solution provided by the embodiment of the present application is applicable. As shown in FIG. 2 , the system at least includes a memory, a processor and an information management interface. The memory is the same as that in FIG. 1 , and will not be repeated here.

As shown in FIG. 2, the memory controller may include an FTL module. Wherein, the FTL module may further include an address translation module and a GC module; the address translation module may be used to perform address translation on the LBA and the PBA. The GC module is used to determine the physical storage area to perform GC operation next time, perform GC operation on the physical storage area, and generate GC information for indicating the physical storage area to perform GC operation.

As shown in FIG. 2, the processor may include an information parsing module and a GC module. Wherein, the information analysis module can be used to analyze the received GC information, and can also be used to send the analysis result to the GC module. The GC module can be used to determine the logical storage area for performing GC operation next time according to the received parsing result, and perform GC operation on the logical storage area.

In one implementation manner, the memory controller determines at least one third physical storage area that needs to perform the third GC operation in the physical storage space through the GC module. The memory controller maps at least one third physical storage area to at least one second logical storage area in the logical storage space through the address translation module. The memory controller obtains second GC information indicating at least one second logical storage area based on the GC module, and sends the second GC information to the processor through the information management interface.

The processor receives the second GC information through the information management interface, and analyzes the second GC information through the information analysis module to obtain at least one second logical storage area. The processor determines the first target logical storage area for the processor to perform the fourth GC operation next time according to the at least one second logical storage area through the GC module.

FIG. 3 is a schematic structural diagram of another possible storage system to which the solution provided by the embodiment of the present application is applicable. As shown in FIG. 3 , the system at least includes a memory, a processor and an information management interface. The memory is the same as the memory shown in FIG. 1 , and the processor is the same as the processor shown in FIG. 2 , which will not be repeated here.

In an implementation manner, the processor may generate the first GC information through the GC module, and send the first GC information to the memory controller through the information management interface. The memory controller parses the first GC information through the information parsing module to obtain the first logical storage area. The memory controller determines the first target physical storage area according to the first logical storage area through the GC module.

In another implementation manner, the memory controller may generate the second GC information through the GC module, and send the second GC information to the processor through the information management interface. The processor parses the second GC information through the information parsing module to obtain the second logical storage area. The processor determines the first target logical storage area according to the second logical storage area through the GC module.

It should be noted that the above-mentioned storage systems shown in FIGS. 1-3 are only exemplary descriptions of storage systems applicable to the solution of this application, and do not limit the system architecture applicable to the solution of this application. Other devices or modules may also be added to the above system architecture, or some devices or modules may be reduced or modified.

The solution provided by the present application will be introduced below in combination with specific embodiments.

Example 1

FIG. 4 is a schematic diagram of a garbage collection method provided by an embodiment of the present application, which can be applied to the processor in the storage system as shown in FIG. 1 , and can also be applied to the processor in the storage system as shown in FIG. 3 . As shown in Figure 4, the method includes:

S401: In a logical storage space, determine a first logical storage area that needs to perform a first GC operation.

It should be noted that the logical storage space is obtained by mapping the physical storage space managed by the memory.

In the logical storage space, the processor determines the first logical storage area that needs to perform the first GC operation according to the logical garbage collection strategy. Wherein, the logical garbage collection policy may be pre-configured.

In the logical storage space, the processor determines a logical storage area satisfying the logical garbage collection policy as the first logical storage area. Wherein, the logical garbage collection strategy may be that the invalid data or garbage data in the logical storage area reaches a certain percentage, or other garbage collection conditions, which are not limited in this application.

Further, in the logical storage space, the number of first logical storage areas that need to perform the first GC operation determined by the processor may be multiple, or may be one.

S402: Send the first GC information to the memory controller through the information management interface.

It should be noted that the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation, that is, before executing S402, the processor has not performed the first GC operation on the first logical storage area. GC operation.

After the processor determines at least one first logical storage area that needs to perform the first GC operation, select the first logical storage area from the at least one first logical storage area; and according to the description information of the selected first logical storage area , to determine the first GC information.

Wherein, the first GC information includes, but is not limited to: description information of valid data in the first logical storage area, and an execution sequence number of the first logical storage area. Moreover, the format of the first GC information is a format supported by the information management interface.

Wherein, the description information of the valid data is used to describe the LBA and the LBA length of the valid data. For example, the description information of valid data may be {start address, length}, such as: {0x10000, 32KB}, {(0x40000000, 256KB), (0x40100000, 256KB)}.

After obtaining the first GC information, the processor may send the first GC information to the memory controller through the information management interface.

After the memory controller receives the first GC information through the information management interface, according to the first GC information, determine the first target physical storage area where the memory controller performs the second GC operation.

In some embodiments, a garbage collection method provided in the embodiment of the present application can be applied to the memory controller in the storage system as shown in FIG. 1 , and can also be applied to the memory controller in the storage system as shown in FIG. 3 controller. As shown in Figure 5, the method includes:

S501: Receive first GC information sent by a processor through an information management interface.

It should be noted that the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation on the logical storage space.

S502: Map the first logical storage area to at least one first physical storage area in the physical storage space.

After receiving the first GC information, the memory controller analyzes the first GC information; and determines the first logical storage area according to the analysis result. Wherein, the parsing result includes, but is not limited to: the LBA of the first valid data located in the first logical storage area (hereinafter may be referred to as the first LBA for short), and the LBA length.

Optionally, after the memory controller determines the first LBA, it may map the first LBA to the first PBA according to the mapping relationship between the LBA and the PBA, and finally use the physical storage area corresponding to the first PBA as the first LBA. A physical storage area.

S503: In the physical storage space, determine multiple second physical storage areas that need to perform the second GC operation.

The memory controller may determine multiple second physical storage areas in the physical storage space according to a preconfigured physical garbage collection policy. Wherein, the physical garbage collection strategy may be that the invalid data or garbage data stored in the physical storage area reaches a certain percentage, or other garbage collection conditions, which are not limited in this application.

After the memory controller determines the multiple second physical storage areas that need to perform the second GC operation, it may add the multiple second physical storage areas to the management queue. Wherein, the second physical storage area in the management queue can be sorted according to the size of the invalid ratio.

For example, as shown in FIG. 6 , when adding the second physical storage area to the management queue, the memory controller may sort the multiple second physical storage areas according to the size of the invalid ratio from large to small. For another example, when the memory controller sorts the multiple second physical storage areas in the management queue, it may sort the invalid ratios from small to large.

It should be noted that the embodiments of the present application include but are not limited to determining the second physical storage area in the above manner, and the memory controller may also determine in other manners, which will not be listed here.

Regardless of the GC operation of the processor or the GC operation of the memory controller, the data in the physical storage space is finally processed. Therefore, if there is an intersection between the data processed by the first GC operation and the data processed by the second GC operation, the first GC operation to be executed by the processor may have an impact on the second GC operation to be executed by the memory controller, That is, performance degradation of the memory may occur due to superposition of GC functions of the memory controller and the processor.

In order to reduce the impact of the above situation on the performance of the memory, in the embodiment of the present application, after the memory controller determines at least one first physical storage area through S502 and determines multiple second physical storage areas through S503, it also It may be determined whether there is an intersection between the plurality of second physical storage areas and at least one first physical storage area; if there is an intersection, step S504 is performed.

S504: When there is an intersection between the at least one first physical storage area and the multiple second physical storage areas, determine at least one second physical storage area to be selected from the multiple second physical storage areas.

It should be noted that there is no intersection between at least one second physical storage area to be selected and at least one first physical storage area.

Optionally, the memory controller may, but is not limited to, determine the at least one second physical storage area to be selected through the following steps.

The memory controller may select from the multiple second physical storage areas that the impact factor is less than the set threshold according to the first valid data located in the first logical storage area and the second valid data stored in the multiple second physical storage areas At least one second physical storage area to be selected.

It should be noted that the impact factor of each second physical storage area is used to represent the intersection of the first valid data and the second valid data in the second physical storage area occupied by the second physical storage area storage.

The memory controller selects a candidate second physical storage area whose impact factor is smaller than a set threshold among the plurality of second physical storage areas. Wherein, the second physical storage area whose impact factor is less than the set threshold means that the intersection of the second physical storage area and the valid data stored in the first logical storage area is not high, therefore, the valid data in the second physical storage area is affected by The first GC operation has less impact.

Optionally, when the memory controller determines the second physical storage area to be selected, the following operations may be performed for each second physical storage area: the memory controller determines the first PBA of the first valid data, and the The intersection of the second PBAs of the second valid data in the second physical storage area, and use the storage space occupied by the valid data corresponding to the intersection in the second physical storage area as an influencing factor of the second physical storage area.

S505: Determine a first target physical storage area where the memory controller performs the second GC operation in the at least one candidate second physical storage area.

The memory controller determines a first target physical storage area in at least one second physical storage area to be selected. Among them, the second physical storage area to be selected whose impact factor is less than the set threshold indicates that the intersection of the second physical storage area to be selected and the valid data stored in the first logical storage area is not high, therefore, the second physical storage area to be selected Valid data in a region is less affected by the first GC operation. Therefore, when the processor executes the first GC operation on the first logical storage area, the invalidated valid data in the candidate second physical storage area whose impact factor is smaller than the set threshold is less, and the memory controller will use the GC operation on the candidate second physical storage area. The impact on the execution efficiency of the second GC operation performed by the second physical storage area is small. However, the impact factor of the second physical storage area is greater than or equal to the set threshold, which means that the intersection of the second physical storage area and the valid data stored in the first logical storage area is relatively high, and when the processor compares the first logical storage area When the first GC operation is performed in the second physical storage area, there are more valid data invalidated in the second physical storage area, which greatly affects the execution efficiency of the second GC operation performed by the memory controller in the second physical storage area. The memory controller selects the second physical storage area whose impact factor is less than the set threshold as the first target physical storage area, so that the second physical storage area whose impact factor is greater than or equal to the set threshold is executed later, so that the processor can When performing the first GC operation on the first logical storage area, reduce the effective data in the second physical storage area whose impact factor is greater than or equal to the set threshold, so as to reduce the memory controller's subsequent impact on the impact factor greater than or equal to the set threshold The workload of moving valid data when performing the second GC operation in the second physical storage area. To sum up, it can be seen that determining the first target physical storage area from the candidate second physical storage areas whose impact factor is smaller than the set threshold can reduce the workload of invalidly moving valid data when the memory controller subsequently executes the second GC operation.

The memory controller selects at least one candidate second physical storage zone whose impact factor is smaller than a set threshold among the plurality of second physical storage zones, and determines each candidate second physical storage zone in the at least one candidate second physical storage zone. Invalid scale for bucket. Then, the memory controller may, but not limited to, select the first target physical storage area among the plurality of second physical storage areas to be selected according to the invalid ratio of the plurality of second physical storage areas to be selected in the following manner.

Mode 1: The memory controller may select the second physical storage area to be selected with the largest invalidation ratio among multiple second physical storage areas to be selected as the first target physical storage area.

For example, the invalid proportions of physical storage area 8 and physical storage area 305 are 78% and 70% respectively, and when the impact factors of physical storage area 8 and physical storage area 305 are less than the set threshold, the storage will invalidate the physical storage area with a proportion of 78%. Area 8 serves as the first target physical storage area.

When the memory controller uses method 1 to determine the first target physical storage area, since it selects the first target physical storage area from multiple candidate second physical storage areas that are less affected by the first GC operation, it can further reduce memory consumption. When the controller performs the subsequent second GC operation, it invalidates the workload of moving valid data; and, since the memory controller selects the candidate second physical storage area with the largest invalid ratio as the first target physical storage area, it can be guaranteed that the memory controller is The efficiency with which the second GC operation is performed on the first target physical storage area. To sum up, the memory controller uses method 1 to determine the first target physical storage area, which can reduce the memory controller’s subsequent execution of the second GC operation while ensuring the efficiency of the memory controller’s execution of the second GC operation on the first target physical storage area. The workload of effectively moving valid data during GC operations.

Way 2: The memory controller may select the second physical storage area to be selected with the second largest invalidation ratio among multiple second physical storage areas to be selected as the first target physical storage area.

For example, the invalid ratios of physical block 8, physical block 80, and physical block 305 are 78%, 75%, and 70% respectively, and the memory controller may use physical block 80 with an invalid ratio of 75% as the first target physical storage area.

When the memory controller uses method 2 to determine the first target physical storage area, since the first target physical storage area is selected from multiple candidate second physical storage areas that are less affected by the first GC operation, the memory can be reduced. The controller invalidates the workload of moving valid data when performing subsequent GC operations; and, since the memory controller selects the candidate second physical storage area with the second largest invalid ratio as the first target physical storage area, it can ensure that the memory Efficiency with which the controller performs the second GC operation on the first target physical storage area. To sum up, the memory controller adopts method 2 to determine the first target physical storage area, which can reduce the workload of the memory controller to invalidly move valid data when the memory controller subsequently executes the second GC operation, and at the same time ensure that the memory controller is as good as possible. The efficiency with which the second GC operation is performed on the first target physical storage area.

Mode 3: The memory controller may select a candidate second physical storage area with a relatively large invalidation ratio and a relatively small impact factor among multiple candidate second physical storage areas as the first target physical storage area.

For example, the threshold is set at 5%; the invalid ratios of physical block 8, physical block 80, and physical block 305 are 78%, 75%, and 70% respectively, and the impact factors of physical block 8, physical block 80, and physical block 305 are respectively When 4%, 1% and 3%, the memory controller may use the physical block 80 with an invalid ratio of 75% as the first target physical storage area.

When the memory controller uses method 3 to determine the first target physical storage area, since it is selected from multiple candidate second physical storage areas that are less affected by the first GC operation, the invalid ratio is relatively large and the impact factor is relatively small. The small second physical storage area to be selected is the first target physical storage area, which can further reduce the memory control workload as much as possible on the basis of reducing the workload of the memory controller to move valid data ineffectively when executing the subsequent second GC operation. While reducing the workload of effectively moving valid data when the memory controller performs the second GC operation on the first target physical storage area, the efficiency of the second GC operation performed by the memory controller on the first target physical storage area is ensured.

In addition, when the memory controller determines that the invalid ratios of the plurality of second physical storage areas to be selected are all relatively small, the memory controller may also, but not limited to The first target physical storage area is selected from the second physical storage area. Wherein, the remaining second physical storage area is a second physical storage area whose impact factor is greater than or equal to a set threshold.

Mode 4: The memory controller selects a second physical storage area with a larger invalidation ratio and a smaller impact factor among the remaining second physical storage areas as the first target physical storage area.

For example, the setting threshold is 5%; the second physical storage area 20, the second physical storage area 30, the second physical storage area 40, the second physical storage area 83, the second physical storage area 8, the second physical storage area 305 and the invalid proportions of the second physical storage area 80 are 61%, 62%, 61%, 63%, 80%, 76% and 72% respectively, the second physical storage area 20, the second physical storage area 30, the second physical storage area The influence factors of storage area 40, second physical storage area 83, second physical storage area 8, second physical storage area 80 and second physical storage area 305 are 2%, 4%, 3%, 2%, 9% respectively , 8%, 11%, wherein, the second physical storage area 20, the second physical storage area 30, the second physical storage area 40, the second physical storage area 83 are the second physical storage areas to be selected; when multiple When the invalid proportions of the second physical storage areas are all less than 65%, the memory controller can select the second physical storage area 305 with an invalid proportion of 76% and an impact factor of 8% as the first target physical storage area; the memory controller can also The second physical storage area 8 with an invalid ratio of 80% and an impact factor of 9% is selected as the first target physical storage area.

When the invalid ratios of multiple second physical storage areas to be selected are small, even if the memory controller selects the first target physical storage area from multiple second physical storage areas to be selected, it can properly reduce the subsequent When the second GC operation is performed, the workload of moving valid data is invalid, but because the invalid ratio of the second physical storage area to be selected is relatively small, the memory controller will reduce the workload of moving valid data by a little bit. When the first target physical storage area performs the second GC operation, the workload of valid data that needs to be moved increases, resulting in low efficiency of the memory controller performing the second GC operation on the first target physical storage area. When the memory controller uses method 4 to determine the first target physical storage area, it will select the remaining second physical storage area with a relatively large invalidation ratio and a relatively small impact factor as the first target physical storage area, thereby ensuring that the memory controller On the basis of the efficiency of performing the second GC operation on the first target physical storage area, the workload of the memory controller for invalidly moving valid data when performing subsequent GC operations is reduced as much as possible.

In some other embodiments, the memory controller may also determine the first target in the plurality of second physical storage areas according to the impact factor of each second physical storage area, but not limited to the following scheme: Physical storage area.

When the memory controller determines that the number of candidate second physical storage areas whose impact factor is smaller than the set threshold is 0 among the plurality of second physical storage areas, the memory controller may use the second physical storage area with the smallest impact factor as the second physical storage area. A target physical storage area, the second physical storage area with the largest invalid ratio can also be used as the first target physical storage area, or the second physical storage area with a larger invalid ratio and a smaller impact factor can be used as the first target physical storage area district.

For example, the threshold is set at 5%; the invalid ratios of physical block 8, physical block 305, and physical block 211 are 80%, 76%, and 70% respectively, and the impact factors of physical block 8, physical block 305, and physical block 211 are respectively When 9%, 8%, and 11% are all greater than the set threshold, the memory controller may use the physical block 305 with the smallest impact factor as the first target physical storage area, and may also use the physical block 8 with the largest invalid ratio as the first target. Physical storage area.

When the memory controller uses the above scheme to determine the first target physical storage area, using the second physical storage area with the smallest impact factor as the first target physical storage area can reduce the work of invalidly moving valid data when the memory controller subsequently executes the second GC operation amount; using the second physical storage area with the largest invalid ratio as the first target physical storage area can ensure the execution efficiency of the second GC operation performed by the memory controller on the first target physical storage area; if the invalid ratio is large, the impact factor is small The second physical storage area as the first target physical storage area can reduce the subsequent execution of the second GC operation by the memory controller as much as possible while ensuring the execution efficiency of the second GC operation performed by the memory controller on the first target physical storage area. The workload of effectively moving valid data is invalid.

It should be noted that the embodiments of the present application include but are not limited to determining the first target physical storage area in the above manner, and the memory controller may also determine in other manners, which will not be listed here.

In the foregoing manners, when the memory controller adds the determined multiple second physical storage areas to the management queue, it may sort the multiple second physical storage areas according to their The size of the influence factor of the physical storage area is sorted. Moreover, after the memory controller determines the first target physical storage area, when performing the second GC operation on the first target physical storage area, the first target physical storage area needs to be deleted from the management queue.

For example, as shown in FIG. 6, the physical block 8, the physical block 305, and the physical block 211 in the management queue 1 determine the second physical storage area for the memory controller, wherein the physical block 8, the physical block 305, and the physical block 211 The invalid ratios are 80%, 76% and 70%; wherein, the second physical storage area in the management queue 1 is sorted according to the size of the invalid ratio from large to small. Wherein, the second physical storage area at the first position is the first target physical storage area for the memory controller to perform the second GC operation next time.

After receiving the first GC information sent by the processor, the memory controller determines that the first physical storage area obtained by mapping the first logical storage area in the physical storage space is physical block 8; the memory controller determines that a part of the physical block 8 or All valid data will be moved to other physical storage areas by the processor. After the memory controller determines that the influence factor of the physical block 8 is 10% greater than the set threshold, it adjusts the sequence of the physical block 8 , the physical block 305 , and the physical block 211 in the management queue 1 . The memory controller may move the position of the physical block 305 in the management queue 1 to the first position, and obtain the management queue 2 as the first target physical storage area. The memory controller performs the second GC operation on the physical block 305 of the first target physical storage area, and deletes the physical block 305 from the management queue 2; after the memory controller completes the second GC operation on the physical block 305, the processor also The first GC operation on the first logical storage area previously sent to the memory controller is completed, and the first valid data in the first logical storage area is moved to other storage areas. At this time, the invalid ratio of physical block 8 is changed from 80 % changed to 90% to get admin queue 3.

It can be seen from the change of the invalid ratio of the physical block 8 that by adopting the garbage collection scheme in the present application, the memory controller can reduce the workload of performing the second GC operation to move valid data. In this embodiment, the physical block 8 reduces the workload of moving valid data by about 10%. Compared with the original 20% workload of moving valid data, the memory controller performs the second GC operation on the physical block 8. Efficiency increased by 50%.

In one embodiment, the processor performs the first GC operation after sending the first GC information to the memory controller.

Optionally, the processor may, but is not limited to, execute the first GC operation through the following steps.

a1: when the processor executes the first GC operation on the first logical storage area, it moves the first valid data located in the first logical storage area to other logical storage areas. Wherein, the other logical storage area is a logical storage area that does not need to perform the first GC operation.

For example, as shown in Figure 7, the logical storage space includes

logical blocks

1 and 2; wherein, valid data is stored in the logical storage interval 1 and the logical storage interval 3 in the logical block 1, and the logical storage interval 2 and the logical storage interval 4 are Free area: valid data is stored in the logical storage area 3 in the logical block 2, and the logical storage area 1, the logical storage area 2 and the logical storage area 4 are free areas. Wherein, logical block 1 is the first logical storage area that needs to perform the first GC operation, and logical block 2 is the logical storage area that does not need to perform the first GC operation.

As shown in Figure 8, the processor performs the first GC operation on logical block 1, and can move the valid data stored in logical storage interval 1 and logical storage interval 3 in logical block 1 to logical storage interval 1 in logical block 2 and logical bucket 4.

a2: The processor may write the first valid data moved to other logical storage areas into other physical storage areas in the memory corresponding to the other logical storage areas through the I/O interface. Wherein, the processor may write the first valid data into other physical storage areas through remote updating.

Optionally, in a2, when the processor moves the first valid data to other logical storage areas, it can send the rewrite first valid data to the memory controller through the I/O interface between the processor and the memory. IO request, so that the memory controller can rewrite the first valid data in other physical storage areas according to the IO request through the I/O interface. Optionally, according to the received IO request, the memory controller may, but not limited to, rewrite the first valid data in other physical storage areas through the following steps.

b1: The memory controller determines the initial LBA and updated LBA of the first valid data according to the IO request; wherein, the initial LBA indicates the LBA before the first valid data is moved, and the updated LBA indicates the LBA after the first valid data is moved.

b2: the memory controller maps the initial LBA to the initial PBA, and marks the first valid data stored in the storage area corresponding to the initial PBA as invalid data.

Optionally, when the processor rewrites the initial valid data to the storage unit in the memory, the memory marks the originally stored first valid data as invalid data, reducing the invalidity of the memory controller when performing the second space operation. data workload.

b3: the memory controller maps the updated LBA to the updated PBA, and rewrites the first valid data contained in the IO request to the storage space in other physical storage areas corresponding to the updated PBA.

For example, as shown in Figure 7, the logical storage space includes logical block 1 and logical block 2; wherein, logical storage interval 1 and logical storage interval 3 in logical block 1 store valid data, logical storage interval 2 and logical storage interval 4 is a free area; valid data is stored in logical storage interval 3 in logical block 2, logical storage interval 1, logical storage interval 2 and logical storage interval 4 are free areas; logical storage interval 1 in logical block 1 in logical storage space The logical storage interval 3 and the physical storage interval 1 and the physical storage interval 2 in the physical block 1 in the physical storage space respectively have a one-to-one mapping relationship.

Further, as shown in FIG. 8 , the processor sends an I/O request to the memory controller through the I/O interface, and rewrites the valid data moved to the logic block 2 into the storage unit. Specifically, the processor sends an IO request for rewriting valid data to the memory controller through the IO interface. Based on the IO request, the memory controller determines that the storage area where the valid data is rewritten is the physical storage interval 2 and the physical storage interval 5 in the physical block 2, and the original storage area of the valid data in the memory is physically stored in the physical block 1 Interval 1 and Physical Storage Interval 2. The memory controller marks the valid data stored in physical storage interval 1 and physical storage interval 2 in physical block 1 as invalid data, and rewrites valid data in physical storage interval 2 and physical storage interval 5 in physical block 2.

In another possible manner, the processor may also write the first valid data into other physical storage areas by means of append writing. Specifically, the processor writes the first valid data to the end of the storage space of the other physical storage area, and marks the first valid data originally stored in the memory as invalid data.

In another embodiment, the processor executes the first GC operation on the first logical storage area, deletes the first valid data in the first logical storage area, and deletes the first valid data stored in the memory through the I/O interface. Data marked as invalid data.

In one embodiment, after the processor finishes performing the first GC operation on the first logical storage area, the processor may send the first GC operation completion information to the memory controller through the information management interface, or may not send the first GC operation completion information to the memory controller Send the completion message of the first GC operation. Wherein, the first GC operation completion information is used to indicate that the processor has completed the first GC operation on the first logical storage area.

Optionally, after receiving the first GC operation completion information sent by the processor through the information management interface, the memory controller sends a first response message to the processor, notifying the processor that the first GC operation completion information has been received. Then, the memory controller determines the invalid ratio of each second physical storage area in the current management queue; the memory controller may use the second physical storage area with the largest invalid ratio as the second target for the memory controller to perform the second GC operation next time The physical storage area may also use the second physical storage area with the largest invalid ratio in the current management queue as the second target physical storage area for the memory controller to perform the second GC operation next time.

In this embodiment of the present application, since the memory controller determines the first target physical storage area for the memory controller to perform the second GC operation on the basis of the first logical storage area, the processor executes the first GC on the first logical storage area. During operation, the valid data in the first logical storage area will be moved correspondingly, thereby reducing the workload of invalidly moving valid data when the memory controller performs the second GC operation, improving the efficiency of the memory controller performing the second GC operation, and then Guaranteed memory performance.

Based on the garbage collection scheme shown in FIG. 4 and FIG. 5 , the following takes the memory in the storage system as an SSD and the processor as a host (host) as an example to introduce the scheme in detail. FIG. 9 is a schematic diagram of an interaction flow of a garbage collection method based on SSD and host provided by an embodiment of the present application. The specific flow of the method will be described below with reference to FIG. 9 .

S901: In the logical storage space, the host determines the first logical storage area that needs to perform the first GC operation.

Specifically, the host can determine the first logical storage area that needs to perform the first GC operation according to the set logical garbage collection policy.

For example, according to the logical garbage collection policy, the host takes the logical storage area with an invalid ratio greater than 50% as the first logical storage area that needs to perform the first GC operation.

S902: The host sends the first GC information to the SSD through the information management interface.

The host converts the format of the description information of the first logical storage area into a format satisfying the information management interface, and obtains the first GC information. The host sends the first GC information to the SSD through the information management interface.

S903: After receiving the first GC information through the information management interface, the SSD parses the first GC information to obtain a first logical storage area.

In a possible manner, after receiving the first GC information, the SSD sends a first response message to the host through the information management interface, to inform the host that the first GC information has been received.

Specifically, the SSD parses the first GC information to obtain the first logical address of the first valid data located in the first logical storage area.

S904: The SSD maps the first logical storage area to at least one first physical storage area in the physical storage space.

Specifically, the SSD maps the first logical address of the first valid data to the first physical address, and uses the physical storage area corresponding to the first physical address as the first physical storage area.

S905: In the physical storage space, the SSD determines multiple second physical storage areas that need to perform the second GC operation, and adds the multiple second physical storage areas to the management queue.

It should be noted that S904 and S905 can be executed concurrently, and there is no execution sequence dependency between S904 and S905.

S906: The SSD determines that there is an intersection between at least one first physical storage area and multiple second physical storage areas.

S907: The SSD determines an impact factor of the first GC operation on each second physical storage area according to the first valid data located in the first logical storage area and the second valid data stored in the plurality of second physical storage areas.

It should be noted that the impact factor is used to characterize the storage space occupied by the intersection of the first valid data and the second valid data in the second physical storage area.

S908: Among the multiple second physical storage areas, the SSD selects multiple second physical storage areas to be selected whose influence factors are smaller than a set threshold.

S909: The SSD determines an invalid ratio of each second physical storage area to be selected in the plurality of second physical storage areas to be selected.

Wherein, the invalid ratio of any second physical storage area to be selected is the ratio of invalid data in the second physical storage area to be selected to the storage space of the second physical storage area to be selected.

S910: Among the multiple second physical storage areas to be selected, the SSD selects the second physical storage area to be selected with the largest invalid ratio as the first target physical storage area.

S911: The SSD performs a second GC operation on the first target physical storage area, and deletes the first target physical storage area from the management queue.

S912: the host performs a first GC operation on the first logical storage area.

S913: the host sends the first GC operation completion information to the SSD through the information management interface.

Wherein, the first GC operation completion information is used to indicate that the SSD has completed the first GC operation on the first logical storage area.

S914: After receiving the completion information of the first GC operation through the information management interface, the SSD determines the invalid ratio of each second physical storage area in the current management queue.

In a possible manner, after receiving the completion information of the first GC operation, the SSD sends a second response message to the host through the information management interface to inform the host that the information of the completion of the first GC operation has been received.

S915: The SSD selects the second physical storage area with the largest invalid ratio as the second target physical storage area for the SSD to perform the second GC operation next time.

In the embodiment shown in FIG. 9, since the SSD receives the first GC information sent by the host through the information management interface, after determining the first logical storage area where the host is about to perform the first GC operation according to the first GC information, based on the first The intersection of the first valid data stored in a logical storage area and the second valid data stored in the second physical storage area determines the influence of the second physical storage area. Moreover, since the SSD selects the first target physical storage area from the second physical storage area based on the impact factor, when the host performs the first GC operation to move valid data in the first logical storage area, the second physical storage area will The valid data in the storage area that is the same as the valid data in the first logical storage area is invalidated, thereby reducing the workload of invalidly moving valid data when the SSD subsequently executes the second GC operation, and improving the efficiency of the SSD's subsequent execution of the second GC operation, Further, the performance of the SSD is guaranteed; at the same time, since the SSD selects the second physical storage area whose impact factor is less than the set threshold and has the largest invalid ratio as the first target physical storage area, the SSD performs the second GC on the first target physical storage area. During operation, while reducing the workload of invalidly moving valid data when the SSD performs the second GC operation as much as possible, the execution efficiency of the SSD performing the second GC operation is guaranteed.

Example 2

A garbage collection method provided in the embodiment of the present application can be applied to the storage system shown in Figure 2, and can also be applied to the storage system shown in Figure 3, the storage system includes: memory and processor, and information management interface. The method includes:

The memory controller sends the second GC information to the processor, and the processor determines the first target logical storage area where the processor performs the fourth GC operation according to the second GC information.

Optionally, the memory controller may, but not limited to, send the second GC information to the processor through the following steps.

c1: the memory controller determines at least one third physical storage area that needs to perform the third GC operation in the physical storage space.

Optionally, the memory is in the physical storage space, and at least one third physical storage area that needs to perform the third GC operation is determined according to the physical garbage collection policy. Wherein, the physical garbage collection policy may be pre-configured in the memory.

The memory controller determines a physical storage area that satisfies the physical garbage collection strategy in the physical storage space as the third physical storage area. Wherein, the physical garbage collection strategy may be that the invalid data or garbage data stored in the physical storage area reaches a certain percentage, or other garbage collection conditions, which are not limited in this application.

In implementation, after determining the multiple third physical storage areas, the memory controller adds the multiple third physical storage areas to the management queue.

c2: mapping at least one third physical storage area to at least one second logical storage area in the logical storage space.

The memory controller maps the PBA of the valid data stored in the third physical storage area to the LBA of the logical storage space, and determines the valid data stored in the third physical storage area according to the PBA length of the valid data stored in the third physical storage area The LBA length in the logical storage space obtains the description information of valid data in the second logical storage area corresponding to the third physical storage area in the logical storage space.

c3: the memory controller sends the second GC information to the processor through the information management interface.

It should be noted that the second GC information is used to indicate at least one second logical storage area where the memory controller needs to perform the third GC operation, that is, before performing S902, the memory has not yet performed the third GC operation.

In an implementation, the memory controller obtains the second GC information based on the description information of the selected at least one second logical storage area.

Wherein, the format of the second GC information is a format supported by the information management interface. The second GC information includes, but is not limited to: description information of valid data located in the second logical storage area, and an execution sequence number of the third physical storage area corresponding to the second logical storage area.

Wherein, the description information of the valid data is used to describe the LBA and LBA length of the valid data in the logical storage space. For example, the description information of valid data may be {start address, length}, such as: {0x10000, 32KB}, {(0x40000000, 256KB), (0x40100000, 256KB)}.

Further, after obtaining the second GC information, the memory controller may send the second GC information to the processor through the information management interface.

In one embodiment, after the memory controller sends the second GC information to the processor through the information management interface, it determines the invalid ratio of each third physical storage area in the plurality of third physical storage areas. The memory controller takes the third physical storage area with the largest invalid ratio as the second target physical storage area for the memory controller to perform the third GC operation next time. The memory performs a third GC operation on the second target physical storage area, and deletes the second target physical storage area from the management queue.

Optionally, after the memory controller sends the second GC information to the processor, the processor may, but not limited to, determine the first target logical storage area through the following steps according to the second GC information.

d1: The processor receives the second GC information from the memory controller through the information management interface.

It should be noted that, the second GC information is used to indicate that the memory controller needs to perform the third GC operation on the physical storage space to map at least one second logic in the logical storage space to the third physical storage area storage area.

After receiving the second GC information, the processor analyzes the second GC information, and determines the second logical storage area according to the analysis result. Wherein, the parsing result includes, but is not limited to: the PBA of the third valid data located in the second logical storage area (hereinafter may be referred to as the third PBA for short), and the length of the PBA.

d2: In the logical storage space, the processor determines a plurality of third logical storage areas that need to perform the fourth GC operation.

In an implementation manner, the processor may determine a plurality of third logical storage areas that need to perform the fourth GC operation in the logical storage space according to a preconfigured logical garbage collection policy. Wherein, the logical garbage collection strategy may be that the invalid data or garbage data in the logical storage area reaches a certain percentage, or other garbage collection conditions, which are not limited in this application.

In an implementation, after the processor determines the multiple third logical storage areas that need to perform the fourth GC operation, it may add the multiple third logical storage areas to the management queue. Wherein, the third logical storage area in the management queue can be sorted according to the size of the invalid ratio.

It should be noted that the embodiment of the present application includes but is not limited to determining the third logical storage area in the above manner, and the processor may also determine in other manners, which will not be listed here.

Regardless of the GC operation of the processor or the GC operation of the memory controller, the data in the physical storage space is finally processed. Therefore, if there is an intersection between the data processed by the third GC operation and the data processed by the fourth GC operation, the fourth GC operation to be executed by the processor may have an impact on the third GC operation to be executed by the memory controller, That is, performance degradation of the memory may occur due to superposition of GC functions of the memory controller and the processor.

In order to reduce the impact of the above situation on the performance of the memory, in the embodiment of the present application, after the processor determines at least one second logical storage area through d1, and determines a plurality of third logical storage areas through d2, it can also Judging whether there is an intersection between at least one first logical storage area and multiple third logical storage areas; if there is an intersection, perform step d3.

d3: When there is an intersection between the at least one second logical storage area and the plurality of third logical storage areas, the processor selects from at least one candidate third logical storage area among the plurality of third logical storage areas , selecting a first target logical storage area where the processor executes the fourth GC operation; wherein, there is an intersection between the at least one candidate third logical storage area and the at least one second logical storage area.

Optionally, the processor determines the first target logical storage area according to at least one third logical storage area to be selected in the following manner.

The processor selects the first target logical storage area with the largest invalid ratio among at least one third logical storage area to be selected.

When the processor determines the first target logical storage area, the third logical storage area to be selected with the largest invalid ratio is directly used as the first target logical storage area for the processor to perform the fourth GC operation next time. When the three physical storage areas perform the third GC operation, the workload of effectively moving valid data is invalidated, while improving the efficiency of the subsequent execution of the third GC operation by the memory controller, and ensuring the execution efficiency of the fourth GC operation by the processor.

As shown in FIG. 10 , a process in which the processor executes the fourth GC operation in this application will be described below with a specific embodiment.

In stage 1, in the logical storage space, the processor determines that the third logical storage area that needs to perform the fourth GC operation is the logical block 16, the logical block 300, and the logical block 119, wherein the logical block 16, the logical block 300, the logical block The invalid ratios of block 119 are 88%, 86% and 72%, respectively. In the physical storage space, the memory controller determines that the third physical storage area that needs to perform the third GC operation is the physical block 410, the physical block 502, and the physical block 95, wherein the physical block 410, the physical block 502, and the physical block 95 are invalid The proportions were 78%, 73% and 68%, respectively. Wherein, the memory controller maps the physical block 502 into a second logical storage area of the logical storage space, and obtains second GC information based on the second logical storage area. The memory controller sends the second GC information to the processor through the information management interface; the processor obtains the second logical storage area as a logical block 300 based on the second GC information, and determines that there is an intersection between the second logical storage area and the third logical storage area .

In stage 2, when the processor determines that the logical block 300 of the second logical storage area is also the third logical storage area, the processor takes the logical block 300 of the second logical storage area as the first target logical storage area, and sets the location of the logical block 300 Move to the first location in the third logical bank of the processor.

In phase 3, the memory controller performs the third GC operation on the physical block 410, and deletes the physical block 410 from the management queue of the memory controller; the processor performs the fourth GC operation on the logical block 300, and removes the logical block 300 Removed from the processor's administrative queue. After the processor completes the fourth GC operation on the logical block 300, the invalid ratio of the physical block 502 in the memory increases from 73% to 77%.

It can be seen from the change of the invalid ratio of the physical block 502 that by adopting the garbage collection solution in the present application, the memory controller can reduce the workload of performing the fourth GC operation to move valid data. In this embodiment, the physical block 502 reduces the workload of valid data that needs to be moved by about 4%. Compared with the original 27% workload of moving valid data, the memory controller performs the fourth GC operation on the physical block 502. Efficiency increased by 15%.

In an implementation, after the processor determines the first target logical storage area, it performs a fourth GC operation on the first target logical storage area. When the processor executes the first target logical storage area, it not only moves the third valid data stored in the first target logical storage area to other logical storage areas, but also rewrites the third valid data in the memory, the processor The process of rewriting the third valid data in the memory is the same as the process of rewriting the first valid data in the memory by the processor in Embodiment 1, and will not be repeated here.

Specifically, the processor rewrites the third valid data in the memory through the information management interface, so that the memory marks the originally stored third valid data as invalid data, thereby reducing the cost of valid data stored in the third physical storage area in the memory. The ratio reduces the workload of moving valid data when the memory controller executes the third GC operation, thereby improving the efficiency of the memory controller executing the third GC operation to ensure the performance of the memory.

Optionally, the processor rewrites the third valid data in the memory by means of append writing or remote updating.

In one embodiment, after the processor executes the fourth GC operation on the first target logical storage area, it may send the fourth GC operation completion information to the memory controller through the information management interface, or may not send the fourth GC operation completion information to the memory controller. Fourth GC operation completion message.

It should be noted that the first target logical storage area is the second logical storage area, and the fourth GC operation completion information is used to indicate that the processor has completed the fourth GC operation on the first target logical storage area; the fourth GC operation completion information Including but not limited to: the LBA and the length of the LBA of the invalid data located in the first target logical storage area.

In implementation, after the memory controller receives the fourth GC operation completion information from the processor through the information management interface, determine the invalid ratio of each third physical storage area in the current management queue; and select the third physical storage area with the largest invalid ratio The third target physical storage area for the memory controller to perform the third GC operation next time.

In the embodiment of the present application, the memory controller selects the third physical storage area from the multiple third physical storage areas, and obtains the second GC information from the second logical storage area obtained by mapping the selected third physical storage area. The memory controller sends the second GC information to the processor through the information management interface, and then, when the second logical storage area intersects with the third logical storage area, the processor selects the second logical storage area to be selected from the second logical storage area. The first target logical storage area is determined among the three logical storage areas. Since the processor is based on the third physical storage area where the memory controller does not perform the third GC operation, determine the first target logical storage area for performing the fourth GC operation next time, so that the processor performs the fourth GC operation on the first target logical storage area. The GC operation moves the valid data located in the first target logical storage area, so that the valid data stored in the third physical storage area corresponding to the first target logical storage area in the physical storage space is reduced, reducing the memory controller's impact on the third physical storage area. When the storage area performs the third GC operation, the workload of effectively moving valid data is invalidated, the efficiency of the memory controller performing the third GC operation is improved, and the performance of the memory is guaranteed.

Based on the garbage collection scheme described in Embodiment 2, the following continues to take the example in which the memory in the storage system is an SSD and the processor is a host to introduce the scheme in detail. FIG. 11 is a schematic flow chart of a garbage collection method based on SSD and host provided in the embodiment of the present application. The specific flow of the method will be described below with reference to FIG. 11 .

S1101: In the physical storage space, the SSD determines at least one third physical storage area that needs to perform a third GC operation, and adds the at least one third physical storage area to a management queue.

S1102: The SSD maps at least one third physical storage area to at least one second logical storage area in the logical storage space.

S1103: The SSD sends the second GC information to the host through the information management interface.

Wherein, the second GC information is used to indicate at least one second logical storage area obtained by mapping the third physical storage area in the logical storage space where the SSD needs to perform the third GC operation on the physical storage space.

S1104: In the logical storage space, the host determines multiple third logical storage areas that need to perform the fourth GC operation.

S1105: When at least one second logical storage area intersects with multiple third logical storage areas, the host selects the host from at least one candidate third logical storage area among the multiple third logical storage areas to execute the second logical storage area next time. The first target logical storage area for four GC operations.

Wherein, there is an intersection between at least one candidate third logical storage area and at least one second logical storage area.

One possible manner is that the host determines the invalid ratio of each third logical storage area to be selected, and selects the third logical storage area to be selected with the largest invalid ratio as the first target logical storage area.

S1106: After the SSD sends the second GC information to the host through the information management interface, determine an invalid ratio of each third physical storage area in the at least one third physical storage area.

S1107: The SSD takes the third physical storage area with the largest invalid ratio as the second target physical storage area for the SSD to perform the third GC operation next time.

S1108: The SSD performs a third GC operation on the second target physical storage area, and deletes the second target physical storage area from the management queue.

S1109: the host performs a fourth GC operation on the first target logical storage area.

S1110: the host sends fourth GC operation completion information to the SSD through the information management interface.

Wherein, the first target logical storage area is the second logical storage area, and the fourth GC operation completion information is used to indicate that the host has completed the fourth GC operation on the first target logical storage area.

S1111: After the SSD receives the completion information of the fourth GC operation from the host through the information management interface, determine the invalid ratio of each third physical storage area in the current management queue.

S1112: The SSD selects the third physical storage area with the largest invalid ratio as the third target physical storage area for the SSD to perform the third GC operation next time.

In the embodiment shown in FIG. 11, the SSD selects a third physical storage area from at least one third physical storage area, maps at least one physical storage area to a second logical storage area in the logical storage space, and based on at least one The second logical storage area obtains the second GC information. The SSD sends the second GC information to the host through the information management interface, and then, the host determines whether there is an intersection between at least one second logical storage area and multiple third logical storage areas according to the second GC information received through the information management interface; And, after the host determines that there is an intersection, select a third logical storage area to be selected that has an intersection with at least one second logical storage area from the plurality of third logical storage areas, and select a third logical storage area from the at least one third logical storage area to be selected. Select the first target logical storage area to perform the fourth GC operation next time, so that the host performs the fourth GC operation on the first target logical storage area, and move the valid data located in the first target logical storage area, so that the first target logical storage area The valid data stored in the corresponding third physical storage area in the physical storage space is reduced, reducing the workload of invalidly moving valid data when the SSD performs the third GC operation on the third physical storage area, and improving the efficiency of the SSD performing the third GC operation Efficiency, guarantee the performance of SSD.

Based on the methods provided in Embodiment 1 and Embodiment 2, FIG. 12 is a schematic diagram of an interaction flow of a garbage collection method provided in the present application, which is applied to the storage system shown in FIG. 3 . In this method, the memory and the processor in the storage system can implement the method provided by Embodiment 1 and the method provided by Embodiment 2. In addition, the two execution processes may or may not overlap in time, which is not limited in this application. As shown in Figure 12, the method includes:

S1201: In the logical storage space, the processor determines a first logical storage area that needs to perform a first GC operation.

It should be noted that the logical storage space is obtained by mapping the physical storage space managed by the memory controller.

S1202: The processor sends first GC information to the memory controller through the information management interface.

Wherein, the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation.

S1203: The memory controller maps the first logical storage area to at least one first physical storage area in the physical storage space.

S1204: The memory controller determines, in the physical storage space, multiple second physical storage areas that need to perform the second GC operation.

S1205: The memory controller determines at least one second physical storage area to be selected from the multiple second physical storage areas when the at least one first physical storage area overlaps with the multiple second physical storage areas. .

Wherein, there is no intersection between at least one second physical storage area to be selected and the at least one first physical storage area.

S1206: The memory controller determines, in the at least one second physical storage area to be selected, a first target physical storage area where the memory controller executes the second GC operation.

S1207: In the physical storage space, the memory controller determines at least one third physical storage area that needs to perform the third GC operation.

S1208: The memory controller maps the at least one third physical storage area to at least one second logical storage area in the logical storage space.

S1209: The memory controller sends the second GC information to the processor through the information management interface.

Wherein, the second GC information is used to indicate the at least one second logical storage area that needs to perform the third GC operation.

S1210: In the logical storage space, the processor determines a plurality of third logical storage areas that need to perform a fourth GC operation.

S1211: When at least one second logical storage area intersects with multiple third logical storage areas, the processor selects the processor from at least one candidate third logical storage area among the multiple third logical storage areas to execute the second logical storage area. The first target logical storage area for four GC operations.

In addition, for the execution process of each step in FIG. 12 , reference may be made to the descriptions in the above corresponding embodiments, and details are not repeated here.

Based on the above embodiments and the same idea, the embodiment of the present application further provides a memory. The memory includes: a memory controller and a storage unit; wherein the storage unit includes a physical storage space;

The memory controller is configured to receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate that the processor needs to perform the first GC operation on the logical storage space. A logical storage area; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

In a possible design, the memory controller is specifically used for:

According to the first valid data located in the first logical storage area and the second valid data stored in the plurality of second physical storage areas, selecting from the plurality of second physical storage areas that the impact factor is less than a set threshold The at least one candidate second physical storage area; the impact factor of each second physical storage area is used to characterize the intersection of the first valid data and the second valid data in the second physical storage area in the The storage space occupied by the second physical storage area.

In a possible design, the memory controller is specifically used for:

In the at least one candidate second physical storage area, select the first target physical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate second physical storage area is the candidate second physical storage area The ratio of invalid data in the storage area to the storage space of the second physical storage area to be selected.

In a possible design, the memory controller is also used for:

The embodiment of the present application also provides a memory management device. As shown in FIG. 13, the memory management device 1300 includes: a processor 1301, a signal management interface 1302;

Among them, the signal management interface 1302 is used to transmit GC information;

The processor 1301 is configured to: in the logical storage space, determine the first logical storage area that needs to perform the first GC operation; the logical storage space is obtained by mapping the physical storage space managed by the memory controller; through the information management interface 1302 Send first GC information to the memory controller; where the first GC information is used to indicate a first logical storage area where the processor needs to perform a first GC operation.

In a possible design, the processor 1301 is specifically used for:

The second GC information from the memory controller is received through the information management interface 1302; wherein, the second GC information is used to indicate that the memory controller needs to perform a third GC operation on the physical storage space. At least one second logical storage area obtained by mapping the storage area in the logical storage space;

In a possible design, the processor 1301 is specifically used for:

In the at least one candidate third logical storage area, select the first target logical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate third logical storage area is the candidate third logical storage area The ratio of invalid data in the storage area to the storage space of the third logical storage area to be selected.

Based on the above embodiments and the same idea, the embodiment of the present application also provides a garbage collection device. As shown in FIG. 14, the garbage collection device 1400 is applied to a memory controller in a memory; the device 1400 includes:

The transmission module 1401 is configured to receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate that the processor needs to perform the first GC operation on the logical storage space. A logical storage area; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

A mapping module 1402, configured to map the first logical storage area to at least one first physical storage area in the physical storage space;

The determining module 1403 is configured to determine, in the physical storage space, a plurality of second physical storage areas that need to perform a second GC operation; when the at least one first physical storage area overlaps with the plurality of second physical storage areas , determining at least one second physical storage area to be selected from the plurality of second physical storage areas; there is no intersection between the at least one second physical storage area to be selected and the at least one first physical storage area; A first target physical storage area for the memory controller to perform the second GC operation is determined in the at least one candidate second physical storage area.

In a possible design, the determination module 1403 is specifically used to:

In a possible design, the determining module 1403 is specifically configured to: in the physical storage space, determine at least one third physical storage area that needs to perform a third GC operation;

The mapping module 1402 is specifically configured to: map the at least one third physical storage area to at least one second logical storage area in the logical storage space;

The transmission module 1401 is specifically configured to: send second GC information to the processor through the information management interface; where the second GC information is used to indicate the at least one GC that needs to perform the third GC operation. Second logical storage area.

Based on the above embodiments and the same idea, the embodiment of the present application also provides a garbage collection device. As shown in Figure 15, the garbage collection device 1500 is applied to a processor; the device 1500 includes:

The processing module 1501 is configured to determine the first logical storage area that needs to perform the first GC operation in the logical storage space; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

A transmission module 1502, configured to send first GC information to the memory controller through the information management interface; wherein the first GC information is used to indicate that the processor needs to perform the first logical storage of the first GC operation district.

In a possible design, the transmission module 1502 is specifically configured to: receive second GC information from the memory controller through the information management interface; where the second GC information is used to indicate that the memory The controller needs to perform at least one second logical storage area mapped in the logical storage space from the third physical storage area that performs the third GC operation on the physical storage space;

The processing module 1501 is specifically configured to: in the logical storage space, determine multiple third logical storage areas that need to perform the fourth GC operation; when the at least one second logical storage area and the multiple third logical storage areas When there is an intersection of logical storage areas, selecting a first target logical storage area for the processor to perform the fourth GC operation from at least one third logical storage area to be selected among the plurality of third logical storage areas; Wherein, there is an intersection between the at least one candidate third logical storage area and the at least one second logical storage area.

In a possible design, the processing module 1501 is specifically configured to:

Based on the above content and the same idea, the present application provides a computer-readable storage medium on which a computer program or instruction is stored, and when the computer program or instruction is executed, the computing device executes the method in the above method embodiment.

Based on the above content and the same idea, the present application provides a computer program product, which enables the computing device to execute the methods in the above method embodiments when the computer executes the computer program product.

It should be understood that the division of modules in the embodiment of the present application is schematic, and is only a logical function division, and there may be another division manner in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into one processor, or physically exist separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

Apparently, those skilled in the art can make various changes and modifications to this application without departing from the protection scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A garbage collection method applied to a memory controller, wherein the method comprises:

Receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation on the logical storage space; the said The logical storage space is obtained by mapping the physical storage space managed by the memory controller;

mapping the first logical storage area to at least one first physical storage area in the physical storage space;

In the physical storage space, determine a plurality of second physical storage areas that need to perform a second GC operation;

When there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas, at least one candidate second physical storage area is determined from the plurality of second physical storage areas; the at least one There is no intersection between the second physical storage area to be selected and the at least one first physical storage area;

A first target physical storage area for the memory controller to perform the second GC operation is determined in the at least one second physical storage area to be selected.
The method according to claim 1, wherein the determining at least one second physical storage area to be selected from the plurality of second physical storage areas comprises:

According to the first valid data located in the first logical storage area and the second valid data stored in the plurality of second physical storage areas, selecting from the plurality of second physical storage areas that the impact factor is less than a set threshold The at least one candidate second physical storage area; the impact factor of each second physical storage area is used to characterize the intersection of the first valid data and the second valid data in the second physical storage area in the The storage space occupied by the second physical storage area.
The method according to claim 1 or 2, wherein the first target physical storage area for the memory controller to perform the second GC operation is determined in the at least one candidate second physical storage area ,include:

In the at least one candidate second physical storage area, select the first target physical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate second physical storage area is the candidate second physical storage area The ratio of invalid data in the storage area to the storage space of the second physical storage area to be selected.
The method according to any one of claims 1 to 3, wherein the method further comprises:

In the physical storage space, determine at least one third physical storage area that needs to perform a third GC operation;

mapping the at least one third physical storage area to at least one second logical storage area in the logical storage space;

Sending second GC information to the processor through the information management interface; wherein the second GC information is used to indicate the at least one second logical storage area that needs to perform the third GC operation.
A garbage collection method applied to a processor, wherein the method comprises:

In the logical storage space, determine the first logical storage area that needs to perform the first GC operation; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

Sending first GC information to the memory controller through an information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation.
The method according to claim 5, wherein the method further comprises:

Receive second GC information from the memory controller through the information management interface; wherein the second GC information is used to indicate that the memory controller needs to perform a third GC operation on the physical storage space for the third physical storage At least one second logical storage area obtained by mapping the area in the logical storage space;

In the logical storage space, determine a plurality of third logical storage areas that need to perform the fourth GC operation;

When there is an intersection between the at least one second logical storage area and the plurality of third logical storage areas, selecting the at least one candidate third logical storage area among the plurality of third logical storage areas The processor executes the first target logical storage area of the fourth GC operation; wherein, the at least one third logical storage area to be selected has an intersection with the at least one second logical storage area.
The method according to claim 6, wherein the processor is selected from at least one candidate third logical storage area among the plurality of third logical storage areas to perform the fourth GC operation The first target logical store, consisting of:

In the at least one candidate third logical storage area, select the first target logical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate third logical storage area is the candidate third logical storage area The ratio of invalid data in the storage area to the storage space of the third logical storage area to be selected.
A kind of memory, described memory comprises: memory controller and storage unit, and described storage unit comprises physical storage space; It is characterized in that, described memory controller is used for:

Receive the first garbage collection GC information sent by the processor through the information management interface; wherein the first GC information is used to indicate the first logical storage area where the processor needs to perform the first GC operation on the logical storage space; the said The logical storage space is obtained by mapping the physical storage space managed by the memory controller;

mapping the first logical storage area to at least one first physical storage area in the physical storage space;

In the physical storage space, determine a plurality of second physical storage areas that need to perform the second GC operation;

When there is an intersection between the at least one first physical storage area and the plurality of second physical storage areas, at least one candidate second physical storage area is determined from the plurality of second physical storage areas; the at least one There is no intersection between the second physical storage area to be selected and the at least one first physical storage area;

A first target physical storage area for the memory controller to perform the second GC operation is determined in the at least one second physical storage area to be selected.
The memory according to claim 8, wherein the memory controller is specifically used for:

According to the first valid data located in the first logical storage area and the second valid data stored in the plurality of second physical storage areas, selecting from the plurality of second physical storage areas that the impact factor is less than a set threshold The at least one candidate second physical storage area; the impact factor of each second physical storage area is used to characterize the intersection of the first valid data and the second valid data in the second physical storage area in the The storage space occupied by the second physical storage area.
The memory according to claim 8 or 9, wherein the memory controller is specifically used for:

In the at least one candidate second physical storage area, select the first target physical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate second physical storage area is the candidate second physical storage area The ratio of invalid data in the storage area to the storage space of the second physical storage area to be selected.
The memory according to any one of claims 8 to 10, wherein the memory controller is further used for:

In the physical storage space, determine at least one third physical storage area that needs to perform a third GC operation;

mapping the at least one third physical storage area to at least one second logical storage area in the logical storage space;

Sending second GC information to the processor through the information management interface; wherein the second GC information is used to indicate the at least one second logical storage area that needs to perform the third GC operation.
A memory management device, the memory management device comprising: a processor and an information management interface, characterized in that the processor is used for:

In the logical storage space, determine the first logical storage area that needs to perform the first GC operation; the logical storage space is obtained by mapping the physical storage space managed by the memory controller;

Sending first GC information to the memory controller through the information management interface; wherein the first GC information is used to indicate a first logical storage area where the processor needs to perform a first GC operation.
The memory management device according to claim 12, wherein the processor is further configured to:

Receive second GC information from the memory controller through the information management interface; wherein the second GC information is used to indicate that the memory controller needs to perform a third GC operation on the physical storage space for the third physical storage At least one second logical storage area obtained by mapping the area in the logical storage space;

In the logical storage space, determine a plurality of third logical storage areas that need to perform the fourth GC operation;

When there is an intersection between the at least one second logical storage area and the plurality of third logical storage areas, selecting the at least one candidate third logical storage area among the plurality of third logical storage areas The processor executes the first target logical storage area of the fourth GC operation; wherein, the at least one third logical storage area to be selected has an intersection with the at least one second logical storage area.
The memory management device according to claim 13, wherein the processor is specifically configured to:

In the at least one candidate third logical storage area, select the first target logical storage area with the largest invalid ratio; wherein, the invalid ratio of each candidate third logical storage area is the candidate third logical storage area The ratio of invalid data in the storage area to the storage space of the third logical storage area to be selected.