CN100517508C - Flash memory device with improved erase function and method for controlling erase operation of the same - Google Patents
Flash memory device with improved erase function and method for controlling erase operation of the same Download PDFInfo
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- CN100517508C CN100517508C CNB200510128852XA CN200510128852A CN100517508C CN 100517508 C CN100517508 C CN 100517508C CN B200510128852X A CNB200510128852X A CN B200510128852XA CN 200510128852 A CN200510128852 A CN 200510128852A CN 100517508 C CN100517508 C CN 100517508C
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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Abstract
The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device includes memory cell blocks, each having a plurality of memory cells sharing local word lines and bit lines, an X-decoder which decodes a row address signal and outputs the decoded signal, a block selection unit, which selects some of the memory cell blocks in response to the decoded signal, and connects local word lines of the selected memory cell blocks to corresponding global word lines, respectively, and a high voltage generator, which generates word line bias voltages in response to one of a read command, a program command and an erase command, and supplies the generated word line bias voltages to the global word lines in response to the decoded signal, respectively, wherein the word line bias voltages, which are generated by the high voltage generator in response to the erase command, have a positive value, respectively. Accordingly, a positive bias voltage is applied to a global word line in an erase operation. It is thus possible to prevent a shallow erase phenomenon of non-selected memory cell blocks due to the leakage current of pass gates.
Description
Technical field
The present invention relates to semiconductor memory apparatus and its method of operating of control, more specifically, relate to the method for flash memory device and its erase operation of control.
Background technology
Usually, flash memory device can be categorized as the NOR type of high speed storing a little information and the NAND type that generally is used for storing bulk information of generally being used for.In addition, flash memory device is carried out read operation, programming operation and erase operation.More particularly, the programming operation of NAND type flash memory device and erase operation are to carry out by Fowler-Nordheim (FN) tunneling effect (tunneling) that takes place in the P-trap of storage unit (cell) and the dielectric film between the floating grid (floating gate).That is to say, when electronics being injected the floating grid of storage unit, carry out the programming operation of flash memory device by the FN tunneling effect.In programming operation, the selected storage unit in a plurality of storage unit that only comprise in memory cell block is programmed (program).In addition, when the electronics that exists in the floating grid of storage unit is discharged into the P-trap by the FN tunneling effect, carry out the erase operation of flash memory device.In erase operation, the data of storing in the whole storage unit that comprise in memory cell block are wiped simultaneously.That is to say that erase operation is to carry out on the basis of memory cell block.
Fig. 1 is used to explain the storage unit of erase operation of conventional flash devices and the circuit diagram of pass gate (pass gate).
With reference to Fig. 1, in erase operation, the bias voltage Vb of 0V is applied to the overall situation (global) word line GWL, and body voltage (bulk voltage) VBK1 of 20V is applied to the P-trap of storage unit CA1 to CAn and CB1 to CBn (wherein n is an integer).The source electrode of storage unit CA1 to CAn and CB 1 to CBn and drain electrode are floated.In addition, the block selection signal BKSEL1 of voltage (Vcc) level is applied to is connected selected (that is, be wiped free of) the local word line WL1 of memory cell block A and the grid of the nmos pass transistor NM1 between the GWL of Overall word line.The body voltage VBK2 of 0V is applied to the substrate (not shown) of nmos pass transistor NM1.Nmos pass transistor NM1 conducting in response to block selection signal BKSEL1, and local word line WL1 is connected to the GWL of Overall word line.Therefore, the voltage of local word line WL1 becomes 0V, and produces the voltage difference of 20V between the P-trap of the control grid (not shown) of the storage unit CA1 to CAn that is connected to local word line WL1 and storage unit CA1 to CAn.Therefore, when the electronics of the floating grid of storage unit CA1 to CAn is released to the P-trap, carry out the erase operation of memory cell block A.
Simultaneously, the grid that is connected the local word line WL2 of non-selected (that is, will can not be wiped free of) memory cell block B and the nmos pass transistor NM2 between the GWL of Overall word line has been applied in the block selection signal BKSEL2 of 0V.In addition, the body voltage VBK2 with 0V is applied on the substrate of nmos pass transistor NM2.Nmos pass transistor NM2 turn-offs in response to block selection signal BKSEL2, and local word line WL2 separates with the GWL of Overall word line.This makes that local word line WL2 is floated.Subsequently, the body voltage VBK1 of 20V that will be applied to the P-trap of storage unit CB1 to CBn by the capacitive coupling phenomenon is applied to local word line WL2, and the voltage level of local word line WL2 correspondingly boosts (boost) to about 19V.This causes the small electric pressure reduction of the 1V between the P-trap of local word line WL2 and storage unit CB1 to CBn, and electronics can not discharge from the floating grid of storage unit CB1 to CBn thus.As a result of, during the erase operation of carrying out memory cell block A, do not carry out the erase operation of memory cell block B.Yet,, may in nmos pass transistor NM2, produce leakage current although nmos pass transistor NM2 is turned off.Therefore, boostedly may reduce gradually to voltage level near the local word line WL2 of the voltage level of body voltage VBK1.This causes the control grid of storage unit CB1 to CBn and the voltage difference between the P-trap to increase.Therefore, there is such problem, i.e. the phenomenon (that is shallow wiping (shallow erase)) that discharges of the floating grid of a little electrons storage unit CB1 to CBn that never should be wiped free of.When the quantity of the memory cell block that comprises in the flash memory device increases, become more serious such as the shallow confusion (erase disturbance) of wiping of wiping.For example, no matter when memory cell block carries out erase operation one by one, all repeats to produce the shallow phenomenon of wiping in the storage unit of the memory cell block that should not be wiped free of.Therefore, when the threshold voltage of the storage unit of correspondence reduces gradually, there is the problem that the read operation failure takes place.
Summary of the invention
Therefore, this patent has solved the problems referred to above, and such flash memory device is disclosed, and wherein, can positive bias prevents because the shallow phenomenon of wiping of the non-selected memory cell block that the leakage current of pass gate causes by applying to Overall word line in erase operation.
This patent also discloses a kind of method of controlling the erase operation of flash memory device, wherein can positive bias prevents because the shallow phenomenon of wiping of the non-selected memory cell block that the leakage current of pass gate causes by applying to Overall word line in erase operation.
To achieve these goals, provide a kind of flash memory device, having comprised: memory cell block, each has a plurality of storage unit of sharing local word line and bit line; The X-demoder, it decodes row address signal, and the signal behind the output decoder; The piece selected cell, it selects some memory cell blocks in response to decoded signal, and the local word line of selected memory cell block is connected respectively to corresponding Overall word line; And high voltage generator, it produces the word line bias voltage in response to one of reading order, program command and data erase order, and the word line bias voltage that is produced is offered Overall word line respectively in response to described decoded signal, wherein, the word line bias voltage that produces in response to erase command by high voltage generator have respectively on the occasion of.
This patent also discloses a kind of method of controlling the erase operation of flash memory device, may further comprise the steps: in response to erase command and row address signal, with each all have on the occasion of the word line bias voltage offer Overall word line respectively; Body voltage is offered the storage unit of whole memory cell blocks; By ground voltage being offered overall situation drain electrode selection wire and overall source electrode selection wire, the drain electrode and the source electrode of storage unit are floated; And in response to row address signal one of select storage unit piece, and the local word line of selected memory cell block is connected to Overall word line.
Description of drawings
Fig. 1 is the storage unit of erase operation of explanation conventional flash devices and the circuit diagram of pass gate;
Fig. 2 is the block scheme according to the example flash equipment of this patent embodiment;
Fig. 3 is the detailed circuit diagram of example storage cell array, piece selected cell, second bias generator and X-demoder shown in Figure 2;
Fig. 4 is the exemplary circuit figure of storage unit, pass gate and biasing selected unit shown in Figure 3;
Fig. 5 A is the example cross-section figure of pass gate shown in Figure 4;
Fig. 5 B is the exemplary plot that variation that can gesture (energy potential) according to the pass gate of word line bias variations shown in Figure 4 is shown;
Fig. 6 is the example block diagram according to the flash memory device of another embodiment of this patent;
Fig. 7 is the exemplary circuit figure of memory cell array, piece selected cell, second bias generator, the second body voltage generator and X-demoder shown in Figure 6;
Fig. 8 is the exemplary circuit figure of storage unit, pass gate, biasing selected unit and body voltage selected cell shown in Figure 7;
Fig. 9 A is the example cross-section figure of pass gate shown in Figure 8; And
Fig. 9 B illustrates the exemplary plot that the pass gate that changes according to the bias voltage of word line shown in Figure 8 and body voltage can gestureization.
Embodiment
Now, various embodiment according to this patent are described with reference to the accompanying drawings.Because provide various embodiment, therefore can in every way it be made amendment, and the scope of this patent is not limited by the various embodiment that describe after a while for those of ordinary skills can understand the purpose of this patent.
Fig. 2 is the block scheme according to the flash memory device of this patent embodiment.
With reference to Fig. 2, flash memory device 100 comprises memory cell array 110, input buffer 120, control logic circuit 130, high voltage generator 140, X-demoder 150, piece selected cell 160, page buffer 170, Y-demoder 180 and data I/O impact damper 190.Memory cell array 110 comprises memory cell block MB1 to MBK (wherein K is an integer), and each has a plurality of storage unit (not shown).Input buffer 120 receives command signal CMD or address signal ADD, and it is outputed to control logic circuit 130.Control logic circuit 130 in response to external control signal/WE ,/RE, ALE and CLE and receive command signal CMD or address signal ADD.Control logic circuit 130 produces one of reading order READ, program command PGM and erase command ERS in response to command signal CMD.Control logic circuit 130 produces row address signal RADD and column address signal CADD in response to address signal ADD.
Fig. 3 is the detailed circuit diagram of memory cell array, piece selected cell, second bias generator and X-demoder shown in Figure 2.
With reference to Fig. 3, the memory cell block MB1 of memory cell array 110 comprises storage unit M111 to M1JT (wherein J and T are integers), drain electrode selection transistor DST1 and drain selection transistor SST1.Storage unit M111 to M1JT share bit lines BL1 to BLT (wherein T is an integer), local word line WL11 to WL1J (wherein J is an integer) and common source polar curve CSL1.That is to say that storage unit M111 to M11T selects transistor DST1 to be connected respectively to bit line BL1 to BLT by drain electrode, and storage unit M1J1 to M1JT is connected to common source polar curve CSL1 by drain selection transistor SST1.In addition, the grid of storage unit M111 to M1JT is connected to local word line WL11 to WL1J.Simultaneously, drain electrode selects the grid of transistor DST1 to be connected to local drain electrode selection wire DSL1, and the grid of drain selection transistor SST1 is connected to local source electrode selection wire SSL1.
The structure of the memory cell block MB2 to MBK of memory cell array 110 is identical with the structure of memory cell block MB1.Therefore, for fear of repetition, being described in detail it will be omitted.Piece selected cell 160 comprises piece switch unit 161 and pass gate circuit PG1 to PGK (wherein K is an integer).Piece switch unit 161 is exported block selection signal BSEL1 to BSELK (wherein K is an integer) in response to the decoded signal DEC that receives from X-demoder 150.Pass gate circuit PG1 to PGK is corresponded respectively to memory cell block MB1 to MBK and is arranged, and is activated in response to block selection signal BSEL1 to BSELK (enabled) or forbids (disabled).
Each of pass gate circuit PG1 to PGK comprises a plurality of pass gate.For example, pass gate circuit PG1 has pass gate GD1, G11 to G1J and GS1.The structure of pass gate circuit PG2 to PGK and detail operations are similar to pass gate circuit PG1's.Therefore, will on the basis of the operation of pass gate circuit PG1, provide narration.Preferably, can use nmos pass transistor to realize pass gate GD1, G11 to G1J and GS1.Hereinafter, will call " nmos pass transistor " to pass gate GD1, G11 to G1J and GS1.Block selection signal BSEL1 is imported into the grid of nmos pass transistor GD1, G11 to G1J and GS1.Nmos pass transistor GD1 has source electrode that is connected to overall situation drain electrode selection wire GDSL and the drain electrode that is connected to local drain electrode selection wire DSL1.The drain electrode that nmos pass transistor G11 to G1J has the source electrode that is connected respectively to the GWL1 to GWLJ of Overall word line and is connected respectively to local word line WL11 to WL1J.Nmos pass transistor GS1 has the source electrode that is connected to overall source electrode selection wire GSSL and is connected to the drain electrode of local source electrode selection wire SSL1.Nmos pass transistor GD1, G11 to G1J and GS1 be quilt conducting simultaneously or shutoff in response to block selection signal BSEL1.More particularly, when block selection signal BSEL1 is activated, nmos pass transistor GD1, G11 to G1J and GS1 conducting, and when block selection signal BSEL1 was under an embargo, nmos pass transistor GD1, G11 to G1J and GS1 turn-offed.When nmos pass transistor GD1, G11 to G1J and GS1 conducting, overall situation drain electrode selection wire GDSL is connected to local drain electrode selection wire DSL1, overall situation source electrode selection wire GSSL is connected to local source electrode selection wire SSL1, and the GWL1 to GWLJ of Overall word line is connected respectively to local word line WL11 to WL1J.
V
CB-V
ERS＞＝15V (1)
(wherein, V
CBBe the body voltage that in erase operation, is applied to the P-trap of storage unit, and V
ERSBe erasing voltage)
Voltage V is selected to read in response to the decoded signal DEC that receives from X-demoder 150 in biasing selected unit 64
RD1 and V
RD2, then with the selected voltage V that reads
RD1 and V
RD2 output to the GWL1 to GWLJ of Overall word line respectively as word line bias voltage V
WF1 to V
WFJ selects program voltage V
PGAnd V
PS, and with selected program voltage V
PGAnd V
PSOutput to the GWL1 to GWLJ of Overall word line respectively as word line bias voltage V
WS1 to V
WSJ (wherein J is an integer), perhaps selective erasing voltage V
ERS, and subsequently with selected erasing voltage V
ERSOutput to the GWL1 to GWLJ of Overall word line as word line bias voltage V
WT1 to V
WTJ.One of ordinary skill in the art will appreciate that the entire infrastructure and the operation of first to the 3rd pump circuit 61,62 and 63, therefore will be for the sake of simplicity and with its omission.
Fig. 4 is the detailed circuit diagram of storage unit, pass gate and biasing selected unit shown in Figure 3.
With reference to Fig. 4, biasing selected unit 64 comprises to be selected signal generator 65 and selects circuit S1 to SJ (wherein J is an integer).Select signal generator 65 to produce signal and select SL1 to SLJ according to decoded signal DEC.Each that select circuit S1 to SJ comprise the switch SW 11 to SW15 that is connected respectively to the GWL1 to GWLJ of Overall word line ..., SWJ1 to SWJ5.Select each reception of circuit S1 to SJ to read voltage V
RD1 and V
RD2, program voltage V
PGAnd V
PSAnd erasing voltage V
ERS, and in response to selecting signal SL1 to SLJ with word line bias voltage V
WF1 to V
WFJ, V
WS1 to V
WSJ or V
WT1 to V
WTJ outputs to the GWL1 to GWLJ of Overall word line.This will be described in more detail.For example, the switch SW 11 to SW15 of selection circuit S1 is connected to and reads voltage V
RD1 and V
RD2, program voltage V
PGAnd V
PSAnd erasing voltage V
ERSAnd between the GWL1 of Overall word line.Switch SW 11 to SW15 is according to the logical value of the position B1 to B5 that selects signal SL1 and conducting or shutoff.In this case, if use nmos pass transistor to realize switch SW 11 to SW15, then when the logical value of a B1 to B5 is 1, switch SW 11 to SW15 conductings.Simultaneously, when the logical value of position B1 to B5 was 0, switch SW 11 to SW15 was turn-offed.
For example, when one of switch SW 11 and SW12 conducting, read voltage V
RD1 and V
RDOne of 2 as word line bias voltage V
WF1 and be imported into the GWL1 of Overall word line.In addition, when one of switch SW 13 and SW14 conducting, program voltage V
PGAnd V
PSOne of as word line bias voltage V
WS1 and be imported into the GWL1 of Overall word line.In addition, when switch SW 15 conductings, erasing voltage V
ERSAs word line bias voltage V
WT1 and be imported into the GWL1 of Overall word line.In this case, because select signal generator 65 that the logical value of one of position B1 to B5 is produced as 1, and the logical value of remaining bit is 0, so switch SW 11 to one of SW15 conductings, and remaining switch turn-offs.As a result of, read voltage V
RD1 and V
RD2, program voltage V
PGAnd V
PSAnd erasing voltage V
ERSOne of be applied to the GWL1 of Overall word line.Select the structure of circuit S2 to SJ similar to the structure of aforementioned selection circuit S1 with detail operations with detail operations.Therefore, for fear of repetition, will omit detailed description.
Figure 4 illustrates each that select circuit S1 to SJ and have 5 switches.Yet, should be noted that as long as select each output word line bias voltage V of circuit S1 to SJ
WF1 to V
WFJ, V
WS1 to V
WSJ or V
WT1 to V
WTJ just can change the structure of selecting circuit S1 to SJ in every way.
In addition, in order to simplify described figure, in Fig. 4, only show nmos pass transistor G11, the GK1, G1J and the GKJ that are connected to the GWL1 of Overall word line and GWLJ, local word line WL11, WL1J, WLK1 and WLKJ and storage unit M111, M11T, M1J1, M1JT, MK11, MK1T, MKJ1 and MKJT.The grid of storage unit M111 to M11T is connected to local word line WL11, and the grid of storage unit M1J1 to M1JT is connected to local word line WL1J.In addition, the grid of storage unit MK11 to MK1T is connected to local word line WLK1, and the grid of storage unit MKJ1 to MKJT is connected to local word line WLKJ.The source electrode of nmos pass transistor G11 and drain electrode are connected respectively to GWL1 of Overall word line and local word line WL11, and the source electrode of nmos pass transistor GK1 and drain electrode are connected respectively to GWL1 of Overall word line and local word line WLK1.In addition, the source electrode of nmos pass transistor G1J and drain electrode are connected respectively to GWLJ of Overall word line and local word line WL1J, and the source electrode of nmos pass transistor GKJ and drain electrode are connected respectively to GWLJ of Overall word line and local word line WLKJ.
The erase operation of flash memory device 100 is described in more detail with reference to Fig. 2 to 4 now.Control logic circuit 130 in response to external control signal/WE ,/RE, ALE and CLE and command signal CMD and produce erase command ERS, and produce row address signal RADD according to address signal ADD.The body voltage generator 40 of high voltage generator 140 produces the body voltage V of high voltage (for example 20V) level in response to erase command ERS
CB, and with the body voltage V that is produced
CBOffer the storage unit of memory cell block MB1 to MBK.In addition, first bias generator 50 of high voltage generator 140 produces the drain bias V of low-voltage (for example 0V) level in response to erase command ERS
GDWith source electrode bias voltage V
GSTherefore, drain bias V
GDBe applied to overall situation drain electrode selection wire GDSL, and source electrode bias voltage V
GSBe applied to overall source electrode selection wire GSSL.Simultaneously, X-demoder 150 is with row address signal RADD decoding, and output decoder signal DEC.Second bias generator 60 of high voltage generator 140 is in response to erase command ERS and decoded signal DEC and produce word line bias voltage V
WT1 to V
WTJ, and the voltage that is produced offered the GWL1 to GWLJ of Overall word line respectively.More particularly, the 3rd pump circuit 63 of second bias generator 60 produce in response to erase command ERS have on the occasion of erasing voltage V
ERSFor example, in erase operation, erasing voltage V
ERSBe lower than the body voltage V of the P-trap that offers storage unit
CB, and have on the occasion of.Preferably, can the body voltage V of the P-trap of storage unit will be provided in erase operation
CBWith erasing voltage V
ERSBetween difference be set to be greater than or equal to 5V.The biasing selected unit 64 of second bias generator 60 is selective erasing voltage V in response to decoded signal DEC
ERS, and with selected voltage as word line bias voltage V
WT1 to V
WTJ output.In more detail, the selection signal generator 65 of biasing selected unit 64 will select the value of the position B1 to B5 of signal SL1 to SLJ to be output as " 00001 " entirely in response to decoded signal DEC.In response to selecting signal SL1 to SLJ, switch SW 15 to the SWJ5 conductings of the selection circuit S1 to SJ of biasing selected unit 64, and switch SW 11 is all turn-offed to SWJ1, SW12 to SWJ1, SW13 to SWJ3 and SW14 to SWJ4.Therefore, erasing voltage V
ERSBe used as word line bias voltage V by switch SW 15 to SWJ5
WT1 to V
WTJ is input to the GWL1 to GWLJ of Overall word line.
In addition, piece selected cell 160 is one of select storage unit piece MB1 to MBK in response to decoded signal DEC, and the local word line of selected memory cell block is connected respectively to the GWL1 to GWLJ of Overall word line.For example, if select storage unit piece MB1, then the piece switch unit 161 of piece selected cell 160 activates block selection signal BSEL1 in response to decoded signal DEC, and forbids all block selection signal BSEL2 to BSELK.Therefore, have only the pass gate circuit PG1 of piece selected cell 160 to be activated, and pass gate circuit PG2 to PGK all is under an embargo.In more detail, pass gate GD1, the G11 to G1J of pass gate circuit PG1 and GS1 conducting simultaneously, and pass gate GD2 to GDK, the G21 to G2J of pass gate circuit PG2 to PGK ..., GK1 to GKJ, GS2 to GSK complete shut-down is disconnected.Therefore, the drain electrode selection wire DSL1 of memory cell block MB 1 is connected to overall situation drain electrode selection wire GDSL, and drain selection line SSL1 is connected to overall source electrode selection wire GSSL.Thereby, as the drain bias V of low voltage level
GDWith source electrode bias voltage V
GSWhen being applied to drain electrode selection wire DSL1 and drain selection line SSL1 respectively, drain electrode selects transistor DST1 and drain selection transistor SST1 to be turned off.Therefore, the drain electrode of the storage unit M111 to M1JT of memory cell block MB1 and source electrode become and float.
In addition, the local word line WL11 to WL1J of memory cell block MB1 is connected respectively to the GWL1 to GWLJ of Overall word line.As a result of, the word line bias voltage V of the GWL1 to GWLJ of Overall word line
WT1 to V
WTJ is delivered to local word line WL11 to WL1J respectively.Therefore, between the grid of the storage unit M111 to M1JT of memory cell block MB1 and main body, (for example produce voltage difference, 15V or more), and passes through the floating grid release electronics of this voltage difference, carry out the erase operation of storage unit M111 to M1JT thus from storage unit M111 to M1JT.
Simultaneously, the drain electrode selection wire DSL2 to DSLJ of memory cell block MB2 to MBK separates with overall situation drain electrode selection wire GDSL, and drain selection line SSL2 to SSLJ also separates with overall source electrode selection wire GSSL.In addition, the local word line WL21 to WL2J of memory cell block MB2 to MBK ..., WLK1 to WLKJ all separates with the GWL1 to GWLJ of Overall word line.Therefore, local word line WL21 to WL2J ..., the body voltage V of high voltage (for example 20V) level of the storage unit of WLK1 to WLKJ by being applied to memory cell block MB2 to MBK
CBAnd boosted (boost).Thereby, local word line WL21 to WL2J ..., produce near body voltage V among the WLK1 to WLKJ
CBBooster voltage V
BSTIn this case, with reference to Fig. 5 a and 5b describe in more detail the local word line WL21 to WL2J that is connected memory cell block MB2 to MBK ..., the nmos pass transistor G21 to G2J between WLK1 to WLKJ and the GWL1 to GWLJ of Overall word line ..., the operation of GK1 to GKJ.Fig. 5 a and 5b show cross-sectional view and the energy gesture thereof of nmos pass transistor GK1 respectively.Nmos pass transistor G21 to G2J ..., the operation of GK2 to GKJ is similar to the operation of nmos pass transistor GK1.Therefore, for the sake of simplicity, will omit detailed description.
Fig. 5 a shows the cross-sectional view as the nmos pass transistor GK1 of pass gate, and described transistor is connected to the local word line WLK1 of memory cell block MBK.The source electrode 72 of nmos pass transistor GK1 be applied in have on the occasion of word line bias voltage V
WT1, and its grid 74 has been applied in the block selection signal BSELK of (for example 0V) level that has low-voltage.The drain electrode 73 of nmos pass transistor GK1 also has been transfused to booster voltage V
BSTWhen block selection signal BSELK was in low level, nmos pass transistor GK1 turn-offed.In addition, because word line bias voltage V
WT1 have on the occasion of, so the energy gesture in source electrode 72 zones is reduced to about Ev2, shown in Fig. 5 b.Therefore, the amount of electrons of introducing substrate 71 from source electrode 72 reduces, and the amount of electrons of introducing the local word line WLK1 that is connected to drain electrode 73 reduces.As a result of, when the leakage current that produces in nmos pass transistor GK reduced, local word line WLK1 was retained as booster voltage V
BSTLevel.Therefore, the data that are connected to the storage unit of local word line WLK1 are not wiped free of.
Simultaneously, relative with top description, at word line bias voltage V with 0V
WT1 is applied in the situation of source electrode 72, and the energy gesture in source electrode 72 zones is increased to about Ev1, shown in Fig. 5 b.Therefore, the amount of electrons of introducing substrate 71 from source electrode 72 increases, and the amount of leakage current of nmos pass transistor GK1 increases.Therefore, in order to reduce the leakage current of nmos pass transistor GK1, need to reduce the energy gesture in source electrode 72 zones.
Fig. 6 is the block scheme of flash memory device according to another embodiment of the present invention.
With reference to Fig. 6, flash memory device 200 comprises memory cell array 210, input buffer 220, control logic circuit 230, high voltage generator 240, X-demoder 250, piece selected cell 260, page buffer 270, Y-demoder 280 and data I/O impact damper 290.Except high voltage generator 240, the structure of flash memory device 200 is identical with whole operation with the structure of all operating with reference to the described flash memory device 100 of Fig. 2.Therefore, for fear of repetition, in Fig. 6, the operation of high voltage generator 240 will only be described.High voltage generator 240 comprises the first body voltage generator 241, first bias generator 242, second bias generator 243 and the second body voltage generator 244.The operation of the first body voltage generator 241, first bias generator 242 and second bias generator 243 is identical with the operation of body voltage generator 40, first bias generator 50 and second bias generator 60 of high voltage generator 140.Therefore, will omit detailed description.The body voltage V that the second body voltage generator 244 will be used to wipe in response to erase command ERS
SBEWith reference body voltage V
SBROne of offer piece selected cell 260.In more detail, when erase command ERS is under an embargo, that is, when reading order READ or program command PGM were activated (or generation), the second body voltage generator 244 will be with reference to body voltage V
SBRBe applied to piece selected cell 260.In addition, when erase command ERS is activated, the body voltage V that the second body voltage generator 244 will be used to wipe
SBEOffer piece selected cell 260.
Fig. 7 is the detailed circuit diagram of the memory cell array 210 shown in Fig. 6, piece selected cell 260, second bias generator 243, the second body voltage generator 244 and X-demoder 250.The structure of memory cell array 210, piece selected cell 260, second bias generator 243 and X-demoder 250 and whole operations with reference to the structure of the described memory cell array 110 of Fig. 3, piece selected cell 160, second bias generator 60 and X-demoder 150 with all operate identical.Therefore, for fear of repetition, omit detailed description.The second body voltage generator 244 comprises the 4th pump circuit 321 and body voltage selected cell 322.The 4th pump circuit 321 produces the body voltage V that is used to wipe in response to erase command ERS
SBEThe body voltage V that is used to wipe
SBEPreferably have negative value, and can be expressed as following equation.
V
CB-V
SBEThe junction breakdown voltage of D pass gate (2)
(V
CBBe the body voltage that in erase operation, is applied to the P-trap of storage unit, and V
SBEBe the body voltage that is used to wipe)
It will be appreciated by those skilled in the art that the entire infrastructure and the operation of the 4th pump circuit 321.Therefore, for the sake of simplicity, will omit detailed description.
Body voltage selected cell 322 is selected the body voltage V that is used to wipe in response to selecting control signal SCTL
SBEWith reference body voltage V
SBROne of, and selected voltage is offered the pass gate circuit PG1 to PGK of piece selected cell 260.More particularly, when selecting control signal SCTL to be activated, the body voltage V that 322 selections of body voltage selected cell are used to wipe
SBE, and with selected voltage offer pass gate circuit PG1 to PGK pass gate GD1 to GDK, G11 to G1J ... GK1 to GKJ, GS1 to GSK.In this case, the time durations that is provided with when erase command ERS is activated selects control signal SCTL to be activated, and with reference to body voltage V
SBRWith the voltage of ground voltage level as the main body that is input to flash memory device 200.
Fig. 8 is the detailed circuit diagram of storage unit 210, pass gate, biasing selected unit 314 and body voltage selected cell 322 shown in Figure 7.Except body voltage selected cell 322, other assembly is identical with assembly shown in Figure 4.Therefore, for fear of repetition, will omit detailed description.With reference to Fig. 8, body voltage selected cell 322 has phase inverter 323 and switch SW B1 and SWB2.Phase inverter 323 will select control signal SCTL anti-phase, and export the selection control signal SCTLB after anti-phase.Switch SW B1 conducting or shutoff in response to selecting control signal SCTL.When switch SW B1 conducting, the body voltage V that it will be used to wipe
SBEOutput to pass gate G11 to G1J ..., GK1 to GKJ.In addition, switch SW B2 conducting or shutoff in response to the selection control signal SCTLB after anti-phase.When switch SW B2 conducting, it will be with reference to body voltage V
SBROutput to pass gate G11 to G1J ..., GK1 to GKJ.In this case, pass gate G11 to G1J ..., GK1 to GKJ has the triple well structure (triple well structure) shown in Fig. 9 a.
The erase operation of flash memory device 200 will be described now.For example, will describe such situation, wherein, in flash memory device 200, memory cell block MB1 carries out erase operation, and memory cell block MB2 to MBK does not carry out erase operation.In this case, except an aspect, the erase operation of flash memory device 200 is identical with the erase operation of flash memory device 100.This difference is: in the erase operation of flash memory device 200, and the body voltage V that the second body voltage generator 244 of high voltage generator 240 also will be used to wipe in response to erase command ERS
SBEOffer piece selected cell 260 pass gate (that is nmos pass transistor) GD1 to GDK, G11 to G2J ..., GK1 to GKJ, GS1 to GSK.In this case, with reference to Fig. 9 a and 9b describe in more detail nmos pass transistor G21 to G2J ..., the operation of GK1 to GKJ, described nmos pass transistor be connected memory cell block MB2 to MBK local word line WL21 to WL2J ..., between WLK1 to WLKJ and the GWL1 to GWLJ of Overall word line.Fig. 9 a and Fig. 9 b are respectively cross-sectional view and the energy gesture thereof of nmos pass transistor GK1.Nmos pass transistor G21 to G2J ..., the operation of GK2 to GKJ is identical with the operation of nmos pass transistor GK1.Therefore, for the sake of simplicity, will omit detailed description.
With reference to Fig. 9 a, it illustrates the cross-sectional view of the nmos pass transistor GK1 of the local word line WLK1 that is connected to memory cell block MBK.Nmos pass transistor GK1 comprises substrate 331, N-trap 332, P-trap 333, source electrode 334, drain electrode 335 and grid 336.Have on the occasion of word line bias voltage V
WT1 is imported into source electrode 334, and the block selection signal BSELK of low (for example 0V) level is imported into grid 336.Drain electrode 335 also has been applied in booster voltage V
BSTWhen block selection signal BSELK was in low level, nmos pass transistor GK1 turn-offed.In addition, because word line bias voltage V
WT1 have on the occasion of, so the energy gesture in source electrode 334 zones is reduced to the about Ev2 shown in the solid line of Fig. 9 b.In addition, because have the body voltage V that is used to wipe of negative value
SBEBe applied to P-trap 333, so the energy gesture of P-trap 333 increases to the about Ev2 shown in the solid line of Fig. 9 b.Therefore, when the amount of electrons of introducing P-trap 333 from source electrode 334 reduced, the amount of electrons of introducing the local word line WLK1 that is connected to drain electrode 335 reduced.Thereby the leakage current that produces in nmos pass transistor GK1 in the erase operation of flash memory device 100 can be higher than the leakage current of the nmos pass transistor GK1 in the erase operation of flash memory device 200.Simultaneously, if with the word line bias voltage V of 0V
WT1 input source electrode 334 and with the reference body voltage V of 0V
SBRInput P-trap 333, then the energy gesture of increase of energy the gesture in source electrode 334 zones and P-trap 333 reduces to the about Ev1 shown in the dotted line of Fig. 9 b.Therefore, because increase, so the leakage current of nmos pass transistor GK1 increases from the amount of electrons of source electrode 334 introducing P-traps 333.
As mentioned above, according to the present invention, in erase operation, positive bias is applied to Overall word line.Therefore, can prevent the shallow phenomenon of wiping of the non-selecteed memory cell block that the leakage current owing to pass gate causes.
Although carried out above description with reference to various embodiment, should be appreciated that under the situation of the spirit and scope that do not deviate from the present invention and described claim those of ordinary skills can change and revise this patent
Cross-reference to related applications
The application requires the right of priority of the korean patent application submitted on March 10th, 2005 2005-0020182 number, and its content is herein incorporated by integral body by reference.
Claims (23)
1. flash memory device comprises:
Memory cell block, each has a plurality of storage unit of sharing local word line and bit line;
The X-demoder, it decodes row address signal, and the output decoder signal;
The piece selected cell, it is some in the select storage unit piece in response to decoded signal, and the local word line of selected memory cell block is connected respectively to corresponding Overall word line; And
High voltage generator, it produces the word line bias voltage in response to one of reading order, program command and erase command, and respectively the word line bias voltage that is produced is offered Overall word line in response to decoded signal,
Wherein, the word line bias voltage that produces in response to erase command by high voltage generator have respectively on the occasion of.
2. flash memory device as claimed in claim 1, wherein, high voltage generator also produces body voltage, drain bias and the source electrode bias voltage of storage unit in response to one of reading order, program command and erase command.
3. flash memory device as claimed in claim 2, wherein, the word line bias voltage that is produced in response to erase command by high voltage generator is lower than the body voltage of the storage unit that is produced in response to erase command by high voltage generator, and
Difference between these two voltages is greater than or equal to 15V.
4. flash memory device as claimed in claim 2, wherein, the piece selected cell comprises the piece switch unit that produces block selection signal in response to decoded signal; And
The pass gate circuit, it corresponds respectively to memory cell block and arranges, and is activated in response to block selection signal respectively or forbids,
Wherein, the pass gate circuit is connected to Overall word line the corresponding local word line of memory cell block respectively when being activated respectively.
5. flash memory device as claimed in claim 4, wherein, each pass gate circuit comprises pass gate, described pass gate is connected between the local word line of Overall word line and corresponding memory cell block, and conducting simultaneously or shutoff in response to one of block selection signal.
6. flash memory device as claimed in claim 5, wherein, each pass gate is the MOS transistor with single well structure.
7. flash memory device as claimed in claim 5, wherein, each pass gate is the MOS transistor with triple well structure.
8. flash memory device as claimed in claim 7, wherein, the body voltage that high voltage generator also will be used for wiping in response to erase command offers some of triple well of the pass gate of pass gate circuit.
9. flash memory device as claimed in claim 8, wherein, the body voltage that is used to wipe has negative value.
10. flash memory device as claimed in claim 9, wherein, the body voltage that is used to wipe is lower than the body voltage of the storage unit that is produced in response to erase command by high voltage generator, and the difference between these two voltages is less than or equal to the junction breakdown voltage of each pass gate.
11. flash memory device as claimed in claim 1, wherein, high voltage generator comprises:
First bias generator, it is in response to one of reading order, program command and erase command and decoded signal and produce drain bias and source electrode bias voltage;
Second bias generator, it is in response to one of reading order, program command and erase command and decoded signal and produce and read voltage, program voltage or erasing voltage as the word line bias voltage, and this word line bias voltage is offered Overall word line respectively; And
The body voltage generator, it produces the body voltage of storage unit in response to one of reading order, program command and erase command,
Wherein, erasing voltage have on the occasion of, and be lower than the body voltage of the storage unit that produces in response to erase command by the body voltage generator, and wherein, the difference between these two voltages is greater than or equal to 15V.
12. flash memory device as claimed in claim 11, wherein, second bias generator comprises:
First pump circuit, it produces in response to reading order and reads voltage;
Second pump circuit, it produces program voltage in response to program command;
The 3rd pump circuit, it produces erasing voltage in response to erase command; And
Biasing selected unit, it selects to read voltage, program voltage or erasing voltage in response to decoded signal, and selected voltage is outputed to Overall word line respectively, as the word line bias voltage.
13. flash memory device as claimed in claim 12, wherein, biasing selected unit comprises:
Select signal generator, it produces according to decoded signal and selects signal; And
Select circuit, it is connected respectively to Overall word line, and will read the Overall word line that one of voltage, program voltage and erasing voltage output to correspondence respectively in response to selecting signal.
14. flash memory device as claimed in claim 7, wherein, high voltage generator comprises:
First bias generator, it is in response to one of reading order, program command and erase command and decoded signal and produce drain bias and source electrode bias voltage;
Second bias generator, it is in response to one of reading order, program command and erase command and decoded signal and produce and read voltage, program voltage or erasing voltage as the word line bias voltage, and respectively this word line bias voltage is offered Overall word line, and
The body voltage generator, it produces the body voltage of storage unit in response to one of reading order, program command and erase command,
Wherein, erasing voltage have on the occasion of, and be lower than the body voltage of the storage unit that produces in response to erase command by the body voltage generator, and wherein, the difference between these two voltages is greater than or equal to 15V.
15. flash memory device as claimed in claim 14, wherein, high voltage generator also comprises the additional body voltage generator, it produces the body voltage that is used to wipe in response to erase command, and the body voltage that is produced is offered in the triple well of each pass gate of each pass gate circuit some, wherein, the body voltage that is used to wipe has negative value and has poorly with the body voltage of the storage unit that is produced in response to erase command by the body voltage generator, and described difference is less than or equal to the junction breakdown voltage of each pass gate.
16. flash memory device as claimed in claim 15, wherein, the additional body voltage generator comprises:
Pump circuit, it produces the body voltage that is used to wipe in response to erase command; And
The body voltage selected cell, it receives with reference to body voltage, select in response to selecting control signal with reference to one of body voltage and body voltage of being used to wipe, and selected voltage is outputed in the triple well of each pass gate of each pass gate circuit some.
17. flash memory device as claimed in claim 16, wherein, when erase command is activated, the selection control signal is activated, when selecting control signal to be activated, the body voltage that the selection of body voltage selected cell is used to wipe, and when selecting control signal to be under an embargo, the body voltage selected cell is selected with reference to body voltage.
18. a method of controlling the erase operation of flash memory device may further comprise the steps:
In response to erase command and row address signal, with each all have on the occasion of the word line bias voltage offer Overall word line respectively;
Body voltage is offered the storage unit of each memory cell block;
By ground voltage being offered overall situation drain electrode selection wire and overall source electrode selection wire, the drain electrode of storage unit and source electrode are floated; And
One of select storage unit piece in response to row address signal, and the local word line of selected memory cell block is connected to Overall word line.
19. method as claimed in claim 18 wherein, provides the word line bias voltage to comprise:
With the row address signal decoding, and the output decoder signal;
Produce in response to erase command have on the occasion of erasing voltage; And
In response to decoded signal erasing voltage is outputed to Overall word line respectively, as the word line bias voltage.
20. method as claimed in claim 19, wherein, erasing voltage is lower than the body voltage that offers storage unit, and the difference between body voltage and the erasing voltage is greater than or equal to 15V.
21. method as claimed in claim 18, wherein, the select storage unit piece also connects word line and comprises:
With the row address signal decoding, and the output decoder signal;
Export block selection signal in response to decoded signal; And
In response to block selection signal, activate respectively and be arranged in one of pass gate circuit between Overall word line and the memory cell block, and connect the local word line of one of Overall word line and memory cell block.
22. method as claimed in claim 21 also comprises: the body voltage that will be used for wiping offers some of triple well of the MOS transistor with triple well structure, and described MOS transistor is respectively the pass gate that comprises in the pass gate circuit.
23. method as claimed in claim 22, wherein, the body voltage that is used to wipe has negative value, and has poorly with the body voltage that offers storage unit, and described difference is less than or equal to the junction breakdown voltage of each pass gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20182/05 | 2005-03-10 | ||
| KR1020050020182A KR100673170B1 (en) | 2005-03-10 | 2005-03-10 | Flash memory device with improved erase function and method for controlling erase operation of the same |
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| Publication Number | Publication Date |
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| CN1832040A CN1832040A (en) | 2006-09-13 |
| CN100517508C true CN100517508C (en) | 2009-07-22 |
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| CNB200510128852XA Active CN100517508C (en) | 2005-03-10 | 2005-12-07 | Flash memory device with improved erase function and method for controlling erase operation of the same |
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| Country | Link |
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| US (2) | US7200039B2 (en) |
| JP (1) | JP2006252744A (en) |
| KR (1) | KR100673170B1 (en) |
| CN (1) | CN100517508C (en) |
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| US6327194B1 (en) * | 2000-04-25 | 2001-12-04 | Advanced Micro Devices, Inc. | Precise reference wordline loading compensation for a high density flash memory device |
| JP2001319486A (en) * | 2000-05-12 | 2001-11-16 | Mitsubishi Electric Corp | Non-volatile semiconductor memory |
| KR100474201B1 (en) * | 2002-05-17 | 2005-03-08 | 주식회사 하이닉스반도체 | Word line decoder of a NAND type flash memory |
| JP4005895B2 (en) * | 2002-09-30 | 2007-11-14 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| JP4156986B2 (en) * | 2003-06-30 | 2008-09-24 | 株式会社東芝 | Nonvolatile semiconductor memory device |
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| KR100673170B1 (en) * | 2005-03-10 | 2007-01-22 | 주식회사 하이닉스반도체 | Flash memory device with improved erase function and method for controlling erase operation of the same |
| JP2006331501A (en) * | 2005-05-24 | 2006-12-07 | Toshiba Corp | Semiconductor memory apparatus |
-
2005
- 2005-03-10 KR KR1020050020182A patent/KR100673170B1/en active IP Right Grant
- 2005-06-07 JP JP2005167480A patent/JP2006252744A/en active Pending
- 2005-06-10 TW TW094119176A patent/TWI269305B/en not_active IP Right Cessation
- 2005-06-16 US US11/160,278 patent/US7200039B2/en active Active
- 2005-06-20 DE DE102005028642A patent/DE102005028642A1/en not_active Withdrawn
- 2005-12-07 CN CNB200510128852XA patent/CN100517508C/en active Active
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2006
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Also Published As
| Publication number | Publication date |
|---|---|
| KR100673170B1 (en) | 2007-01-22 |
| TW200632918A (en) | 2006-09-16 |
| US7304892B2 (en) | 2007-12-04 |
| JP2006252744A (en) | 2006-09-21 |
| TWI269305B (en) | 2006-12-21 |
| CN1832040A (en) | 2006-09-13 |
| KR20060099142A (en) | 2006-09-19 |
| US20070121388A1 (en) | 2007-05-31 |
| US7200039B2 (en) | 2007-04-03 |
| US20060203550A1 (en) | 2006-09-14 |
| DE102005028642A1 (en) | 2006-09-14 |
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