200818332 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種高應力薄M沾制a + ，寻膜的製作方法，尤指一種於 應變矽金氧半導體電晶體上形诸古厭成丄―^ 〜成回壓應力薄膜的方法。 【先前技術】200818332 IX. Description of the invention: [Technical field of the invention] The present invention relates to a method for manufacturing a high-stress thin M-dip a+ film, especially a strain-formed ruthenium-oxygen semiconductor transistor.丄 ― ^ ~ into a method of compressive stress film. [Prior Art]
Ik著半導體製造技術越來越精密，積體電路也發生重大 的變革’使得電腦的運算性能和存儲容量突飛猛進，並帶 動周邊産業迅速發展。而半導體產業也如同摩爾定律所預 測的，以每18個月；％加一倍電晶體數目在積體電路上的速 度發展著，同時半導體製程也已經從1999年的0.18微米、 2001年的0.13微米、2003年的90奈米（〇·〇9微米），進入 到2005年65奈米（ 0.065微米製程）。 而隨著半導體製程進入深次微米時代，在半導體製程中 如何利用一高應力薄膜來提升金氧半導體(MOS)電晶體的 驅動電流(drive current)已逐漸成為一熱門課題。目前利用 高應力薄膜來提升金氧半導體電晶體的驅動電流可概分為 兩方面：其一係應用在鎳化矽等金屬矽化物形成前的多晶 矽應力層（poly stressor);另一方面則係應用在鎳化矽等金 屬發化物形成後之接觸洞姓刻停止層（contact etch stop layer，CESL) 〇 6 200818332 一般而言，多晶矽應力層的製程可容忍較高的熱效應 (thermal budget)，例如大於1〇〇〇。〇。然而，在接觸洞蝕刻 铋止層（CESL)的製程上由於需考量形成錄化石夕時不能忍受 較高熱效應的緣故，因此必須限制製程溫度小於43〇ΐ。 所以先前技術在製作接觸洞钱料止層（CESL)之高應力薄 膜時’ -般會先沈積-由氮化邦叫所組成的薄膜，然後 再藉由此薄膜來提升金氧半導體電晶體的驅動電流。 請參考第1圖至第3圖’第i圖至第3圖為習知製作 一高壓應力薄膜於PMOS t晶體表面的方法示意圖。如第 1圖所示，首先提供一半導體基底1〇，例如一矽基底，.且 半導體基底1G上包含有1極結構12。其中，閘極結構 12另包含有一閘極氧化層（gate⑽丨心)14、一位於閘極氧化 層14上之_ 16、-位於閘極16頂表面之覆蓋層(cap layer) 18以及一氧化物-氮化物_氧化物偏位侧壁子（ON。 offset SpaCer)20。一般而言，閘極氧化層14係由二氧化矽 (silicon dioxide，Si〇2)所構成，閘極16係由摻雜多晶矽 (doped polysilicon)所構成，而覆蓋層18則係由一氮化矽層 所組成，用以保護閘極16。此外，閘極結構12所在之主 動區域(active area)外圍的半導體基底1〇内另環繞有一淺 溝隔離(STI)22。 如第2圖所示，隨後進行一離子佈植(i〇n implantati〇n) 7 200818332 製程，以於側壁子20周圍之半導體基底10内形成〆源極/ 汲極區域26。接著於半導體基底10與閘極結構12表面藏 鍍一金屬層（圖未示），例如一鎳金屬層。然後進行一快速 升溫退火(rapid thermal annealing，RTA)製程，使該金屬層 與閘極16以及源極/汲極區域26接觸的部分反應成矽化金 屬層。最後再去除未反應的金屬層。 如第3圖所示，接著通入矽曱烷(silane，SiH4)與氨氣 (ammonia，NH3)，並進行一電漿增強化學氣相沈積(plasma enhanced chemical vapor deposition, PECVD)製程，以形成 一高壓應力薄膜(high compressive stress film)28覆蓋於閘 極結構12與源極/汲極區域26表面。然後藉由高壓應力薄 膜28來壓縮閘極16下方’亦即通道區（channel region)之 半導體基底’ 10的晶格排列，進而提升通道區的電洞遷移率 以及應變矽（strained silicon)PMOS電晶體之驅動電流（drive current) 〇 一般而έ，先剷技術係利用調整製程機台的高、低頻無 線電波的功率以及提高矽曱烷與氨氣比例的方式來製作出 高品質的高壓應力薄膜。然而，習知於4〇〇艽下的電漿增 強化學氣相沈積製程中最高僅能製作出具有_ 1 應力 的初鑛(as-deposite)薄膜。由於壓縮應力的不足，此薄膜將 會嚴重影響後續薄膜所產生的應力以及金氧半導體電晶體 8 200818332 的驅動電流。因此如何有效提升高壓應力薄膜之應力（stress) 即為目前業界一重要技術能力指標。 【發明内容】 因此本發明之主要目的係提供一種製作應變矽金氧半 導體電晶體的方法，以解決習知無法有效提升高壓應力薄 膜之應力的問題。 根據本發明之申請專利範圍，係揭露一種製作應變矽金 氧半導體電晶體的方法。首先提供一半導體基底，並於該 半導體基底上形成一閘極、至少一側壁子以及一源植/没極 區域。然後通入一前驅物(precursor)，再通入石夕曱烧(silane) 以及氨氣（ammonia)，並使該前驅物與矽曱烷以及氨氣反 應，以形成一高壓應力薄膜(high compressive film)於該閘 極與該源極/汲極區域表面。 本發明係於利用矽曱烷與氨氣形成氮化矽薄膜前先通 入一由四甲基矽烷、醚類、醛類、或羧酸類所組成的前驅 物’然後使该岫驅物與石夕甲炫與氨氣反應而產生如鍵 與/或Si_0_R鍵等雜質鍵結，進而藉由這些鍵結來大幅提 昇高壓應力薄膜的應力。因此，本發明方法除了可應用於 -般多晶石夕應力層（poly stressor)的製作，又可應用於接觸 洞敍刻停止層以及雙接觸洞姓刻停止層的製作，以有饮改 9 200818332 良應變矽金氧半導體電晶體的良率與效能。 【實施方式】 請參照第4圖至第6圖，第4圖至第6圖為本發明製作 -高壓應力薄膜於PMQS電晶體表面的方法示意圖。如第 4圖所示’首編一半導體基底6〇,例如一矽晶圓⑽㈣ 或一矽覆絕緣(SOI)基底，且半導體基底6〇上包含有—閘 極結構63。其中，閘極結構63包含有_閘極介電層^ -位於閘極介電層64上之閘極66、一位於間極化頂表面 之覆蓋層68以及一氧化物-氮化物-氧化物偏位側壁子 _〇細Spaeer)7G。—般而言，閘極介電層Μ可為一 利用熱^纽積等製朗形成之氧切錢魏合物等 絕緣物貝所構成，而覆蓋層6 > ⑽則可由一用以保護閘極66 之氮化矽層所組成。此外，間極紝 .. 外園之丰藤μ ““ 構所在之主動區域(AA) 外圍之+導體基底60内另環繞一淺溝隔離_，用來 使此PM0S電晶體與其他元件相隔離。 如第5圖所示，接著進γ 制 丁 離子佈植（ion implantation) 製程，以於閘極結構63周 π 阗之+導體基底60中形成一源 極/>及極區域74。緊接著進料 麵eaHng)製程，利用_ —快速升溫退火(_dth議1 極區域74内的摻雜質，並同：C的高溫來活化源緣 損之半導體基底60表面的曰^補在各離子佈植製程中受 _格結構。此外，亦可視產品需 200818332 求及功能性考量，另於源極/汲極區域74與閘極結構63之 間分別形成一輕摻雜汲極（LDD)或源極/汲極延伸 (source/drain extension)，或者於源極/汲極區域74與閘極 結構63表面再形成一自行對準金屬石夕化物（salicide)，此皆 為習知相關技藝者與通常知識者所熟知，在此不多加贅述。 然後如第6圖所示，進行一電漿增強化學氣相沈積 (plasma enhanced chemical vapor deposition，PECVD)製 程，以於閘極結構63與源極/汲極區域74表面形成一高壓 應力薄膜76。在本發明之一較佳實施例中，此PECVD是 先將半導體基底60置於一沉積反應室中，接著通入一由四 甲基石夕烧（tetra-methyl-silane)、醚類（ether)、搭類 (aldehyde).、或叛酸類（carboxylic acid)等組成當作前驅物 (precursor)，隨後再通入石夕曱烧(silane)以及氨氣(ammonia) 等主成分進行電漿增強化學氣相沈積，以於閘極結構63與 源極/汲極區域74表面形成一高壓應力薄膜76。其中，前 驅物之流量係介於30至3000克，該矽曱烷之流量係介於 30 每分鐘標準毫升(standard cubic centimeter per minute, seem)至3000sccm，且該氨氣之流量係介於30sccm至 2000sccm。此外，形成高壓應力薄膜76之高、低頻無線電 波的功率均係介於50瓦至3000瓦。 值得注意的是，本發明在進行電漿增強化學氣相沈積製 200818332 程的過程中，所通入的前驅物會與形成高壓應力薄膜76中 的梦甲烧與氨氣反應並產生各種雜質（impurity)鍵結，例如 0/CH3/0-CH3等。請參照第7圖，第7圖為本發明之高壓 應力薄膜之傅立葉轉換紅外光譜（Fourier Transform Infrared Spectroscopy, FTIR)示意圖。如第7圖所示，藉由 前驅物與矽甲炫與氨氣的反應，本發明於電漿增強化學氣 相沈積製程中所產生的高壓應力薄膜76可於-2.86GPa與 -2.7GPa的壓力下產生如Si-0-(CH3)等之Si-0-R鍵與/或如 SKH；j鍵等之Si-R鍵鍵雜質鍵結’並藉由這些鍵結來大幅 提昇高壓應力薄膜76的應力，以壓縮閘極66下方，亦即 通道區内半導體基底60的晶格排列，進而提升通道區的電 洞遷移率以及PMOS電晶體的驅動電流。 請參照第8圖，第8圖為本發明之高壓應力薄膜與習知 高壓應力薄膜之應力與PMOS離子增益百分比之比較圖。 如第8圖所示，當傳統製程與本發明所沈積的高壓應力薄 膜的沈積厚度同為1000埃(angstrom)時，本發明可藉由前 驅物的通入來將初鍵(aS-deposite)薄膜的應力由-1 6GPa大 幅提昇至_2.70?3左右，並同時將PMOS的離子增益百分 比（Ion gain percentage)由 24%提昇至 45%。 請參照第9圖，第9圖為本發明之高壓應力薄膜與 PMOS離子增益之關係示意圖。如第9圖所示，在相同 12 200818332 PMOS離子增益(20%)的條件下，當高壓應力薄膜的應力為 -1.6GPA時’所需的薄膜厚度係約為85〇埃。根據本發明 之較佳實施例，本發明可將高壓應力薄膜的應力提升至 -2.7GPA，因此可於相同離子增益(2〇%)的條件下降低所需 薄膜的厚度至450# ’進而能大幅提昇後續餘刻接觸洞的 製程範嘴(process window)。此外，如將薄膜的應力維持 -2.7GPa，本發明又可將高壓應力薄膜的厚度增加至1〇〇〇 埃，進而可將PMOS的離子增益提高至45%。 請參照第10圖至第12圖，第10圖至第12圖為本發明 另一實施例製作接觸洞蝕刻停止層（c E s L)之方法示意圖。. 如第10圖所示，首先在半導體基底8〇上形成由閘極介電 層82與閘極84所構成的閘極結構86，接著進行一離子植 入步驟，以於半導體基底8〇中形成輕摻雜汲極結.構9〇。· 隨後於閘極結構86的側壁形成襯墊層87及側壁子88，並 進行另一離子植入步驟，以於側壁子88兩侧的半導體基底 80中形成源極/汲極區域92。接著於半導體基底80表面濺 鍍一金屬層94，例如一鎳金屬層，且金屬層94係覆蓋於 閘極84、側壁子88、及源極/沒極區域92表面。如第u 圖所示’接著進行一快速升溫退火（rapid thermal anneal, RTA)製程’使金屬層94與閘極84以及源極/汲極區域92 接觸的部分反應成矽化金屬層96，完成一自行對準金屬矽 化物製程(salicide)，最後再去除未反應之金屬層94。 13 200818332 如第12圖所示，接著進行一電漿增強化學氣相沈積 (PECVD)製程，以於閘極結構86、侧壁子88與源極/及極 區域92表面形成一高壓應力薄膜94。在本發明之一較佳 實施例中，此PECVD是先將半導體基底8〇置於一沉積反 應至中’接著通入一由四曱基石夕烧(tetra methyl-Silane)、鱗 類（ether)、备類（aldehyde)、或叛酸類（carb〇Xyiic acid)等組 成當作前驅物(precursor)，隨後再通入矽甲烷(silane)以及氨 氣(ammonia)等主成分進行電漿增強化學氣相沈積，以使該 前驅物與矽甲烷（silane)以及氨氣（amm〇nia)反應產，生如 O/CHVO-CH3等之鍵結，進而於閘極結構86、側壁子88 與源極/汲極區域92表面形成一含有Si-CH3鍵以及Si_〇_R 鍵之氮石夕化合物層當做揍觸洞姓刻停止層98。其中，：前驅 物之流量係介於30至3000克，該矽甲烷之流量係介於3〇 seem至3000 SCCm，且該氨氣之流量係介於3〇 sccm至2〇〇〇 seem。此外，形成接觸洞姓刻停止層98之高、低頻無線電 波的功率均係介於50瓦至3000瓦。 隨後，使用者可於接觸洞蝕刻停止層98完成後覆蓋一 層間介電層（inter-layer dielectric，ILD)(圖未示）於接觸洞姓 刻停止層98表面。接著利用一圖案化光阻層（圖未示）作為 姓刻遮罩，然後進行一非等向性姓刻，以於該層間介電層 中形成複數個接觸洞（圖未示），做為電子元件連接的橋樑。 14 200818332 請參照第13圖至第18圖，第13圖至第18圖為本發明 另一實施例製作雙接觸洞蝕刻停止層（dual CESL)之方法示 意圖。如第12圖所示，首先提供一個以淺溝隔離(STI)1〇6 區隔出NMOS電晶體區102以及PMOS電晶體區1〇4的半 導體基底1〇〇，且各NMOS電晶體區102及PMOS電晶體 區104上各具有一 NMOS閘極1〇8、一 PMOS閘極11〇以 及一設置於各閘極與半導體基底100之間的閘極介電層 114。接著於NMOS閘極108與PMOS閘極110的側壁表 面各別形成一由矽氧層與氮化矽層所構成的襯墊層112。 然後進行一離子佈植製程，以於NMOS閘極108與 PMOS閘極110周圍的半導體基底1〇〇中各形成一源極/汲 極區域116與117。緊接著進行一快速升溫退火製程，利用 900至1050°C的高溫來活化源極/汲極區域116與in内的 摻雜質，並同時修補在各離子佈植製程中受損之半導體基 底100表面的晶格結構。此外，亦可視產品需求及功能性 考量，另於源極/汲極區域116、117與各閘極108、110之 間分別形成一輕摻雜汲極(LDD)118與119。 接著於半導體基底1〇〇表面濺鍍一金屬層（圖未示），例 如一鎳金屬層，然後進行一快速升溫退火(RTA)製程，使金 屬層與NMOS閘極1〇8、PMOS閘極110以及源極/汲極區 15 200818332 域116與117接觸的部分反應成矽化金屬層115,完成自行 對準金屬矽化物製程(salicide)。 在去除未反應之金屬層之後，接著進行一電漿增強化學 氣相沈積(PECVD)製程，以於NMOS電晶體區1〇2與PMOS 電晶體區104中的石夕化金屬層115表面形成一高張應力薄 膜(high tensile stress film)120 〇 然後如第14 ·圖所示，進行一光阻塗佈、曝光以及顯影 製程，以形成一圖案化光阻層122並覆蓋整個NMOS電晶 體區102。接著進行一蝕刻製程，去除未被圖案化光阻層 122覆蓋的區域，亦即覆蓋於PMOS電晶體區104上的高 張應力薄膜120，以形成一高張應力薄膜120於NMOS閘 極108與源極/汲極區域Γ16表面。 如第15圖所示，接著移除覆蓋於NMOS電晶體區102 上的圖案化光阻層122。如第16圖所示，隨後進行一電漿 增強化學氣相沈積(PECVD)製程：先通入一由四甲基矽烷 (tetra-methyΙ-silane)、醚類（ether)、醛類（aldehyde)、或羧酸 類（carboxylic acid)等組成的前驅物（precursor)，再通入矽曱 烷(silane)以及氨氣(ammonia)等主成分，並使該前驅物與隨 後通入之石夕甲烧（silane)以及氨氣（ammonia)反應，以於 NMOS電晶體區102與PMOS電晶體區1〇4上形成一高壓 16 200818332 應力薄膜(high compressive stress film)124。其中，前驅物 之流量係介於30至3000克，該矽甲烷之流量係介於3〇 seem至3000 seem，且該氨氣之流量係介於30 seem至2〇〇〇 seem。此外，形成高壓應力薄膜124之高、低頻無線電波 的功率均係介於50瓦至3000瓦之間。 如同先前所述之實施例，本實施例之高壓應力薄祺124 同樣係將所通入的前驅物與高壓應力薄膜124中的矽甲烷 與氨氣反應並產生如Si_CH3鍵以及Si-0-R鍵等雜質鍵 結，進而可藉由這些鍵結大幅提昇高壓應力薄膜124的壓 縮應力。‘ 進行一光阻塗佈、曝光以及顯影Ik is becoming more and more sophisticated in semiconductor manufacturing technology, and major changes have taken place in the integrated circuit. The computer's computing performance and storage capacity have soared, and the surrounding industries have developed rapidly. The semiconductor industry is also predicted by Moore's Law, every 18 months; % doubles the number of transistors on the integrated circuit, and the semiconductor process has also been 0.18 micron in 1999 and 0.13 in 2001. Micron, 90 nm in 2003 (〇·〇9 μm), entered the 65 nm (0.065 μm process) in 2005. As the semiconductor process enters the deep submicron era, how to use a high stress film to enhance the drive current of a metal oxide semiconductor (MOS) transistor has become a hot topic in semiconductor manufacturing. At present, the use of high-stress films to enhance the driving current of MOS transistors can be divided into two aspects: one is applied to the poly-stressor before the formation of metal bismuth such as nickel bismuth; on the other hand, Contact etch stop layer (CESL) 形成6 200818332 In general, the process of polycrystalline yttrium stress layer can tolerate higher thermal budgets, for example, in the case of metal halides such as nickel bismuth. More than 1〇〇〇. Hey. However, in the process of contact hole etching stop layer (CESL), it is necessary to limit the process temperature to less than 43 Å because of the high thermal effect that cannot be tolerated when the formation of the recording stone is considered. Therefore, the prior art in the fabrication of the high-stress film of the contact hole material stop layer (CESL) will be deposited first--a film composed of nitriding state, and then the film is used to enhance the MOS transistor. Drive current. Please refer to Fig. 1 to Fig. 3'th to Fig. 3 for a schematic view of a method for fabricating a high voltage stress film on the surface of a PMOS t crystal. As shown in Fig. 1, a semiconductor substrate 1 is first provided, such as a germanium substrate, and a semiconductor structure 1G includes a 1-pole structure 12. The gate structure 12 further includes a gate oxide layer (gate), a _16 on the gate oxide layer 14, a cap layer 18 on the top surface of the gate 16, and an oxidation. Material-nitride_oxide offset sidewall (ON. offset SpaCer) 20. In general, the gate oxide layer 14 is composed of silicon dioxide (Si2), the gate 16 is composed of doped polysilicon, and the cap layer 18 is nitrided. The enamel layer is formed to protect the gate 16. In addition, a shallow trench isolation (STI) 22 is surrounded by a semiconductor substrate 1 in the periphery of the active area where the gate structure 12 is located. As shown in FIG. 2, an ion implantation process (2008) is performed to form a germanium source/drain region 26 in the semiconductor substrate 10 around the sidewall 20. A metal layer (not shown), such as a nickel metal layer, is then deposited on the surface of the semiconductor substrate 10 and the gate structure 12. A rapid thermal annealing (RTA) process is then performed to react the portion of the metal layer that is in contact with the gate 16 and the source/drain regions 26 into a deuterated metal layer. Finally, the unreacted metal layer is removed. As shown in Fig. 3, silane (SiH4) and ammonia (NH3) are introduced, and a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a plasma enhanced chemical vapor deposition (PECVD) process. A high compressive stress film 28 covers the surface of the gate structure 12 and the source/drain regions 26. The lattice arrangement of the semiconductor substrate '10 under the gate region, that is, the channel region, is then compressed by the high voltage stress film 28, thereby improving the hole mobility and the strained silicon PMOS of the channel region. The drive current of the crystal is general and flawless. The first shovel technology uses high- and low-frequency radio waves to adjust the power of the process machine and increase the ratio of decane to ammonia to produce high-quality high-pressure stress film. . However, it is known that only the as-deposite film having a _ 1 stress can be produced in the plasma enhanced chemical vapor deposition process under the 4 〇〇艽. Due to the lack of compressive stress, the film will seriously affect the stress generated by the subsequent film and the drive current of the MOS transistor 8 200818332. Therefore, how to effectively improve the stress of the high-pressure stress film is an important technical capability index in the industry. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method of fabricating a strained gold-oxide semiconductor transistor to solve the problem that the stress of the high-pressure stress film cannot be effectively improved. In accordance with the scope of the present invention, a method of making a strained gold oxide semiconductor transistor is disclosed. First, a semiconductor substrate is provided, and a gate, at least one sidewall, and a source/drain region are formed on the semiconductor substrate. Then a precursor is introduced, and then silane and ammonia are introduced, and the precursor is reacted with decane and ammonia to form a high compressive film (high compressive film). Film) is on the surface of the gate and the source/drain region. The present invention is based on the use of decane and ammonia to form a tantalum nitride film prior to the introduction of a precursor consisting of tetramethyl decane, ethers, aldehydes, or carboxylic acids, and then the ruthenium drive and stone The singular reaction with the ammonia gas produces an impurity bond such as a bond and/or a Si_0_R bond, and the bond of the high-pressure stress film is greatly increased by these bonds. Therefore, the method of the present invention can be applied not only to the fabrication of a polycrystalline polyorthorium, but also to the fabrication of a contact hole stop layer and a double contact hole surname stop layer. 200818332 Yield and performance of good strain 矽 MOS transistors. [Embodiment] Please refer to Figs. 4 to 6 , and Figs. 4 to 6 are schematic views showing a method of fabricating a high voltage stress film on the surface of a PMQS transistor. As shown in Fig. 4, a semiconductor substrate 6 is fabricated, for example, a wafer (10) (4) or a silicon-on-insulator (SOI) substrate, and the semiconductor substrate 6 includes a gate structure 63. The gate structure 63 includes a gate dielectric layer, a gate 66 on the gate dielectric layer 64, a cap layer 68 on the interpolarized top surface, and an oxide-nitride-oxide. Deviated side wall _ 〇 fine Spaeer) 7G. In general, the gate dielectric layer can be made of an insulating material such as an oxygen-cutting compound formed by a heat and a product, and the cover layer 6 > (10) can be used for protection. The tantalum layer of the gate 66 is composed of a tantalum layer. In addition, the 纴 之 纴 丰 “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 主动 主动 主动 主动 主动 主动 主动 主动 + + + + + + + + + + + + + + + + + + + + + + + + As shown in Fig. 5, a gamma ion implantation process is then performed to form a source/> and a polar region 74 in the + conductor substrate 60 of the gate structure 63 π 阗. Immediately following the feed surface eaHng) process, using _- rapid thermal annealing (_dth to discuss the doping in the 1-pole region 74, and the same as: C high temperature to activate the source of the semiconductor substrate 60 surface damage The ion implantation process is subject to the _ lattice structure. In addition, the product needs 200818332 for functional considerations, and a lightly doped drain (LDD) is formed between the source/drain region 74 and the gate structure 63, respectively. Or a source/drain extension, or a self-aligned salicide on the surface of the source/drain region 74 and the gate structure 63, which are known in the art. It is well known to those skilled in the art and will not be described here. Then, as shown in FIG. 6, a plasma enhanced chemical vapor deposition (PECVD) process is performed to gate the structure 63 and the source. A high voltage stress film 76 is formed on the surface of the pole/drain region 74. In a preferred embodiment of the invention, the PECVD is performed by placing the semiconductor substrate 60 in a deposition reaction chamber and then introducing a tetramethyl stone. Tetra-methyl-silane, ether Ether), aldehyde, or carboxylic acid is used as a precursor, and then passed into the main component such as silane and ammonia for plasma treatment. Enhanced chemical vapor deposition to form a high-pressure stress film 76 on the surface of the gate structure 63 and the source/drain region 74. The flow rate of the precursor is between 30 and 3000 grams, and the flow rate of the decane is introduced. The standard cubic centimeter per minute (m) is 3,000 sccm, and the flow rate of the ammonia gas is between 30 sccm and 2000 sccm. In addition, the high and low frequency radio waves of the high pressure stress film 76 are both interposed. 50 watts to 3000 watts. It is worth noting that during the process of plasma enhanced chemical vapor deposition (200818332), the precursors introduced will be combined with the formation of the high pressure stress film 76. The reaction produces various impurity bonds, such as 0/CH3/0-CH3, etc. Please refer to Fig. 7, which is a Fourier Transform Infrared Spectroscopy (FTI) of the high pressure stress film of the present invention. R) Schematic. As shown in Fig. 7, the high pressure stress film 76 produced by the present invention in the plasma enhanced chemical vapor deposition process can be used at -2.86 GPa by the reaction of the precursor with the bromide and ammonia gas. Under the pressure of -2.7 GPa, a Si-0-R bond such as Si-0-(CH3) and/or a Si-R bond impurity bond such as SKH;j bond is generated and is substantially increased by these bonds. The stress of the high voltage stress film 76 is increased to compress the lattice arrangement of the semiconductor substrate 60 under the gate 66, that is, the channel region, thereby increasing the hole mobility of the channel region and the driving current of the PMOS transistor. Referring to Fig. 8, Fig. 8 is a graph comparing the stress of the high-pressure stress film of the present invention with the conventional high-pressure stress film and the percentage of PMOS ion gain. As shown in Fig. 8, when the conventional process and the deposition thickness of the high-pressure stress film deposited by the present invention are 1000 angstroms, the present invention can introduce the initial bond (aS-deposite) by the passage of the precursor. The stress of the film is greatly increased from -1 6 GPa to about 2.0.7?3, and the Ion gain percentage of the PMOS is increased from 24% to 45%. Please refer to FIG. 9. FIG. 9 is a schematic diagram showing the relationship between the high voltage stress film and the PMOS ion gain of the present invention. As shown in Fig. 9, under the same 12 200818332 PMOS ion gain (20%), when the stress of the high-pressure stress film is -1.6 GPA, the required film thickness is about 85 Å. According to a preferred embodiment of the present invention, the stress of the high-pressure stress film can be raised to -2.7 GPA, so that the thickness of the desired film can be lowered to 450# in the same ion gain (2%). The process window of the subsequent contact hole is greatly improved. Further, if the stress of the film is maintained at -2.7 GPa, the present invention can increase the thickness of the high-pressure stress film to 1 Å, thereby increasing the ion gain of the PMOS to 45%. Referring to FIGS. 10 to 12, FIGS. 10 to 12 are schematic views showing a method of fabricating a contact hole etch stop layer (c E s L) according to another embodiment of the present invention. As shown in FIG. 10, a gate structure 86 composed of a gate dielectric layer 82 and a gate electrode 84 is first formed on the semiconductor substrate 8A, followed by an ion implantation step for the semiconductor substrate 8A. Form a lightly doped yttrium junction. A pad layer 87 and sidewall spacers 88 are then formed on the sidewalls of the gate structure 86 and another ion implantation step is performed to form source/drain regions 92 in the semiconductor substrate 80 on either side of the sidewall spacers 88. A metal layer 94, such as a nickel metal layer, is then sputtered over the surface of the semiconductor substrate 80, and the metal layer 94 covers the surface of the gate 84, the sidewall spacers 88, and the source/nominal regions 92. The portion of the metal layer 94 in contact with the gate 84 and the source/drain region 92 is reacted into a deuterated metal layer 96 as shown in Fig. 5, followed by a rapid thermal anneal (RTA) process. Self-alignment of the metal telluride salicide, and finally removal of the unreacted metal layer 94. 13 200818332 As shown in FIG. 12, a plasma enhanced chemical vapor deposition (PECVD) process is then performed to form a high voltage stress film 94 on the surface of the gate structure 86, the sidewalls 88 and the source/polar regions 92. . In a preferred embodiment of the invention, the PECVD is performed by first placing a semiconductor substrate 8 in a deposition reaction and then introducing a tetramethyl-Silane, an ether. The composition of aldehyde, or carb〇Xyiic acid is used as a precursor, and then the main components such as silane and ammonia are used for plasma-enhanced chemical gas. Phase deposition to react the precursor with silane and ammonia (amm〇nia), such as bonding of O/CHVO-CH3, etc., and further to the gate structure 86, the sidewalls 88 and the source On the surface of the /polarizing region 92, a nitriding compound layer containing a Si-CH3 bond and a Si_〇_R bond is formed as a stop layer 98. Wherein: the flow rate of the precursor is between 30 and 3000 grams, the flow rate of the helium methane is between 3 〇 seem and 3000 SCCm, and the flow rate of the ammonia gas is between 3 〇 sccm and 2 〇〇〇 seem. In addition, the power of the high-frequency, low-frequency radio waves forming the contact hole stop layer 98 is between 50 watts and 3000 watts. Subsequently, the user may cover an inter-layer dielectric (ILD) (not shown) on the surface of the contact hole stop layer 98 after the contact hole etch stop layer 98 is completed. Then, a patterned photoresist layer (not shown) is used as the mask of the surname, and then an anisotropic surname is formed to form a plurality of contact holes (not shown) in the interlayer dielectric layer, as A bridge connecting electronic components. 14 200818332 Referring to FIGS. 13 to 18, FIGS. 13 to 18 are schematic views showing a method of fabricating a dual contact hole etch stop layer (dual CESL) according to another embodiment of the present invention. As shown in FIG. 12, first, a semiconductor substrate 1A is provided which partitions the NMOS transistor region 102 and the PMOS transistor region 1〇4 by shallow trench isolation (STI) 1〇6, and each NMOS transistor region 102 The PMOS transistor region 104 has an NMOS gate 1 〇 8 , a PMOS gate 11 〇 , and a gate dielectric layer 114 disposed between each gate and the semiconductor substrate 100 . Next, a pad layer 112 composed of a tantalum oxide layer and a tantalum nitride layer is formed on the sidewall surfaces of the NMOS gate 108 and the PMOS gate 110, respectively. An ion implantation process is then performed to form a source/drain region 116 and 117 in each of the semiconductor substrate 1A around the NMOS gate 108 and the PMOS gate 110. A rapid thermal annealing process is then performed, using a high temperature of 900 to 1050 ° C to activate the dopants in the source/drain regions 116 and in, and simultaneously repairing the damaged semiconductor substrate 100 in each ion implantation process. The lattice structure of the surface. In addition, depending on product requirements and functional considerations, a lightly doped drain (LDD) 118 and 119 is formed between the source/drain regions 116, 117 and the gates 108, 110, respectively. Then, a metal layer (not shown), such as a nickel metal layer, is sputtered on the surface of the semiconductor substrate 1 and then subjected to a rapid thermal annealing (RTA) process to make the metal layer and the NMOS gate 1 〇 8 and the PMOS gate. 110 and source/drain regions 15 200818332 The portions of the domains 116 and 117 that are in contact with each other are reacted into a deuterated metal layer 115 to complete the self-alignment of the metal salicide process. After removing the unreacted metal layer, a plasma enhanced chemical vapor deposition (PECVD) process is then performed to form a surface of the NMOS transistor region 1〇2 and the surface of the iridium metal layer 115 in the PMOS transistor region 104. A high tensile stress film 120 〇 is then subjected to a photoresist coating, exposure, and development process as shown in FIG. 14 to form a patterned photoresist layer 122 and cover the entire NMOS transistor region 102. Then, an etching process is performed to remove the region not covered by the patterned photoresist layer 122, that is, the high tensile stress film 120 covering the PMOS transistor region 104, to form a high tensile stress film 120 on the NMOS gate 108 and the source. / bungee area Γ 16 surface. As shown in FIG. 15, the patterned photoresist layer 122 overlying the NMOS transistor region 102 is then removed. As shown in Fig. 16, a plasma enhanced chemical vapor deposition (PECVD) process is followed by first introduction of tetra-methy-silane, ether, or aldehyde. Or a precursor of a carboxylic acid or the like, and then a main component such as silane or ammonia, and the precursor and the subsequently introduced stone (silane) and ammonia reaction to form a high pressure 16 200818332 high compressive stress film 124 on the NMOS transistor region 102 and the PMOS transistor region 1〇4. Wherein, the flow rate of the precursor is between 30 and 3000 grams, the flow rate of the helium methane is between 3 〇 seem and 3000 seem, and the flow rate of the ammonia gas is between 30 seem and 2 〇〇〇 seem. In addition, the high and low frequency radio waves forming the high voltage stress film 124 are between 50 watts and 3000 watts. As in the previously described embodiment, the high-pressure stress enthalpy 124 of the present embodiment also reacts the introduced precursor with the methane in the high-pressure stress film 124 and ammonia gas to produce, for example, Si_CH3 bonds and Si-0-R. Bonds such as bonds are bonded, and the compressive stress of the high-pressure stress film 124 can be greatly increased by these bonds. ‘ Perform a photoresist coating, exposure and development
然後如第17圖所示 製程，以形成一圖案化 體區104。接著進行一 126覆蓋的區域，亦即, CESL)之實施The process is then performed as shown in Fig. 17 to form a patterned body region 104. Then proceed to a 126 coverage area, ie, CESL) implementation
108下方之半導體基底ι〇〇 7溽膘120來拉大NMOS閘極 的晶格排列，同時利用高壓應 根據本製作雙接觸―刻停止層㈣ 例， 200818332 力薄膜m級缩PM0S閘極110下方之半導體基底ι〇〇 的晶格排列，進而提升NM0S電晶體以及pM〇s電晶體的 驅動電流。 如第18 S所示，接著覆蓋一層間介電層（inter-— didectde，ILD⑽於高張應力薄獏⑶與高壓應力薄膜 124表面。然後利用-圖案化光阻層（圖未示)作為姓刻遮 罩，將高張應力薄膜12〇與高壓應力薄膜124作為一接觸 洞侧停止層’並進行-㈣向性_，以於和介電層 128中形成複數個接觸洞13G，做錢子元件連接的橋襟曰。 此外，不偈限於先前第13圖至第18圖所述先製作高張 應力薄膜然後再製作高壓應力薄膜的順序，本發明又可先 形成一高壓應力薄膜於PMOS電晶體上，然後於進行相對 應之蝕刻製程後形成一高張應力薄膜於NM〇s電晶體上。 隨後再形成所需層間介電層與接觸洞於層間介電層於高張 應力薄膜與南壓應力薄膜上。 綜上所述，相較於習知製作高壓應力薄膜的方法，本發 明係於利用矽甲烷與氨氣形成氮化矽薄膜前先通入一由四 甲基矽烷、醚類、醛類、或羧酸類等組成的前驅物，然後 使該前驅物與矽甲烷與氨氣反應而產生如Si-R鍵以及 Si_0-R鍵等雜質鍵結，進而藉由這些鍵結來大幅提昇高壓 200818332 應力薄膜的應力。因此，本發明方法除了可應用於一般多 晶矽應力層（poly stressor)的製作，又可應用於接觸洞蝕刻 停止層以及雙接觸洞钱刻停止層的製作，以有效改良應變 碎金氧半導體電晶體的良率與效能。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖為習知製作—高壓應力薄膜於pM〇s電晶 體表面的方法示意圖。 第4圖至第6圖為本發明製作一高壓應力薄膜於pM〇s電 晶體表面的方法示意圖。 第7圖為本發明之高壓應力薄.膜之傅立葉轉換紅外光譜 (FTIR)示意圖。 第8圖為本發明之高壓應力賴與f知高壓應力薄膜之應 力與PM0S離子增益百分比之比較圖。 第9圖為本發明之高壓應力薄膜與_s離子增益之關係 不意圖。 第10圖至f 12圖為本發明另一實施例製作接觸洞姓刻停 止層之方法示意圖。 第13圖至第18圖為本發明灵 ^ ^ μ M aat a另一實施例製作雙接觸洞蝕刻 停止層之方法示意圖。 19 200818332 【主要元件符號說明】 10 半導體基底 12 14 閘極氧化層 16 18 覆蓋層 20 22 淺溝隔離 26 28 高壓應力薄膜 60 62 淺溝隔離 63 64 閘極氧化層 66 68 覆蓋層 ’ 70 74 源極/汲極區域 76 80 半導體基底 82 84 閘極 86 87 襯塾層 .88 90 輕摻雜汲極結構 92 94 金屬層 96 98 接觸洞餘刻停止層 100 102 NMOS電晶體區 104 106 淺溝隔離 108 110 PMOS閘極 112 114 閘極介電層 115 116 源極/汲極區域 117 118 輕摻雜汲極 119 閘極結構 閘極 側壁子 源極/汲極區域 半導體基底 閘極結構 閘極 側壁子 高壓應力薄膜 閘極介電層 閘極結構 側壁子 源極/ >及極區域 矽化金屬層 半導體基底 PMOS電晶體區 NMOS閘極 襯墊層 石夕化金屬層 源極/沒極區域 輕摻雜汲極 20 200818332 120 高張應力薄膜 122 圖案化光阻層 124 高壓應力薄膜 126 圖案化光阻層 128 層間介電層 130 接觸洞 21The semiconductor substrate ι〇〇7溽膘120 below 108 is used to pull up the lattice arrangement of the NMOS gate, and the high voltage should be used according to the two-contact-cut stop layer (4). In this case, the 200818332 force film m-level shrink PM0S gate 110 The lattice arrangement of the semiconductor substrate ι〇〇 further enhances the driving current of the NM0S transistor and the pM〇s transistor. As shown in Fig. 18S, an interlayer dielectric layer (inter--dectect, ILD (10) is applied to the surface of the high tensile stress thin layer (3) and the high-voltage stress film 124. Then, a patterned photoresist layer (not shown) is used as the surname. The mask, the high tensile stress film 12 〇 and the high voltage stress film 124 are used as a contact hole side stop layer 'and a - (tetra) directional _ to form a plurality of contact holes 13G in the dielectric layer 128 to be connected to the money component In addition, the present invention is not limited to the prior art of preparing a high tensile stress film and then fabricating a high voltage stress film as described in FIGS. 13 to 18, and the present invention may first form a high voltage stress film on the PMOS transistor. Then, a high tensile stress film is formed on the NM〇s transistor after performing the corresponding etching process, and then the desired interlayer dielectric layer and the contact hole are formed on the interlayer dielectric layer on the high tensile stress film and the south compressive stress film. In summary, the present invention is based on a conventional method for producing a high-pressure stress film, which is obtained by using methane and ammonia to form a tantalum nitride film, and then introducing a tetramethyl decane, an ether, an aldehyde, or Carboxylic acid The precursor is composed of the precursor, and then the precursor is reacted with methane and ammonia to generate impurity bonds such as Si-R bond and Si_0-R bond, thereby greatly increasing the stress of the high-pressure 200818332 stress film by these bonds. Therefore, the method of the present invention can be applied not only to the fabrication of a general polycrystalline stressor but also to the fabrication of a contact hole etch stop layer and a double contact hole stop layer to effectively improve the strained metal oxide semiconductor. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. 1 to 3 are schematic views showing a method of fabricating a high-voltage stress film on the surface of a pM〇s transistor. FIGS. 4 to 6 show a method for fabricating a high-voltage stress film on the surface of a pM〇s transistor. Fig. 7 is a schematic diagram of the Fourier transform infrared spectroscopy (FTIR) of the high pressure stress thin film of the present invention. Fig. 8 is a view of the high pressure stress and the high pressure stress film of the present invention. Comparison with the PM0S ion gain percentage. Fig. 9 is a schematic view showing the relationship between the high voltage stress film and the _s ion gain of the present invention. Figs. 10 to f12 show another embodiment of the present invention. FIG. 13 to FIG. 18 are schematic diagrams showing a method for fabricating a double contact hole etch stop layer according to another embodiment of the present invention. 19 200818332 [Major component symbol description] 10 Semiconductor substrate 12 14 gate Polar oxide layer 16 18 Cover layer 20 22 Shallow trench isolation 26 28 High voltage stress film 60 62 Shallow trench isolation 63 64 Gate oxide layer 66 68 Cover layer ' 70 74 Source/drain region 76 80 Semiconductor substrate 82 84 Gate 86 87 lining layer. 88 90 lightly doped 汲 structure 92 94 metal layer 96 98 contact hole residual stop layer 100 102 NMOS transistor region 104 106 shallow trench isolation 108 110 PMOS gate 112 114 gate dielectric layer 115 116 Source/drain region 117 118 lightly doped drain 119 gate structure gate sidewall source/drain region semiconductor substrate gate structure gate sidewall high voltage stress film gate dielectric layer Gate structure sidewall source/gt; and pole region deuterated metal layer semiconductor substrate PMOS transistor region NMOS gate pad layer Shihua metal layer source/no-polar region lightly doped gate 20 200818332 120 high tensile stress film 122 patterned photoresist layer 124 high voltage stress film 126 patterned photoresist layer 128 interlayer dielectric layer 130 contact hole 21