JP3954589B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a field effect transistor.

  In order to increase the functionality of integrated circuits, it is necessary to improve the performance of elements such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The enhancement of the performance of the element has been basically performed by the proportional reduction law, but various problems have occurred at the boundary of the 0.1 μm (gate length) generation. One of them is a problem of a gate insulating film.

  Conventionally, SiO2 has been used for the gate insulating film. However, since SiO 2 has a low relative dielectric constant (about 3.9), the leakage current between the gate electrode and the semiconductor substrate increases at a gate insulating film thickness of 3 nm required for the 0.1 μm generation gate insulating film.

  Therefore, it has been studied to suppress the leakage current by using a high dielectric insulating film having a high relative dielectric constant (about 10 or more). Examples of the high dielectric insulating film include metal oxides such as ZrO 2 and HfO 2, and mixed crystal compounds (so-called silicates) of these with SiO 2.

However, it has been clarified that when these high dielectric insulating films are combined with a gate electrode such as polycrystalline Si, the threshold fluctuation of the MOSFET becomes large (see Non-Patent Document 1). The threshold fluctuation is very large, and it is difficult to adjust the threshold by the impurity concentration of the semiconductor substrate that is normally performed.
C. Hobbs, etal., 2003 Tech. Digest of VLSI symposium, 4.

  The inventors investigated the cause of this threshold fluctuation and found the following.

  Usually, the gate electrode forming step is performed in the atmosphere containing hydrogen or hydrogen using CVD (Chemical Vapor Deposition) after the gate insulating film forming step. At this time, the surface of the high dielectric insulating film is reduced, and the activated metal atoms are exposed. This metal atom reacts with a semiconductor atom such as Si or Ge used for the gate electrode, and charges are formed at the interface between the gate electrode and the gate insulating film. This charge is the cause of MOSFET threshold fluctuations.

  In order to suppress this charge formation, it is conceivable to form the gate electrode after coating the gate insulating film with another type of insulating film. However, since the formation process of the other type of insulating film normally uses CVD, it has been found that metal atoms are exposed to the surface after entering the other type of insulating film, and the same phenomenon occurs.

  On the other hand, when the heat treatment temperature is high, impurities such as As, P, and B introduced into the gate electrode also cause a charge formation reaction with metal atoms after entering the high dielectric insulating film, which may cause fluctuations in the threshold value of the MOSFET. I understood that.

  Furthermore, in the previous technology generation, the use of metals, mixed crystals of metals and semiconductors, etc. for the gate electrode has been studied. However, these metal atoms are activated by heat treatment to destroy the insulating properties of the gate insulating film. There is also a problem that it is easy. Although depending on the semiconductor substrate and the gate electrode material, for example, this problem is caused by heat treatment at about 600 ° C. or higher.

  In view of the above circumstances, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device using a gate insulating film having a metal atom with little threshold fluctuation.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation on a semiconductor substrate, a step of selectively forming a pseudo film on a semiconductor exposed surface surrounded by the element isolation, and a pseudo film in the gate width direction. A step of forming a gate electrode straddling, a step of removing the pseudo film, a step of forming a gate insulating film having a metal atom in the void formed by the pseudo film, and then a source on the surface of the semiconductor substrate sandwiching the gate electrode A step of forming a drain region, and the pseudo film is made of any one of a mixed crystal compound of Si and Ge, W, and Ti silicide .

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation on a semiconductor substrate, a step of selectively forming a pseudo film on a semiconductor exposed surface surrounded by the element isolation, and a pseudo film in the gate width direction. A step of forming a gate electrode straddling, a step of forming a source / drain region on the surface of the semiconductor substrate sandwiching the gate electrode, a step of removing the pseudo film, and a metal atom in the void formed by the pseudo film And a step of forming a gate insulating film, wherein the pseudo film is made of any one of a mixed crystal compound of Si and Ge, W, and Ti silicide.

  According to the present invention, a semiconductor device manufacturing method and a semiconductor device with less threshold fluctuation are provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be attached | subjected to a common structure through embodiment, and the overlapping description is abbreviate | omitted. Each figure is a schematic diagram for promoting explanation and understanding of the invention, and its shape, dimensions, ratio, and the like are different from those of an actual device. However, these are in consideration of the following explanation and known techniques. The design can be changed as appropriate.

  In each embodiment, an n-type MOSFET using an oxide as a gate insulating film will be described. Needless to say, the present invention can also be applied to a p-type MOSFET and a CMOSFET (complementary MOSFET). The gate insulating film is not limited to an oxide, and each embodiment can be similarly applied to a MISFET using other insulators such as nitride and fluoride.

  Also, the embodiments can be similarly applied to PROMs such as EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically EPROM), and flash memory.

  Further, a memory, a logic circuit, and the like in which the above-described semiconductor elements are integrated, and a system LSI in which these are mixedly mounted on the same chip are also within the scope of the present invention.

(First embodiment)
The MOSFET manufacturing method of the first embodiment includes a step of forming a pseudo film on a semiconductor substrate, a step of forming a gate electrode straddling the pseudo film in the gate width direction, a step of removing the pseudo film, A step of forming a gate insulating film having a metal atom in a void formed in the film, and a step of forming a source / drain region on the surface of the semiconductor substrate sandwiching the gate electrode in the gate length direction. To do.

  An example of a MOSFET manufacturing method according to the first embodiment will be described with reference to FIGS.

  FIGS. 1 to 5 are schematic cross-sectional views for explaining first to fifth steps of an example of the MOSFET manufacturing method according to the first embodiment. FIG. 1A is a schematic cross-sectional view in the gate length direction, and FIG. 1B is a schematic cross-sectional view in the gate width direction. The same applies to FIGS. 2 to 5.

  The first step will be described with reference to FIG.

  A trench for STI (Shallow Trench Isolation) is dug to a depth of about 0.4 μm on the Si substrate 10, and then SiO 2 for element isolation is deposited on the entire surface of the Si substrate 10 using the CVD method, and then CMP (Chemical Mechanical Polish) Is planarized to form element isolation 11 (SiO 2).

  Next, after threshold adjustment is performed on the Si substrate 10 by using B ion implantation, gas exposure CVD of dichlorosilane, germane, and hydrochloric acid is used to selectively form the Si exposed surface, that is, on the Si substrate 10. A pseudo film 12 (SiGe having a Ge content of 20%, hereinafter referred to as SiGe) was deposited to 4 nm.

  Next, polycrystalline Si to be the gate electrode 13 is deposited on the entire surface of the Si substrate 10 by CVD using an atmosphere containing Si2H6 or SiH4. Thereafter, the gate electrode 13 (polycrystalline Si) is formed using RIE (Reactive Ion Etching). At this time, by adding SFx gas to CFx gas, a protective layer is formed on the pseudo film 12 (SiGe) and is not etched. As shown in FIG. 1, the gate electrode 13 (polycrystalline Si) is formed on the element isolation 11 (SiO 2) and the pseudo film 12 so as to straddle the pseudo film 12 in the gate length direction and across the pseudo film 12 in the gate width direction. Formed.

  As shown in FIG. 2, in the second step, the pseudo film 12 (SiGe) is removed using wet etching, and a gap is formed between the Si substrate 10 and the gate electrode 13 (polycrystalline Si). At this time, if a mixed solution of nitric acid, hydrofluoric acid, and water is used, SiGe can be selectively removed with respect to Si and SiO2.

  Note that a mixed solution of acetic acid, hydrofluoric acid, and water, or a mixed solution of ammonia water, hydrofluoric acid, and water may be used instead of the mixed solution of nitric acid, hydrofluoric acid, and water. Further, instead of wet etching, selective etching in plasma containing CFx is also possible.

  As shown in FIG. 3, the third step is about 0.5 nm on the surface of the Si substrate 10 and the gate electrode 13 (polycrystalline Si) using thermal oxidation by heat treatment at 700 ° C. under normal pressure and steam atmosphere. The interfacial film 14 (SiO2) is formed.

  The step of forming the interface film 14 (SiO 2) is preferably performed from the viewpoint of suppressing charge formation at the interface between the gate electrode and the gate insulating film, but may not be performed. Further, when the gate insulating film 15 is deposited, the interface film 14 (SiO 2) may naturally grow on the surfaces of the Si substrate 10 and the gate electrode 13.

  Next, the gate insulating film 15 (a mixed crystal compound of HfO 2 and SiO 2 (hereinafter referred to as HfO 2 —SiO 2)) is formed on the entire surface of the Si substrate 10 at a temperature of 500 ° C. by MOCVD (Metal Organic Chemical Vapor Deposition). Deposit 3 nm. At this time, the gate insulating film 15 (HfO 2 —SiO 2) may be nitrided by mixing ammonia gas. The nitrogen concentration at this time is preferably 20% or more and 40% or less. In this step, the gate insulating film 15 is formed in the gap where the pseudo film 12 has been formed.

  The gate insulating film 15 may be deposited by halide CVD or atomic layer deposition in addition to the MOCVD method. The nitriding method may use CVD in an atmosphere containing N activated by plasma in addition to CVD in an atmosphere containing ammonia gas. When the gate length is about 20 nm or less, nitridation by heat treatment in an ammonia atmosphere, nitridation in plasma N, or the like can be performed after the gate insulating film 15 is deposited.

As shown in FIG. 4, in the fourth step, RIE containing chlorine is used to remove the gate insulating film 15 (HfO 2 —SiO 2), leaving the side immediately below the gate electrode 13 (polycrystalline Si) and the side surface. Next, a shallow diffusion layer 16 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻² is formed using ion implantation of As ⁺ with an energy of 200 eV.

  The method for forming the shallow diffusion layer 16 includes a method in which impurity-doped Si is deposited and formed by solid solution diffusion in addition to a method by ion implantation, and a method in which the gate sidewall 17 is doped by impurity and formed by solid solution diffusion. May be used.

As shown in FIG. 5, in the fifth step, SiO 2 serving as a gate side wall is deposited by 10 nm on the entire surface using CVD, and then gate side wall 17 (SiO 2) is formed on the side surface of the gate electrode using RIE. . Next, a deep diffusion layer 18 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻² is formed using ion implantation of As ⁺ with an energy of 10 keV. Thereafter, a heat treatment at 600 ° C. or higher, for example, a short-time high-temperature heat treatment at 1000 ° C. for 20 seconds is performed to activate the impurities.

  Next, after Co is deposited using CVD, a silicide layer 19 (CoSi2) is formed using heat treatment at about 400 ° C. Next, unreacted Co is removed by performing wet etching using a solution of sulfuric acid and hydrogen peroxide solution.

  According to the first embodiment, since the gate insulating film is formed after the gate electrode is formed, the charge forming reaction at the interface between the gate electrode and the gate insulating film, which has occurred in the gate electrode forming step, can be suppressed. Therefore, the threshold fluctuation of the MOSFET can be reduced. In addition, the first embodiment is highly consistent with the conventional manufacturing method.

  The material of the MOSFET according to the first embodiment will be described.

  When the gate electrode 13 has impurities such as As, P, and B, the charge formation reaction at the interface between the gate electrode 13 and the gate insulating film 15 is activated. Therefore, the effect given by the present invention is great.

  The gate electrode 13 can be made of SiGe, silicide, germanide or the like in addition to polycrystalline Si. Examples of silicide include WSi2, NiSi, CoSi2, PtSi, and MoSi2. Examples of germanides include WGI2, NiGe, NiGe2, CoGe2, PtGe, and MoGe2. Note that the Ge concentration of SiGe is lower than that of the pseudo film 12. This is because the pseudo film 12 is selectively removed in the second step described above.

  By forming the gate insulating film 15 in a laminated structure with the interface film 14, the charge formation reaction at the interface between the gate electrode 13 and the gate insulating film 15 can be further suppressed. Note that a structure in which the composition gradually changes may be used instead of the laminated structure.

  Examples of the gate insulating film 15 include a high dielectric insulating film, or a mixed crystal compound of this with SiO 2 or Al 2 O 3. Examples of the high dielectric insulating film include HfO 2, oxides of IV transition metals typified by ZrO 2 and TiO 2, oxides of lanthanoid metals typified by La 2 O 3, and the like.

  Examples of the interfacial film 14 include Si nitride film Si3N4, Si oxynitride film SiON, and the like in addition to Si oxide film SiO2. In the case of SiO2, oxidation in O2, oxidation in plasma O, etc., in the case of Si3N4, nitriding in ammonia atmosphere, nitriding in plasma N, etc., in the case of SiON, oxynitriding in NO atmosphere, in N2O atmosphere The interface film 14 is formed by oxynitriding or the like or a combination of the above-described oxidation method and nitriding method.

  The gate insulating film 15 preferably has Hf atoms. This is because particularly good characteristics are obtained in the combination of the gate insulating film 15 having Hf atoms and the SiO 2 interface film. In the case of a mixed crystal compound of HfO2 and SiO2, the concentration of HfO2 is preferably 30% or more and 80% or less from the viewpoint of gate insulating film characteristics.

  The pseudo film 12 is preferably one that can be selectively deposited on the Si substrate 10. For example, in addition to SiGe, W, TiSi2 and the like can be mentioned.

  The pseudo film 12 using W is deposited using, for example, CVD of a mixed gas system of WF6 and SiH4 in the first step, and using a mixed solution of sulfuric acid and hydrogen peroxide solution in the second step. Remove. The pseudo film 12 using TiSi2 is deposited using, for example, CVD of a mixed gas system of TiCl4 and SiH4 in the first process, and removed using dilute hydrofluoric acid in the second process.

  The pseudo film 12 preferably has a multilayer structure in which the above-described layer is used as a lower layer and a SiO2 layer is used as an upper layer. This is because the SiO2 layer has high etching resistance when the gate electrode 13 is formed, so that the gate electrode can be processed with high accuracy.

  When the source / drain region is a high-concentration impurity diffusion layer, a charge forming reaction that occurs at the interface between the gate electrode 13 and the gate insulating film 15 is activated because a high-temperature heat treatment for impurity activation is usually performed. Therefore, the effect given by the present invention is great.

  Examples of the source / drain region include the shallow diffusion layer 16, the deep diffusion layer 18, and the silicide layer 19, only the shallow diffusion layer 16, only the silicide layer 19, and a combination of the shallow diffusion layer 16 and the silicide layer 19.

  The shallow diffusion layer 16 and the deep diffusion layer 18 are formed by injecting B, P or the like according to the conductivity type in addition to As. The silicide layer 19 is made of metal silicide such as V, Cr, Mn, Y, Mo, Ru, Rh, Hf, Ta, W, Ir, Co, Ti, Pt, Pd, Zr, Gd, Dy, Ho, and Er. Use.

  The Si substrate 10 uses SiGe, Ge, strained Si, strained Ge, or other channel region material. As described above, impurities may be added. The Si substrate 10 may use an SOI (Silicon On Insulator) structure having a buried insulating film.

  The element isolation 11 and the gate sidewall 17 use SiN or SiON in addition to SiO2.

  Modification 1 is shown below.

  The MOSFET of the present invention can be applied not only to the planar type described above but also to a Fin type, a vertical type, etc. In Modification 1, a method for manufacturing a Fin-type MOSFET will be described.

  An example of a MOSFET manufacturing method according to Modification 1 will be described with reference to FIGS. For convenience, an n-type MOSFET having an SOI structure will be described in different points from the first embodiment.

  6 to 8 are schematic perspective views for explaining the MOSFET manufacturing method according to the first modification.

  First, the first step will be described.

  As shown in FIG. 6, an SOI structure is formed by stacking a Si substrate 110, a buried insulating film 111, and a Si layer 112 in order from the bottom.

  Next, after depositing a Si nitride layer 113 on the Si layer 112, the Si layer 112 and the Si nitride layer 113 are formed in a rectangular parallelepiped shape using photolithography. This rectangular parallelepiped later becomes a source / drain region and a channel region.

  Next, the surface of the Si layer 112 is cleaned using an acid and hydrogen peroxide solution mixture or ammonia and hydrogen peroxide solution mixture, and then the exposed surface of the Si layer 112 is cleaned. B ion implantation for

  Next, a pseudo-film 114 (SiGe with a Ge content of 20%, hereinafter referred to as SiGe) is deposited to 4 nm on the exposed Si surface, that is, the surface of the Si layer 112 by using gas-based CVD of dichlorosilane, germane, and hydrochloric acid. did.

  Next, using a CVD method in an atmosphere containing Si2H6 or SiH4, polycrystalline Si to be the gate electrode 115 is deposited on the entire surface of the Si substrate 110, and then the gate electrode 115 (polycrystalline Si) is formed using RIE. To do. At this time, by not mixing the SFx gas into the CFx gas, Si and SiGe formed on the side surface of the Si layer 112 other than the pseudo film 114 (SiGe) immediately below the gate electrode 115 are completely removed. Note that the Si layer 112 itself is not removed because it is masked by the Si nitride layer 113.

  FIG. 7 is a schematic perspective view of the MOSFET in the first step.

  The second to fifth steps are the same manufacturing steps as the MOSFET of the first embodiment.

  FIG. 8 is a schematic perspective view of the MOSFET in the fifth step.

(Second Embodiment)
The MOSFET manufacturing method of the second embodiment includes a step of forming a pseudo film on a semiconductor substrate, a step of forming a gate electrode straddling the pseudo film in the gate width direction, and a semiconductor sandwiching the gate electrode in the gate length direction. A step of forming a source / drain region on the surface of the substrate; a step of removing the pseudo film; and a step of forming a gate insulating film having metal atoms in the voids formed of the pseudo film. To do.

  An example of a MOSFET manufacturing method according to the second embodiment will be described with reference to FIGS. For convenience, the difference between the n-type MOSFET and the first embodiment will be described.

  9 to 13 are schematic cross-sectional views for explaining the first to fifth steps of an example of the MOSFET manufacturing method according to the second embodiment. FIG. 9A is a schematic cross-sectional view in the gate length direction, and FIG. 9B is a schematic cross-sectional view in the gate width direction. The same applies to FIGS. 10 to 13.

  The first step will be described with reference to FIG.

  The pseudo film 22 (lamination of the lower SiGe layer and the upper SiO 2 layer, hereinafter referred to as SiGe / SiO 2) is the same as the first step of the first embodiment except that it is a multilayer. This SiO2 layer is formed using plasma oxidation, thermal oxidation or the like after the formation of the SiGe layer.

  The second step will be described with reference to FIG. A shallow diffusion layer 26, a gate sidewall 27 (SiO2), and a deep diffusion layer 28 are formed in this order. These detailed forming methods are the same as the methods shown in the fourth and fifth steps of the first embodiment.

  The third step will be described with reference to FIG. By performing wet etching using hydrofluoric acid, the gate sidewall 27 (SiO2) is removed. When SiN is used for the gate side wall 27, phosphoric acid at about 100 ° C. is used instead of hydrofluoric acid. Next, the pseudo film 12 (SiGe / SiO 2) is removed by using the same method as in the second step of the first embodiment.

  The fourth step will be described with reference to FIG. After forming the interface film 24 (SiO2), a gate insulating film (HfO2-SiO2) is formed. These detailed formation methods are the same as the methods shown in the third step and the fourth step of the first embodiment.

  The fifth step will be described with reference to FIG. After the gate sidewall 27 (SiO2) is formed, a silicide layer 29 (CoSi2) is formed. These detailed forming methods are the same as the method shown in the fifth step of the first embodiment.

  According to the second embodiment, since the gate insulating film is formed after the source / drain region forming step using heat treatment, activation of the charge formation reaction at the gate electrode 13 / gate insulating film 15 interface due to the heat treatment can be suppressed. . Therefore, the threshold fluctuation of the MOSFET can be reduced as compared with the first embodiment.

  Modification 2 is shown below.

  In Modification 2, a method for manufacturing a MOSFET using a metal for the gate electrode will be described.

  An example of a MOSFET manufacturing method according to Modification 2 will be described with reference to FIGS. For convenience, the difference between the n-type MOSFET and the second embodiment will be described.

  14 to 18 are schematic cross-sectional views for explaining the first to fifth steps of the MOSFET according to Modification 2. 14A is a schematic sectional view in the gate length direction, and FIG. 14B is a schematic sectional view in the gate width direction. The same applies to FIGS. 14 to 18.

  The first step will be described with reference to FIG.

  First, as in the first step of the second embodiment, an element isolation 31 (SiO2) is formed. Next, after adjusting the threshold value by ion implantation of B into the Si substrate 10, a pseudo film is formed on the Si exposed surface, that is, on the Si substrate 30 by using dichlorosilane, tetrachlorosilane, or ammonia gas-based CVD. 32 (SiN) was deposited to 4 nm.

  Next, after depositing the gate electrode 33 (W) using a gas-based CVD containing WF6 and SiH4, a SiO2 layer 310 is deposited using a gas-based CVD containing TEOS (tetraethoxysilane). Next, the gate electrode 33 (W) is formed using RIE in an atmosphere containing CFx gas.

  The second step will be described with reference to FIG. A shallow diffusion layer 36, a gate sidewall 37 (SiN), and a deep diffusion layer 38 are sequentially formed. These forming methods are the same as the methods shown in the second step of the second embodiment.

  The third step will be described with reference to FIG. By performing wet etching, the gate sidewall 37 (SiN) and the pseudo film (SiN) are removed. At this time, if phosphoric acid at about 100 ° C. is used, SiN can be selectively removed with respect to Si and SiO 2.

  The fourth step will be described with reference to FIG. After depositing an interface film 34 (SiO2) to a thickness of 0.5 nm on the surface of the Si substrate 30 using CVD, a gate insulating film (HfO2-SiO2) is formed using the same method as in the fourth step of the second embodiment. Form.

  The fifth step will be described with reference to FIG. After removing the interface film 34 (SiO 2) on the deep diffusion layer 38 using etching, a silicide layer 29 (CoSi 2) is formed using the same method as in the fifth step of the second embodiment. In this fifth step, the SiO2 layer 310 plays a role in hindering the silicide reaction of the gate electrode 33 (W).

  The gate electrode 33 has a metal atom, and in addition to W, a metal or alloy such as Hf, Zr, Al, Cu, Mo, Pt, Pd, TiN, WN, MoN, HfN, ZrN, TiB, Compounds such as TiC and HfC, silicides such as WSi2, NiSi, CoSi2, PtSi, and MoSi2, and germanides such as WGe2, NiGe, NiGe2, CoGe2, PtGe, and MoGe2 are conceivable.

  In the case where the gate electrode has a metal atom, the metal atom is activated by heat treatment, and the insulating property of the gate insulating film is easily broken. Therefore, the effect given by the present invention is great.

(Third embodiment)
A planar MOSFET according to a third embodiment will be described with reference to FIG.

  FIG. 19 is a schematic top view of the MOSFET shown in FIG.

  As shown in FIG. 19, the element isolation 11 (SiO 2) is formed so as to surround the Si substrate, and the gate electrode 13 is surrounded by the gate insulating film 15. The gate electrode 13 is formed on the Si substrate and the element isolation 11 (SiO 2) so as to straddle the gate insulating film 15 in the gate width direction. In addition, since it becomes a connection part with an electrode, the gate electrode 13 on the element isolation | separation 11 (SiO2) is large compared with another part. A gate sidewall 17 is formed on the Si substrate so as to sandwich the gate electrode 13 and the gate insulating film 15 in the gate length direction. A silicide layer 19 is formed on the upper surface of the gate electrode 13, and a silicide layer 19 is formed on the surface of the Si substrate 10.

  Although not shown, the gate insulating film 15 is formed between the Si substrate and the gate electrode 13, but is not formed between the element isolation 11 and the gate electrode 13. That is, the gate insulating film 15 is formed on the Si substrate sandwiched between the source / drain regions (a region surrounded by a dotted line in FIG. 19).

  According to the third embodiment, the contact surface between the gate insulating film 15 and the gate electrode 13 is reduced as compared with a normal planar MOSFET. For this reason, peeling due to poor adhesion between the gate insulating film 15 having metal atoms and the gate electrode 13 can be suppressed.

  In addition, when the gate electrode 13 is polycrystalline Si, since the adhesiveness with the gate insulating film 15 is especially bad, the effect which this invention gives is large.

  Further, according to the third embodiment, since the manufacturing method described above is used, the MOSFET has a small threshold fluctuation.

  As mentioned above, although embodiment of this invention was described, this invention is not restricted to these, In the category of the summary of the invention as described in a claim, it can change variously. In addition, the present invention can be variously modified without departing from the scope of the invention in the implementation stage. Furthermore, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

FIG. 3 is a schematic cross-sectional view for explaining a first step of the MOSFET according to the first embodiment. Sectional schematic diagram for demonstrating the 2nd process of MOSFET which concerns on 1st Embodiment. Sectional schematic diagram for demonstrating the 3rd process of MOSFET which concerns on 1st Embodiment. Sectional schematic diagram for demonstrating the 4th process of MOSFET which concerns on 1st Embodiment. Sectional schematic diagram for demonstrating the 5th process of MOSFET which concerns on 1st Embodiment. FIG. 10 is a schematic perspective view for explaining an intermediate stage of a first step of a MOSFET according to Modification 1; FIG. 9 is a schematic perspective view for explaining a first step of a MOSFET according to Modification 1. FIG. 10 is a schematic perspective view for explaining a fifth step of the MOSFET according to Modification 1. Sectional schematic diagram for demonstrating the 1st process of MOSFET which concerns on 2nd Embodiment. Sectional schematic diagram for demonstrating the 2nd process of MOSFET which concerns on 2nd Embodiment. Sectional schematic diagram for demonstrating the 3rd process of MOSFET which concerns on 2nd Embodiment. Sectional schematic diagram for demonstrating the 4th process of MOSFET which concerns on 2nd Embodiment. Sectional schematic diagram for demonstrating the 5th process of MOSFET which concerns on 2nd Embodiment. 10 is a schematic cross-sectional view for explaining a first step of a MOSFET according to Modification 2. FIG. 9 is a schematic cross-sectional view for explaining a second step of a MOSFET according to Modification 2. FIG. 9 is a schematic cross-sectional view for explaining a third step of a MOSFET according to Modification 2. FIG. 9 is a schematic cross-sectional view for explaining a fourth step of a MOSFET according to Modification 2. FIG. 9 is a schematic cross-sectional view for explaining a fifth step of a MOSFET according to Modification 2. FIG. The upper surface schematic diagram of MOSFET which concerns on 3rd Embodiment.

Explanation of symbols

10 Si substrate 11 Element isolation 12 Pseudo film 13 Gate electrode 14 Interface film 15 Gate insulating film 16 Shallow diffusion layer 17 Gate sidewall 18 Deep diffusion layer 19 Silicide layer 110 Si substrate 111 Buried insulating layer 112 Si layer 113 Si nitride layer 114 Pseudo Film 115 Gate electrode 116 Gate insulating film 20 Si substrate 21 Element isolation 22 Pseudo film 23 Gate electrode 24 Interface film 25 Gate insulating film 26 Shallow diffusion layer 27 Gate sidewall 28 Deep diffusion layer 29 Silicide layer 30 Si substrate 31 Element isolation 32 Pseudo film 33 Gate electrode 34 Interface film 35 Gate insulating film 36 Shallow diffusion layer 37 Gate sidewall 38 Deep diffusion layer 39 Silicide layer 310 SiO 2 layer

Claims (10)

Forming a device isolation on a semiconductor substrate;
Selectively forming a pseudo film on a semiconductor exposed surface surrounded by the element isolation;
Forming a gate electrode straddling the pseudo film in the gate width direction;
Removing the pseudo film;
Forming a gate insulating film having a metal atom in the void formed by the pseudo film;
Then, forming a source / drain region on the semiconductor substrate surface sandwiching the gate electrode ,
The method of manufacturing a semiconductor device, wherein the pseudo film is made of any of a mixed crystal compound of Si and Ge, W, and Ti silicide . Forming a device isolation on a semiconductor substrate;
Selectively forming a pseudo film on a semiconductor exposed surface surrounded by the element isolation;
Forming a gate electrode straddling the pseudo film in the gate width direction;
Forming source / drain regions on a semiconductor substrate surface sandwiching the gate electrode;
Thereafter, the step of removing the pseudo film,
A step of forming a gate insulating film having a metal atom in the void formed by the pseudo film ,
The method of manufacturing a semiconductor device, wherein the pseudo film is made of any of a mixed crystal compound of Si and Ge, W, and Ti silicide .   The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode is made of polycrystalline Si.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode contains As, P, or B. 5.   The method of manufacturing a semiconductor device according to claim 2, wherein the gate electrode has a metal atom.   6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an interface film on the surface of the semiconductor substrate after the step of removing the pseudo film.   The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film contains Hf atoms. The gate electrode, a method of manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that it has a silicide. The source / drain regions, a method of manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that it comprises a high concentration impurity diffusion layer. The pseudo film, method of manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the thickness of 4 nm.

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