JP2006012900A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is prevented from a change in threshold value and equipped with a MOS transistor having high reliability against electrical stress. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate (11) wherein an element isolation region (12) for demarcating an element region is formed, a source/drain region (25) formed away from the element region of the semiconductor substrate, gate insulation films (13 and 14) formed on the element region of the semiconductor substrate, and a gate electrode (15) containing a semiconductor which is formed on the gate insulation films. The gate insulation films are a first insulation film (13) containing metal and oxygen, and a second insulation film (14) which is formed on the first insulation film and contains silicon and oxygen. The content of metal contained in the second insulation film is 6.6 atomic % at an interface with the gate electrode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a CMOS LSI element using a dielectric film as a gate insulating film and a manufacturing method thereof.

In MOS transistors, there is a problem that leakage current between a gate and a substrate increases due to a direct tunneling phenomenon in a carrier film. In order to avoid such a tunneling phenomenon, it has been proposed to form a gate insulating film using a material whose dielectric constant is significantly higher than that of SiO ₂ . Specifically, it is a metal oxide film having a high dielectric constant such as an oxide of a high dielectric constant metal such as ZrO ₂ or HfO ₂ , or a compound of the compound with SiO ₂ so-called silicate. Furthermore, the silicate containing nitrogen can maintain an amorphous state even at 1000 ° C., and the relative dielectric constant is as high as about 20. In addition, since diffusion of impurities such as boron in the film is small, application to a CMOS process requiring heat resistance is expected.

  However, when a polycrystalline Si gate material is combined with a metal oxide gate insulating film such as Hf, Zr, or Al, the threshold value varies. This variation is very large, and it is difficult to adjust by adjusting the impurity concentration of the substrate portion as is usually done. Such a phenomenon has been confirmed to occur not only in the case of a pure semiconductor gate electrode such as Si or Ge but also in a metal silicide or metal germanide.

Therefore, after depositing a high dielectric film, after removing impurities in the film and performing a solution treatment to increase the oxygen concentration in the film, Si is deposited and deposited at a low temperature (typically 500 ° C. or lower). ) A method of forming a Si gate electrode after forming SiO ₂ by plasma oxidation has been proposed. (For example, refer to Patent Document 1) However, the solution treatment eventually causes a trace amount of organic matter to adhere to the high dielectric film from the treatment layer or the air in the clean room, so that the film has high reliability against long-term electrical stress. descend. In addition, the process itself takes time, and the overall process cost increases. Further, when plasma oxidation at about 500 ° C. is performed, it is difficult to completely remove a large variation factor of the threshold. In particular, when the accumulation of organic matter is large, the introduction of oxygen into the interface and the high dielectric film is greatly hindered, and the threshold shift cannot be improved.
US Pat. No. 6,696,327

  An object of the present invention is to provide a semiconductor device provided with a MOS transistor that is highly reliable against electrical stress while avoiding fluctuations in threshold value, and a method for manufacturing the same.

A semiconductor device according to one embodiment of the present invention includes a semiconductor substrate provided with an element isolation region that defines an element region;
A source / drain region provided apart from the element region of the semiconductor substrate;
A gate insulating film provided on the element region of the semiconductor substrate;
A gate electrode provided on the gate insulating film and including a semiconductor;
The gate insulating film includes a first insulating film containing a metal and oxygen, and a second insulating film formed on the first insulating film and containing silicon and oxygen, and the second insulating film In the film, the metal content at the interface with the gate electrode is 6.6 atomic. It is characterized by being less than%.

A method of manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a first insulating film containing a metal and oxygen over a semiconductor substrate provided with an element isolation region that defines an element region.
The first insulating film contains Si and has a metal concentration of 19.8 at. A step of forming an interface film of less than
The interface film is oxidized so that the metal concentration on the surface is 6.6 at. Forming a second insulating film of less than% on the first insulating film to obtain a gate insulating film having a laminated structure;
Forming a gate electrode including a semiconductor on the gate insulating film; and introducing an impurity into the element region of the semiconductor substrate using the gate insulating film and the gate electrode as a mask to form a source / drain region The process of forming is characterized by comprising.

  According to the aspects of the present invention, there are provided a semiconductor device including a MOS transistor with high reliability against electrical stress while avoiding threshold fluctuations, and a manufacturing method thereof.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. As shown in the figure, in the semiconductor device 10, a first insulating film 13 and a second insulating film 12 are sequentially deposited on a semiconductor substrate 11 on which an element isolation region 12 is formed, thereby forming a gate insulating film having a stacked structure. Further, a semiconductor gate electrode 15 is provided. The metal contained in the first insulating film 11 is lanthanoid such as Hf, Zr, or La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Preferably, the first insulating film 11 is a high dielectric insulating film. The second insulating film 12 provided thereover has a metal concentration of 6.6 at. It is specified to be less than%.

  The semiconductor device according to the present embodiment can be manufactured by the following method, for example. As shown in FIG. 2, the element isolation structure 12 is formed on the semiconductor substrate 11 and ion implantation for threshold adjustment is performed, and then the first insulating film 13 is formed. On the first insulating film 13, an interface film containing Si is preferably deposited continuously in a vacuum without performing solution treatment.

  The interface film does not need to be made of only Si, and an oxide film, a nitride film, or an oxynitride film can also be used. Moreover, if it is low concentration, the metal may contain. In this case, the metal concentration on the surface of the interface film after oxidation is 6.6. The metal concentration in the interface film must be 19.8 at. It is calculated | required that it is prescribed | regulated to less than%.

  Thereafter, heat treatment is performed in an oxygen or nitrogen-containing atmosphere so that the entire interface film is oxidized or oxynitrided, whereby silicon in the interface film is oxidized to form a second insulating film containing silicon oxide. The oxide thus generated prevents the metal in the first insulating film from newly reacting with the semiconductor constituting the gate electrode. Even if metal silicide (metal germanide) is already formed on the interface by deposition, the metal silicide (metal germanide) is oxidized by performing heat treatment in an oxidizing atmosphere. Thus, it is converted into a mixed state of metal oxide and Si oxide.

  On the second insulating film 14, a layer to be the semiconductor gate electrode 15 is formed and processed. Here, semiconductor, silicate, germanide, or the like may be deposited. Thereafter, a normal MOS formation process, that is, the second insulating film 14 and the first insulating film 13 are selectively removed with respect to the gate electrode 15 and the element isolation region 12, and the source / drain (see FIG. The semiconductor device according to the present embodiment is completed.

  There is no undesired accumulation of organic substances at the upper and lower interfaces of the second insulating film 14, that is, the substrate-side interface 17 and the gate electrode-side interface 16. Moreover, oxidation is performed by exposure to a high-temperature oxygen atmosphere. In the semiconductor device thus obtained, since no metal silicide (germanide) is contained in any part of the gate stack and no dipole at the interface is induced, the problem of large threshold shift of MOS Tr is solved. Became possible.

FIG. 3 shows a cross-sectional view of a conventional semiconductor device. In the illustrated semiconductor device 20, the semiconductor gate electrode 15 is directly formed on the high dielectric gate insulating film 32. The semiconductor device having such a structure has a large fluctuation of -0.9 V with respect to the ideal threshold value of the P-MOS transistor, and cannot be used as a transistor in the circuit.
On the other hand, in the semiconductor device according to the present embodiment shown in FIG. 1, the fluctuation can be suppressed to −0.3 V, and it can be sufficiently used as a transistor by combining other part structures such as channel concentration. It will be possible.

  FIG. 4 shows the relationship between the metal concentration at the electrode-side interface of the gate insulating film and the threshold value change. Here, a P-MOS transistor is formed using hafnium as the high dielectric metal. The metal concentration on the surface of the gate insulating film was measured by EDX (Electron Dispersive X-ray). 10 at. When hafnium is contained in the surface of the gate insulating film at a high concentration of at least%, a large shift of about −0.7 V is observed. In contrast, the hafnium concentration is 6.6 at. When it is less than%, the shift amount is reduced to -0.4V or less. This amount of shift is allowed because it has substantially no effect. Based on these results, the metal concentration at the electrode side interface of the gate insulating film was 6.6 at. It was prescribed to be less than%. More preferably, the metal concentration at the electrode-side interface of the gate insulating film is 5 at. % Or less.

  In order to increase the relative dielectric constant and reduce the leakage current, it is preferable that a metal exists at the electrode side interface of the gate insulating film. In this case, the interfacial film containing Si can be a metal-containing film, and such a film has a property of being easily oxidized. Therefore, oxidation proceeds at room temperature or higher, and plasma oxidation can be used. On the other hand, when no metal is present at the electrode-side interface of the gate insulating film (metal concentration is 0 at.%), The threshold change can be further reduced. The metal concentration at the electrode side interface is 0 at. In order to reduce the content to 50%, a film containing no metal, preferably a Si film, is formed as an interface film, and the oxidation is performed at a high temperature of 600 ° C. or higher.

  As described above, in the embodiment of the present invention, the gate insulating film is constituted by the laminated film of the first insulating film containing metal and the second insulating film containing silicon. Moreover, the metal concentration at the gate electrode side interface of the second insulating film is 6.6 at. It is specified to be less than%. By containing a high dielectric metal in the gate insulating film, the dielectric constant can be increased and the leakage current can be reduced, and the metal concentration can be reduced to 6.6 at. By defining it as less than%, threshold fluctuation is suppressed. As a result, a semiconductor device including a MOS transistor capable of normal operation is obtained.

  Hereinafter, an N-type MOS transistor will be taken as an example, and a specific example of the present invention will be shown to explain in more detail.

(Embodiment 1)
5 to 13 are sectional views showing the method for manufacturing the semiconductor device according to this embodiment.

  First, as shown in FIG. 5, the element isolation region 12 is provided in the semiconductor substrate 11. Here, a p-type Si substrate was used as the semiconductor substrate, and the element isolation region 12 was formed by a conventional method. That is, first, a trench (depth: about 0.4 μm) for STI (Shallow Trench Isolation) was provided on the substrate 11, and a silicon oxide film was deposited on the entire surface by CVD. Subsequently, CMP (Chemo-Mechanical Polish) was performed to fill the trench with a silicon oxide film, thereby obtaining an element isolation region 12 as shown in FIG.

After B ion implantation for adjusting the threshold value was performed in a region where an element is to be formed, HfSiO _x N _y as a first insulating film 13 was formed by sputtering as shown in FIG. The ratio of Hf to Si in the film (Hf / (Hf + Si)) was controlled by controlling the power ratio to be applied using two targets of Hf target and Si target. In this embodiment, this ratio is 0.6, but can be any value within the range of 0.5 to 1.0.

  By controlling the amount of nitrogen and oxygen mixed in the atmosphere, the amount of these elements in the film can be controlled. Here, an oxynitride film having x = 1.55 and y = 0.45 was formed. The substrate temperature at the time of film formation can be arbitrarily set, but in this embodiment, it was performed at room temperature.

  The film thickness of the first insulating film 13 can be appropriately determined within a range of 2 to 5 nm, and is 3 nm here. The composition of the first insulating film 13 does not necessarily have to be uniform in the film thickness direction and may have a distribution.

  After the first insulating film 13 having a predetermined film thickness was formed, the power to the Hf target was stopped, and an interface film 18 containing Si was deposited by sputtering as shown in FIG. The film thickness of the interface film 18 can be appropriately determined within the range of 0.3 to 0.7 nm, but here it is set to 0.5 nm. The interface film 18 is formed in an inert gas atmosphere such as Ar, and the surface of the first insulating film before the film formation is required to be as clean as possible. Therefore, the solution treatment was not performed, and the exposure time to the clean room atmosphere was limited to about 30 minutes or less. It is most preferable to deposit the interface film 18 in the same vacuum after depositing the first insulating film 13.

  Subsequently, heat treatment is performed to oxidize the interface film 18. The heat treatment at this time is desirably performed under such a condition that the oxidant reaches the interface between the interface film 18 and the first insulating film 13 and the reaction proceeds sufficiently there. For example, the interface film 18 is sufficiently oxidized in an atmosphere containing oxygen at 800 ° C. As a result, the second insulating film 14 is formed as shown in FIG. 8, and a gate insulating film having a laminated structure is formed.

On the gate insulating film, a polycrystalline silicon film to be the semiconductor gate electrode 15 was deposited on the entire surface of the wafer as shown in FIG. 9 by a CVD method in an atmosphere containing Si ₂ H ₆ or SiH ₄ . Before the deposition, it is desired that the surface of the second insulating film 14 be kept clean, so that the solution treatment is not performed and the exposure time to the clean room atmosphere is limited to about 30 minutes or less.

Next, the gate electrode 15 was formed as shown in FIG. 10 by anisotropically etching the polycrystalline silicon film using reactive ion etching using CF _x gas. After the first insulating film 13 and the second insulating film 14 were etched with a hydrofluoric acid aqueous solution and processed as shown in FIG. 11, the structure shown in FIG. That is, As was ion-implanted into the exposed element region of the substrate 11 to form a shallow impurity region. The implantation conditions at this time were about 200 eV 1 × 10 ¹⁵ cm ⁻² . Then, SiO ₂ or SiN is deposited on the entire surface by the CVD method or the like, by repeating the entire surface etching was leaving the gate sidewall 23 with a thickness of 10nm on gate electrode 15 side.

Using the gate sidewall 23 and the gate electrode 15 as a mask, As was ion-implanted into the substrate 11 under conditions of, for example, 10 keV 1 × 10 ¹⁵ cm ⁻² to form deep impurity regions. Next, heat treatment was performed at 600 ° C. or higher to activate the impurities, and the extension layer 24 and the source / drain regions 25 were formed. In order to activate the impurities, it is preferable to perform high-temperature treatment for a short time at about 1000 ° C. for about 10 seconds.

  After forming a Ni film on the entire surface and performing a heat treatment at about 400 ° C., unreacted Ni was removed by etching with a mixed liquid of sulfuric acid and hydrogen peroxide. Thus, the NiSi layer 26 is formed on the source / drain region 25, and as shown in FIG. 13, the silicon oxide film 27 is deposited on the entire surface by the CVD method to form an interlayer insulating film.

  Although not shown in the drawing, a MOS structure up to the first layer wiring is obtained thereafter by processing according to a conventional method. For example, contact holes are opened in the interlayer insulating film, TiN as a barrier metal is deposited by CVD, and W as a plug material is deposited on the entire surface. After filling the contact holes with TiN and W by CMP on the entire surface, an Al—Cu film is deposited as a wiring material and processed by photolithography to obtain a MOS structure up to the first layer wiring.

(Embodiment 2)
The present embodiment will be described with reference to FIGS. 14 and 15. The structure shown in FIG. 13 is prepared in the same manner as in the first embodiment.

As shown in FIG. 14, a Ni film 28 is deposited on the entire surface, and heat treatment is performed at about 400 ° C. to react all of the polycrystalline silicon and Ni to form Ni silicide. Since the temperature is about 400 ° C., the profile in the channel and the profile of the source / drain region do not change. P, As, Sb, or B may be introduced into the polycrystalline silicon in advance.
After the reaction, NiSi gate electrode 29 is obtained as shown in FIG. 15 by removing unreacted Ni using a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Although not shown in the drawing, a MOS structure up to the first layer wiring is obtained thereafter by processing according to a conventional method. For example, contact holes are opened in the interlayer insulating film, TiN as a barrier metal is deposited by CVD, and W as a plug material is deposited on the entire surface. After filling the contact holes with TiN and W by CMP on the entire surface, an Al—Cu film is deposited as a wiring material and processed by photolithography to obtain a MOS structure up to the first layer wiring.

Various modifications can be made to Embodiments 1 and 2 described above. For example, as a silicide layer formed on the source / drain region 25, CoSi ₂ or TiSi ₂ can be used, and SiGe may be used as a gate electrode. SiGe, for example a gas SiH ₄ or Si ₂ H _6, can be formed by mixing a gas containing Ge such as Ge ₂ H _6. Silicide and / or germanide may be used as the gate electrode. Examples of the silicide include WSi ₂ , NiSi, CoSi ₂ , PtSi, and MoSi ₂ . Examples of germanide include WGi ₂ , NiGe, NiGe ₂ , CoGe ₂ , PtGe, and MoGe ₂ . Alternatively, the gate electrode may be formed using a lanthanoid metal silicide or germanide.

As the first insulating film 13, HfO ₂ , or an oxide of aluminum and HfO ₂ , or a mixed film of ZrO ₂ or an oxide of silicon and Al ₂ O ₃ may be used. Mixed film of TiO ₂ or greater and an oxide of silicon, or a mixture of Al ₂ O _3. It may be an oxide of a lanthanoid metal typified by La ₂ O ₃ or a mixture thereof with SiO ₂ . A lanthanoid metal oxide or a mixture thereof with Al ₂ O ₃ may also be used.

The first insulating film 13 and the second insulating film 14 may be formed by MOCVD, halide CVD, or atomic layer deposition. It is desirable to nitride such an insulating film because it causes phase separation and crystallization of the film due to heat treatment such as electrode activation, leading to an increase in leakage current. For example, in an atmosphere containing NH ₃ It can be nitrided by CVD. Alternatively, an atmosphere containing N, for example, Hf in the case of Hf, can be performed by CVD using Hf (N (C ₂ H ₅ ) ₂ ) ₄ .

When the metal in the metal oxide is changed, a precursor containing nitrogen may be selected as a precursor containing the metal. Further, nitrogen activated by plasma can be contained in the atmosphere. Or you may expose to N plasma after film-forming. The interface film 18 is not necessarily a pure Si film, and may be SiN, SiO _x N _y , or SiO _x . Alternatively, a film containing a metal, for example, Hf at a low concentration (less than 19.8 at.%) Can also be used.

For the deposition of the interface film 18, a CVD method, a vapor deposition method, or a sol-gel method can be used. The interface film 18 may be oxidized in an NO or N ₂ O atmosphere. The temperature at this time is preferably 700 ° C. or higher and 1100 ° C. or lower. In order to maintain the impurity profile of the channel portion, short-time heat treatment RTA (Rapid Thermal Annealing) is desirable at a high temperature of 900 ° C. or higher. FLA (Flash Lamp Annealing) at 1200 to 1300 ° C. can also be used.

The source / drain region 25 can also be formed by depositing impurity-doped Si and diffusing from it. Alternatively, diffusion from an impurity-doped gate sidewall from SiO ₂ or SiON may be used. Further, the metal concentration in the second insulating film 14 need not be uniform. For example, it is also within the scope of the present invention to provide a gradient that decreases from the metal concentration in the first insulating film 13 to 6.6 at% or less at the gate electrode interface.

(Embodiment 3)
FIG. 16 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the present embodiment.

  In the semiconductor device shown in the figure, a first insulating film 32, a second insulating film 33, and a semiconductor gate electrode 34 are sequentially formed on the semiconductor substrate 31. The first insulating film 32 can be made of an insulating metal oxide, metal silicate, metal aluminate, or metal composite oxide.

  Hereinafter, a method of forming a gate insulating film including the first insulating film 32 and the second insulating film 33 by forming two types of nitrogen-added Hf silicate films (HfSiON films) having different compositions by sputtering. Will be explained.

A p-type Si (100) substrate was used as the semiconductor substrate, and normal SC ₂ (HCl / H ₂ O ₂ / H ₂ O) cleaning and HF treatment were performed. This was washed with pure water and dried, and then placed in an off-axis sputtering apparatus. Two targets, an Hf target and an Si target, were installed in the sputtering apparatus. A lower HfSiON film was formed by sputtering Hf and Si in an Ar, O ₂ , and N ₂ atmosphere.

  It was confirmed by RBS (Rutherford Backscattering Spectrometry) measurement that the Hf / (Hf + Si) ratio in the lower HfSiON film was about 80% and the nitrogen concentration was about 20 atomic%.

  Next, an upper HfSiON film was formed on the lower HfSiON film under the same conditions except that the power applied to the target was changed. Specifically, the power applied to the Hf target was reduced and the power applied to the Si target was increased to reduce the Hf content in the formed insulating film. As a result of measuring the Hf / (Hf + Si) ratio and the nitrogen concentration by RBS measurement, the Hf / (Hf + Si) ratio was about 0 to 60%, and the nitrogen concentration was about 15 atomic%. Since two types of HfSiON films having different compositions are successively deposited in the same vacuum, organic substances do not enter these boundaries. As a result, the upper HfSiON film surface is oxidized while obtaining a good interface.

  On the upper HfSiON film, a polycrystalline silicon film having a thickness of about 300 nm was deposited by low pressure CVD, and impurities were ion-implanted to obtain a predetermined conductivity type. When phosphorus is ion-implanted as an impurity, it becomes an n + -type polycrystalline silicon film, and when boron is ion-implanted, it becomes a p + -type polycrystalline silicon film. Impurities in the polycrystalline silicon film were activated by heat treatment at about 1000 ° C. for about 30 seconds.

  Finally, using the mask pattern, the polycrystalline silicon film, the upper HfSiON film, and the lower HfSiON film were processed by dry etching to obtain a semiconductor device as shown in FIG.

The gate insulating film including the first insulating film 32 and the second insulating film 33 can be formed by a similar method using an HfO ₂ film, an Hf aluminate film, an HfYO film, or the like. Further, Hf may be replaced with Zr or a lanthanoid element.

  For the formation of the first insulating film 32 and the second insulating film 33, a technique such as a CVD method, a vapor deposition method, an MBE method, or a laser ablation method may be used. For the reasons already described, it is preferable to nitride such an insulating film, and a similar method can be employed.

  Also in this embodiment, the gate electrode 34 can be changed to the material already described in the first and second embodiments. The other changes that can be made in the first and second embodiments are also applied to the third embodiment.

  In the above first to third embodiments, the present invention has been described by taking a CMOS LSI formed directly on a Si substrate as an example, but the present invention is not limited to such a structure. The present invention can also be applied to an SOI (Silicon ON Insulator) structure, a vertical MOS MOS LSI with a gas flowing in a direction perpendicular to the substrate, and a vertical MOS CMOS LSI with a current flowing through the side of a Si pillar.

  Furthermore, even when Ge, SiGe, strained Si, or strained Ge is used as the substrate, the semiconductor device according to the embodiment of the present invention can be manufactured by the above-described method, and the same effect can be obtained.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. Sectional drawing showing the detail of the layer structure of the semiconductor device concerning one Embodiment of this invention. Sectional drawing showing the conventional semiconductor device. The figure which shows the interface part Hf density | concentration dependence of the threshold value of P-MOS. FIG. 6 is a cross-sectional view showing a process in the method for manufacturing a semiconductor device according to the first embodiment. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. FIG. 11 is a cross-sectional view showing a step following FIG. 10. Sectional drawing which shows the process following FIG. Sectional drawing which shows the process following FIG. FIG. 6 is a cross-sectional view showing a process in a method for manufacturing a semiconductor device according to a second embodiment. FIG. 15 is a cross-sectional view showing a step following FIG. 14. FIG. 9 is a cross-sectional view showing a process in a method for manufacturing a semiconductor device according to a third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 20, 30 ... Semiconductor device; 11, 31 ... Semiconductor substrate; 12 ... Element isolation region 13, 32 ... 1st insulating film; 14, 33 ... 2nd insulating film 15, 34 ... Semiconductor gate electrode; Gate electrode side interface 17 ... Substrate side interface; 18 ... Interface film; 21 ... High dielectric gate insulating film 23 ... Gate side wall; 24 ... Extension layer; 25 ... Source / drain region 26 ... NiSi film; 28 ... Ni film 29 ... NiSi gate electrode.

Claims (6)

A semiconductor substrate provided with an element isolation region for defining an element region;
A source / drain region provided apart from the element region of the semiconductor substrate;
A gate insulating film provided on the element region of the semiconductor substrate;
A gate electrode provided on the gate insulating film and including a semiconductor;
The gate insulating film includes a first insulating film containing a metal and oxygen, and a second insulating film formed on the first insulating film and containing silicon and oxygen, and the second insulating film In the film, the metal content at the interface with the gate electrode is 6.6 atomic. A semiconductor device characterized by being less than%.   The second insulating film has a metal content of 5 atomic. At the interface with the gate electrode. % Or less of a semiconductor device.   3. The semiconductor device according to claim 1, wherein the metal is at least one selected from the group consisting of Hf, Zr, and a lanthanoid element. Forming a first insulating film containing metal and oxygen on a semiconductor substrate provided with an element isolation region for defining an element region;
The first insulating film contains Si and has a metal concentration of 19.8 at. A step of forming an interface film of less than
The interface film is oxidized so that the metal concentration on the surface is 6.6 at. Forming a second insulating film of less than% on the first insulating film to obtain a gate insulating film having a laminated structure;
Forming a gate electrode including a semiconductor on the gate insulating film; and introducing an impurity into the element region of the semiconductor substrate using the gate insulating film and the gate electrode as a mask to form a source / drain region The manufacturing method of the semiconductor device characterized by comprising the process of forming.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the interface film is a Si film, and the oxidation is performed by a heat treatment at 600 [deg.] C. or more.   The method of manufacturing a semiconductor device according to claim 4, wherein the interface film further contains a metal, and the oxidation is performed at room temperature or higher.

Images