JP2010141051A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device increasing the thermal stability of an NiPtSi electrode formed on a semiconductor substrate, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device including the semiconductor substrate, a channel region formed in the semiconductor substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and source/drain electrodes formed on both sides of the channel region and constituted of metal semiconductor compound layers containing Ni and Pt as the main components, wherein at an interface between the metal semiconductor compound layer and the semiconductor substrate, a maximum Pt concentration at a boundary between a single crystal grain of the metal semiconductor compound layer and the semiconductor substrate is higher than an average Pt concentration at the interface and the method of manufacturing the same are provided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a metal semiconductor compound layer is formed on a semiconductor substrate and a method for manufacturing the semiconductor device.

  In order to increase the functionality of integrated circuits, it is necessary to improve the performance of MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is a component of the integrated circuit. Until now, the improvement of device performance has been advanced by the proportional reduction law (scaling).

  As the channel length of the MISFET becomes shorter due to miniaturization, the channel resistance decreases. Therefore, the part performance other than the channel, that is, the resistance at the source / drain electrode, so-called parasitic resistance, greatly affects the device performance.

  A large proportion of the parasitic resistance is the interface resistance (Rc) between the source / drain electrodes and the semiconductor substrate. Therefore, reducing the interface resistance (Rc) is an important issue for improving the performance of the MISFET.

  A metal semiconductor compound such as nickel monosilicide (hereinafter also referred to as nickel silicide or NiSi) is often used as the source / drain electrode material. Since NiSi has a low specific resistance and consumes a small amount of Si in the silicidation reaction, it is an effective material as an ultrathin electrode material.

However, NiSi tends to cause abnormal diffusion of excess Ni atoms into the channel. When such abnormal diffusion of Ni occurs, junction leakage increases, causing a problem that, for example, the standby current of the LSI increases. In addition, there is a problem that nickel disilicide (NiSi ₂ ) having a high resistivity is generated depending on process conditions.

  In contrast, nickel silicide in which Pt (platinum) is mixed with Ni (hereinafter also referred to as nickel platinum silicide or NiPtSi) is the most promising electrode material at present because of its excellent characteristics of having both thermal stability and low interface resistance. is there. Conventionally, when forming a source / drain electrode of NiPtSi, an impurity (dopant) is ion-implanted and activated in Si of a substrate, Ni and Pt are sputter deposited, and finally silicidation is performed by heat treatment. Lived. This method is also referred to as Impurity Before Silicidation (IBS).

Further, as a technique for realizing low resistance of the interface resistance (Rc) between the metal silicide layer and the Si substrate, an impurity layer formed by ion implantation before the metal silicide formation is changed from a metal silicide layer at the time of metal silicide formation. There is a so-called impurity segregation process that segregates at the Si substrate interface and forms a high concentration impurity segregation layer at this interface. Furthermore, regarding p-type MISFETs, a method of performing impurity ion implantation after silicidation, a so-called impurity after-silicidation process (IAS) has been proposed (Non-patent Document 1).
T. T. Yamauchi et al. , “Novel doping technology for a 1 nm NiSi / Si junction with dipoles forming Schottky (DCS) barrier” IEDM Tech. Dig. , 2007, pp. 963-966

  The inventors focused on the fact that it is desirable that a high-concentration layer of Pt be formed at the interface in order to maximize the effect of Pt in the NiPtSi / Si junction.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that improve the thermal stability of the NiPtSi electrode provided on the semiconductor substrate. It is in.

  A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, a channel region in the semiconductor substrate, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film. A source / drain electrode formed on both sides of the channel region and made of a metal semiconductor compound layer mainly composed of Ni and Pt, and at the interface between the metal semiconductor compound layer and the semiconductor substrate, the metal semiconductor compound The maximum Pt concentration at the boundary between the single crystal grain of the layer and the semiconductor substrate is higher than the average Pt concentration at the interface.

  In the semiconductor device of the first aspect, an As impurity layer is formed at the interface, the As concentration peak is in the vicinity of the interface, and the As concentration at the bottom of the peak is on the side of the semiconductor substrate on the metal semiconductor layer side. Higher than that.

  A method for manufacturing a semiconductor device according to a second aspect of the present invention includes forming a gate insulating film on a semiconductor substrate, forming a gate electrode on the gate insulating film, and forming a first metal made of Ni on the semiconductor substrate. A film is deposited, a second metal film mainly composed of Ni and Pt is deposited on the first metal film, and the first and second metal films are reacted with the semiconductor substrate by heat treatment. A metal semiconductor compound layer is formed on both sides of the gate electrode.

  A method for manufacturing a semiconductor device according to a third aspect of the present invention is a method for manufacturing a semiconductor device having an n-type MISFET, wherein a gate insulating film is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating film. And depositing a metal film mainly composed of Ni and Pt on the semiconductor substrate, and reacting the metal film with the semiconductor substrate by a first heat treatment to form a metal semiconductor compound layer on both sides of the gate electrode. Forming As, introducing As into the metal semiconductor compound layer, and diffusing As to the interface between the metal semiconductor compound layer and the semiconductor substrate.

  In the method for manufacturing a semiconductor device according to the third aspect, it is preferable that As is introduced into the metal semiconductor compound layer by ion implantation and then diffused into the interface by a second heat treatment.

  In the semiconductor device manufacturing method of the third aspect, a solid phase film containing As is deposited on the metal semiconductor compound layer, and the As is transferred from the solid phase film to the metal semiconductor compound layer by a second heat treatment. It is desirable to introduce and diffuse the As to the interface.

  A semiconductor device according to a fourth aspect of the present invention includes a semiconductor substrate, a metal semiconductor compound layer containing Ni and Pt as main components on the semiconductor substrate, and a metal electrode on the metal semiconductor compound layer, The maximum Pt concentration at the boundary between the single crystal grain of the metal semiconductor compound layer and the semiconductor substrate at the interface between the metal semiconductor compound layer and the semiconductor substrate is higher than the average Pt concentration at the interface. And

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: depositing a first metal film made of Ni on a semiconductor substrate; and forming Ni and Pt as main components on the first metal film. A metal film is deposited, and the first and second metal films are reacted with the semiconductor substrate by heat treatment to form a metal semiconductor compound layer, and a metal electrode is formed on the metal semiconductor compound layer. And

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: depositing a metal film containing Ni and Pt as main components on a semiconductor substrate; and reacting the metal film with the semiconductor substrate by a first heat treatment. A metal semiconductor compound layer is formed, As is introduced into the metal semiconductor compound layer, the As is diffused into the interface, and a metal electrode is formed on the metal semiconductor compound layer.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the semiconductor device which improves the thermal stability of the NiPtSi electrode provided on a semiconductor substrate, and the manufacturing method of a semiconductor device.

  Hereinafter, a semiconductor device manufacturing method and a semiconductor device according to embodiments of the present invention will be described with reference to the drawings. In the present specification, “range” is synonymous with Projected Range (Rp) in the ion implantation process.

  First, knowledge obtained by the inventors about the NiPtSi / Si junction will be described first. FIG. 2 shows an element profile in the depth direction of NiPtSi / Si formed on a Si substrate by a standard NiPtSi layer forming method. Here, the standard production method is a so-called impurity prepreg process in which As is introduced into the Si substrate by ion implantation before the NiPtSi layer is formed on the Si substrate.

  FIG. 2 shows the result of analyzing the impurity distribution at the NiPtSi / Si interface using an atom probe. The horizontal axis indicates the depth from the surface of the silicide layer, and the vertical axis indicates the atomic concentration (%) of Pt. For confirmation of the interface position, Ni and Si distributions are also shown.

  2 that the highest Pt concentration is in the vicinity of the surface of the NiPtSi layer. It can also be seen that there is a Pt concentration peak near the center of the NiPtSi layer and further at the interface between the NiPtSi layer and the Si substrate. It can be seen that Pt does not reach the interface sufficiently due to the highest Pt concentration peak on the surface and the peak near the center of the NiPtSi layer.

  Here, the significance of the presence of Pt at the interface between the NiPtSi layer and the Si substrate will be described. As described in the background art, NiSi containing Pt has improved thermal stability compared to NiSi not containing Pt. In order to explore this basic principle, the inventors conducted verification by first-principles calculation and led to the elucidation of the principle. As a calculation method, a SP-GGA (Spin-Polarized Generalized Gradient Application) method that takes local polarization functional approximation into consideration and also considers spin polarization was adopted.

  FIG. 3 is a diagram for explaining the interface Pt behavior in NiSi / Si by the first principle calculation. FIG. 3A is a diagram illustrating a layer structure used in the calculation, and FIG. 3B is a diagram illustrating a total energy difference of Pt at each lattice position corresponding to the structure in FIG.

  According to this result, when Pt is contained in NiSi, it was derived that it is most energetically advantageous that Pt is replaced with Ni to become PtSi. Moreover, it was also derived from the analysis of the behavior of Pt atoms at the NiSi / Si interface that Pt has a stable point at the Si interface. From the above, it has been derived from the first principle that PtSi is stably formed at the interface with Si in the NiPtSi / Si structure.

  Next, the reason why the thermal stability of NiSi can be realized when PtSi is present at the interface was examined using two models of PtSi / Si and NiSi / Si. FIG. 4 is a diagram for explaining the thermal stability of PtSi by the first principle calculation. FIG. 4A is a diagram showing the total energy difference when Ni is present at the Si substitution position. FIG. 4 (b) shows the Ni reaction rate obtained from FIG. 4 (a).

  FIG. 4A shows that PtSi is more likely to adsorb Ni at the interface than NiSi. Also, from FIG. 4B, Ni is less likely to desorb from NiSi in PtSi in a practical annealing temperature range from 350 ° C. to 550 ° C. in the semiconductor device manufacturing process, and the thermal stability of the interface. It shows that it is excellent.

From the above, it can be concluded that PtSi is formed at the NiPtSi / Si interface, and that the thermal stability related to Ni desorption is improved by the benefit of the interface PtSi. That is, the increase in the PN junction junction leak is suppressed by suppressing the Ni desorption. In addition, it is possible to suppress the deterioration of the interface steepness due to NiSi ₂ which is caused by excess Ni regardless of the plane orientation.

  Thus, in principle, PtSi should be formed at the NiPtSi / Si interface, and the thermal stability of the silicide layer should be improved. However, as shown in FIG. 2, there is actually a factor that prevents the formation of PtSi at the interface, and the Pt concentration cannot be sufficiently increased at the interface.

  Therefore, first, in order to investigate the possibility of diffusion of Pt in the silicide, the diffusion barrier was calculated by the first principle calculation. FIG. 5 is a diagram for explaining an atomic diffusion barrier in silicide according to the first principle calculation. As shown in the figure, it can be seen that the energy barrier when Pt moves through the interstitial position in NiSi is about 1.8 eV. On the other hand, it can be seen that Ni in PtSi has a barrier of 2.6 eV or more. From the above, it can be seen that theoretically, Pt should be able to move relatively easily in NiSi.

  FIG. 6 is a diagram showing experimental results of Pt diffusion in the NiSi film. After depositing Pt on NiSi, annealing was performed at 450 ° C. for 30 seconds to analyze the concentration of Pt in the depth direction. From this result, it can be seen that Pt moves in the NiSi film toward the interface as theoretically.

  From the result of changing the annealing temperature and increasing the amount of movement of Pt, when the diffusion energy was derived experimentally, it was 1.6 eV, and a good correspondence with the above calculation result was obtained. This means that in the process of Pt segregation, the process of diffusing in the bulk of NiSi, in other words, in the crystal grains, is dominant.

  Thus, in principle, Pt should move easily in NiSi, and PtSi should be easily formed at the NiPtSi / Si interface. However, in reality, PtSi formation at the interface is hindered. The embodiments of the present invention completed by the inventors will be specifically described below based on the above knowledge.

(First embodiment)
The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having an n-type MISFET, in which a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, and the semiconductor A metal film composed mainly of Ni and Pt is deposited on the substrate, and the metal film is reacted with the semiconductor substrate by a first heat treatment to form a metal semiconductor compound layer on both sides of the gate electrode. As is introduced into the compound layer, and the introduced As is diffused in the interface between the metal semiconductor compound layer and the semiconductor substrate. Note that the semiconductor device of the present embodiment is an n-type MISFET.

  Hereinafter, a Si substrate will be described as an example of a semiconductor substrate, and a NiPtSi layer will be described as an example of a metal semiconductor compound layer. In this specification, the metal film containing Ni and Pt as main components is a metal film in which the atomic ratios of Ni and Pt in the metal film are larger than those of other components. Hereinafter, a metal film containing Ni and Pt as main components is also referred to as a NiPt film.

  Here, a case will be described in which As is introduced into the NiPtSi layer by ion implantation and As is diffused into the interface by the second heat treatment.

  FIG. 1 is a schematic view of a method for manufacturing a semiconductor device of the present embodiment. A NiPtSi layer is formed as a silicide layer on the Si substrate before the high concentration impurity layer is formed. The NiPtSi layer is formed by, for example, sputter deposition of a NiPt film and annealing.

  Next, As is introduced into the NiPtSi layer by ion implantation (IAS). Since no impurities are contained in the silicidation process, a reaction that excludes the interaction between Pt and impurities occurs. As a result, in the case of As, the Pt concentration at the interface is higher in the post-striking than in the pre-striking, and in particular, the Pt concentration can be increased at the interface with the Si substrate. Therefore, the thermal stability of the NiPtSi layer is improved.

  Further, As impurities are segregated at the interface by performing ion implantation and annealing after the NiPtSi layer is formed. As described above, an extremely shallow junction and a junction with low interface resistance can be obtained.

  7 to 11 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment.

First, for example, an element isolation region 12 (STI: Shallow Trench Isolation) made of a Si oxide film is formed on a p-type Si substrate 10 having a plane orientation (100) plane doped with B (boron) by about 10 ¹⁵ atoms / cm ^3. Form.

  Next, on the Si substrate 10, for example, a gate insulating film 14 made of an Si oxide film is formed to about 1 nm by EOT (Effective Oxide Thickness). Then, a polysilicon film to be the gate electrode 16 is deposited on the gate insulating film 14 by about 100 to 150 nm by a low pressure chemical vapor deposition (hereinafter also referred to as LP-CVD) method. Then, the gate insulating film 14 and the gate electrode 16 are patterned so as to have a gate length of about 30 nm by lithography techniques and etching techniques such as reactive ion etching (hereinafter also referred to as RIE). If necessary, post-oxidation of 1 to 2 nm is performed here.

  Next, after a silicon nitride film is deposited by, for example, about 8 nm by the LP-CVD method, the silicon nitride film is left only on the side surface portion of the gate electrode 16 by etching back by the RIE method. Thereby, the sidewall insulating film 18 is formed. Thus, the structure shown in FIG. 7 is formed.

  Next, as shown in FIG. 8, a NiPt film 20 having a thickness of about 10 nm is formed on the Si substrate 10 by sputtering, for example. That is, the NiPt film is deposited in contact with the source and drain regions of the n-type MISFET.

  Then, as shown in FIG. 9, as the first heat treatment, annealing is performed at 500 ° C. for about 30 seconds, for example, by RTA, the NiPt film 20 is reacted with the Si substrate 10 to be silicided, and the thickness is increased. A NiPtSi layer 22 having a thickness of about 20 nm is formed. At this time, the gate electrode 16 is also silicided to form a so-called FUSI structure. Thereafter, the unreacted excess NiPt film 20 is peeled off with a chemical solution. This NiPtSi layer 22 becomes a source / drain electrode of the n-type MISFT.

Next, As is ion-implanted as shown in FIG. This As will be introduced into the NiPtSi layer 22. The amount of As ion implantation is, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² .

  After that, as shown in FIG. 11, as the second heat treatment, for example, annealing is performed at 550 ° C. for about 30 seconds by RTA. As a result of this annealing, As is segregated at the NiPtSi layer 22 / Si substrate 10 interface, an As segregation layer 24 is formed.

  The temperature of the second heat treatment is desirably 350 ° C. or higher and 550 ° C. or lower. This is because if it falls below this range, the concentration of the As segregation layer 24 may not be sufficiently high. Further, if this temperature is exceeded, Ni in the NiPtSi layer 22 may abnormally diffuse into the Si substrate 10, which may increase junction leakage.

  The As ion implantation conditions are preferably set so that the range (Rp) immediately after the ion implantation is in the NiPtSi layer. As a result, As can be effectively segregated, the impurity concentration of the As segregation layer 24 can be further increased, and the As segregation layer 24 can be formed shallower.

  The semiconductor device according to the present embodiment is manufactured by the above-described method for manufacturing a semiconductor device. As shown in FIG. 11, the Si substrate 10, the channel region 29 in the Si substrate 10, and the gate insulation formed on the channel region 29. The n-type MISFET includes a film 14, a gate electrode 16 formed on the gate insulating film 14, and source / drain electrodes formed on both sides of the channel region 29 and made of the NiPtSi layer 22.

  The maximum Pt concentration at the boundary between the single crystal grain of the NiPtSi layer 22 and the Si substrate 10 at the interface between the NiPtSi layer 22 and the Si substrate 10 is higher than the average Pt concentration at this interface. To do. For this reason, the thermal stability of the NiPtSi layer is improved.

Further, an As segregation layer 24 is formed as an As impurity layer at the interface between the NiPtSi layer 22 and the Si substrate 10 and has an As concentration peak in the vicinity of the interface, and the As concentration at the bottom of this peak is on the NiPtSi layer 22 side. It is characterized by being higher than the Si substrate side. The As concentration of the As segregation layer 24 is, for example, 8 × 10 ^{19 to} 5 × 10 ²⁰ atoms / cm ³ . As will be described in detail later, the thermal stability of the NiPtSi layer 22 is further improved by the As distribution at the bottom of the peak.

  Here, a case where only the As segregation layer 24 is provided as the source / drain impurity layer will be described. However, for example, an extension diffusion layer having a concentration lower than that of the As segregation layer 24 may be provided. By providing the extension diffusion layer, it is possible to easily optimize the characteristics of the MISFET, specifically, to optimize the short channel effect and the operating current.

  Pt present at the interface between the NiPtSi layer 22 and the Si substrate 10 needs to be present in crystal grains such as the NiPtSi layer 22 from the viewpoint of improving thermal stability. However, Pt that is not taken into the crystal grains may be present at the grain boundaries of the NiPtSi layer 22 or the like.

  FIG. 12 is a diagram showing a distribution of Pt concentration in the vicinity of the NiPtSi / Si interface formed by the present embodiment and the conventional manufacturing method. FIG. 12 shows the result of evaluating the boundary between the single crystal grain of the NiPtSi layer at the interface and the Si substrate. FIG. 12A shows the impurity post-treatment process of the present embodiment, and FIG. 12B shows the impurity pre-treatment process of the prior art.

Here, the Pt atom concentration in the deposited NiPt film is 5%, the heat treatment for silicidation is 500 ° C. for 30 seconds, and the As ion implantation amount is 1 × 10 ¹⁵ cm ⁻² . Further, the heat treatment after silicide in the impurity post-implantation process is 550 ° C. and 30 seconds.

  FIG. 12 shows the result of analysis using an atom probe. In this specification, the interface position and atomic concentration of NiPtSi / Si are defined as follows based on the atom probe analysis. That is, the region where the Si concentration is 75% of the bulk Si substrate concentration is defined as the interface. This is called Proxigram. Draw a normal vector for the interface and integrate the element amount to obtain the atomic concentration.

  FIG. 12 shows a one-dimensional concentration distribution and interface position based on this definition. As is clear from FIG. 12, in the prior art, the maximum value of the Pt concentration at the boundary between the single crystal grain of the NiPtSi layer at the interface and the Si substrate is about 2.2%. Then, it is high at about 4.0%.

  FIG. 13 is a diagram comparing the Pt concentration at the NiPtSi / Si interface for the same sample as FIG. FIG. 13A is a diagram showing the measurement result of the Pt concentration, and FIG. 13B is an explanatory diagram of the measurement location. As in FIG. 12, the measurement is performed with an atom probe. The measurement is performed on a cylindrical region having a diameter of about 100 nm and a height of about 20 nm including the NiPtSi / Si interface. FIG. 13A shows the interface average, the Pt concentration at the boundary A, and the boundary B. Here, the interface average is a value obtained by averaging the Pt concentration in the entire cylindrical region. A cross-section of a portion corresponding to the entire cylindrical region is schematically shown by a horizontally long rectangle indicated by a thin broken line in FIG. The boundary portion A is a cylindrical region having a maximum Pt concentration when calculating the Pt concentration at the boundary between the crystal grain boundary portion of the NiPtSi layer and the Si substrate in the cylindrical region having a diameter of about 20 nm in the previous cylindrical region. Show. FIG. 13B schematically shows a cross section of a portion corresponding to the boundary portion A with a bold broken line rectangle. The boundary B is a cylindrical region showing the maximum Pt concentration when calculating the Pt concentration at the boundary between the single crystal grain of the NiPtSi layer and the Si substrate in the cylindrical region having a diameter of about 20 nm in the previous cylindrical region. Is shown. FIG. 13B schematically shows a cross section of a portion corresponding to the boundary portion B with a bold broken line rectangle.

  As is clear from FIG. 13, in the prior art, the Pt concentration at the boundary B is equal to the average Pt concentration at the interface. On the other hand, in the post-working of the present embodiment, the Pt concentration at the boundary portion B is higher than the average Pt concentration at the interface.

  Here, high-concentration Pt in the region of the boundary B is mainly present in the crystal grains of the NiPtSi layer or in the silicide microcrystal grains existing in the region sandwiched between the crystal grains of the NiPtSi layer and the Si substrate. . In addition, the Pt concentration at the boundary portion A is higher than that at the boundary portion B because the Pt that is not taken into the crystal grains exists in the grain boundary portion of the NiPtSi layer and the grain boundary between the Si substrates. This is because it is composed of What contributes to the thermal stability of the NiPtSi layer is only Pt present in the crystal grains. Therefore, as in this embodiment, the thermal stability is improved by increasing the Pt concentration in the crystal grains present at the interface. Furthermore, the fact that the Pt concentration in the crystal grains is higher than the average Pt concentration at the interface means that the added Pt is efficiently taken into the crystal grains and contributes to thermal stability. Also from this point, the Pt concentration distribution of the present embodiment is preferable.

  In the manufacturing method of the present embodiment, the reason why the Pt concentration at the interface becomes high is considered to be due to eliminating the influence of impurities in the NiPtSi formation process. That is, if As is present in the Si substrate before silicidation, Pt and As interact with each other by charge transfer during the silicidation process, and the movement of Pt is hindered. In NiPtSi on the n-type impurity layer, the problem that the Pt concentration at the interface does not become higher than that on the p-type impurity layer is also considered to be caused by this phenomenon.

  In the present embodiment, the impurities are post-implanted after NiPtSi is formed, so that the interaction between Pt and As is excluded as much as possible. As a result, as already shown in FIG. 12 and FIG. 13, in the impurity post-implantation process of the present embodiment, the concentration at the Pt interface increases. In particular, the Pt concentration increases in the crystal grains at the interface.

  FIG. 14 is a diagram showing the results of measuring the voltage-current characteristics at the NiPtSi / Si interface of the semiconductor device of the present embodiment. In the figure, for comparison, the measurement result of the NiSi / Si interface in the impurity post-implantation process is also shown. The preparation conditions for the NiPtSi / Si sample of the present embodiment are the same as those shown in FIGS.

  FIG. 14 shows that a high current is obtained with NiPtSi / Si. Here, from the current path of the sample, the resistance of NiPtSi and NiSi itself is also included in the voltage-current characteristics. Therefore, it can be said that the overall resistance includes not only the interface resistance but also the component of the silicide film itself.

In particular, since the resistance of NiPtSi / Si is low even in the forward characteristics, NiPtSi indicates that the resistance of the film itself is lower than that of NiSi. It can be said that NiSi has a high resistance because NiSi _{2 and the} like are formed by heat treatment.

  That is, this result also shows the thermal stability of NiPtSi. In addition, each sample has shown the case where annealing after As ion implantation is 550 degreeC. When the conditions were examined, the cases of 450 ° C. and 500 ° C. were also prepared, but the highest current was obtained when the annealing temperature was 550 ° C.

  However, it is also known that the optimum conditions for the annealing temperature differ depending on the silicide film thickness and the ion-implanted impurity concentration. It has also been found that it depends not only on the annealing temperature but also on the annealing time. By optimizing these conditions, it is possible to obtain the desired structure and characteristics.

  FIG. 15 is a diagram showing the As impurity distribution at the NiPtSi / Si interface according to the present embodiment. The sample preparation conditions of the present embodiment are the same as those in FIGS. FIG. 15 shows the results of analysis using an atom probe. The horizontal axis represents the depth from the silicide layer / Si substrate interface, and the vertical axis represents the atomic concentration (%) of As.

  As is apparent from the figure, As piles up near the interface. In addition, Proxigram of atom probe analysis is evaluated by excluding the distribution spread due to the interface roughness, and it can be seen from the figure that the impurity has an As concentration peak in a region of ± 1 nm or less with respect to the depth direction of the interface. Further, the half width of this peak is in the range of ± 1 nm or less with respect to the interface. Further, the As concentration at the bottom of the peak is higher on the silicide side (range from −6 to −1 nm on the horizontal axis in FIG. 15) than on the Si substrate side (range from 1 to 6 nm on the horizontal axis in FIG. 15).

However, in FIG. 15, the As concentration is not so high as a whole because the As ion implantation amount was set to be as low as 1 × 10 ¹⁵ cm ⁻² because of the sample for principle verification. The Pt concentration in the deposited NiPt film is 5%, which is not so high. Nevertheless, the As segregation effect by adding Pt to NiSi clearly appears.

  Thus, in the post-As process for the NiPtSi layer according to the present embodiment, the impurities diffuse to the interface by the heat treatment after the ion implantation, and are contained in a self-aligned manner at a stable point on the Si side of the interface. A concentration As segregation layer is formed.

  Hereinafter, this principle will be described. In the first-principles calculation, total energy was calculated for both PtSi / Si and NiSi / Si with a structure in which the impurity As or B was inserted at the substitution position.

  FIG. 16 is a diagram for explaining the interfacial impurity behavior based on the first principle calculation. FIG. 16 shows calculation results, where the vertical axis indicates energy and the horizontal axis indicates the position in the depth direction of the site. The energy standard is Si bulk.

  In both cases of As and B, there is a minimum of energy on the Si side of the interface. In addition, it can be seen that PtSi has higher energy for impurities than NiSi in silicide. From this result, in the case of As in particular, when PtSi is formed at the interface, it is derived that the post-impact of impurities is effective in segregating the impurities at the interface.

  Here, the reason will be described. FIG. 17 is a diagram for explaining the principle of the impurity post-implantation process of the present embodiment. According to FIG. 17, since PtSi seems to have higher potential energy for impurities than NiSi, PtSi behaves as a diffusion barrier during impurity migration.

In the conventional As segregation by the so-called snow shoveling effect, impurities are taken into the silicide film during the silicidation process, particularly at the stage of Ni ₂ Si or Pt ₂ Si. After that, monosilicidation is performed, and As taken in the silicide film cannot move to the Si side due to the PtSi barrier.

  On the other hand, in the case where a silicide structure, that is, NiSi / PtSi / Si has already been formed, if the impurity is post-implanted to this structure, the impurity is introduced into an interstitial position in the silicide. For this reason, As can easily exceed the PtSi barrier by heat treatment, and As will naturally fit in a stable position on the Si side. Therefore, it can be said that the increase in As concentration in NiPtSi due to post-impurity strikes is theoretically derived. Furthermore, as the diffusion of As from the inside of the silicide toward the interface is promoted, the As concentration at the bottom of the peak is higher on the NiPtSi layer side than on the Si substrate side.

  Thus, according to this embodiment, when As is used as an impurity, the impurity concentration in the vicinity of the NiPtSi layer / Si substrate interface can be increased, and as a result, the Schottky barrier height (SBH) is effectively reduced. Can be made. Further, the As concentration at the bottom of the peak is higher on the NiPtSi layer side than on the Si substrate side. Since As is present at a high concentration on the NiPtSi layer side, Si and unbonded Pt in the NiPtSi layer are combined with As and stabilized. Then, desorption of Pt to the Si substrate side is prevented. For this reason, the Pt concentration of the NiPtSi layer is maintained. As a result, the Ni diffusion suppressing effect of the NiPtSi layer is enhanced. In particular, this effect is remarkable when the NiPtSi layer is partially amorphized by post-strike by As ion implantation and Pt which is not bonded to Si increases. Therefore, the thermal stability of the NiPtSi layer is further improved. As described above, it can be said that this process is extremely effective for realizing low resistance of the interface resistance (Rc) of n-type MISFET and improving thermal stability.

  The amount of Pt contained in the Ni film is preferably 5% or more and 10% or less in terms of atomic concentration. This is because the effect of suppressing the abnormal diffusion of Ni starts to fall below this range. Moreover, if it exceeds this range, there is a concern about an increase in manufacturing cost due to the use of expensive Pt.

  Further, according to the present embodiment, the Pt concentration at the interface is higher than the average Pt concentration in the NiPtSi film. Therefore, even if the Pt concentration contained in the original Ni film is 10%, the Pt concentration at the interface is higher than that, and the characteristics of Pt can be fully utilized.

  As described above, according to the method for manufacturing a semiconductor device of the present embodiment, an n-type MISFET having a source / drain electrode with excellent thermal stability and low resistance and an extremely shallow impurity layer is realized. The n-type MISFET, which is the semiconductor device of the present embodiment, is excellent in thermal stability, reduces parasitic resistance, and has a very shallow impurity layer, thereby realizing high transistor characteristics.

(Second Embodiment)
In the method for manufacturing a semiconductor device according to the present embodiment, a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, a first metal film made of Ni is deposited on the semiconductor substrate, A second metal film containing Ni and Pt as main components is deposited on the first metal film, and the first and second metal films are reacted with the semiconductor substrate by heat treatment, and a metal semiconductor is formed on both sides of the gate electrode. A compound layer is formed. Note that the semiconductor device of the present embodiment is an n-type MISFET.

  Hereinafter, a Si substrate will be described as an example of a semiconductor substrate, and a NiPtSi layer will be described as an example of a metal semiconductor compound layer. Here, a case will be described in which As is introduced into the NiPtSi layer by ion implantation after the NiPtSi layer is formed and diffused to the interface by subsequent heat treatment. The semiconductor device manufacturing method of the present embodiment is different from the first embodiment in that the metal film deposited for silicide formation is a stacked film of Ni and NiPt. In addition, description is abbreviate | omitted about the content which overlaps with 1st Embodiment.

  FIG. 18 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the present embodiment. The manufacturing method of the semiconductor device according to the present embodiment will be described focusing on differences from the first embodiment.

  Similar to FIG. 7 of the first embodiment, a structure having a sidewall insulating film 18 on the side surface of the gate electrode 16 is formed. Thereafter, as shown in FIG. 18, a Ni film 26 having a thickness of about 3 nm is formed on the Si substrate 10 by, for example, sputtering. Next, a NiPt film 28 having a thickness of about 7 nm is formed on the Ni film 26. That is, the stacked film of Ni and NiPt is deposited in contact with the source / drain regions of the n-type MISFET.

  After that, as in the first embodiment, after the NiPtSi layer 22 is formed by heat treatment, the As segregation layer 24 is formed by As ion implantation and As diffusion by heat treatment. In this way, an n-type MISFET similar to that shown in FIG. 11 is formed.

  However, according to the present embodiment, the deposited Pt concentration at the interface between the NiPtSi layer 22 and the Si substrate 10 can be further increased by forming the deposited metal film as a laminated film of Ni and NiPt. Therefore, the thermal stability of the NiPtSi layer 22 is further improved.

  The reason why the Pt concentration at the interface is higher than that in the first embodiment will be described below. In the formation of the NiPtSi layer according to the first embodiment, a NiPt film is deposited on a Si substrate and then silicided by heat treatment to form a NiPtSi layer.

Considering the reaction process in time series, the production temperatures of Pt ₂ Si and Ni ₂ Si are approximately equal at about 200 ° C., and Si, Ni, and Pt are silicidized in the first reaction. However, at this point, it is not monosilicide but diplatinum silicide or dienickel silicide.

  Next, when the heat treatment temperature and time are increased, monosilicide is formed, but PtSi is formed first because the production temperature of PtSi is 300 ° C., which is lower than NiSi. Once this PtSi is formed, it is difficult to break the bond easily due to the high cohesive energy, and it remains at a specific location in the film.

  The PtSi formed at the initial stage of the reaction corresponds to the Pt concentration peak existing near the center of the NiPtSi layer in FIG. Therefore, it can be said that the root cause that prevents the high concentration at the interface of PtSi is the initial reaction of Pt.

  As described above, Pt basically moves easily in NiSi and can exist stably at the interface. Therefore, in order to suppress the Pt concentration in the central portion of the NiPtSi layer and increase the Pt concentration at the interface, it is important to suppress the initial reaction of Pt and prevent Pt immobilization.

FIG. 19 is a diagram for explaining the Ni / NiPt laminated film deposition method of the manufacturing method of the present embodiment. As shown in the figure, the Ni film in the lower layer is reacted first to form Ni ₂ Si, and the generation of Pt ₂ Si at the interface is suppressed. Thereafter, Pt diffuses from the NiPt film to the interface side to form PtSi.

  Thus, by depositing the Ni film first, the initial reaction of Pt is suppressed, and the Pt immobilization is prevented. Therefore, the Pt concentration at the interface between the NiPtSi layer and the Si substrate can be further increased.

  Here, the n-type MISFET has been described as an example. However, for example, it is also useful to apply this technique to a p-type MISFET by changing the impurity from As to B. In particular, the p-type MISFET has an advantage that a higher contact resistance reduction effect can be obtained by increasing the Pt concentration at the interface between the NiPtSi layer and the Si substrate to reduce the height of the Schottky barrier against holes.

(Third embodiment)
The manufacturing method of the semiconductor device of the present embodiment is a mode in which the manufacturing method of the second embodiment is applied not to the impurity post-treatment process but to the impurity pre-treatment process.

  Hereinafter, a Si substrate will be described as an example of a semiconductor substrate, and a NiPtSi layer will be described as an example of a metal semiconductor compound layer. Here, an As impurity is introduced by ion implantation before deposition of the metal film for forming the NiPtSi layer.

  20 to 22 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. A method for manufacturing a semiconductor device according to the present embodiment will be described focusing on differences from the first and second embodiments.

  Similar to FIG. 7 of the first embodiment, a structure having a sidewall insulating film 18 on the side surface of the gate electrode 16 is formed. Next, as shown in FIG. 20, As is ion-implanted and activation heat treatment is performed to form n-type impurity layers 30 on both sides of the channel region.

  Thereafter, as shown in FIG. 21, a Ni film 26 having a thickness of about 3 nm is formed on the Si substrate 10 by, eg, sputtering. Next, a NiPt film 28 having a thickness of about 7 nm is formed on the Ni film 26. That is, the stacked film of Ni and NiPt is deposited in contact with the source / drain regions of the n-type MISFET.

  Thereafter, similarly to the first embodiment, the NiPtSi layer 22 is formed by heat treatment. At this time, the As segregation layer 24 is formed by a so-called snow shoveling effect. In this way, the n-type MISFET shown in FIG. 22 is formed.

  According to the present embodiment, it is not possible to obtain the effect of improving the Pt concentration at the interface by post-stripping As as described in the first embodiment. However, it is possible to increase the Pt concentration at the interface between the NiPtSi layer and the Si substrate as compared with the conventional process in which no Ni film is interposed. Therefore, the thermal stability of the NiPtSi layer is improved. Therefore, an n-type MISFET having excellent thermal stability can be realized.

  Further, it is the same as the second embodiment that it is useful to apply this technique to the p-type MISFET.

(Fourth embodiment)
The manufacturing method of the semiconductor device of this embodiment is different from the manufacturing method of the first embodiment in that As is introduced into the metal semiconductor compound layer by ion implantation, while As is solid-phased in the metal semiconductor compound layer. It differs in that it is introduced by diffusion. Hereinafter, an Si substrate as a semiconductor substrate, a NiPtSi layer as a metal semiconductor compound layer, and an AsSG film (As Silicate Glass) that is an Si oxide containing As will be described as an example of a solid phase film containing As. Hereinafter, the description overlapping with the first embodiment is omitted.

  In this embodiment, after the NiPtSi layer is formed, an AsSG film is deposited on the NiPtSi layer, As is introduced from the AsSG film into the NiPtSi layer by the second heat treatment, and As is diffused at the interface between the NiPtSi layer and the Si substrate. It is characterized by making it.

  23 and 24 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. The manufacturing method of the semiconductor device according to the present embodiment will be described focusing on differences from the first embodiment.

  As shown in FIG. 9, the NiPt film 20 is reacted with the Si substrate 10 to be silicided to form the NiPtSi layer 22 having a thickness of about 20 nm, which is the same as in the first embodiment. Next, as shown in FIG. 23, an AsSG film 32 is deposited.

  The AsSG film 32 is formed by, for example, applying a solution in which AsSG is dissolved in a suitable solvent on a semiconductor, and then controlling the film thickness by spin coating. Thereafter, the solvent is volatilized by heat treatment to form the AsSG film 32.

  Next, as shown in FIG. 24, as the second heat treatment, for example, a heat treatment at 100 ° C. to 550 ° C. is performed. By this heat treatment, As is diffused from the AsSG film 32 in the crystal grains of the NiPtSi layer 22 or through the crystal grain boundaries. Then, As is segregated at the NiPtSi layer 22 / Si substrate 10 interface, the As segregation layer 24 is formed.

  Note that the processing temperature of the second heat treatment is preferably lower than the processing temperature of the first heat treatment for silicidation. This is to prevent the resistance of the electrode itself from increasing due to the composition change on the surface side of the NiPtSi layer 22.

  Here, after the AsSG film is deposited on the NiPtSi layer, when the As element is diffused into the NiPtSi film by heat treatment, As may diffuse unevenly due to the difference in crystallinity of the NiPtSi layer. For example, since a NiPtSi film on a Si (100) substrate is generally polycrystalline, a crystal grain boundary exists. It is conceivable that the diffusion of As element preferentially occurs at this crystal grain boundary.

  However, in the NiPtSi film, the size of the crystal grains can be changed depending on the Pt concentration. Rather, the As concentration at the NiPtSi / Si interface can be increased by increasing the diffusion at the grain boundary. is there. Therefore, the manufacturing method of the present embodiment basically has the same effect as the impurity post-implantation process of the first embodiment.

  Furthermore, according to the present embodiment, when As is introduced into the NiPtSi layer 22, there is no possibility that the NiPtSi layer 22 becomes amorphous unlike ion implantation. Therefore, there is no possibility that As is taken into the crystal when the amorphous NiPtSi layer 22 is resilicided. Therefore, there is an advantage that the segregation of As at the interface is promoted.

  Here, the AsSG film is selected as an example of the solid phase film, but other semiconductor materials or oxides thereof may be used. It is important to select a material that contains As as an impurity but does not diffuse other than As into the NiPtSi layer.

(Fifth embodiment)
The semiconductor device of the present embodiment is a method and a semiconductor device manufacturing method of a semiconductor device having a CMIS structure including the n-type MISFET and the p-type MISFET of the first embodiment. Accordingly, the description overlapping with the first embodiment is omitted.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 25 to 30 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment.

  First, the element isolation region 12 is formed on the p-type Si substrate 10. The element isolation region 12 is formed at the boundary between the first semiconductor region 50 where the n-type MISFET is formed and the second semiconductor region 60 where the p-type MISFET is formed. Thereafter, the p-type well 52 and the n-type well 62 are formed by ion implantation of impurities.

  Then, the gate insulating film 14 is formed on the semiconductor regions 50 and 60. Further, a polysilicon film to be the gate electrode 16 is deposited on the gate insulating film 14. Then, the gate insulating film 14 and the gate electrode 16 are patterned by a lithography technique and an etching technique such as RIE.

  Next, after depositing a silicon nitride film, the silicon nitride film is left only on the side surface of the gate electrode 16 by etching back by RIE. Thereby, the sidewall insulating film 18 is formed. As described above, the structure shown in FIG. 25 is formed.

  Next, as shown in FIG. 26, a NiPt film 20 is formed on the Si substrate 10. That is, the NiPt film 20 is deposited in contact with the source / drain regions of the n-type MISFET and the p-type MISFET.

  Then, as shown in FIG. 27, a first heat treatment is performed, and the NiPt film 20 is reacted with the Si substrate 10 to be silicided to form the NiPtSi layer 22. At this time, the gate electrode 16 is also silicided to form a so-called FUSI structure. Thereafter, the unreacted excess NiPt film 20 is peeled off with a chemical solution. This NiPtSi layer 22 becomes source / drain electrodes of n-type MISFT and p-type MISFT.

  Next, as shown in FIG. 28, B is selectively implanted into the NiPtSi layer 22 of the second semiconductor region 60 by ion implantation using the gate electrode 16, the sidewall insulating film 18 and the resist (not shown) as a mask. Introduce.

  Next, as shown in FIG. 29, As is selectively implanted into the NiPtSi layer 22 of the first semiconductor region 50 by ion implantation using the gate electrode 16, the sidewall insulating film 18 and the resist (not shown) as a mask. Introduce.

  Then, as shown in FIG. 30, as the second heat treatment, for example, annealing is performed at 550 ° C. for about 30 seconds by RTA. By this annealing, B impurities and As impurities are segregated at the NiPtSi layer 22 / Si substrate 10 interface, so that the B segregation layer 34 and the As segregation layer 24 are formed. In this way, a semiconductor device having a CMIS structure is formed.

  According to the method for manufacturing a semiconductor device of the present embodiment, both n-type MISFET and p-type MISFET have excellent thermal stability, low resistance source / drain electrodes, and CMIS having an extremely shallow impurity layer. A semiconductor device having a structure is realized. In the semiconductor device having the CMIS structure of the present embodiment, both the n-type MISFET and the p-type MISFET are excellent in thermal stability, and the parasitic resistance is reduced and the transistor characteristics are high by realizing the extremely shallow impurity layer. Is done.

  In particular, for the p-type MISFET, it is possible to reduce the interface resistance by reducing the Schottky barrier height due to the increase in the Pt concentration at the interface between the NiPtSi layer and the Si substrate.

Note that when B is introduced into the p-type MISFET by ion implantation, BF ₂ may be ion-implanted. According to the ion implantation of BF _2, the range (Rp) can be made smaller than B. That is, even with the same acceleration voltage as in the case of B, the distribution peak at the time of ion implantation is easily contained in the silicide, and the ion implantation conditions can be optimized more easily than in the case of B. Further, the effect of facilitating introduction of B into a thinner silicide layer can be obtained.

(Sixth embodiment)
This embodiment is the same as the fifth embodiment except that the impurity introduced into the p-type MISFET is not B but Mg in the method for manufacturing a semiconductor device having a CMIS structure and the semiconductor device.

  According to the present embodiment, it is possible to further reduce the interface resistance of the p-type MISFET as compared with the fifth embodiment.

  According to the present embodiment, an impurity segregation layer made of Mg is formed instead of B. The Mg impurity segregation layer is extremely effective in reducing the Schottky barrier height at the NiPtSi layer / Si substrate interface of the p-type MISFET and lowering the interface resistance. This is because when the impurity segregation layer containing Mg as an impurity is used more than in the case of B, the influence of an electric dipole (dipole) at the interface becomes stronger and the Schottky barrier height decreases.

  In the present embodiment, an impurity segregation layer may be formed together with B instead of Mg alone. This is because the solid solubility limit of Mg with respect to Si is lower than that of B, and therefore, when an impurity segregation layer is formed of Mg alone, the Schottky barrier height may not be sufficiently lowered due to insufficient impurity concentration.

  Further, even if Ca or Ba is applied instead of Mg, the same effect as Mg can be obtained.

(Seventh embodiment)
The semiconductor device manufacturing method and the semiconductor device of the present embodiment are the same as those of the fifth embodiment except that the n-type MISFET and the p-type MISFET constituting the semiconductor device are Fin-type MISFETs. Therefore, the description overlapping with that of the fifth embodiment is omitted.

  FIG. 31 is a perspective view of the semiconductor device of the present embodiment. As shown in FIG. 31, the semiconductor device of the present embodiment includes, for example, a Fin-type n-type MISFET 70 and a Fin-type p-type MISFET 80 on a silicon semiconductor substrate.

  The n-type MISFET 70 has a source / drain electrode made of the NiPtSi layer 22 and an As segregation layer 24 formed between the NiPtSi layer 22 and the substrate on both sides of the first channel region 72.

  The p-type MISFET 80 has a source / drain electrode made of the NiPtSi layer 22 and a B segregation layer 34 formed between the NiPtSi layer 22 and the substrate on both sides of the second channel region 82.

  The channel regions 72 and 82 of the n-type MISFET 70 and the p-type MISFET 80 have a Fin shape perpendicular to the Si substrate 10 and have two opposing main surfaces. A gate insulating film (not shown) is formed on each of the two main surfaces. A gate electrode 16 is formed on the gate insulating film. Thus, the MISFET of the seventh embodiment is a Fin-type MISFET having a so-called double gate structure.

  In the manufacturing method of the semiconductor device of the present embodiment, a known Fin type MISFET manufacturing method is applied. Among them, the NiPtSi layer 22, the B segregation layer 34, and the As segregation layer 24 are formed by the same method as in the fifth embodiment.

  The Fin-type MISFET has a characteristic that it has a strong resistance to a short channel because it has a very strong gate dominance and can suppress a drop in the barrier at the source end due to the drain electric field (Drain Induced Barrier Lowering). Therefore, according to the semiconductor device manufacturing method and the semiconductor device of the present embodiment, it is possible to obtain the effect of suppressing the short channel effect in addition to the effect of the fifth embodiment.

(Eighth embodiment)
In the method for manufacturing a semiconductor device of the present embodiment, a metal film containing Ni and Pt as main components is deposited on a semiconductor substrate, and the metal film is reacted with the semiconductor substrate by a first heat treatment. And As is introduced into the metal semiconductor compound layer, As is diffused into the interface between the metal semiconductor compound layer and the semiconductor substrate, and a metal electrode is formed on the metal semiconductor compound layer.

  In this embodiment, the first embodiment is applied to a metal contact electrode structure for establishing conduction from a wiring layer to a semiconductor substrate or an impurity layer formed in the semiconductor substrate. Accordingly, the description overlapping with the first embodiment is omitted.

  Hereinafter, a Si substrate will be described as an example of a semiconductor substrate, and a NiPtSi layer will be described as an example of a metal semiconductor compound layer. Here, a case where As is introduced into the NiPtSi layer by ion implantation and As is diffused to the interface by the second heat treatment will be described.

  32 to 36 are process cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. First, as shown in FIG. 32, an element isolation region 12 made of a Si oxide film is formed on a p-type Si substrate 10. Next, a NiPt film 20 having a thickness of about 10 nm is deposited on the Si substrate 10 by sputtering, for example.

  Thereafter, as shown in FIG. 33, as the first heat treatment, for example, annealing is performed at 500 ° C. for about 30 seconds by RTA, and the NiPt film 20 is reacted with the Si substrate 10 to be silicided to have a thickness of about 20 nm. The NiPtSi layer 22 is formed. Thereafter, the unreacted excess NiPt film 20 is peeled off with a chemical solution.

  Next, As is ion-implanted as shown in FIG. This As is introduced into the NiPtSi layer 22.

  Then, as shown in FIG. 35, as the second heat treatment, for example, annealing is performed at 550 ° C. for about 30 seconds by RTA. By this annealing, As is segregated at the interface of the NiPtSi layer 22 / Si substrate 10 and the As segregation layer 24 is formed.

  Next, as shown in FIG. 36, an Si oxide interlayer insulating film 90 is deposited on the Si substrate 10 by, eg, CVD. Thereafter, a contact hole is formed by a known lithography method and an etching technique such as reactive ion etching (hereinafter also referred to as RIE).

  Thereafter, a contact electrode 92 made of TiN barrier metal and W is formed in the contact hole by, eg, CVD. Thereafter, a Cu wiring layer 94 is formed on the contact electrode 92, for example.

  The semiconductor device of the present embodiment shown in FIG. 36 includes a Si substrate 10, a NiPtSi layer 20 on the Si substrate 10, and a contact electrode 92 on the NiPtSi layer 20. As in the first embodiment, in the region in the metal semiconductor compound layer within 1 nm in the depth direction from the interface between the NiPtSi layer 20 and the Si substrate 10, the Pt concentration in the crystal grains in this region is It is higher than the average Pt concentration in this region.

  According to the manufacturing method of the semiconductor device of the present embodiment, a contact electrode structure with high Pt concentration and excellent thermal stability at the interface between the NiPtSi layer 20 and the Si substrate 10 is realized. In addition, a low-resistance contact electrode structure having a high As concentration at the interface between the NiPtSi layer 20 and the Si substrate 10 can be realized. The contact electrode structure that is the semiconductor device of this embodiment has high thermal stability and low resistance contact characteristics.

  Here, the contact structure having no n-type impurity layer other than the As segregation layer 24 has been described as an example. From the viewpoint of suppressing junction leakage between the contact electrode 92 and the Si substrate 10, it is desirable to have an n-type impurity layer having a lower concentration than the As segregation layer 24. However, a low-concentration n-type impurity layer is not necessarily essential from the viewpoint of reducing contact resistance.

  Further, here, the contact electrode structure in which the n-type impurity layer on the p-type Si substrate is electrically connected from the wiring layer has been described. However, this embodiment can also be applied to a contact electrode structure in which a p-type Si substrate is replaced with an n-type Si substrate, that is, a contact electrode structure that is electrically connected to the n-type Si substrate itself. is there.

  Further, a p-type impurity layer on the n-type Si substrate or the p-type Si substrate is formed by introducing a p-type impurity such as B into the NiPtSi layer 20 to form a B segregation layer. This embodiment can also be applied to a contact electrode structure in which the p-type impurity layer is electrically connected from the wiring layer.

(Ninth embodiment)
In the present embodiment, the second embodiment is applied to a metal contact electrode structure for establishing conduction from a wiring layer to a semiconductor substrate or an impurity layer formed in the semiconductor substrate. That is, this embodiment is different from the eighth embodiment in that the metal film deposited for silicide formation is a laminated film of Ni and NiPt. Hereinafter, the description overlapping with the second and eighth embodiments is omitted.

  FIG. 37 is a process sectional view showing the method for manufacturing the semiconductor device of this embodiment. A method for manufacturing a semiconductor device according to the present embodiment will be described focusing on differences from the eighth embodiment.

  As in the eighth embodiment, an element isolation region 12 made of a Si oxide film is formed on a p-type Si substrate 10. Thereafter, as shown in FIG. 37, a Ni film 26 having a thickness of about 3 nm is formed on the Si substrate 10 by sputtering, for example. A NiPt film 28 having a thickness of about 7 nm is formed on the Ni film 26.

  Thereafter, as in the eighth embodiment, after the NiPtSi layer 22 is formed by heat treatment, an As segregation layer is formed by As ion implantation and As diffusion by heat treatment. In this way, a contact electrode structure similar to that shown in FIG. 36 is formed.

  According to the present embodiment, the deposited metal film is a multilayer film of Ni and NiPt, so that the Pt concentration at the interface between the NiPtSi layer 22 and the Si substrate 10 is higher than that in the eighth embodiment. It becomes possible to do. Therefore, the thermal stability of the NiPtSi layer 22 is further improved. Therefore, in addition to the effect of the eighth embodiment, a contact electrode structure with further improved thermal stability can be realized.

(Tenth embodiment)
In the semiconductor device manufacturing method of the present embodiment, the third embodiment is applied to a metal contact electrode structure for establishing conduction from a wiring layer to a semiconductor substrate or an impurity layer formed in the semiconductor substrate. It is a form. That is, this embodiment is different from the eighth embodiment in that impurities are introduced into the NiPtSi layer not by the impurity post-treatment process but by the impurity pre-treatment process. Hereinafter, the description overlapping with the third and eighth embodiments is omitted.

  According to the present embodiment, the effect of improving the Pt concentration at the interface by post-stripping As cannot be obtained. However, it is possible to increase the Pt concentration at the interface between the NiPtSi layer and the Si substrate as compared with the conventional process in which no Ni film is interposed. Therefore, it is possible to realize a contact electrode structure that improves the thermal stability of the NiPtSi layer.

(Eleventh embodiment)
In the semiconductor device manufacturing method of the present embodiment, the fourth embodiment is applied to a metal contact electrode structure for establishing conduction from a wiring layer to a semiconductor substrate or an impurity layer formed in the semiconductor substrate. It is a form. That is, this embodiment is different from the eighth embodiment in that As is not introduced by ion implantation but As is introduced by solid phase diffusion. Hereinafter, the description overlapping with the fourth and eighth embodiments is omitted.

  According to the present embodiment, in addition to the effects of the eighth embodiment, there is no possibility of making the NiPtSi layer 22 amorphous as in the case of ion implantation when introducing As into the NiPtSi layer 22. Therefore, there is no possibility that As will be taken into the crystal when the amorphous NiPtSi layer 22 is resilicided. Therefore, As segregation at the interface is promoted, and a contact structure with lower resistance can be realized.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example and does not limit the present invention. In the description of the embodiments, the description of the semiconductor device manufacturing method, the semiconductor device, etc., which is not directly necessary for the description of the present invention is omitted, but the required semiconductor device manufacturing method, Elements related to the semiconductor device and the like can be appropriately selected and used.

  In addition, all semiconductor device manufacturing methods and semiconductor devices that include elements of the present invention and whose design can be changed as appropriate by those skilled in the art are included in the scope of the present invention.

For example, the semiconductor substrate has been described by taking the Si substrate as an example. However, the substrate is not necessarily limited to the Si substrate, and an Si _x Ge _1-x (0 <x <1) substrate may be applied.

  Also, the Si substrate has been described as an example of a substrate having a (100) plane orientation. However, not only (100) but also Si substrates having other plane orientations such as (110) and (111) can be applied.

  Further, for example, the gate insulating film has been described by taking the Si oxide film as an example. However, it is desirable to apply a high-k insulating film instead of the Si oxide film because the performance of the MISFET is improved. As the high-k insulating film, for example, oxides of rare earth elements such as Hf, Zr, Al, and La, silicate, nitride silicate, or a mixture or laminate thereof can be used.

  Further, for example, the gate electrode has been described by taking as an example a so-called FUSI (FULY Silicided) structure formed of NiPtSi similarly to the source / drain electrodes. However, it is not essential that the gate electrode has a FUSI structure. For example, a laminated structure of polysilicon and metal silicide may be used. Further, for example, a stacked structure of metal and metal silicide may be used. Alternatively, a metal gate structure in which the entire gate electrode is made of metal may be used. In this case, as the metal material, for example, a single metal of Ti, Ta, or W, or a nitride or carbide of these metals can be applied. In addition, for example, a gate having a laminated structure composed of three layers of a single metal of Ti, Ta, W, or a nitride or carbide of these metals, a barrier metal such as WN, and a silicide such as NiSi or NiPtSi. It may be an electrode.

  In addition, the elements of the above embodiments can be applied to other embodiments as appropriate.

  The scope of the present invention is defined by the appended claims and equivalents thereof.

It is the schematic of the manufacturing method of the semiconductor device of 1st Embodiment. It is a figure which shows the result of having analyzed the impurity distribution of the NiPtSi / Si interface. It is a figure explaining the interface Pt behavior in NiSi / Si by the first principle calculation. It is a figure explaining the thermal stability of PtSi by a first principle calculation. It is a figure explaining the atomic diffusion barrier in silicide by the first principle calculation. It is a figure which shows the experimental result of Pt diffusion in a NiSi film. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a figure which shows distribution of Pt density | concentration of the NiPtSi crystal grain vicinity of the NiPtSi / Si interface formed with the manufacturing method of this Embodiment and a prior art. It is the figure which compared Pt density | concentration near NiPtSi / Si interface. It is a figure which shows the result of having measured the voltage-current characteristic of the NiPtSi / Si interface of the semiconductor device of 1st Embodiment. It is a figure which shows As impurity distribution in the NiPtSi / Si interface of 1st Embodiment. It is a figure explaining the interface impurity behavior by the first principle calculation. It is a figure explaining the principle of the impurity post-implantation process of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is a figure explaining the Ni / NiPt laminated film deposition method of the manufacturing method of the semiconductor device of 2nd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 5th Embodiment. The perspective view of the semiconductor device of 7th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 8th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 8th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 8th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 8th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 8th Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 9th Embodiment.

Explanation of symbols

10 Si substrate 12 Element isolation region 14 Gate insulating film 16 Gate electrode 18 Side wall insulating film 20 NiPt film 22 NiPtSi layer 24 As segregation layer 26 Ni film 28 NiPt film 29 Channel region 30 n-type impurity layer 32 AsSG film 34 B segregation layer 50 First semiconductor region 52 p-type well 60 Second semiconductor region 62 n-type well 70 n-type MISFET
72 channel region 80 p-type MISFET
82 Channel region 90 Interlayer insulating film 92 Contact electrode 94 Wiring layer

Claims (9)

A semiconductor substrate;
A channel region in the semiconductor substrate;
A gate insulating film formed on the channel region;
A gate electrode formed on the gate insulating film;
A source / drain electrode formed on both sides of the channel region and comprising a metal semiconductor compound layer mainly composed of Ni and Pt;
The maximum Pt concentration at the boundary between the single crystal grain of the metal semiconductor compound layer and the semiconductor substrate at the interface between the metal semiconductor compound layer and the semiconductor substrate is higher than the average Pt concentration at the interface. A featured semiconductor device.   An As impurity layer is formed at the interface, has an As concentration peak near the interface, and an As concentration at the bottom of the peak is higher on the metal semiconductor layer side than on the semiconductor substrate side. Item 14. A semiconductor device according to Item 1. Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Depositing a first metal film made of Ni on the semiconductor substrate;
Depositing a second metal film mainly composed of Ni and Pt on the first metal film;
A method of manufacturing a semiconductor device, comprising: reacting the first and second metal films with the semiconductor substrate by heat treatment to form metal semiconductor compound layers on both sides of the gate electrode. A method of manufacturing a semiconductor device having an n-type MISFET,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Depositing a metal film mainly composed of Ni and Pt on the semiconductor substrate;
A first heat treatment to react the metal film with the semiconductor substrate to form a metal semiconductor compound layer on both sides of the gate electrode;
A manufacturing method of a semiconductor device, wherein As is introduced into the metal semiconductor compound layer, and the As is diffused in an interface between the metal semiconductor compound layer and the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 4, wherein after As is introduced into the metal semiconductor compound layer by ion implantation, the As is diffused into the interface by a second heat treatment.   A solid phase film containing As is deposited on the metal semiconductor compound layer, the As is introduced from the solid phase film into the metal semiconductor compound layer by a second heat treatment, and the As is diffused into the interface. The method of manufacturing a semiconductor device according to claim 4, wherein: A semiconductor substrate;
A metal semiconductor compound layer mainly composed of Ni and Pt on the semiconductor substrate;
A metal electrode on the metal semiconductor compound layer,
The maximum Pt concentration at the boundary between the single crystal grain of the metal semiconductor compound layer and the semiconductor substrate at the interface between the metal semiconductor compound layer and the semiconductor substrate is higher than the average Pt concentration at the interface. A featured semiconductor device. Depositing a first metal film made of Ni on a semiconductor substrate;
Depositing a second metal film mainly composed of Ni and Pt on the first metal film;
The first and second metal films are reacted with the semiconductor substrate by heat treatment to form a metal semiconductor compound layer,
A method of manufacturing a semiconductor device, comprising forming a metal electrode on the metal semiconductor compound layer. Depositing a metal film mainly composed of Ni and Pt on a semiconductor substrate;
By the first heat treatment, the metal film is reacted with the semiconductor substrate to form a metal semiconductor compound layer,
As is introduced into the metal semiconductor compound layer, and the As is diffused to the interface between the metal semiconductor compound layer and the semiconductor substrate,
A method of manufacturing a semiconductor device, comprising forming a metal electrode on the metal semiconductor compound layer.

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