JP5589474B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a P-type transistor and an N-type transistor on a semiconductor substrate, and a method for manufacturing the same.

  In recent LSIs of the so-called 90 nm node and beyond, further miniaturization has been demanded, and it has become difficult to improve the performance of transistors. This is because the standby off-leakage current increases as the gate length is shortened, so that it is extremely difficult to improve the current driving capability if the off-leakage current is kept constant. For this reason, new approaches for improving the performance of transistors are being searched.

  As one of the attempts, strained silicon technology is one of the most promising technologies being developed. This is a technique for applying strain to the channel region of a CMOS transistor. Specifically, thin films for applying compressive stress or tensile stress as appropriate are formed in the channel regions of the N-type transistor and the P-type transistor, respectively. As a result, stress is applied to the channel region, the band structure is changed, the effective mass of carriers is reduced, and carrier mobility is improved.

JP 2007-49092 A JP 2007-59473 A JP 2006-229071 A JP 2007-208166 A

In general, when manufacturing a CMOS transistor, the number of processes is reduced by making the manufacturing process common to both the N-type transistor and the P-type transistor as much as possible.
However, in the conventional strained silicon technology, although the number of processes is reduced, a device for applying an optimum stress to each channel region of the N-type transistor and the P-type transistor is not so much studied.

  The present invention has been made in view of the above-described problems. Both the N-type transistor and the P-type transistor share the same manufacturing process as much as possible to reduce the number of processes as much as possible. It is an object of the present invention to provide a highly reliable semiconductor device and a method for manufacturing the same, in which a stress suitable for each of a p-type transistor and a p-type transistor is appropriately applied to realize a significant improvement in transistor performance.

An aspect of the semiconductor device is a semiconductor device including a P-type transistor and an N-type transistor on a semiconductor substrate, and the P-type transistor covers a first gate and a part of a side wall of the first gate. Covers all of the first sidewall film and the surface of the first sidewall film on the side opposite to the first gate, and the first gate is formed only on both side surfaces of the first gate. A first film that applies tensile stress; and a second film that is formed so as to cover the first gate and the first film and that applies compressive stress; Is formed so as to cover the second gate, and has a third film for applying a tensile stress.

An aspect of a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device provided with a P-type transistor and an N-type transistor on a semiconductor substrate, and the first region of the P-type transistor is first on the semiconductor substrate. Forming a second gate in the second region of the N-type transistor, forming a first sidewall film covering a part of the sidewall of the first gate, The first region covers the entire surface of the first sidewall film on the side opposite to the first gate, and the second gate is formed only on both side surfaces of the first gate . Forming a first film for applying tensile stress in the region so as to cover the second gate; and compressive stress in the first region so as to cover the first gate and the first film. Forming a second film that provides

  According to each aspect described above, both the N-type transistor and the P-type transistor share the same manufacturing process as much as possible to reduce the number of processes as much as possible. As a result, a semiconductor device can be realized in which a significant improvement in transistor performance is obtained by appropriately applying a stress suitable for the above.

It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by this embodiment in order of a process. FIG. 2 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes subsequent to FIG. 1. FIG. 3 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing method of the CMOS transistor according to the present embodiment in order of processes following FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes following FIG. 5. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the method of manufacturing the CMOS transistor according to the present embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view showing the CMOS transistor manufacturing method according to the present embodiment in the order of steps, following FIG. 7. FIG. 9 is a schematic cross-sectional view subsequent to FIG. 8 showing the method of manufacturing the CMOS transistor according to the present embodiment in the order of steps. It is a characteristic view showing an experimental result of investigating the relationship between the on-current and off-current of the P-type MOS transistor in the present embodiment. FIG. 11 is a partial cross-sectional view schematically showing that the tensile stress film in FIG. 10 is formed with a different thickness.

  Hereinafter, specific embodiments of a semiconductor device and a manufacturing method thereof will be described in detail with reference to the drawings. In this embodiment, a CMOS transistor is exemplified as a semiconductor device, and the device configuration will be described together with a manufacturing method.

1 to 9 are schematic sectional views showing the method of manufacturing the CMOS transistor according to the present embodiment in the order of steps.
First, as shown in FIG. 1A, a semiconductor substrate, here, a silicon substrate 10 having a plane orientation (100) or the like is prepared. An element isolation structure 11 is formed on the silicon substrate 10.
Specifically, the isolation trench 11a is formed in the element isolation region on the silicon substrate 10 by, for example, STI (Shallow Trench Isolation). An insulator such as silicon oxide is embedded in the isolation groove 11a, and the silicon oxide is planarized by a chemical mechanical polishing (CMP) method or the like. As a result, an element isolation structure 11 for defining an element active region on the silicon substrate 10 is formed. In the illustrated example, as the element active region defined by the element isolation structure 11, the left side in the drawing is an N-type MOS transistor formation region (N-type region) 10 a, and the right side in the drawing is a P-type MOS transistor formation region (P-type). Region) 10b.

Subsequently, as shown in FIG. 1B, wells 12a and 12b are formed.
Specifically, a resist mask is appropriately formed by lithography, and a P-type impurity such as boron (B) is ion-implanted into the N-type region 10a with a predetermined dose and acceleration energy. On the other hand, an N-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the P-type region 10b with a predetermined dose and acceleration energy. As a result, a well 12a is formed in the N-type region 10a, and a well 12b is formed in the P-type region 10b.

Subsequently, as shown in FIG. 2A, gate electrodes 14a and 14b are formed.
Specifically, a thin gate insulating film 13 having a thickness of, for example, about 3 nm is formed on the N-type region 10a and the P-type region 10b by a thermal oxidation method or the like. A polycrystalline silicon film is deposited. Then, the polycrystalline silicon film and the gate insulating film 13 are patterned into electrode shapes by lithography and subsequent dry etching. As a result, the gate electrode 14a is formed on the gate insulating film 13 in the N-type region 10a, and the gate electrode 14b is formed on the gate insulating film 13 in the P-type region 10b.

Subsequently, as shown in FIG. 2B, an extension region 16a is formed in the N-type region 10a.
More specifically, first, a resist is applied on the silicon substrate 10, and the resist is processed by lithography to form a resist pattern 15b that covers the P-type region 10b and exposes the N-type region 10a.
Next, using the resist pattern 15b as a mask, N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the N-type region 10a with a predetermined dose and acceleration energy. Thereby, extension regions 16a are formed on both sides of the gate electrode 14a in the N-type region 10a.
Thereafter, the resist pattern 15b is removed by ashing (ashing) or the like.

Subsequently, as shown in FIG. 3A, an extension region 16b is formed in the P-type region 10b.
More specifically, first, a resist is applied on the silicon substrate 10, and the resist is processed by lithography to form a resist pattern 15a that covers the N-type region 10a and exposes the P-type region 10b.
Next, using the resist pattern 15a as a mask, a P-type impurity such as boron (B) is ion-implanted into the P-type region 10b with a predetermined dose and acceleration energy. Thereby, extension regions 16b are formed on both sides of the gate electrode 14b in the P-type region 10b.
Thereafter, the resist pattern 15a is removed by ashing or the like.

Subsequently, as shown in FIG. 3B, sidewall insulating films 17 are formed on both side surfaces of the gate electrodes 14a and 14b, respectively.
Specifically, an insulating film such as a silicon oxide film (or silicon nitride film) is deposited on the entire surface of the silicon substrate 10 by the CVD method, and the entire surface of the silicon oxide film is etched back. As a result, the silicon oxide film remains only on both side surfaces of the gate electrodes 14a and 14b, and the sidewall insulating film 17 is formed.

Subsequently, as shown in FIG. 4A, source / drain regions 19b are formed in the P-type region 10b.
Specifically, first, a resist is applied on the silicon substrate 10, and the resist is processed by lithography to form a resist pattern 18a that covers the N-type region 10a and exposes the P-type region 10b.
Next, using the resist pattern 18a as a mask, a P-type impurity such as boron (B) is ion-implanted into the P-type region 10b with a predetermined dose and acceleration energy. As a result, source / drain regions 19b partially overlapping with the extension regions 16b are formed on both sides of the gate electrode 14b in the P-type region 10b.

Subsequently, as shown in FIG. 4B, only the sidewall insulating films 17 formed on both side surfaces of the gate electrode 14b are etched to be lowered.
Specifically, using the resist pattern 18a as a mask, only the sidewall insulating film 17 formed on both side surfaces of the gate electrode 14b in the P-type region 10b is etched, here wet etching. The wet etching is performed, for example, for about 10 seconds using, for example, 0.5% concentration hydrofluoric acid as an etching solution. As a result, the tops of the sidewall insulating films 17 formed on both side surfaces of the gate electrode 14b recede downward, and the sidewall insulating films 17 are lowered. In the present embodiment, the sidewall insulating film 17 formed on both side surfaces of the gate electrode 14b is lowered by, for example, about 10 nm to 20 nm due to the above etching conditions. The etching amount of the sidewall insulating film 17 is adjusted to a value within the above range in consideration of the amount of reduction of the sidewall insulating film 17 due to the pre-processing of the silicide processing described later.
Thereafter, the resist pattern 18a is removed by ashing (ashing) or the like.

In the present embodiment, as will be described later, the height of the sidewall insulating film 17 is adjusted to be lower than that of the upper surface of the gate electrode 14b in order to ensure a desired thickness of the tensile stress film formed on both side surfaces of the P-type region 10b. . Here, if the sidewall insulating film 17 is etched before the formation of the P source / drain regions 19b, the effective gate length (L _eff ) of the manufactured P-type MOS transistor is reduced, resulting in characteristic fluctuations. In this embodiment, paying attention to this point, after forming the source / drain regions 19b in the P-type region 10b, the sidewall insulating films 17 formed on both side surfaces of the gate electrode 14b are etched. This realizes transistor characteristics in which the short channel effect is suppressed without reducing L _eff of the P-type MOS transistor.

  On the other hand, when the sidewall insulating film is formed low, there is a concern that spikes due to the silicide layer formed in the upper layer portion of the gate electrode and the upper layer portion of the source / drain region may occur due to the silicide treatment described later. If a spike due to the silicide layer of the gate electrode is generated, there is a risk of adversely affecting the gate insulating film. When a spike is generated by the source / drain region silicide layer, there is a possibility that junction leakage occurs at the edge portion of the gate electrode. However, the occurrence of an adverse effect on the gate insulating film has a greater effect on the N-type MOS transistor than on the P-type MOS transistor. In the present embodiment, only the sidewall insulating film 17 in the P-type region 10b is etched, and the sidewall insulating film 17 in the N-type region 10a is masked so as not to be etched. As a result, it is possible to minimize the occurrence of adverse effects on the gate insulating film.

Subsequently, as shown in FIG. 5A, source / drain regions 19a are formed in the N-type region 10a.
Specifically, first, a resist is applied on the silicon substrate 10, and the resist is processed by lithography to form a resist pattern 18b that covers the P-type region 10b and exposes the N-type region 10a.
Next, using the resist pattern 18b as a mask, an N-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the N-type region 10a with a predetermined dose and acceleration energy. As a result, source / drain regions 19a partially overlapping with the extension regions 16a are formed on both sides of the gate electrode 14a in the N-type region 10a.
Thereafter, the resist pattern 18b is removed by ashing (ashing) or the like.

Subsequently, as shown in FIG. 5B, pre-processing of silicide processing (salicide processing) of the gate electrodes 14a and 14b and the source / drain regions 19a and 19b is performed.
Specifically, as a pretreatment for the silicide treatment, the entire surface of the silicon substrate 10 is wet-etched using, for example, hydrofluoric acid. Thereby, the sidewall insulating films 17 on both side surfaces of the gate electrodes 14a and 14b are also etched and lowered. In the present embodiment, each sidewall insulating film 17 is lowered by, for example, about 10 nm to 30 nm. That is, the sidewall insulating films 17 on both sides of the gate electrode 14a are lowered by, for example, about 10 nm to 30 nm from the initial state (the state shown in FIG. 3B). On the other hand, the sidewall insulating films 17 on both side surfaces of the gate electrode 14b are lowered from the initial state (the state of FIG. 3B) by, for example, (about 10 nm to 20 nm) + (about 10 nm to 30 nm) by about 20 nm to 50 nm. . Since the side wall insulating films 17 on both side surfaces of the gate electrode 14b are substantially the same height as the upper surface of the gate electrode 14b in the initial state, the sidewall insulating films 17 are about 20 to 50 nm lower than the upper surface.

Subsequently, as shown in FIG. 6A, silicide processing (salicide processing) is performed on the gate electrodes 14a and 14b and the source / drain regions 19a and 19b.
Specifically, first, a silicide metal such as Co or Ni is deposited to a predetermined thickness by sputtering or the like so as to cover the entire surface of the silicon substrate 10. Then, the silicon substrate 10 is annealed at a predetermined temperature, for example, about 500 ° C. to 550 ° C. in the case of Co, and about 200 ° C. to 250 ° C. in the case of Ni, so that the gate electrodes 14a and 14b and the source / drain regions The upper layer portions 19a and 19b are silicided. Thereafter, unreacted silicide metal is removed by wet etching or the like. For this wet etching, for example, a mixed solution of ammonia and hydrogen peroxide solution or a mixed solution of sulfuric acid and hydrogen peroxide solution is used as an etching solution. Thereafter, the silicon substrate 10 is annealed again at a predetermined temperature, for example, about 650 ° C. to 750 ° C. in the case of Co, and about 350 ° C. to 450 ° C. in the case of Ni. Thus, the silicide layer 21 is formed in the upper layer portions of the gate electrodes 14a and 14b and the source / drain regions 19a and 19b.

Subsequently, as shown in FIG. 6B, a tensile stress film 22 is formed.
Specifically, first, an insulating film, here a silicon nitride film, is formed so as to cover the entire surface of the silicon substrate 10. This silicon nitride film is formed in a vacuum chamber using, for example, a parallel plate type plasma CVD apparatus. The substrate temperature when forming the silicon nitride film is, for example, about 400 ° C. For example, N ₂ gas, NH ₃ gas, and SiH ₄ gas are simultaneously supplied into the vacuum chamber as source gases. The flow rate of N ₂ gas is, for example, 500 sccm to 3000 sccm. The flow rate of NH ₃ gas is, for example, 100 sccm to 1000 sccm. The flow rate of the SiH ₄ gas is, for example, 200 sccm to 500 sccm. The pressure in the vacuum chamber is, for example, about 1 Torr to 15 Torr. The frequency of the applied high frequency power is, for example, 13.56 MHz. The magnitude of the high frequency power to be applied is, for example, about 100 W to 500 W. The film formation time of the silicon nitride film, that is, the plasma excitation time is, for example, about 10 seconds to 100 seconds. By forming the film under the above conditions, a silicon nitride film made of a silicon nitride film is formed to a thickness of, for example, about 30 nm to 90 nm, here about 80 nm.

  Next, the formed silicon nitride film is contracted (shrinked). For example, the formed silicon nitride film is irradiated with ultraviolet rays using an ultraviolet irradiation device. As the ultraviolet light source, a broadband ultraviolet light source is used. The atmosphere when irradiating with ultraviolet rays is, for example, a He atmosphere. The irradiation time of ultraviolet rays is, for example, about 180 seconds to 600 seconds. By this ultraviolet irradiation, the silicon nitride film shrinks, and a property of applying a tensile stress, for example, a tensile stress of about 1.6 GPa, to the outside is given, and the tensile stress film 22 is formed.

Subsequently, as shown in FIG. 7A, a resist pattern 23 covering the N-type region 10a is formed.
Specifically, a resist is applied onto the tensile stress film 22 and the resist is processed by lithography to form a resist pattern 23 that covers the N-type region 10a on the tensile stress film 22 and exposes the P-type region 10b.

Subsequently, as shown in FIG. 7B, the tensile stress film 22 is etched back.
Specifically, using the resist pattern 23 as a mask, the entire surface exposed in the P-type region 10b of the tensile stress film 22 is etched back. This etch back (anisotropic dry etching) needs to be performed under etching conditions in which a part of the tensile stress film 22 exposed in the P-type region 10b is not removed but under the etching conditions in which some remain as follows. Thereby, in the N-type region 10a, the tensile stress film 22 under the resist pattern 23 remains as it is, and in the P-type region 10b, a tensile stress film is formed so as to cover the sidewall insulating film 17 only on both side surfaces of the gate electrode 14b. 22 remains. Therefore, the tensile stress film 22 in the P-type region 10b is thinner than the tensile stress film 22 in the N-type region 10a.
Thereafter, the resist pattern 23 is removed by ashing or the like.

  In the present embodiment, in the N-type region 10a, a tensile stress film 22 is formed on the entire surface so as to cover the gate electrode 14a and the sidewall insulating film 17. Thereby, a sufficient tensile stress is applied to the channel region of the N-type MOS transistor, the carrier mobility is increased, and the transistor characteristics are improved. Here, substantially the entire side surfaces of both sides of the gate electrode 14a are covered with the sidewall insulating film 17, and the adverse effects on the gate insulating film 13 and the occurrence of junction leakage in the source / drain regions 18a can be minimized. .

  On the other hand, in the P-type region 10b, the sidewall insulating film 17 is adjusted to be, for example, about 20 nm to 50 nm lower than the upper surface of the gate electrode 14b, and the tensile stress film 22 is relatively thick so as to cover the sidewall insulating film 17. Remains. In a P-type MOS transistor, a tensile stress is applied to the channel region by forming a tensile stress film only on both sides of the gate electrode. In this embodiment, by forming the tensile stress film 22 thick only on both side surfaces of the gate electrode 14b, a large tensile stress on the channel region due to the tensile stress film 22 can be secured.

Subsequently, as shown in FIG. 8A, a compressive stress film 24 is formed.
Specifically, an insulating film, here, a compressive stress film 24 made of a silicon nitride film is formed so as to cover the entire surface of the silicon substrate 10. The compressive stress film 24 is formed in a vacuum chamber using, for example, a parallel plate type plasma CVD apparatus. The substrate temperature when forming the compressive stress film is, for example, about 400 ° C. For example, N ₂ gas, H ₂ gas, NH ₃ gas, SiH ₄ gas, and (CH ₃ ) ₃ SiH gas (trimethylsilane gas) are simultaneously supplied into the vacuum chamber. The flow rate of N ₂ gas is, for example, 500 sccm to 3000 sccm. The flow rate of H ₂ gas is, for example, 500 sccm to 3000 sccm. The flow rate of NH ₃ gas is, for example, 100 sccm to 1000 sccm. The flow rate of the SiH ₄ gas is, for example, 200 sccm to 500 sccm. The flow rate of (CH ₃ ) ₃ SiH gas is, for example, 50 sccm to 150 sccm. The pressure in the vacuum chamber is, for example, about 1 Torr to 10 Torr. The frequency of the applied high frequency power is, for example, 13.56 MHz. The magnitude of the high frequency power to be applied is, for example, about 100 W to 500 W. The film formation time of the compressive stress film 24, that is, the plasma excitation time is, for example, about 10 seconds to 100 seconds. By forming the film under the above conditions, a compressive stress film 24 made of a silicon nitride film is formed. The compressive stress film 24 is thicker than the underlying tensile stress film 22 and has a film thickness of, for example, about 30 nm to 90 nm, here about 80 nm. For example, a compressive stress of about 2.8 GPa to 3.4 GPa is applied to the outside. It has the property to do.

Subsequently, as shown in FIG. 8B, a resist pattern 25 covering the P-type region 10b is formed.
Specifically, a resist is applied on the compressive stress film 24, and the resist is processed by lithography to form a resist pattern 25 that covers the P-type region 10b on the compressive stress film 24 and exposes the N-type region 10a.

Subsequently, as shown in FIG. 9A, the compressive stress film 24 is etched.
Specifically, using the resist pattern 23 as a mask, the entire surface of the portion exposed in the N-type region 10a of the compressive stress film 24 is etched, and the portion of the compressive stress film 24 is removed. This etching may be anisotropic dry etching or wet etching using phosphoric acid or the like as an etchant, but is performed under etching conditions that remove all exposed portions of the N-type region 10a of the tensile stress film 22. It takes a thing.
Thereafter, the resist pattern 25 is removed by ashing or the like.

  In the present embodiment, only the tensile stress film 22 is formed in the N-type region 10a, the tensile stress film 22 is formed only on the side wall of the gate electrode 14b, and the compressive stress film 24 is further formed in the P-type region 10b. An N-type MOS transistor requires a tensile stress in its channel region regardless of the direction of the stress, and has a characteristic that the characteristic is likely to change relatively. Therefore, the tensile stress film 22 is formed in the N-type region 10a without forming the compressive stress film, thereby securing a sufficient tensile stress to the channel region. On the other hand, the P-type MOS transistor has a stress direction dependency, and it is desirable that the channel region requires a compressive stress in the channel length direction and a tensile stress in the channel width direction. Therefore, the tensile stress film 22 is formed only on the side wall of the gate electrode 14b in the P-type region 10b, and the compressive stress film 24 is further formed to ensure the stress having the desired direction dependency on the channel region. As described above, in the present embodiment, although the manufacturing process is shared by the N-type MOS transistor and the P-type MOS transistor as much as possible, the necessary stress can be efficiently and reliably applied to the channel region of each transistor. Become.

Subsequently, as shown in FIG. 9B, an interlayer insulating film 26, a conductive plug 27, a thin wire 28, and the like are formed.
Specifically, first, an insulating film, for example, a silicon oxide film is deposited on the entire surface so as to cover the entire surface of the silicon substrate 10 by, for example, a CVD method or the like to form an interlayer insulating film 26. Thereafter, the interlayer insulating film 26 is planarized by, for example, CMP (Chemical Mechanical Polishing).
Next, an opening is formed so as to penetrate the interlayer insulating film 27, the tensile stress film 22, the interlayer insulating film 27, and the compressive stress film 24 by lithography and subsequent dry etching. Thereby, in the N-type region 10a, each connection hole 26a exposing a part of the surface of each silicide layer 21 on the gate electrode 14a and the source / drain region 18a is formed. On the other hand, in the P-type region 10b, each connection hole 26a exposing a part of the surface of each silicide layer 21 on the gate electrode 14b and the source / drain region 18b is formed.

Next, tungsten (W) is deposited on the interlayer insulating film 26 so as to embed each connection hole 26a by, for example, sputtering. Using the interlayer insulating film 26 as a polishing stopper, the deposited W is polished and planarized by CMP. Thereby, the conductive plug 27 which fills each connection hole 26a with W is formed.
Next, a wiring metal, for example, aluminum (Al) or an alloy thereof is deposited on the interlayer insulating film 26 including the conductive plug 27 by, for example, sputtering. The deposited wiring metal is processed into a wiring shape by lithography and subsequent dry etching. As a result, wirings 28 that are electrically connected to the silicide layers 21 via the conductive plugs 27 are formed.

  Thereafter, through various processes such as formation of an interlayer insulating film and formation of an upper layer wiring, an N-type MOS transistor is formed in the N-type region 10a and a P-type MOS transistor is formed in the P-type region 10b. As described above, the CMOS transistor 20 including the N-type MOS transistor and the P-type MOS transistor is formed.

  Regarding the CMOS transistor formed as described above, the relationship between the on-current and off-current of the P-type MOS transistor was examined. The experimental results are shown in each figure of FIG. FIG. 10A shows the experimental results when the source / drain region is wide in the isolated pattern (sparse) gate electrode and the distance from the gate electrode to the connection hole is relatively long as shown in the schematic diagram at the upper left. Indicates. The form of FIG. 10A has little application in actual products. FIG. 10B shows an experimental result when the width of the source / drain region is narrow and the distance from the gate electrode to the connection hole is relatively short with an isolated pattern (sparse) gate electrode as shown in the upper left schematic diagram. Indicates. FIG. 10 (c) shows an experiment in which the width of the source / drain region is narrow and the distance from the gate electrode to the connection hole is relatively short as shown in the upper left schematic diagram. Results are shown.

  In each drawing of FIG. 10, “Tensile thick” means a case where the sidewall insulating film 17 of the gate electrode 14b is prepared relatively low and the tensile stress film 22 is formed relatively thick as shown in FIG. Show. “Tensile thinning” refers to the case where the sidewall insulating film 17 of the gate electrode 14b is prepared relatively high and the tensile stress film 22 is formed relatively thin as shown in FIG. 11B. “Tensile intermediate” indicates a case where the tensile stress film 22 is formed at an intermediate thickness between FIG. 11 (a) and FIG. 11 (b). In each drawing of FIG. 11, only the gate electrode 14b, the sidewall insulating film 17, and the tensile stress film 22 are shown, and the other components are not shown.

  10B and 10C, the on-current tends to increase as the tensile stress film 22 is formed thicker. In the case of FIG. 10A, the tensile stress film 22 has an intermediate thickness and tends to provide a high on-current. This means that the applied stress changes depending on the thickness of the tensile stress film 22 and the mobility changes. Overall, it is suggested that the thickness of the tensile stress film 22 has an optimum value at which the mobility of the P-type MOS transistor is substantially maximized.

  As described above, according to the present embodiment, both the N-type transistor and the P-type transistor share the same manufacturing process as much as possible to reduce the number of processes as much as possible. A CMOS transistor capable of significantly improving the transistor performance by appropriately applying stress suitable for each of the P-type transistors is realized.

    Hereinafter, various aspects of the semiconductor device manufacturing method will be collectively described as additional notes.

(Appendix 1) A semiconductor device including a P-type transistor and an N-type transistor on a semiconductor substrate,
The P-type transistor is
A first film formed on the side wall of the first gate and applying a tensile stress;
A second film which is formed so as to cover the first gate and the first film and which applies compressive stress;
The N-type transistor is formed so as to cover the second gate, and has a third film for applying a tensile stress.

  (Appendix 2) The P-type transistor has a first sidewall film that covers a sidewall of the first gate, and the first sidewall is covered with the first sidewall film on the sidewall of the first gate. The semiconductor device according to appendix 1, wherein a film is formed.

(Supplementary Note 3) The N-type transistor has a second sidewall film covering the sidewall of the second gate,
The semiconductor device according to appendix 2, wherein the first sidewall film is lower than the second sidewall film.

  (Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the first film is formed to be lower than the upper surface of the first gate by 20 nm or more and 50 nm or less.

  (Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the first film is thinner than the second film and the third film.

(Appendix 6) A method of manufacturing a semiconductor device comprising a P-type transistor and an N-type transistor on a semiconductor substrate,
Forming a first gate in a first region of the P-type transistor and a second gate in a second region of the N-type transistor on the semiconductor substrate;
Forming a film for applying a tensile stress in the first region on the side wall of the first gate and in the second region so as to cover the second gate;
Forming a film for applying compressive stress in the first region so as to cover the first gate and the film for applying tensile stress.

(Additional remark 7) Before forming the film | membrane which gives the said tensile stress, the process of forming the 1st side wall film which covers the side wall of the said 1st gate is further included,
7. The method of manufacturing a semiconductor device according to appendix 6, wherein a film that applies the tensile stress is formed on a side wall of the first gate so as to cover the first side wall film.

  (Appendix 8) A step of etching the first side wall film and forming the top of the first side wall film backward before forming the film giving the tensile stress and after forming the first side wall film. The manufacturing method of a semiconductor device according to appendix 7, further comprising:

(Additional remark 9) After forming the said 1st side wall film, it further includes the process of introduce | transducing an impurity into the part of the both sides of the said 1st gate in the said 1st area | region,
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the etching is performed after the impurity is introduced.

(Additional remark 10) It further includes the process of forming the 2nd side wall film which covers the side wall of the 2nd gate with the 1st side wall film,
10. The method for manufacturing a semiconductor device according to appendix 8 or 9, wherein the etching is performed only on the first region.

DESCRIPTION OF SYMBOLS 10 Silicon substrate 10a N type area | region 10b P type area | region 11 Element isolation structure 11a Isolation groove | channel 12a, 12b Well 13 Gate insulating film 14a, 14b Gate electrode 15a, 15b, 18a, 18b, 23, 25 Resist pattern 16a, 16b Extension area | region 17 Sidewall insulating films 19a and 19b Source / drain regions 21 Silicide layer 22 Tensile stress film 24 Compressive stress film 26 Interlayer insulating film 26a Connection hole 27 Conductive plug 28 Wiring

Claims (5)

A semiconductor device comprising a P-type transistor and an N-type transistor on a semiconductor substrate,
The P-type transistor is
A first gate;
A first sidewall film covering a part of the sidewall of the first gate;
Covering the entire surface of the first side wall film on the side opposite to the first gate, the first gate is formed only on both side surfaces of the first gate, and gives a tensile stress. A first membrane;
A second film which is formed so as to cover the first gate and the first film and which applies compressive stress;
The N-type transistor is formed so as to cover the second gate, and has a third film for applying a tensile stress. The N-type transistor has a second sidewall film covering the sidewall of the second gate,
The semiconductor device according to claim 1, wherein the first sidewall film is lower than the second sidewall film. The P-type transistor has a first silicide in a portion protruding from the first sidewall film of the first gate,
The semiconductor device according to claim 2, wherein the N-type transistor has a second silicide that is thinner than the first silicide on the second gate. A method for manufacturing a semiconductor device comprising a P-type transistor and an N-type transistor on a semiconductor substrate,
Forming a first gate in a first region of the P-type transistor and a second gate in a second region of the N-type transistor on the semiconductor substrate;
Forming a first sidewall film covering a portion of the sidewall of the first gate;
The first region covers the entire surface of the first sidewall film on the side opposite to the first gate, and the first gate is formed only on both sides of the first gate . Forming a first film for applying a tensile stress in the region 2 so as to cover the second gate;
Forming a second film for applying a compressive stress so as to cover the first gate and the first film in the first region. Forming a second sidewall film covering the sidewall of the second gate;
Forming a first silicide on a portion of the first gate protruding from the first sidewall film, and forming a second silicide thinner than the first silicide on the second gate. The method of manufacturing a semiconductor device according to claim 4.

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