TW200814313A - Semiconductor device - Google Patents

Abstract

The semiconductor device in accordance with the present invention is an IGBT which includes a first base area of a first conductive type; a second base area of a second conductive type, provided at one of main surfaces of the first semiconductor area; an emitter area of the first conductive type, which is formed in the second base area; a collector area of the second conductive type, which is formed at the other main surface of the first semiconductor area; and a collector short area of the first conductive type, which is formed at the other main surface of the first semiconductor area, in a manner such that the collector short area is inserted into the collector area, so as to divide the collector area. An external electrode forming part, where no second base area is formed, is provided at the periphery of one of the main surfaces of the first base area, and the second base area is formed in a cell forming area inside the external electrode forming part. The collector short area is formed only in the cell forming area.

Description

200814313 IX. Description of the invention: [Technical field of the invention] A permanent structure of a vertical structure (with the present invention relating to a gated bipolar transistor (insulated gate bip) under the edge of an integrated circuit A semiconductor device having a structure called IGBT. [Prior Art] ^ The IGBT has a gate, and by applying a voltage to the gate, it is possible to perform conduction (ON)/non-conduction (〇FF) control of the transistor. A polar transistor, which has both a high input impedance characteristic of a field effect transistor and a low output impedance characteristic of a bipolar transistor. In the case of a PNP type lGBT, there is a defect. 5 (see, for example, Patent Document 1). The second drawing shows that the p-type semiconductor region (collector region) 100 and the N-type semiconductor region (the collector short-circuit region) are alternately arranged on the collector region side. A schematic diagram of a cross-sectional structure of an IGBT of a universal substrate. The IGBT is formed by sequentially forming an N-type buffer layer 1 〇 2 and an n-type base region 1 on the above-mentioned general-purpose substrate by an epitaxial growth method. 〇 3. In addition' The surface of the N-type base region 1 〇3 (the surface on the upper side in the drawing) is formed by a P-type impurity diffusion process to form a plurality of P-type base regions 104' in addition to the surface in the p-type substrate region 1. The N-type emitter region 1〇5 is formed by the n-type impurity diffusion treatment. A gate insulating film 1〇6 is formed on the surface of the N-type base region 103 between the respective P-type base regions 104. 319357 5 200814313 A gate electrode 1〇7 is formed on the gate insulating film 106, and the gate electrode 107 is covered by an insulating film 108. The P-type base region 104 and the N-type emitter region 1〇5 are connected to the emitter electrode 109. In addition, a collector electrode no is formed on the lower surface (the surface on the lower side in the drawing) of the P-type semiconductor region 1 of the P-type semiconductor region in the general-purpose substrate. Thereby, the p-type semiconductor region 100 & Each of the N-type semiconductor regions ι〇ι has a function as a collector region and a collector short-circuit region. In the above-described structure of the brain T, an N-type buffer layer 1〇2 is not formed on the substrate for use, but directly The case where the N-type base region 1〇3 is formed. In the N-type semiconductor region 1〇1 as described above In the excitation T having the region functioning as the collector short-circuit region, a PN junction diode having the N-type base region 103 as a cathode and the p-type base region ι 4 as an anode is formed inside the semiconductor device. (PN juncti〇n di〇de). Fig. 6 shows the equivalent circuit concept diagram of the IGBT of Fig. 5, as shown in the figure 'The cathode of the PN junction diode and the collector electrode of the IGBT. Connected, the anode of the PN junction diode is electrically connected to the emitter electrode 1〇9 of the igbt. Here, the PN junction surface dipole system is formed by the N-type semiconductor region 1 (the Π, Ν type buffer layer 1G2u type base layer (that is, the core base region 'below the same) 103) constitutes a cathode, and the anode is composed of a p-type base. The structure of the region ι〇4. By the structure having the collector short-circuit region, the time from the on state of the igbt to the non-conduction state (〇ff) can be shortened. (Patent Document 1) Japanese Patent Laid-Open No. 05_ 〇32〇5号公告319357 6 200814313 [Problem to be Solved by the Invention] However, the PN junction surface is configured as follows: The reverse recovery time trr of the diode is based on (1) the PN junction surface diode The current is reduced from the forward current value to "〇, and the current (hereinafter referred to as reverse current) flows in the reverse direction.

= the flow becomes a period until a large value, that is, a period in which the pN junction diode is in a short-circuit state; and (7) a time point from when the reverse current becomes the maximum value to almost "5% or less of the maximum value" During the period, that is, the period until the state of the junction electrode of the state exerts the reverse blocking (reverse voltage blocking) function, when the above period is strict to 1 to the bean ts, it is generally known that the valley is ringing the output ( Ringing), it is easy to generate noise caused by the ringing. In order to reduce the noise, it is necessary to have the period td longer than the period ', that is, td/ts is formed to be two poles than the conventional example A. On the other hand, in the IGBT of the built-in diode described above, as shown in Fig. 7, when the emitter electrode and the collector electrode m are applied, the improvement is performed. When the voltage of the potential on the side of the emitter electrode 109 (the forward bias state), the forward current flows to the PN junction in which the N-type base region 1〇3 is the cathode and the p-type base region 104 is the anode. Face diode (〇N state). 隹 Next, when in the emitter When the potential of the collector electrode 110 side is higher than the voltage of the emitter electrode 1〇9 between the pole 109 and the collector electrode 110 (reverse bias 319357 7 200814313 state), that is, by the reverse blocking function?]^ The junction surface diode is in an anti-electric rhinoceros blocking state (OFF state). However, in the above-described conventional built-in diode IGBt, it is in the entire surface of the general substrate opposite to the collector electrode m. , the collector region semiconductor region _ and the collector short region _ semiconductor region (8) are alternately connected to the collector electrode Π〇. For the above reason, as shown in the seventh _), when the reverse bias state w•, Since electrons accumulated in the N-type base region 103 and the like are discharged to the collector electrode (4) earlier through the n-type semiconductor region (8) (collector short-circuit region), soft repair of the built-in diode cannot be achieved well. The present invention has been made in view of the above circumstances, and compared with a conventional example in which a collector short-circuited region is formed on the entire surface of a wind substrate, the above-described (four) ω is longer than the period ts, that is, to the PN. The joint surface diode achieves a soft repairing fit to reduce A semiconductor device having an IGBT structure of noise. (Means for Solving the Problem) The semiconductor device of the present invention is a semiconductor device having an insulated gate type bipolar transistor structure, and is characterized in that: a base region or a second base region of the second 'electric type is disposed on one of the main surface sides of the first base region; and an emitter region of the first conductivity type is formed in the base region of the second base The collector region of the 帛2 conductivity type is disposed on the other main surface side of the first earth electrode region; and the collector short region of the work conductivity type is in the other side of the ith base region The main surface side is formed by the division: the method of describing the ф pole region is inserted between the collector regions, and the outer peripheral portion on the main surface side of one of the base regions of the first base is not formed with 319357 8 200814313 = The external electrode forming portion 'in the second base region> and the second base region are formed in a transistor unit (=nsistW) forming region inside the external electrode forming portion, and the collector short-circuit region is formed only in the foregoing The yuan is formed within the area. Preferably, the collector short-circuit region is formed only at a position overlapping with the front base 2 base region in plan view. Typically, in the first base region, an upper portion of the interpole electrode/the main surface side is provided between the emitter regions, and the trench is formed in the emitter region. (Effect of the Invention) According to the present invention, when the unit formation region of the collector short-circuit region of the polar transistor is disposed in the vertical bipolar formation portion, the drain is not disposed: the roadbar = the external electric portion having the unit region First! It is said that the external electrode is formed with an external electrode to form a counter-polar diode to apply a reverse layer of money, and when it is called a repairing property, the softness of the PN junction surface diode of the king is, that is, according to the present invention, the period tS of the short-circuit state, In the period from the point of the reverse dynasty diode to the PN junction surface of the period in which the PN junction diode is in the period of time, the PN junction diode is a period of time. Long, even if the ratio td/ts is larger than the conventional 319357 9 200814313. Further, according to the present invention, in a plan view, since a collector short-circuit region is formed in a cell formation region in which a vertical bipolar transistor is formed, that is, in existence The collector short-circuit region is formed in the region where the condition substrate of the lower portion of the IGBT is formed. Therefore, the IGBT&; FF operation time characteristic can be shortened. [Invention] The following description and diagram of the semiconductor device of the embodiment are shown. Does not explain an IGBT of the present invention

Fig. 1 shows a plan view of the planar structure of the IGBT according to the above-described embodiment. A cross-sectional view of the cross-section of the mBT in the line a_a of the figure (for convenience of illustration, it is described that the cell is formed in the region 2 and is under-reduced (the number of the P-type base regions 104 is reduced)). The structure of each unit of the IGBT is the same as the conventional structure shown in FIG. 5, but the position i (ie, the area) of the semiconductor region (8) (collector short-circuit region) is formed in the semiconductor device, and is implemented in the present embodiment. The state and the conventional examples are not the same. A conventional example is in which a semiconductor short-circuited region is formed on the entire surface of the substrate when the semiconductor is placed. On the other hand, in the present embodiment, the collector short-circuit region is formed only in the cell formation region 2 of the transistor unit for forming the IGBT. That is, in a plan view, the surface in the lower direction of the N-type base region 103 (the other main surface side) is opposed to the N-type buffer layer 1〇2, and the substrate is used in the substrate. The N-type semiconductor region is formed by interposing a P-type semiconductor region 1 〇〇 (collector region) between the 1 >-type semiconductor region 1QQ only in a range of the general-purpose substrate overlapping the region 2; 319357 10 200814313 In the present invention, the plan view is used to view the substrate surface from a direction perpendicular to the plane of the general-purpose substrate, and to display a planar overlapping state of the formation regions of the respective semiconductors. In the first embodiment, the semiconductor device 1 (vertical IGBT) f in the present embodiment is divided into: an external electrode forming portion 3 for forming an electrode 2A other than the electrode for pulling out the material of the pad (4). And a single A formation region 2 for forming the electric body body το, the N-type semiconductor region (8) (collector short circuit region) is formed only in the cell formation region 2, and more specifically, in a plan view, The N-type half & body region ii is formed only at a position opposite to the p-type base region 1 (10) so that the carrier is not suddenly discharged by the N-type semiconductor region 101 (collector short-circuit region), at the external electrode The formation portion 3 does not form the collector short-circuit region 1〇1. ', the carrier existing in the external electrode forming portion 3 by this means, as shown in the carrier of the single-form formation region 2, does not rush to the N-type semiconductor region.

The field 1〇1 (the wood pole short-circuited region) is discharged, and moves toward the N (the semiconductor region 1G1 located in the cell formation region 2, and sequentially discharges to the collector electrode ιι. Next, in Fig. 2, the igBT structure is present. On the side of the wood pole region of the semiconductor device (the side in the lower direction of the drawing), the p-type semiconductor region (collector region) (10) and the n-type semiconductor region (collector short-circuit region) are alternately formed in the external cell formation region 2 In the case where only the P-type semiconductor region (collector region) is formed in the external electrode forming portion 3, an IGBT having an N-type base region 1〇3 is formed. 1 is applied to the above-mentioned general-purpose substrate having the N-type semiconductor region 101 and the ?> semiconductor 319357 11 200814313 region 100, and the N-type buffer layers 102 and N are sequentially formed by the epitaxial growth method as in the conventional example. In the surface of the N-type base region 103 (the surface on the upper side and the other main surface side), a plurality of P-type groups are formed by P-type impurity diffusion treatment. Polar region 104, in addition, in the P-type base region The surface in 1〇4 is formed by N-type impurity diffusion treatment to form an N-type emitter region 105. That is, the N-type emitter region 105 is formed in the plan view and is formed in the p-type base region 104. Position, and depth is also formed shallower than the p-type base region 104, completely in the configuration included by the p-type base region 1〇4, that is, connected to other semiconductor regions other than the (upper) surface The outer peripheral surface is formed by a structure in contact with the P-type base region 104. A gate insulating film 1 〇6 is formed on the surface of the N-type base region 1〇3 between the respective P-type base regions 104. A gate electrode 107' is formed on the gate insulating film 106 by a conductor. The gate electrode 1 〇7 is covered by the insulating film 1. In the P-type base region 104 and the N-type emitter region 1〇5 The surface is electrically connected to the emitter electrode 1〇9, in other words, the p-type base region ι4 and the N-type emitter region 1〇5 are electrically connected through the emitter electrode 1〇9. The P-type semiconductor region 100 in the general-purpose substrate and the lower surface of the N-type semiconductor region 101 (the lower side surface of the illustration, the other main On the surface side, the collector electrode 110 is formed. In this manner, each of the p-type semiconductor region 100 and the N-type semiconductor region 101 has a function as a collector region and a collector short-circuit region. In the plan view, that is, when the N-type base region!Q3 is viewed perpendicular to a 319357 12 200814313 = the money, the p-type base region 1〇4 is as shown in Fig. 1 in a strip shape (striped shape). Then, in the direction orthogonal to the extending direction of the P-type base region 1〇4 (the first FIG. #A_A line), when the cross section of the semiconductor device i is viewed as shown in FIG. 2, On the center side of the semiconductor device i, a plurality of P-type base regions 104 are disposed apart from each other. An N-type emitter region ι 5 is formed inside each of the base regions 1G4 disposed apart from each other.

That is, in a plan view, a long-shaped N-type emitter region (8) having a similar shape is formed in a strip-shaped base region of a strip shape (band shape). The dust emitter region 105 extends in a strip shape toward the strip direction along the outer peripheral edge ' of the p-type base region 1〇4. The strip-shaped region of the P-type base region 104 is opposed to the gate electrode 1G7 by the gate insulating film 106, and has a function as a well-known channel region. That is, by applying the electric s' of (1) to the gate impurity H)7, the surface of the p-type base region 1 opposite to the gate electrode j 〇7 is formed to be in a conducting state, and N is made The type base region 1〇5 and the _2nd region 1〇3 are in an on state. Therefore, in the plan view, the gate 2: 〇7iN type emitter region 1〇5, p-type base region (10) and soil The order of the polar regions 4 1G3 is such that the respective surfaces are formed opposite to each other by the gates 1 〇 6 . The P-type base region 104 and the Γ Γ P-type base are extended by the band. The N-type emitter region 105 inside the region 1〇4 and the gate electrode 1〇7 formed in the corresponding direction form a single element region (cell region) of the IGBT. J P. 319357 13 200814313 As described above, in the diagram of '苐1 In the Feng guide -^ ^ ^ ^ „ in the central side of the cattle set 1 sigh. The region of the type base region 1〇4, that is, the single quadruple region 2 having a plurality of unit regions. On the other hand, an external electrode forming portion 3 in which an early region is not formed is provided on the outer peripheral side of the semiconductor device 1. The external electrode forming portion 3 in which the unit region is not formed surrounds the unit forming region 2 in which the unit of the IGBT is formed in a ring shape or a surrounding shape.

Here, the external electrode 2A such as a known connection electrode (joint bonding pad) or a gate bus bar is disposed in the external electrode forming portion 3 in which the cell region is not formed. In the present embodiment, in order to provide the external electrode forming portion 3 for forming the bonding pad, the unit forming region 2 is formed in a partially concave inner shape, and as a result, as shown in Fig. 1, the central side unit region The extension length of the (P-type base region 104) is shorter than the extension length of the other unit regions. As described above, in the IGBT of the present embodiment, the N-type semiconductor region 1〇1 (collector short-circuit region) electrically connecting the collector private electrode 110 and the N-type buffer layer i 02 is formed. However, the region formed by this is different from the conventional IGBT, and the collector short-circuit region ιοί is disposed only in the cell formation region 2 ′ where the IGBT is formed. The external electrode formation portion 3 in which the cell region is not formed is not disposed. Type semiconductor region 1〇1 (collector short-circuit region). Further, as shown in Fig. 1, the N-type semiconductor region 1〇1 is formed as a diffusion layer which is formed to be separated from each other in plan view, and is N-type base region 1〇4 phased in the field 'and is included in the outer periphery in the N-type The position of the base region 104 is arranged in a plurality of directions in the strip direction of the N-type base region 1 () 4 of 14 319 357 200814313. The configuration is as described above, such as the semiconductor device of Fig. 3 (4)! After that, the carrier (electron) is moved from the vicinity of the collector short-circuit region (8), that is, the N-type buffer layer (10) and the N-type US layer H in the single-turn formation region 2 to N. The material conductor region 1〇1 (collector short-circuit region) = is distributed by the collector electrode 110 as a current. However, in the case where the N-type semiconductor region 1〇1 (collector short-circuit region) is not formed, the N-type buffer layer 1 () 2 and the N-type base layer in the pole forming portion 3 are carrier systems of the N-type base layer Slowly moving, and flowing through the N-type semiconductor region 1〇1 (collector short-circuit region) as current flows to the collector electrode 11〇

As shown in FIG. 3(b), the N-type semiconductor region 1G1 (collector short-circuit region) also formed in the external electrode forming portion, that is, the surface of the substrate for the case: the N-type semiconductor region 101 is formed. In comparison with the conventional example, the period td is longer than the period ts (td in the figure), and the ratio of td/ts becomes large, whereby the soft repair characteristic can be realized. ^ P In Fig. 3(b), the solid line indicates the maneuver state of the current ^ in the present embodiment, and the money indicates the flow state of the current worker in the conventional example. It can be seen from: (b) that compared with the conventional example, the junction surface diode is in the short-circuit period ts system, and there is no change, but it can be made from the reverse power to the maximum = day-to-day point with the joint surface In the period td of the reverse body blocking function, the relationship between (10)/order (9)/(8) is formed, and the soft repair characteristics of the joint surface diode can be improved. 319357 15 200814313 丨^丁外. In other embodiments, the semiconductor device 1 of the present embodiment can be used in the same manner as the embodiment of the first embodiment. (Vertical IGBT) is divided into: an external electrode forming portion 3 for forming external electric power belonging to an external drawing electrode such as a pad, and a cell forming region 2 for forming a transistor f element, an N-type semiconductor region (8) (collective short = ί domain) is formed only in the cell formation region 2, and more specifically, in a plan view, the N-type semiconductor region 101 (collector short-circuit region) is formed only in the P-type base region 104A The position of the phase is not formed in the external electrode forming portion 3 〇 (following in the fourth figure, on the side of the collector region side of the semiconductor layer structure (10) showing the lower direction), and one of the above is implemented In the same manner, in the early formation region 2, the p-type semiconductor region (collector region) 100 and the N-type semiconductor region (collector short-circuit region) are alternately arranged, and only the p-type is disposed in the external electrode forming portion 3. On the so-called sink substrate of the semiconductor region To have IGBT. The IGBT system is formed in the same manner as in the embodiment, and the N ^ buffer layer 1 〇 2 and the N-type base region 1 〇 3 are sequentially formed by the stray crystal growth method on the above-mentioned condition substrate. Further, on the surface of the N-type base region 103 (the upper side surface of Fig. 4), the groove 200 is formed in a strip shape, adjacent to the thin side wall of the groove, and a plurality of p are formed by p (tetra) diffusion treatment. The base region i 〇 4a is further formed with an N-type emitter region i 〇 5A on the surface of the 319357 16 200814313 in the P-type base region 104A. Here, the 'N-type emitter region 1' 5a is also formed adjacent to the sidewall of the trench 2''. That is, the N-type emitter region 105A is formed in a plan view, is formed at a position included in the p-type base region 104A, and is formed to be shallower than the p-type base region 104A as a completely P-type base region 1 The structure included in 〇4A is formed. Further, the trench 2 formed between the respective P-type base regions i 〇 4A electrically insulates the gate electrode, the P-type base region 1〇4, and the N-type emitter region i〇5a. A gate insulating film 1G6A is formed on the inner surface. A gate electrode 107A is formed on the surface of the gate insulating film 106A, and the gate electrode 1 is covered with an insulating film (not shown). That is, the gate electrode 1 〇 7A is formed by interposing the gate insulating film 1 (10) a on the inner surface of the trench 2 in the trench 200. The p-type base region H) 4A & N-type emitter region 1Q5A_ the emitter electrode 109A is electrically connected, that is, the surface of the p-type base region i〇4a and the n-type emitter region 1G5A is formed. The emitter electrode 1Q9a is connected to the p-type base region i〇4a & n-type emitter region 1G5Af. Further, the collector electric power f 110 is formed on the lower surface (the surface on the lower side in the drawing) of the p-type semiconductor region (10) and the (four) conductor region 1〇1 in the case substrate. The P-type semiconductor region (10) and the core semiconductor region (8) each have a function as a collector region and a collector short-circuit region. The /type base region 1G4A is the same as the above-described embodiment, and when viewed from the upper side of the N-type base region 103, it is stretched in a strip shape (in a stripe shape) ) form a plurality of. 319357 17 200814313 In the direction orthogonal to the above-described extending direction of the p-type base region i 〇 4A (the AA line in FIG. 1), when the semiconductor device 1 is viewed as shown in the figure, in the semiconductor On the center side of the device 1, a plurality of P-type base regions 104A are disposed apart from each other. An N-type emitter region i〇5a is formed inside each of the p-type base regions 104A which are disposed apart from each other. Further, a p-type base region 104A is formed in a strip shape between the trenches 200 in the cell formation region, and is formed to face the n-type emitter region 105A on the inner surface of the p-type base region 1A4. The N-type emitter region 105A extends in a strip shape along the outer peripheral edge ' of the p-type base region i〇4a toward the strip direction. In the winter, the strip region of the p-type base region ι〇4Α is opposed to the sidewall of the gate electrode 1A7A through the gate insulating film 106A, and has a function as a well-known channel formation region. That is, by applying a (+) voltage to the gate electrode, it is in contact with the side surface of the p-type base region 104A opposite to the gate electrode 1〇7, that is, the side wall of the trench 2〇〇. The region forms a channel and is in an on state, and the N-type emitter region 1〇5 person and the n-type base region 103 are electrically connected. The mouth is as shown in the cross-sectional view of Fig. 4, and the sides are arranged by the arrangement order of the N-type emitter region 1〇5Α, the Ρ-type base region 1〇4A&N-type base region 1〇3. The gate insulating film 1A6A is formed to face the side surface of the gate electrode 107A. That is, the hierarchical structure is formed in the order of the n-type emitter region 1〇5, the P-type base region 104A, and the N-type base region 1〇3. The gate electrode 1 is formed by a p-type base region 104A extending in a strip shape, an N-type emitter region 1〇5A formed inside the P-type base region 104A at 319357 18 200814313, and a gate electrode 1 formed corresponding thereto 〇7A, a single element region (cell region) of the IGBT forming a channel on the sidewall of the trench 2〇〇. As mentioned above, in the first! In the figure, on the center side of the semiconductor device 1, a region in which the P-type base regions 1A and 4A are disposed apart from each other, that is, a cell formation region 2 in which a plurality of single-it regions are disposed is disposed. About other actions

The description is the same as that of the embodiment, and thus the description thereof is omitted. As in the first embodiment, the N-type semiconductor region 101 is formed only in a portion overlapping the cell formation region 2 in plan view. Further, the IGBT and the other embodiments can be formed by deforming the IGBT into the structure shown below. (1) It is possible to form the Ν-type base layer 1 〇 3 directly on the substrate on which the p-type semiconductor region 100 and the Ν-type semiconductor region 1 〇 1 are formed without forming the 缓冲-type buffer layer 1 〇 2 structure. (7) The Ν-type semiconductor region 1G1 (collector short (four) domain) is provided in the lower portion of the p-type base region 1〇4 (or 104A), but may be formed between the P-type base regions 104 on the strip in plan view. (Of course formed inside the cell formation region). () Although the P-type base region 1G4 (or the theory) is formed into a stripe shape of a long shape, the p-type base region of the elongated shape may be formed in an orthogonal lattice shape or divided into regions of a predetermined width. The island shape (10) rings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a planar structure of a semiconductor device according to an embodiment of the present invention. 319357 19 200814313 A line cross-sectional view of a semiconductor device 1 in AA is a line view of FIG. . Fig. 3 (a) and (8) are diagrams for explaining the concept of the carrier (electron) in the present embodiment from the N-type buffer layer 1 〇 2 and the N-type base. Line 1G3 (4) to the collector short-circuit region (8). FIG. 4 is a cross-sectional view of the semiconductor device 1 in the semiconductor device according to another embodiment of the present invention, and FIG. 1 is a cross-sectional view showing the transistor structure of the IGBT. Cutaway view. > Figure 6 is a conceptual diagram showing the equivalent circuit of the coffee. Fig. 7 (4) and (8) are diagrams for explaining the discharge operation of the carrier discharged from the collector short-circuit region 1〇1 when the forward electric power is applied and the voltage is applied. [Description of main component symbols] 2A 100 101 102 104, 106, 108 110 Semiconductor device external electrode P-type semiconductor region (collector region) N-type semiconductor region (collector short-circuit region) Cell formation region External electrode formation portion N-type buffer layer 104A P-type base layer 106A gate insulating film insulating film collector electrode 103 N-type base layer 105, 105A N-type emitter region 107, 107A gate electrode 109, 109A emitter electrode 200 groove 319357 20

Claims (1)

200814313 X. Patent application scope: 1. A semiconductor device comprising a semiconductor device having an insulated gate bipolar transistor structure, characterized by having: a first base region of a first conductivity type; and a second conductivity type 2 base region is provided on one of the main surface sides of the second base region; the first conductivity type emitter region is formed in the second base region; / the second conductivity type collector region is disposed On the other main surface side of the second base region; and the collector short-circuit region of the first conductivity type, the other main surface side of the first base region is inserted so as to divide the collector region Formed between the collector regions, and the outer peripheral portion of the main surface side of the ith base region is further = the outer electrode forming portion of the 帛2 base region is not formed, and The 2 base region is formed in the electrode unit forming region inside the external electrode forming portion, and the collector short-circuit region is formed only in the cell forming region. 2. If the patent application area 1st short-circuit area is formed only in the overlapping position. The semiconductor device of the present invention, wherein the collector is in a plan view and the second base region. 3. As claimed in the patent application, there is no interpole electrode term or second term between the first base region and the first base region. The semiconductor device of the semiconductor device of the present invention, wherein the electrode is disposed between the emitter regions of the semiconductor device of claim 3, wherein the electrode is provided in the emitter region. Inside the ditch. 22 319357