CN100585872C

CN100585872C - Semiconductor device

Info

Publication number: CN100585872C
Application number: CN200710130434A
Authority: CN
Inventors: 河野好伸
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2006-08-09
Filing date: 2007-07-19
Publication date: 2010-01-27
Anticipated expiration: 2027-07-19
Also published as: CN101123270A; TW200814313A; TWI350001B; JP2008042073A

Abstract

The invention provides a kind of semiconductor device of IGBT structure, it is provided with the collector electrode shorting region, has accelerated the action that ends of element, and can realize soft recovery characteristics, has reduced noise.Semiconductor device of the present invention is IGBT, have first conductivity type first base, be configured in second base of second conductivity type of an interarea side of first base, be formed on the emitter region of first conductivity type in second base, be configured in the collector region of second conductivity type of another interarea side of first base, and, be inserted between the collector region and the collector electrode shorting region of first conductivity type that forms in the mode of cutting apart collector region in another interarea side of first base; Be provided with the outer electrode formation portion that does not form second base at the peripheral part of an interarea side of first base, the unit that second base is formed on the inboard of outer electrode formation portion forms the zone, and the collector electrode shorting region only is formed on the unit and forms in the zone.

Description

Semiconductor device

Technical field

The present invention relates to be used for the semiconductor device of insulated gate bipolar transistor (the to call IGBT in the following text) structure of the vertical shape structure of having of integrated circuit.

Background technology

IGBT has grid and can be by this grid being applied the bipolar transistor that voltage carry out the control of transistorized conduction and cut-off, is the device that has the low output impedance characteristic that high input impedance charcteristic and bipolar transistor had that field-effect transistor has concurrently.An example as the IGBT of positive-negative-positive has structure shown in Figure 5 (for example, with reference to patent documentation 1).

Fig. 5 is illustrated in the schematic diagram of collector region top-cross for the cross-sectional configuration that has disposed P type semiconductor zone (collector region) 100 and IGBT N type semiconductor zone (collector electrode shorting region) 101, that used so-called common substrate.

This IGBT adopts epitaxial growth method, on above-mentioned common substrate, has formed N type resilient coating 102 and N type base 103 successively.

In addition,, utilize the DIFFUSION TREATMENT of p type impurity, formed a plurality of P types base 104 on the surface of N type base 103 (face of the upper side of figure), and, utilizing the DIFFUSION TREATMENT of N type impurity, the surface in this P type base 104 has formed a plurality of N types emitter region 105.

The surface of the N type base 103 between each P type base 104 is formed with gate insulating film 106.

Be formed with gate electrode 107 on above-mentioned gate insulating film 106, this gate electrode 107 is insulated film 108 and covers.

P type base 104 and N type emitter region 105 are electrically connected with emitter electrode 109.

In addition, in the P type semiconductor zone 100 of common substrate and the bottom surface (face of the lower side of figure) in N type semiconductor zone 101, be formed with collector electrode 110.Thus, worked in P type semiconductor zone 100 and N type semiconductor zone 101 respectively as collector region and collector electrode shorting region.

In the structure of above-mentioned IGBT, also have on common substrate, do not form N type resilient coating 102, and directly form the situation of N type base 103.

For having for the IGBT in the zone of working as the collector electrode shorting region the above-mentioned N type semiconductor zone 101, be formed with N type base 103 as negative electrode, with the PN junction diode of P type base 104 as anode at semiconductor device inside.

Fig. 6 is the schematic diagram of equivalent electric circuit of the IGBT of presentation graphs 5, and as shown in the figure, the negative electrode of PN junction diode is electrically connected with the collector electrode of IGBT 110, and the anode of PN junction diode is electrically connected with the emitter electrode of IGBT 109.At this, the negative electrode of PN junction diode is made of N type semiconductor zone 101, N type resilient coating 102 and N type base 103, and its anode is made of P type base 104.

Structure with this collector electrode shorting region can shorten from the conducting state of the IGBT time to the cut-off state transition.

[patent documentation 1] Japanese kokai publication hei 05-03205 communique.

But trr reverse recovery time of above-mentioned PN junction diode comprises:

(1) electric current of above-mentioned PN junction diode reduces to " 0 " by the forward current value, and then electric current (to call reverse current in the following text) flows round about, the time till its reverse current becomes maximum, promptly, the PN junction diode be in short-circuit condition during ts,

(2) become the peaked moment from reverse current, to be roughly till " 0 " (for example, peaked below 5%) during, promptly, till the performance of PN junction diode oppositely stops (prevention reverse voltage) effect during td.

At this, known above-mentioned during td than during ts in short-term, usually output easily produces ring (ringing), and easily produces the noise that is caused by this ring.

For reduce this noise, need have make above-mentioned during td be longer than during ts, promptly, make td/ts greater than in the past the example diode characteristic (soft recovery characteristics).

On the other hand, for the above-mentioned IGBT that is built-in with diode, when shown in Fig. 7 (a), when between emitter electrode 109 and collector electrode 110, having applied the voltage of the current potential that improves emitter electrode 109 sides (forward bias condition), N type base 103 will flow through forward current (conducting state) in as negative electrode, with the above-mentioned PN junction diode of P type base 104 as anode.

Then, between emitter electrode 109 and collector electrode 110, applied (reverse bias condition) behind the voltage that the current potential that makes collector electrode 110 sides is higher than emitter electrode 110, the PN junction diode becomes reverse voltage blocked state (cut-off state) because of oppositely stoping function.

But, in the above-mentioned IGBT that in the past is built-in with diode, on whole of the common substrate relative with collector electrode 110, collector region (P type semiconductor zone 100) alternately is connected with collector electrode 110 with collector electrode shorting region (N type semiconductor zone 101).

Because above-mentioned reason, shown in Fig. 7 (b), when becoming reverse bias condition, be stored in the electronics in N type base 103 grades, via N type semiconductor zone 101 (collector electrode shorting region), be discharged to collector electrode 110 quickly, therefore, existence can't realize the soft recoveryization of diode-built-in well.

Summary of the invention

The present invention be exactly Given this situation of planting make, purpose is to provide a kind of semiconductor device of IGBT structure, it is compared with the example in the past that forms the collector electrode shorting region on whole of common substrate, make above-mentioned during td be longer than during ts, just for the PN junction diode, realize soft recovery characteristics, reduced noise.

Semiconductor device of the present invention has the insulated gate bipolar transistor structure, it is characterized in that having: first base of first conductivity type; Be configured in second base of second conductivity type of an interarea side of first base; Be formed on the emitter region of first conductivity type in above-mentioned second base; Be configured in the collector region of second conductivity type of another interarea side of above-mentioned first base; And, be inserted between the collector region and the collector electrode shorting region of first conductivity type that forms in the mode of cutting apart above-mentioned collector region in another interarea side of above-mentioned first base; Peripheral part in an interarea side of above-mentioned first base is provided with the outer electrode formation portion that does not form above-mentioned second base, the transistor unit that above-mentioned second base is formed on the inboard of this outer electrode formation portion forms the zone, and above-mentioned collector electrode shorting region only is formed in the vertical view and forms in the described collector region of region overlapping with said units.

Preferred above-mentioned collector electrode shorting region only is formed at and above-mentioned second base position overlapped in vertical view.

Be typically, an interarea upper lateral part in above-mentioned first base is provided with gate electrode between above-mentioned emitter region.

At this moment, above-mentioned gate electrode also can be arranged in the ditch that is formed between the above-mentioned emitter region.

According to the present invention, because only the collector electrode shorting region being configured in the unit that is formed with vertical shape bipolar transistor forms in the zone, and do not dispose the collector electrode shorting region in the outer electrode formation portion that does not form the unit area, therefore, when the PN junction diode has been applied reverse voltage, because externally the zone of electrode formation portion does not form the collector electrode shorting region, so charge carrier can be discharged to first base of outer electrode formation portion sharp, can sharply be discharged to resilient coating under the situation that has formed resilient coating.Therefore, be easy to remaining charge carrier, can obtain the soft recovery characteristics of required PN junction diode.

Promptly, according to the present invention, compare with example in the past, with respect to during ts, td during can increasing promptly strengthens td/ts, and ts PN junction diode is in during the short-circuit condition during this period, during this period the td reverse current be carved into when peaked from becoming basic for during " 0 ", promptly, to the performance of PN junction diode oppositely stop till the function during.

In addition, according to the present invention, in vertical view, form the zone in the unit that is formed with vertical shape bipolar transistor, formed the collector electrode shorting region, promptly, in the common substrate zone that is present in the bottom that has formed IGBT, be formed with the collector electrode shorting region, so can not damage the shortening of IGBT by all characteristics such as operate times.

Description of drawings

Fig. 1 is the vertical view of overlooking the planar configuration when observing of the semiconductor device 1 of expression an embodiment of the invention.

Fig. 2 is the cutaway sectional view of semiconductor device 1 at the line A-A place of Fig. 1.

Fig. 3 is the concept map that the charge carrier (electronics) from N type resilient coating 102 and N type base 103 of explanation present embodiment moves to collector electrode shorting region 101.

Fig. 4 is the cutaway sectional view that the line A-A (Fig. 1) of the semiconductor device 1 of another embodiment of the invention locates.

Fig. 5 is the sectional view of the transistor configurations of expression IGBT.

Fig. 6 is the concept map of the equivalent electric circuit of expression IGBT.

Fig. 7 is that explanation is when applying forward voltage and discharge the concept map of the discharging operation of charge carriers when applying reverse voltage from collector electrode shorting region 101.

Symbol description: 101... collector electrode shorting region, 102...N type resilient coating, 103...N the type base, 104,104A...P type base, 105,105A...N type emitter region, 106,106A... gate insulating film, 107,107A... cathode electrode, 108... dielectric film, 109, the 109A... emitter electrode, 110... collector electrode, the 200... ditch

Embodiment

Below, with reference to accompanying drawing, the IGBT as the semiconductor device of one embodiment of the present invention is described.

Fig. 1 is the vertical view of planar structure of the IGBT of the above-mentioned execution mode of expression.Fig. 2 be presentation graphs 1 line A-A place IGBT cross-sectional configuration cutaway sectional view (owing to illustrated reason, and to the unit form the zone 2 carried out dwindling (quantity that has reduced P type base 104) expression).

Though each unit structure of this IGBT is identical with structure in the past shown in Figure 5, about the position (promptly regional) in the N type semiconductor zone 101 (collector electrode shorting region) that forms semiconductor device, present embodiment is different with example in the past.Example was to form the collector electrode shorting region on whole of the common substrate of semiconductor device in the past.On the other hand, in the present embodiment, the unit that the collector electrode shorting region only is formed on the transistor unit that forms IGBT forms zone 2.

Promptly, in vertical view, face (another interarea side) in the bottom direction of N type base 103, on the relative common substrate of N type resilient coating 102, only forming in the scope of zone 2 overlapping common substrate with the unit, to cut apart the mode of P type semiconductor zone 101 (collector region), between P type semiconductor zone 100, formed N type semiconductor zone 101.

In the present embodiment, vertical view is used for: observe substrate surface from the direction vertical with the common substrate plane, represent each semi-conductive situation that forms the plane overlap condition in zone.

In Fig. 1, the semiconductor device 1 of present embodiment (vertical shape IGBT) is divided into: form the outer electrode formation portion 3 of drawing the outer electrode 2A that uses electrode as outsides such as pads, form zone 2 with the unit of the transistor unit that forms IGBT, N type semiconductor zone 101 (collector electrode shorting region) only is formed on the unit and forms zone 2, more particularly, in vertical view, only forming N type semiconductor zone 101 with P type base 104 position overlapped, for do not make charge carrier from N type semiconductor zone 101 (collector electrode shorting region) discharged sharp, externally electrode formation portion 3 does not form collector electrode shorting region 101.

Thus, the charge carrier that is present in outer electrode formation portion 3, can be as being in the charge carrier that the unit forms zone 2, (collector electrode shorting region) discharged sharp from N type semiconductor zone 101, but form 2 N type semiconductor zone 101, zone and move, and be discharged to collector electrode 110 successively to being in the unit.

Next, in Fig. 2, collector region side (the bottom direction side of figure) at semiconductor device with IGBT structure, in the unit forms zone 2, alternately be formed with P type semiconductor zone 100 (collector region) and N type semiconductor zone 101 (collector electrode shorting region), for outer electrode formation portion 3, on the common substrate that has only formed P type semiconductor zone (collector region) 100, be formed with the IGBT that N type base 103 becomes structural matrix.

This IGBT on the above-mentioned common substrate with N type semiconductor zone 101 and P type semiconductor zone 100, has successively formed N type resilient coating 102 and N type base 103 by epitaxial growth method with routine identical in the past.

In addition, on the surface of N type base 103 (face of the upper side of figure, an interarea side), DIFFUSION TREATMENT by p type impurity has formed a plurality of P types base 104, and, the surface in this P type base 104, the DIFFUSION TREATMENT by N type impurity has formed N type emitter region 105.Promptly, N type emitter region 105 is in vertical view, be formed on the position that is comprised by P type base 104, and the degree of depth also is shallower than P type base 104, it forms the structure that is comprised by P type base 104 fully, promptly, with contacted outer peripheral face of other semiconductor regions and P type base 104 contacted structures except (upside) surface.

On above-mentioned gate insulating film 106, formed gate electrode 107 by electric conductor, this gate electrode 107 is insulated film 108 and covers.

Emitter electrode 109 is connected with the surface electrical of P type base 104 with N type emitter region 105, and in other words, P type base 104 and N type emitter region 105 are electrically connected by emitter electrode 109.

In addition, below the P type semiconductor of common substrate zone 100 and N type semiconductor zone 101 (face of the lower side of figure, another interarea side), be formed with collector electrode 110.Thus, work as collector region, collector electrode shorting region respectively in each P type semiconductor zone 100 and N type semiconductor zone 101.

In vertical view, promptly, when observing N type base 103 with the upper surface of common substrate Surface Vertical, as shown in Figure 1, P type base 104 is banded (strip) and extends.

And, with the direction (the A-A line of Fig. 1) of the above-mentioned bearing of trend quadrature of P type base 104, when observing the cross section of semiconductor device 1, as shown in Figure 2,, have the compartment of terrain each other and dispose a plurality of P types base 104 in the center side of semiconductor device 1.In this inside that has the P type base 104 of compartment of terrain configuration each other, be formed with N type emitter region 105 respectively.

Promptly, in vertical view, be formed with the N type emitter region 105 of the similar long film shape of shape in the P type base 104 of long film shape (band shape).

N type emitter region 105 is along the outer peripheral edges of P type base 104, in the banded extension of length direction.

The belt-like zone of above-mentioned P type base 104, relative across gate insulating film 106 with gate electrode 107, work as well-known channel formation region territory.Promptly, by applying the voltage of (+) to gate electrode 107, form raceway groove on the surface of the P type base 104 relative, and become conducting state with gate electrode 107, N type emitter region 105 and N type base 103 become conducting state.Therefore, in vertical view, N type emitter region 105, P type base 104 and surface separately, N type base 103 with the such arrangement in N type emitter region 105, P type base 104 and N type base 103, relatively form across gate insulating film 106 and gate electrode 107.

Therefore, the P type base 104 that this band shape is extended, be formed on these 104 inside, P type base N type emitter region 105 and with its gate electrode that forms accordingly 107, formed the discrete component zone (unit area) of IGBT.

As mentioned above, in Fig. 1,, be provided with the zone that P type base 104 has compartment of terrain configuration each other, promptly, the unit that disposed a plurality of unit areas forms zone 2 in the center side of semiconductor device 1.

On the other hand, at the outer circumferential side of semiconductor device 1, formed the outer electrode formation portion 3 of unit area.The outer electrode formation portion 3 that does not form this unit area surrounds the unit that is formed with the IGBT unit with the shape of ring-type or encirclement and forms zone 2.

At this,, outer electrode 2A such as well-known connection electrode (bonding welding pad) and grid bus have been disposed not forming the said external electrode formation portion 3 of unit area.

In the present embodiment, for the outer electrode formation portion 3 that will form bonding welding pad is set, the unit forms zone 2 and becomes the local shape of depression to the inside, its result, as shown in Figure 1, the development length of the unit area of center side (P type base 104) is shorter than the development length of other unit areas.

As mentioned above, in the IGBT of present embodiment, be formed with the N type semiconductor zone 101 (collector electrode shorting region) that is electrically connected collector electrode 110 and N type resilient coating 102.

But, its formed zone is different with in the past IGBT, collector electrode shorting region 101 only is configured in the unit that is formed with the IGBT unit and forms zone 2, and is not forming the outer electrode formation portion 3 of this unit area, does not dispose N type semiconductor zone 101 (collector electrode shorting region).

In addition, as shown in Figure 1, N type semiconductor zone 101 forms the diffusion layer that has each other at interval in vertical view, overlapping with N type base 104, and is contained in the position of N type base 104 in periphery, and the length direction in N type base 104 is disposed with a plurality of.

According to said structure, shown in the concept map of the cross-sectional configuration of the semiconductor device 1 of Fig. 3 (a), from the status transition that applied forward bias behind the state that has applied reverse biased, charge carrier (electronics) near the collector electrode shorting region 101, be N type resilient coating 102 and the N type base 103 that the unit forms zone 2, move to N type semiconductor zone (collector electrode shorting region) 101, flow out from collector electrode 110 as electric current.

But, savings gently flows at the N type resilient coating 102 and the charge carrier in the N type base 103 of the outer electrode formation portion 3 that does not form N type semiconductor zone 101 (collector electrode shorting region), via N type semiconductor zone 101 (collector electrode shorting region), flow and discharge to collector electrode 110 as electric current.

Therefore, shown in Fig. 3 (b), for the time that Weak current I flows, with electrode formation portion 3 externally also formed N type semiconductor zone 101 (collector electrode shorting region), promptly compare in whole example in the past that has formed N type semiconductor zone 101 of common substrate, with respect to during ts, td elongated (td ' among the figure) during this time, the ratio of td/ts become big, so can realize soft recovery characteristics.

That is, in Fig. 3 (b), solid line is represented the flow regime of the electric current I of present embodiment, and dotted line is represented the flow regime of the electric current I of example in the past.From Fig. 3 (b) as can be known, compare with example in the past, junction diode be in short-circuit condition during ts do not change, but with in the past the example during td compare, can extend from reverse voltage become that the reverse prevention function that is carved into junction diode when peaked works during td ', make (td '/ts)＞(td/ts) relation sets up, and relatively can improve the soft recovery characteristics of junction diode with example in the past.

In addition, as another execution mode, can make its IGBT corresponding with structure shown in Figure 4.

At this moment, planar configuration as semiconductor device 1, its Fig. 1 with an execution mode is identical, the semiconductor device 1 of present embodiment (vertical shape IGBT) is divided into: form the outer electrode formation portion 3 of drawing the outer electrode 2A that uses electrode as outsides such as pads, form zone 2 with the unit of the transistor unit that forms IGBT, N type semiconductor zone 101 (collector electrode shorting region) only is formed at the unit and forms zone 2, more particularly, in vertical view, only forming N type semiconductor zone 101 (collector electrode shorting regions), and externally electrode formation portion 3 does not form collector electrode shorting region 101 with P type base 104A position overlapped.

Next, in Fig. 4, the same with an above-mentioned execution mode, collector region side (the bottom direction side of figure) at the structure of semiconductor device 1, in forming zone 2, the unit alternately disposes P type semiconductor zone (collector region) 100 and N type semiconductor zone (collector electrode shorting region) 101, externally electrode formation portion 3 forms IGBT on the so-called common substrate that has only disposed P type semiconductor zone 100.

This IGBT is identical with an execution mode, on above-mentioned common substrate, with example was the same in the past, has formed N type resilient coating 102 successively by epitaxial growth method, and N type base 103.

In addition, on the surface of N type base 103 (face of the upper side of Fig. 4), ditch 200 forms long glue sheet, DIFFUSION TREATMENT by p type impurity, be adjacent to be formed with a plurality of P type base 104A with the sidewall of this ditch 200, and then, the surface in this P type base 104A, by the DIFFUSION TREATMENT of N type impurity, formed N type emitter region 105A.

At this, N type emitter region 105A still is adjacent to form with the sidewall of ditch 200.That is, N type emitter region 105A is formed on the position that is comprised by P type base 104A in vertical view, and the degree of depth also is shallower than P type base 104A, forms the structure that is comprised by P type base 104A fully.

In addition, in order to make electric insulation between gate electrode, P type base 104A and the N type emitter region 105A, formed gate insulating film 106A at the inner face that is formed at the ditch 200 between each P type base 104A.

At above-mentioned gate insulating film 106A inner face, be formed with gate electrode 107A, this gate electrode 107A is covered by not shown dielectric film.Promptly, in ditch 200, at these ditch 200 inner faces, be formed with gate electrode 107A across gate insulating film 106A.

P type base 104A and N type emitter region 105A are electrically connected by emitter electrode 109A, promptly, on the surface of P type base 104A and N type emitter region 105A, are formed with emitter electrode 109A, and P type base 104A and N type emitter region 105A are electrically connected.

In addition, in the P type semiconductor zone 100 of common substrate and the bottom surface (face of the lower side of figure) in N type semiconductor zone 101, be formed with collector electrode 110.Thus, work as collector region and collector electrode shorting region respectively in each P type semiconductor zone 100 and N type semiconductor zone 101.

Identical with an above-mentioned execution mode, in vertical view, promptly, when when the upper face side of N type base 103 is observed, as shown in Figure 1, P type base 104A extends bandedly, and it is a plurality of to form (strip ground).

And, such as shown when observing the cross section of semiconductor device 1 on direction (the A-A line of Fig. 1) at P type base 104A and above-mentioned bearing of trend quadrature, in the center side of semiconductor device 1, have the compartment of terrain each other and dispose a plurality of P type base 104A.In this inside that has the P type base 104A of compartment of terrain configuration each other, be formed with N type emitter region 105A respectively.In addition, form in the unit between the ditch 200 in zone, be formed with P type base 104A bandedly,, relatively be formed with N type emitter region 105A at this P type base 104A inner surface.

N type emitter region 105A, extends towards length direction along the outer peripheral edges of P type base 104A bandedly.

The belt-like zone of above-mentioned P type base 104A is across gate insulating film 106A, and is relative with the sidewall of gate electrode 107A, works as well-known channel formation region territory.Promptly, by apply the voltage of (+) to gate electrode 107A, in the side of the P type base 104A relative with gate electrode 107A, promptly, with the contacted zone of sidewall of ditch 200, form raceway groove and become conducting state, thereby N type emitter region 105A and N type base 103 become conducting state.

For this reason, shown in the cutaway sectional view of Fig. 4, N type emitter region 105A, P type base 104A and side separately, N type base 103, with the such arrangement in N type emitter region 105A, P type base 104A and N type base 103, relative with gate electrode 107 across gate insulating film 106A.Promptly, press the order cambium layer structure of N type emitter region 105A, P type base 104A and N type base 103.

A P type base 104A, the N type emitter region 105A that is formed on this 104A inside, P type base that extends by this band shape and with the gate electrode 107A that it forms accordingly, formed the discrete component zone (unit area) that forms the IGBT of raceway groove at the sidewall of ditch 200.

As described above, in Fig. 1,, be provided with the zone that P type base 104A has compartment of terrain configuration each other, promptly, the unit that disposed a plurality of unit areas forms zone 2 in the center side of semiconductor device 1.About other actions, since identical with an execution mode, so omit explanation.The same with an execution mode, N type semiconductor zone 101 only is formed at the unit and forms zone 2 overlapping part in vertical view.

In addition, in an execution mode and another execution mode, also IGBT can be deformed into structure shown below.

(1) also can adopt and do not form N type resilient coating 102, and on the common substrate that is formed with P type semiconductor zone 100 and N type semiconductor zone 101, directly form the structure of N type base 103.

(2) though N type semiconductor zone 101 (collector electrode shorting region) is arranged on the bottom of P type base 104 (or 104A), but also can be in vertical view, be arranged between the P type base 104 that forms long glue sheet and (certainly, be formed on the inside that the unit forms the zone).

(3) though P type base 104 (or 104A) is formed the strip of long film shape, also can form the clathrate of the P type base quadrature of long film shape, or be divided into the island in the zone of Rack.

Claims

1. one kind has the semiconductor device that insulated gate bipolar transistor is constructed, and it is characterized in that having:

First base of first conductivity type,

Be disposed at second base of second conductivity type of an interarea side of this first base,

Be formed on the emitter region of first conductivity type in above-mentioned second base,

Be configured in the collector region of second conductivity type of another interarea side of above-mentioned first base, and

Another interarea side in above-mentioned first base is inserted between the collector region and the collector electrode shorting region of first conductivity type that forms in the mode of cutting apart above-mentioned collector region;

Peripheral part in an interarea side of above-mentioned first base is provided with the outer electrode formation portion that does not form above-mentioned second base, the transistor unit that above-mentioned second base is formed on the inboard of this outer electrode formation portion forms the zone, and above-mentioned collector electrode shorting region only is formed in the vertical view and forms in the described collector region of region overlapping with said units.

2. semiconductor device according to claim 1 is characterized in that, above-mentioned collector electrode shorting region only is formed in the vertical view and forms in the overlapping described collector region, interior above-mentioned second base, zone with said units.

3. semiconductor device according to claim 1 and 2 is characterized in that, an interarea upper lateral part in above-mentioned first base is provided with gate electrode between above-mentioned emitter region.

4. semiconductor device according to claim 3 is characterized in that above-mentioned gate electrode is arranged in the ditch that is formed between the above-mentioned emitter region.